WO2023193311A1 - 显示面板 - Google Patents

显示面板 Download PDF

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Publication number
WO2023193311A1
WO2023193311A1 PCT/CN2022/088551 CN2022088551W WO2023193311A1 WO 2023193311 A1 WO2023193311 A1 WO 2023193311A1 CN 2022088551 W CN2022088551 W CN 2022088551W WO 2023193311 A1 WO2023193311 A1 WO 2023193311A1
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WO
WIPO (PCT)
Prior art keywords
auxiliary
auxiliary layer
layer
substrate
display panel
Prior art date
Application number
PCT/CN2022/088551
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English (en)
French (fr)
Inventor
张向向
Original Assignee
武汉华星光电半导体显示技术有限公司
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Filing date
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Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/772,619 priority Critical patent/US20240172539A1/en
Priority to JP2022565852A priority patent/JP2024519233A/ja
Priority to KR1020227020188A priority patent/KR20230144933A/ko
Publication of WO2023193311A1 publication Critical patent/WO2023193311A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/127—Active-matrix OLED [AMOLED] displays comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/351—Thickness

Definitions

  • the present application relates to the field of display technology, in particular to the manufacturing of display devices, and specifically to display panels.
  • OLED Organic Light Emitting Diode, organic light-emitting display
  • OLED panels achieve bendable characteristics through flexible substrates.
  • the large number of polarizable charges present in the flexible substrate can easily be polarized to form a large number of polarized charges, thereby polarizing the active layer of the transistor in the pixel circuit. , resulting in lower reliability of transistor operation and lowering the quality of the OLED panel display.
  • the purpose of this application is to provide a display panel to solve the problem of low reliability of transistors in existing OLED panels due to the polarization effect of the flexible substrate on the active layer of the transistor in the pixel circuit.
  • Embodiments of the present application provide a display panel, including:
  • the thin film transistor layer located on the substrate, the thin film transistor layer including a plurality of transistors;
  • the auxiliary layer is located between the substrate and the thin film transistor layer.
  • the auxiliary layer includes a first auxiliary layer and a second auxiliary layer located at least on a side of the first auxiliary layer close to the substrate, so
  • the second auxiliary layer includes a plurality of auxiliary parts, and there is a gap between two adjacent auxiliary parts;
  • the dielectric constant of the constituent material of the first auxiliary layer is smaller than the dielectric constant of the substrate and greater than the dielectric constant of the constituent material of the second auxiliary layer.
  • the present application provides a display panel, including: a substrate; a thin film transistor layer located on the substrate, the thin film transistor layer including a plurality of transistors; an auxiliary layer located between the substrate and the thin film transistor layer,
  • the auxiliary layer includes a first auxiliary layer and a second auxiliary layer located at least on a side of the first auxiliary layer close to the substrate.
  • the second auxiliary layer includes a plurality of auxiliary parts. Two adjacent auxiliary parts There is a gap between the parts; wherein the dielectric constant of the constituent material of the first auxiliary layer is smaller than the dielectric constant of the constituent material of the substrate and greater than the dielectric constant of the constituent material of the second auxiliary layer.
  • this application reduces the impact on charge movement in the active layer by arranging a first auxiliary layer with a dielectric constant smaller than that of the substrate, and by arranging a second auxiliary layer with a smaller dielectric constant.
  • the second auxiliary layer includes a plurality of auxiliary parts arranged at intervals, which can further reduce the impact on charge movement in the active layer.
  • FIG. 1 is a schematic cross-sectional view of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional view of another display panel provided by an embodiment of the present application.
  • FIG. 3 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a display panel manufacturing method provided by an embodiment of the present application.
  • the present application provides a display panel, which includes but is not limited to the following embodiments and combinations between the following embodiments.
  • the display panel 100 includes: a substrate 10; a thin film transistor layer located on the substrate 10, the thin film transistor layer including a plurality of transistors 20; an auxiliary layer, located between the substrate 10 and the thin film transistor layer.
  • the auxiliary layer includes a first auxiliary layer 30 and a second auxiliary layer located at least on a side of the first auxiliary layer 30 close to the substrate 10 .
  • Layer 40, the second auxiliary layer 40 includes a plurality of auxiliary parts 401, and there is a gap between two adjacent auxiliary parts 401; wherein the dielectric constant of the constituent material of the first auxiliary layer 30 is smaller than that of the lining.
  • the dielectric constant of the material of the bottom 10 is greater than the dielectric constant of the material of the second auxiliary layer 40 .
  • the constituent material of the substrate 10 may include polyimide.
  • the substrate 10 may include a first substrate 101 , a second substrate 102 located near the first substrate 101 and the thin film transistor layer, and a second substrate 102 located between the first substrate 101 and the second substrate.
  • the first buffer layer 103 between the substrate 102, the component material of the first substrate 101 and the second substrate 102 may include polyimide, and the component material of the first buffer layer 103 may include silicon oxide, nitride
  • At least one of the silicon, such as the first buffer layer 103 made of silicon oxide, has the functions of water absorption and heat preservation, which can extend the life of the display panel 100 .
  • the transistor 20 may include an active layer 201 , a gate layer 202 located on a side of the active layer 201 away from the substrate 10 , and a side of the gate layer 202 located away from the substrate 10 .
  • the source and drain layer on the side of the active layer 201 includes a source portion 203 that is opposite to and electrically connected to one end of the active layer 201, and a drain portion that is opposite to and electrically connected to one end of the active layer 201. 204.
  • the display panel 100 further includes a first insulating layer 205 located between the active layer 201 and the gate layer 202 and covering the active layer 201 , and a second insulating layer covering the side of the gate layer 202 away from the substrate 10 layer 206, a metal layer 207 located on the side of the second insulating layer 206 away from the substrate 10, and an interlayer dielectric layer 208 located between the metal layer 207 and the source and drain layers and covering the metal layer 207.
  • the component material of the active layer 201 may include at least one of amorphous silicon and polysilicon, and the polysilicon may include low-temperature polysilicon. Furthermore, the component material of the active layer 201 may also include oxide. It can be understood that, for example, the active layer 201 prepared using low-temperature polysilicon technology can have higher electron mobility, so that when the transistor 20 charges the corresponding pixel, a larger driving current can be generated to increase the charging speed; The active layer 201 made of crystalline silicon or oxide can have low leakage current to prevent the leakage of the transistor 20 from causing signal interference during exposure.
  • the two ends of the active layer 201 that are electrically connected to the source and drain layers can be doped with particles to form two doped regions.
  • the doped particles can include The concentrations of phosphorus ions and doping particles in the doping region can be set according to actual conditions; for example, when the component material of the active layer 201 includes oxide, it is possible to avoid setting doping particles to form the doping region.
  • the source and drain layers can be extended to the electrical circuit through via holes penetrating the interlayer dielectric layer 208 , the second insulating layer 206 , and part of the first insulating layer 205 .
  • the first via hole is connected to the side of one end of the active layer 201 away from the substrate 10 and the side of the interlayer dielectric layer 208 away from the substrate 10, and the second via hole is connected to The other end of the active layer 201 is away from the substrate 10 and the interlayer dielectric layer 208 is away from the substrate 10 .
  • the source portion 203 is filled in the first via hole and extends to the interlayer dielectric layer 208 away from the substrate.
  • the drain portion 204 is filled in the second via hole and extends to the side of the interlayer dielectric layer 208 away from the substrate 10 .
  • the metal layer 207 may be disposed opposite to the gate layer 202 to form a corresponding capacitor in the pixel circuit.
  • the constituent materials of the first insulating layer 205, the second insulating layer 206, and the interlayer dielectric layer 208 may include at least one of inorganic dielectric materials and organic dielectric materials.
  • Inorganic dielectric materials It can be silicon oxide, silicon nitride or silicon oxynitride, and the organic dielectric material can be polyimide resin, epoxy resin or acrylic resin material.
  • the constituent materials of the gate layer 202, the metallic layer 207, and the source and drain layers may include at least one of conductive materials such as metal, metal oxide, metal nitride, and metal oxynitride, The metal can be copper, aluminum, molybdenum or titanium.
  • the large amount of polarizable charges present in the substrate 10 is easily affected by external influences or the internal electric field of the display panel 100 , and is polarized to form a large amount of polarized charges. If not If the auxiliary layer is provided, a large amount of polarized charges in the substrate 10 located on the side of the substrate 10 close to the thin film transistor layer will produce a polarization effect on the active layer 201, causing the charge movement in the active layer 201 to be affected, reducing the Reliability of transistor 20 operation.
  • the dielectric constant of the material of the first auxiliary layer 30 in this embodiment is smaller than the dielectric constant of the substrate 10. It can be seen from the rule that "the larger the dielectric constant, the easier it is to produce polarization". It is difficult for an auxiliary layer 30 to be polarized relative to the substrate 10 .
  • the third layer 30 between the substrate 10 and the transistor 20 The amount of polarization charges formed by polarization of an auxiliary layer 30 can still be much smaller than the amount of polarization charges formed by polarization of the substrate 10 when the first auxiliary layer 30 is not provided, so the charges in the active layer 201 move The impact can be reduced and the reliability of the operation of the transistor 20 is improved.
  • the dielectric constant of the material of the second auxiliary layer 40 is smaller than the dielectric constant of the material of the first auxiliary layer 30 .
  • at least those located close to the first auxiliary layer 30 The number of polarization charges formed by polarization of the second auxiliary layer 40 on one side of the substrate 10 can still be much smaller than the number of polarization charges formed by the polarization of the first auxiliary layer 30 when the second auxiliary layer 40 is not provided. Therefore, the influence of charge movement in the active layer 201 can be further reduced, further improving the reliability of the operation of the transistor 20 .
  • the second auxiliary layer 40 by arranging the second auxiliary layer 40 to be composed of a plurality of auxiliary parts 401 arranged at intervals, it can be avoided that the second auxiliary layer 40 completely covers the substrate 10.
  • the display panel 100 includes components located under the auxiliary layer or on the substrate
  • the second auxiliary layer 40 can be arranged in a manner to ensure the light transmittance of the display panel 100 to avoid blocking more light. At least one of the brightness of the display panel 100 and the operation reliability of the photosensitive device is improved.
  • the shape and size of the auxiliary part 401 are not limited in this embodiment.
  • the dielectric constant of the material of the second auxiliary layer 40 is small, the light transmittance is generally smaller than that of the first auxiliary layer 30 , that is, although the second auxiliary layer 40 can weaken the existing light to a greater extent.
  • the second auxiliary layer 40 is configured to be composed of a plurality of auxiliary portions 401 arranged at intervals, so that Based on the aspect that "the dielectric constant of the constituent material of the second auxiliary layer 40 is relatively small", the first auxiliary layer 30 of the constituent material with greater light transmittance is filled between two adjacent auxiliary portions 401 to avoid the The light transmittance of the plane where the second auxiliary layer 40 is located is too small.
  • the first auxiliary layer 30 fills the gap. Based on the above discussion, it can be seen that on the one hand, this embodiment can effectively improve the light transmittance of the display panel 100 by setting gaps and filling the gaps with the first auxiliary layer 30 with larger light transmittance. On the other hand, based on multiple gaps, , the multiple auxiliary parts 401 cannot be overlapped with the substrate 10 , so that they cannot act on the entire substrate 10 . In this embodiment, the first auxiliary layer 30 whose dielectric constant is smaller than the dielectric constant of the substrate is used to fill the gap to act.
  • the amount of polarization charges formed by polarization of the first auxiliary layer 30 can still be much smaller than the amount of polarization charges formed by polarization of the substrate 10 when the first auxiliary layer 30 is not provided.
  • the first auxiliary layer 30 can further reduce the impact on the charge movement in the active layer 201 based on the second auxiliary layer 40 acting on the substrate 10 .
  • the second auxiliary layer 40 is a conductor. It can be understood that, on the one hand, the dielectric constant of the conductor is close to 0, which, combined with the above discussion, can greatly reduce the impact of charge movement in the active layer 201; on the other hand, the resistivity of the conductor is very small and is easy to conduct current. , there are a large number of freely movable charged particles in the conductor, which can attract the polarization charges formed by the polarization of the first auxiliary layer 30 with a relatively large dielectric constant, so as to uniformize the positively charged polarization charges and the negatively charged electrodes.
  • the distribution of polarization charges can further make the positively charged polarization charges and negatively charged polarization charges recombine to reduce the number of polarization charges, weaken the directionality of polarization, and also greatly reduce the charge in the active layer 201 The impact of movement.
  • the constituent material of the second auxiliary layer 40 may include a metal conductor. Since the electrical conductivity of metal conductors is usually greater than that of other conductor materials, and the resistivity of metal conductors generally decreases as the temperature decreases, at extremely low temperatures, certain The resistivity of some metal conductors and alloys will disappear and transform into "superconductors", which can further reduce the impact of charge movement in the active layer 201.
  • the metal conductor in this embodiment can be, but is not limited to, indium tin oxide, silver element, molybdenum element, aluminum element, graphene, superconducting metal, superconducting alloy. It can be understood that the metal conductors listed above are relatively Other metal conductors have higher light transmittance to avoid significantly reducing the light transmittance of the display panel 100 , and have smaller elastic modulus to meet the stress and strain requirements required by the display panel 100 .
  • a plurality of the auxiliary parts 401 are evenly arranged and in direct contact with the substrate surface. It can be understood based on the above discussion that on the one hand, the number of polarization charges formed by polarization of the second auxiliary layer 40 is very small, and the second auxiliary layer 40 is disposed close to the active layer 201 , that is, each auxiliary portion 401 The polarization effect of corresponding positions in the substrate 10 and corresponding positions in the first auxiliary layer 30 on the active layer 201 can be weakened, so the uniformly arranged plurality of auxiliary portions 401 can even out the influence of charge movement in the active layer 201.
  • the weakened area further optimizes the way in which the influence of charge movement in the active layer 201 is weakened; on the other hand, the multiple auxiliary parts 401 evenly arranged can even out the arrangement of the corresponding multiple gaps to even out the display panel 100
  • the light transmittance of each area in the display panel 100 is optimized to improve the light transmittance of the display panel 100 .
  • the plurality of evenly arranged auxiliary parts 401 in this embodiment can also uniformize the area of the second auxiliary layer 40 used to attract the polarization charges of the first auxiliary layer 30 , to further homogenize the charge distribution of the first auxiliary layer 30 , and at the same time, further homogenize the area in the second auxiliary layer 40 used to recombine the polarization charges in the first auxiliary layer 30 to further weaken the polarization of the first auxiliary layer 30 . Therefore, this embodiment can further greatly reduce the influence of charge movement in the active layer 201 .
  • the first auxiliary layer 30 covers a side of the plurality of auxiliary parts 401 close to the thin film transistor layer.
  • the side of the plurality of auxiliary parts 401 close to the first auxiliary layer 30 in this embodiment can be wrapped in the first auxiliary layer 30 , so that on the basis of the plurality of auxiliary parts 401 being formed on the substrate 10 , and when the surface area of the auxiliary part 401 is constant, the other surfaces of the auxiliary part 401 that are not in contact with the substrate 10 can be in contact with the first auxiliary layer 30 to fully act on the polarizable charges in the first auxiliary layer 30 , to reduce the amount of polarization charges, thereby reducing the impact on charge movement in the active layer 201 .
  • the first auxiliary layer 30 can cover a plurality of the auxiliary portions 401 and fill the gaps between two adjacent auxiliary portions 401 , and the first auxiliary layer 30 is also in direct contact with the surface of the substrate 10 .
  • the side of the auxiliary part 401 close to the first auxiliary layer 30 includes at least one of a convex part and a recessed part.
  • the side of the auxiliary portion 401 close to the first auxiliary layer 30 is in an uneven state, and based on the above discussion, the shape of the side of the first auxiliary layer 30 close to the second auxiliary layer 40 is different from the shape of the first auxiliary layer 30 .
  • the shape of the side of each of the auxiliary parts 401 close to the first auxiliary layer 30 matches, that is, the side of the first auxiliary layer 30 close to the second auxiliary layer 40 also includes at least one of a convex part and a recessed part.
  • the side of the auxiliary part 401 close to the first auxiliary layer 30 is convex, and the shapes of the two sides close to each other match, that is, the second auxiliary part 401 includes very few polarization charges.
  • the area of the auxiliary layer 40 and the first auxiliary layer 30 that are in contact with the first auxiliary layer 30 is larger, and a larger proportion of the charges in the first auxiliary layer 30 can be applied.
  • the first auxiliary layer 30 can be charged by the substrate 10 The smaller number of polarized charges can reduce the polarization effect on the active layer 201 .
  • the second auxiliary layer 40 and the first auxiliary layer 30 having larger relative areas in this embodiment increase the area of the second auxiliary layer 40 for attracting the second auxiliary layer 40 .
  • the area of the polarized charge of an auxiliary layer 30 further increases the uniformity effect on the charge distribution of the first auxiliary layer 30 , and also increases the area of the second auxiliary layer 40 used to composite the first auxiliary layer 30 Therefore, this embodiment can further greatly reduce the impact of charge movement in the active layer 201 .
  • the first distance between the surface of the first auxiliary layer 30 corresponding to the auxiliary part 401 and close to the thin film transistor layer and the surface of the substrate 10 is greater than the first distance between the surface of the first auxiliary layer 30 and the surface of the first auxiliary layer 30 corresponding to the gap.
  • the second distance from the surface of the thin film transistor layer to the surface of the substrate 10 .
  • a plurality of transistors are also provided on the first auxiliary layer 30.
  • the first distance is defined to be greater than the second distance, so as to control the side of the first auxiliary layer 30 close to the thin film transistor layer.
  • the planarization process can facilitate the formation of multiple stable transistors in the later stage and improve the yield of the process.
  • the side of the first auxiliary layer 30 close to the thin film transistor layer can be parallel to the substrate 10 .
  • the thickness of the first auxiliary layer 30 is less than 10 angstroms. It can be understood that since the function of the first auxiliary layer 30 is to reduce the impact of polarization charges in the substrate 10 on the charge movement in the active layer 201, and it is not expected that the thickness of the first auxiliary layer 30 is large, this implementation In this example, the thickness of the first auxiliary layer 30 is limited to less than 10 angstroms, which can maintain the function of the first auxiliary layer 30 while preventing the thickness of the first auxiliary layer 30 from being too large to increase the thickness of the display panel 100 or affect the performance of the display panel 100 . stress. Of course, the thickness of the auxiliary part 401 may also be greater than the thickness of the first auxiliary layer 30 .
  • the second auxiliary layer 40 is also located on the side of the first auxiliary layer 30 away from the substrate 10 , and is located on the side of the first auxiliary layer 30 away from the substrate 10 .
  • a plurality of the auxiliary parts 401 in are in one-to-one correspondence, and the two auxiliary parts 401 in the one-to-one correspondence are arranged oppositely.
  • a plurality of grooves may be formed through, but not limited to, a yellow light process.
  • the plurality of grooves may be connected to the second auxiliary layer located on the side of the first auxiliary layer 30 close to the substrate 10
  • the plurality of auxiliary portions 401 in 40 correspond one to one, and then are formed in multiple grooves by, but not limited to, physical vapor deposition to form a side of the first auxiliary layer 30 close to the substrate 10 another second auxiliary layer 40.
  • first auxiliary layer 30 when the thickness of the first auxiliary layer 30 is greater than the thickness of the second auxiliary layer 40 on the side close to the substrate 10, multiple auxiliary portions 401 on the side far from the substrate 10 can be formed to further act on the The polarization charges in the first auxiliary layer 30 further reduce the impact on the charge movement in the active layer 201 . At the same time, due to the one-to-one corresponding arrangement of the two auxiliary parts 401 relative to each other, additional reduction in the size of the display panel 100 is also avoided. of light transmittance.
  • the first auxiliary layer 30 is made of a polarizing material.
  • polarization can be understood as the phenomenon that the electric potential deviates from the open-circuit potential of the electrode due to the movement of electric current.
  • the "polarized material” here can be understood as a material with polarization properties, for example, it can produce a polarizing effect on the substrate 10.
  • the first auxiliary layer 30 itself may be polarized.
  • the constituent material of the first auxiliary layer 30 may include amorphous silicon.
  • the adsorption force between amorphous silicon and the substrate 10 is relatively large, which is beneficial to the formation of the first auxiliary layer 30 and improves the stability between the auxiliary layer and the substrate 10 .
  • amorphous silicon can be produced from natural silicon oxide, which has a lower cost
  • amorphous silicon is a semiconductor, which can reduce the impact of polarized charges in the substrate 10 on the charge movement of the active layer 201 effect.
  • the display panel 100 further includes: a buffer layer 50 located on the side of the auxiliary layer close to the thin film transistor layer.
  • the buffer layer 50 is made of a composition material. Including at least one of silicon nitride and silicon oxide. It should be noted that the auxiliary layer formed by the chemical vapor deposition process or the physical vapor deposition process will be rough on the side close to the thin film transistor layer. In this embodiment, the chemical vapor deposition process may be used, but is not limited to, to form a buffer layer with a certain thickness. 50, that is, it can be understood that the side of the buffer layer 50 close to the thin film transistor layer will be relatively flat, which is beneficial to the formation of the thin film transistor layer.
  • the buffer layer 50 formed of at least one of silicon nitride and silicon oxide can absorb water to prevent external water vapor from infiltrating and damaging the light-emitting device, and can also have a heat preservation function to prevent strong temperature changes during the manufacturing process. Reducing the reliability of active layer 201.
  • the buffer layer 50 may include a second buffer layer 501 and a third buffer layer 502 located on the second buffer layer 501.
  • the constituent material of one of the second buffer layer 501 and the third buffer layer 502 may include oxynitride.
  • the constituent material of the other one of silicon, the second buffer layer 501 and the third buffer layer 502 may include silicon oxide; further, the buffer layer 50 may further include a third buffer layer made of silicon oxynitride.
  • a dielectric layer may be provided between the buffer layer 50 and the thin film transistor layer.
  • the dielectric layer is used to insulate the active layer 201 and other film layers.
  • the composition material of the dielectric layer please refer to the composition of the buffer layer 50 mentioned above. A description of the material.
  • This application also provides a method for manufacturing a display panel, which method includes but is not limited to the following embodiments and combinations between the following embodiments.
  • the manufacturing method of the display panel includes but is not limited to the following steps.
  • the substrate 10 may include a first substrate 101 , a second substrate 102 located near the first substrate 101 and the thin film transistor layer, and a second substrate 102 located between the first substrate 101 and the second substrate.
  • the first buffer layer 103 between the substrate 102, the component material of the first substrate 101 and the second substrate 102 may include polyimide, and the component material of the first buffer layer 103 may include silicon oxide, nitride
  • At least one of the silicon, such as the first buffer layer 103 made of silicon oxide, has the functions of water absorption and heat preservation, which can extend the life of the display panel 100 .
  • the auxiliary layer includes a first auxiliary layer and a second auxiliary layer located at least on a side of the first auxiliary layer close to the substrate.
  • the second auxiliary layer It includes a plurality of auxiliary parts, and there is a gap between two adjacent auxiliary parts.
  • the dielectric constant of the constituent material of the first auxiliary layer is smaller than the dielectric constant of the substrate and larger than the dielectric constant of the second auxiliary layer.
  • the dielectric constant of the constituent material, the light transmittance of the first auxiliary layer is greater than the light transmittance of the second auxiliary layer.
  • the second auxiliary layer 40 is at least located on a side of the first auxiliary layer 30 close to the substrate 10 , that is, the second auxiliary layer 40 can be formed before the first auxiliary layer 30 is formed.
  • the second auxiliary layer 40 can be formed at least on the second substrate 102 by physical vapor deposition, for example, the material source surface of the constituent material of the second auxiliary layer 40 is vaporized into gaseous atoms or molecules, or partially ionized into The ions are deposited on the surface of the second substrate 102 through a plasma process to form the second auxiliary layer 40 .
  • the energy used to deposit the second auxiliary layer 40 may be small to prevent the constituent materials of the second auxiliary layer 40 from sputtering into the substrate 10 and even causing the substrate 10 to warp.
  • a plurality of auxiliary portions 401 corresponding to the plurality of openings can be deposited on the surface of the second substrate 102 through a mask with a plurality of openings, combined with physical vapor deposition, to form a The second auxiliary layer 40.
  • the number and arrangement of the plurality of auxiliary parts 401 are not limited here, and reference may be made to the relevant description of the auxiliary parts 401 above.
  • the first auxiliary layer 30 can be formed on the second auxiliary layer 40 by chemical deposition.
  • the first auxiliary layer 30 can cover the second auxiliary layer 40 . part or all of layer 40.
  • the second auxiliary layer 40 includes a plurality of auxiliary parts 401 arranged at intervals as an example.
  • the second auxiliary layer 40 may be deposited on the substrate 10 and the plurality of auxiliary parts 401 .
  • the thickness of the first auxiliary layer 30 may be less than 10 angstroms.
  • the dielectric constant of the material of the first auxiliary layer 30 in this embodiment is smaller than the dielectric constant of the substrate 10. It can be seen from the rule that "the larger the dielectric constant, the easier it is to produce polarization". It is difficult for an auxiliary layer 30 to be polarized relative to the substrate 10 .
  • the third layer 30 between the substrate 10 and the transistor 20 The amount of polarization charges formed by polarization of an auxiliary layer 30 can still be much smaller than the amount of polarization charges formed by polarization of the substrate 10 when the first auxiliary layer 30 is not provided, so the charges in the active layer 201 move The impact can be reduced and the reliability of the operation of the transistor 20 is improved.
  • the dielectric constant of the material of the second auxiliary layer 40 is smaller than the dielectric constant of the material of the first auxiliary layer 30 .
  • at least those located close to the first auxiliary layer 30 The number of polarization charges formed by polarization of the second auxiliary layer 40 on one side of the substrate 10 can still be much smaller than the number of polarization charges formed by the polarization of the first auxiliary layer 30 when the second auxiliary layer 40 is not provided. Therefore, the influence of charge movement in the active layer 201 can be further reduced, further improving the reliability of the operation of the transistor 20 .
  • the dielectric constant of the second auxiliary layer 40 is small, the light transmittance is larger than that of the first auxiliary layer 30 , that is, although the second auxiliary layer 40 can further weaken the light in the active layer 201 polarization phenomenon, but has the disadvantage of low light transmittance. It can be understood that in this embodiment, by arranging the second auxiliary layer 40 to be composed of a plurality of auxiliary portions 401 arranged at intervals, it can be avoided that the second auxiliary layer 40 completely covers the substrate 10.
  • the second auxiliary layer 40 can be arranged in a manner to ensure the light transmittance of the display panel 100 to avoid occlusion. More light improves at least one of the brightness of the display panel 100 and the reliability of the operation of the photosensitive device.
  • the shape and size of the auxiliary part 401 are not limited in this embodiment.
  • S30 Form a thin film transistor layer on a side of the auxiliary layer away from the substrate, where the thin film transistor layer includes a plurality of transistors.
  • the transistor 20 may include an active layer 201, a gate layer 202 located on a side of the active layer 201 away from the substrate 10, and a gate layer 202 located on a side away from the substrate 10.
  • the source and drain layer on one side of the active layer 201 includes a source portion 203 that is opposite to and electrically connected to one end of the active layer 201, and a drain layer that is opposite to and electrically connected to one end of the active layer 201.
  • Jibu 204 Jibu 204.
  • the display panel 100 further includes a first insulating layer 205 located between the active layer 201 and the gate layer 202 and covering the active layer 201 , and a second insulating layer covering the side of the gate layer 202 away from the substrate 10 layer 206, a metal layer 207 located on the side of the second insulating layer 206 away from the substrate 10, and an interlayer dielectric layer 208 located between the metal layer 207 and the source and drain layers and covering the metal layer 207.
  • a first insulating layer 205 located between the active layer 201 and the gate layer 202 and covering the active layer 201
  • a second insulating layer covering the side of the gate layer 202 away from the substrate 10 layer 206
  • a metal layer 207 located on the side of the second insulating layer 206 away from the substrate 10
  • an interlayer dielectric layer 208 located between the metal layer 207 and the source and drain layers and covering the metal layer 207.
  • the buffer layer 50 may be formed on the side of the auxiliary layer away from the substrate 10 , for example, it may be further away from the substrate 10 than the auxiliary layer.
  • the second buffer layer 501 is formed on one side of the second buffer layer 501
  • the third buffer layer 502 is formed on the side of the second buffer layer 501 away from the substrate 10 .
  • the composition materials of the second buffer layer 501 and the third buffer layer 502 can be referred to Related descriptions above.
  • the active layer 201 can be formed directly from the amorphous silicon material on the side of the buffer layer 50 away from the substrate 10 .
  • excimer laser annealing can also be used.
  • the amorphous silicon film is processed to form a polysilicon film, and then the active layer 201 is formed through patterning.
  • doping particles can be injected into both ends of the active layer 201 to form two doped regions, and then a first insulating layer covering the active layer 201 is formed.
  • the gate layer 202 can be formed on the side of the first insulating layer 205 away from the substrate 10 through, but not limited to, an evaporation process or a physical vapor deposition process, and combined with patterning. Further, the gate layer 202 has The orthographic projection on the plane of the source layer 201 can be located within the boundary of the active layer 201.
  • the gate layer 202 can be used as a blocking part, and doping particles can be injected into the part of the active layer 201 beyond the gate layer 202 to promote both sides. In the formation of a doped region, the concentration of this doping can be higher than the concentration of the previous doping.
  • the second insulating layer 206 covering the gate layer 202 can be formed, and then passed through but not limited to an evaporation process or a physical vapor deposition process on the second insulating layer 206, and combined with patterning to form the metal layer 207.
  • the metal layer 207 and the gate layer 202 are arranged opposite to form a capacitor.
  • an interlayer dielectric layer 208 covering the metal layer 207 may be formed, and then two via holes may be formed penetrating the interlayer dielectric layer 208, the second insulating layer 206 and part of the first insulating layer 205, and the two via holes may be connected to the active Both ends of the layer 201 and the side of the interlayer dielectric layer 208 away from the substrate 10 are filled with the material of the source and drain layers in the via holes and extend to the side of the interlayer dielectric layer 208 away from the substrate 10, and the pattern is combined to form the source portion 203 and the drain portion 204.
  • film layers such as a light-emitting layer, a pixel definition layer, and an encapsulation layer may be formed on the side of the interlayer dielectric layer 208 away from the substrate 10 and the side of the source and drain layers away from the substrate 10 .
  • the present application provides a display panel, including: a substrate; a thin film transistor layer located on the substrate, the thin film transistor layer including a plurality of transistors; an auxiliary layer located between the substrate and the thin film transistor layer,
  • the auxiliary layer includes a first auxiliary layer and a second auxiliary layer located at least on a side of the first auxiliary layer close to the substrate.
  • the second auxiliary layer includes a plurality of auxiliary parts. Two adjacent auxiliary parts There is a gap between the parts; wherein the dielectric constant of the constituent material of the first auxiliary layer is smaller than the dielectric constant of the constituent material of the substrate and greater than the dielectric constant of the constituent material of the second auxiliary layer.
  • this application reduces the impact on charge movement in the active layer by arranging a first auxiliary layer with a dielectric constant smaller than that of the substrate, and by arranging a second auxiliary layer with a smaller dielectric constant.
  • the second auxiliary layer includes a plurality of auxiliary parts arranged at intervals, which can further reduce the impact on charge movement in the active layer.

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Abstract

本申请提供了显示面板，包括衬底、位于衬底上的薄膜晶体管层、位于衬底和薄膜晶体管层之间的辅助层，辅助层包括第一辅助层、至少位于第一辅助层靠近衬底的一侧的第二辅助层，第一辅助层的组成材料的介电常数小于衬底的组成材料的介电常数且大于第二辅助层的组成材料的介电常数，第二辅助层包括间隔排布的多个辅助部。

Description

显示面板
技术领域
本申请涉及显示技术领域，尤其涉及显示器件的制造，具体涉及显示面板。
 背景技术
OLED(Organic Light Emitting Diode,有机发光显示)面板的组件结构较简单、生产成本较低、较为节能，且具有可弯曲的特性，应用范围极广。
目前，OLED面板通过柔性基底实现可弯曲的特性，柔性基底中存在的大量可极化电荷极易被极化形成大量的极化电荷，从而对像素电路中的晶体管的有源层产生极化作用，造成晶体管工作的可靠性较低，降低了OLED面板显示画面的质量。
因此，现有的OLED面板中像素电路中的晶体管的可靠性较低，急需改进。
 技术问题
本申请的目的在于提供显示面板，以解决现有的OLED面板中因柔性基底对于像素电路中的晶体管的有源层的极化作用，而造成的晶体管的可靠性较低问题。
 技术解决方案
本申请实施例提供显示面板，包括：
衬底；
薄膜晶体管层，位于所述衬底上，所述薄膜晶体管层包括多个晶体管；
辅助层，位于所述衬底和所述薄膜晶体管层之间，所述辅助层包括第一辅助层、至少位于所述第一辅助层靠近所述衬底的一侧的第二辅助层，所述第二辅助层包括多个辅助部，相邻两所述辅助部之间具有间隙；
其中，所述第一辅助层的组成材料的介电常数小于所述衬底的介电常数，且大于所述第二辅助层的组成材料的介电常数。
 有益效果
本申请提供了显示面板，包括：衬底；薄膜晶体管层，位于所述衬底上，所述薄膜晶体管层包括多个晶体管；辅助层，位于所述衬底和所述薄膜晶体管层之间，所述辅助层包括第一辅助层、至少位于所述第一辅助层靠近所述衬底的一侧的第二辅助层，所述第二辅助层包括多个辅助部，相邻两所述辅助部之间具有间隙；其中，所述第一辅助层的组成材料的介电常数小于所述衬底的组成材料的介电常数，且大于所述第二辅助层的组成材料的介电常数。其中，本申请通过设置介电常数小于所述衬底的介电常数的第一辅助层，减少了对有源层中的电荷移动的影响，以及通过设置介电常数更小的第二辅助层，但第二辅助层包括间隔排布的多个辅助部，可以进一步减少对有源层中的电荷移动的影响。
 附图说明
下面通过附图来对本申请进行进一步说明。需要说明的是，下面描述中的附图仅仅是用于解释说明本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种显示面板的截面示意图。
图2为本申请实施例提供的另一种显示面板的截面示意图。
图3为本申请实施例提供的显示面板的制作方法的流程图。
图4为本申请实施例提供的显示面板的制作方法的场景示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“上”、“下”、“靠近”、“远离”、“两端”等指示的方位或位置关系为基于附图所示的方位或位置关系，例如，“上”只是表面在物体上方，具体指代正上方、斜上方、上表面都可以，只要居于物体水平之上即可；“两端”是指代图中可以体现出的物体的相对的两个位置，所述两个位置可以和物体直接或者间接接触，以上方位或位置关系仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
另外，还需要说明的是，附图提供的仅仅是和本申请关系比较密切的结构和步骤，省略了一些与申请关系不大的细节，目的在于简化附图，使申请点一目了然，而不是表明实际中装置和方法就是和附图一模一样，不作为实际中装置和方法的限制。
本申请提供显示面板，所述显示面板包括但不限于以下实施例以及以下实施例之间的组合。
在一实施例中，如图1和图2所示，所述显示面板100包括：衬底10；薄膜晶体管层，位于所述衬底10上，所述薄膜晶体管层包括多个晶体管20；辅助层，位于所述衬底10和所述薄膜晶体管层之间，所述辅助层包括第一辅助层30、至少位于所述第一辅助层30靠近所述衬底10的一侧的第二辅助层40，所述第二辅助层40包括多个辅助部401，相邻两所述辅助部401之间具有间隙；其中，所述第一辅助层30的组成材料的介电常数小于所述衬底10的组成材料的介电常数，且大于所述第二辅助层40的组成材料的介电常数。
其中，衬底10的组成材料可以包括聚酰亚胺。进一步的，如图1和图2所示，衬底10可以包括第一衬底101、位于第一衬底101靠近薄膜晶体管层的第二衬底102、位于第一衬底101和第二衬底102之间的第一缓冲层103，第一衬底101的组成材料和第二衬底102的组成材料可以包括聚酰亚胺，第一缓冲层103的组成材料可以包括氧化硅、氮化硅中的至少一者，例如采用氧化硅制作的第一缓冲层103具有吸水、保温的作用，可以延长显示面板100的寿命。
具体的，如图1和图2所示，晶体管20可以包括有源层201、位于有源层201远离衬底10的一侧的栅极层202、位于栅极层202远离衬底10的一侧的源漏极层，源漏极层包括与有源层201的一端部相对设置且电性连接的源极部203，与有源层201的一端部相对设置且电性连接的漏极部204。进一步的，显示面板100还包括位于有源层201和栅极层202之间且覆盖有源层201的第一绝缘层205、覆盖于栅极层202远离衬底10的一侧的第二绝缘层206、位于第二绝缘层206远离衬底10的一侧的金属层207、位于金属层207和源漏极层之间且覆盖金属层207的层间介质层208。
其中，有源层201的组成材料可以包括非晶硅、多晶硅中的至少一者，多晶硅可以包括低温多晶硅，进一步的，有源层201的组成材料还可以包括氧化物。可以理解的，例如采用低温多晶硅技术制备有源层201可以具备较高的电子迁移率，这样当晶体管20给对应的像素充电时，可以产生较大的驱动电流，以提高充电速度；例如采用非晶硅或者氧化物制备的有源层201可以具备低漏电流，以防止曝光情况下晶体管20的漏电对信号造成干扰。具体的，例如有源层201的组成材料包括非晶硅时，有源层201中电性连接至源漏极层的两端可以掺杂粒子以形成两个参杂区域，掺杂粒子可以包括磷离子，参杂区域内掺杂粒子的浓度可以根据实际情况设置；例如有源层201的组成材料包括氧化物时，可以避免设置掺杂粒子以形成参杂区域。
进一步的，结合上文论述，如图1和图2所示，源漏极层可以通过贯穿层间介质层208、第二绝缘层206、部分第一绝缘层205的过孔以延伸至电性连接于有源层201，具体的，第一过孔连通于有源层201的一端部远离衬底10的一侧和层间介质层208远离衬底10的一侧，第二过孔连通于有源层201的另一端部远离衬底10的一侧和层间介质层208远离衬底10的一侧，源极部203填充于第一过孔并延伸至层间介质层208远离衬底10的一侧，漏极部204填充于第二过孔并延伸至层间介质层208远离衬底10的一侧。其中，金属层207可以与栅极层202相对设置以形成对应的像素电路中的电容。
具体的，第一绝缘层205的组成材料、第二绝缘层206的组成材料和层间介质层208的组成材料可以包括无机介电材料、有机介电材料中的至少一种，无机介电材料可以为氧化硅、氮化硅或者氮氧化硅，有机介电材料可以为聚酰亚胺系树脂、环氧系树脂或者压克力系树脂材料。具体的，栅极层202的组成材料、金属层207的组成材料和源漏极层的组成材料可以包括金属、金属氧化物、金属氮化物、金属氮氧化物等导电材料中的至少一种，金属可以为铜、铝、钼或者钛。
需要注意的是，结合图1和图2所示，衬底10中存在的大量可极化电荷极易受到外界影响或者显示面板100内部电场影响，被极化形成大量的极化电荷，若未设置辅助层，则衬底10内位于衬底10靠近薄膜晶体管层一侧的大量的极化电荷会对有源层201产生极化作用，造成有源层201中的电荷移动受到影响，降低了晶体管20工作的可靠性。
可以理解的，本实施例中的第一辅助层30的组成材料的介电常数小于衬底10的介电常数，由“介电常数越大，越容易产生极化”这一规律可知，第一辅助层30相对于衬底10被极化的难度较大，因此即使衬底10中形成有大量的极化电荷以及显示面板100内部存在电场影响，位于衬底10和晶体管20之间的第一辅助层30被极化形成的极化电荷的数量还是可以远小于未设置第一辅助层30时衬底10被极化形成的极化电荷的数量，因此有源层201中的电荷移动的影响可以减小，提高了晶体管20工作的可靠性。
进一步的，本实施例中的第二辅助层40的组成材料的介电常数小于第一辅助层30的组成材料的介电常数，同理，根据上文分析，至少位于第一辅助层30靠近衬底10的一侧的第二辅助层40被极化形成的极化电荷的数量还是可以远小于未设置第二辅助层40时第一辅助层30被极化形成的极化电荷的数量，因此有源层201中的电荷移动的影响可以进一步减小，进一步提高了晶体管20工作的可靠性。
本实施例中的通过将第二辅助层40设置为由间隔排列的多个辅助部401构成，可以避免第二辅助层40完全覆盖衬底10，当显示面板100包括位于辅助层下方或者衬底10下方的感光器件、显示面板100为底发光显示器件两者中至少一者情况存在时，第二辅助层40的设置方式可以保证显示面板100的透光率，以避免遮挡较多的光线，提高了显示面板100的亮度、感光器件的工作的可靠性两者中的至少一者。其中，本实施例对于辅助部401的形状和尺寸不作限制。
需要注意的是，第二辅助层40的组成材料的介电常数虽然较小，但是透光率相对于第一辅助层30而言一般较小，即第二辅助层40虽然可以更大地弱化有源层201内的极化现象，但存在透光率较小的劣势；但是结合上文论述，本实施例中，将第二辅助层40设置为由间隔排列的多个辅助部401构成，可以基于“第二辅助层40的组成材料的介电常数较小”这一方面，结合于相邻两辅助部401之间填充组成材料的透光率较大的第一辅助层30，以避免第二辅助层40所处平面的透光率过小。
在一实施例中，所述第一辅助层30填充所述间隙。结合上文论述可知，一方面，本实施例通过设置间隙，且采用透光率较大的第一辅助层30填充间隙可以有效提高显示面板100的透光率，另一方面，基于多个间隙，多个辅助部401无法实现与衬底10重合设置，以至于无法作用于整个衬底10，本实施例通过采用介电常数小于衬底的介电常数的第一辅助层30填充间隙以作用于衬底10，结合上文论述，即第一辅助层30被极化形成的极化电荷的数量还是可以远小于未设置第一辅助层30时衬底10被极化形成的极化电荷的数量，可以在第二辅助层40作用于衬底10的基础上，通过第一辅助层30进一步减小对有源层201中的电荷移动的影响。
在一实施例中，所述第二辅助层40为导体。可以理解的，一方面，导体的介电常数接近于0，结合上文论述，可以极大地降低有源层201中的电荷移动的影响；另一方面，导体的电阻率很小且易于传导电流，导体中存在大量可自由移动的带电粒子，可以吸引介电常数相对较大的第一辅助层30被极化形成的极化电荷，以均匀化带正电的极化电荷、带负电的极化电荷的分布，进一步还可以使得带正电的极化电荷、带负电的极化电荷复合以减少极化电荷的数量，减弱极化的方向性，同样极大地降低有源层201中的电荷移动的影响。
其中，第二辅助层40的组成材料可以包括金属导体，由于金属导体的电导率通常比其他导体材料的大，且金属导体的电阻率一般随温度降低而减小，在极低温度下，某些金属导体与合金的电阻率将消失而转化为“超导体”，可以进一步降低有源层201中的电荷移动的影响。具体的，本实施例中的金属导体可以为但不限于氧化铟锡、银单质、钼单质、铝单质、石墨烯、超导金属、超导合金，可以理解的，以上列举的金属导体相对于其它的金属导体，具有较高的透光率以避免较多地降低显示面板100的透光率，且具有较小的弹性模量以满足显示面板100所需的应力、应变需求。
在一实施例中，如图1和图2所示，多个所述辅助部401均匀排布，并与所述衬底表面直接接触。可以理解的，结合上文论述，一方面，第二辅助层40被极化形成的极化电荷的数量极少，且第二辅助层40靠近有源层201而设置，即每一辅助部401可以削弱衬底10中相应位置以及第一辅助层30中相应位置对于有源层201的极化作用，因此均匀排布的多个辅助部401可以均匀化有源层201中电荷移动的影响被削弱的区域，进一步优化有源层201中电荷移动的影响削弱的方式；另一方面，均匀排布的多个辅助部401可以均匀化对应的多个间隙的排布，以均匀化显示面板100中各个区域的透光率，优化对于显示面板100的透光率的提高方式。
进一步的，当第二辅助层40为导体时，本实施例中均匀排布的多个辅助部401也可以均匀化第二辅助层40中用于吸引第一辅助层30的极化电荷的区域，进一步均匀化第一辅助层30的电荷分布，同时也可以进一步均匀化第二辅助层40中用于复合第一辅助层30中的极化电荷的区域，以进一步减弱第一辅助层30极化的方向性，因此，本实施例可以进一步极大地降低有源层201中的电荷移动的影响。
在一实施例中，所述第一辅助层30覆盖多个所述辅助部401靠近所述薄膜晶体管层的一侧。具体的，本实施例中的多个辅助部401靠近第一辅助层30的一侧可以包裹于第一辅助层30之内，使得在多个辅助部401形成于衬底10之上的基础上，且当辅助部401的表面积一定的情况下，可以使得辅助部401未接触于衬底10的其它表面均接触于第一辅助层30而充分作用于第一辅助层30中的可极化电荷，以减少极化电荷的数量，从而减少对于有源层201中电荷移动的影响。进一步的，结合上文论述，第一辅助层30可以覆盖多个所述辅助部401并填充相邻两辅助部401之间的间隙，且第一辅助层30还与衬底10表面直接接触。
在一实施例中，如图1和图2所示，所述辅助部401靠近所述第一辅助层30的一侧包括凸起部、凹陷部中的至少一者。具体的，所述辅助部401靠近所述第一辅助层30的一侧呈现为不平坦的状态，且结合上文论述，第一辅助层30靠近第二辅助层40的一侧的形状与多个所述辅助部401靠近第一辅助层30的一侧的形状相匹配，即第一辅助层30靠近第二辅助层40的一侧也包括凸起部、凹陷部中的至少一者。可以理解的，本实施例中的辅助部401靠近第一辅助层30的一侧呈凸出状，且两者靠近彼此的一侧的形状相匹配，即包括极少数的极化电荷的第二辅助层40与第一辅助层30接触于第一辅助层30的面积较大，可以作用第一辅助层30中的电荷的比例较多，对应的，第一辅助层30中可被衬底10极化的电荷的数量较少，可以减少对于有源层201的极化作用。
进一步的，当第二辅助层40为导体时，本实施例中具有较大相对设置的面积的第二辅助层40与第一辅助层30，增大了第二辅助层40中用于吸引第一辅助层30的极化电荷的区域面积，进一步增大了对于第一辅助层30的电荷分布的均匀化作用，同时也增大了第二辅助层40中用于复合第一辅助层30中的极化电荷的区域面积，以进一步减弱第一辅助层30极化的方向性，因此，本实施例可以进一步极大地降低有源层201中的电荷移动的影响。
其中，所述第一辅助层30对应所述辅助部401处靠近所述薄膜晶体管层的表面到所述衬底10表面的第一距离，大于所述第一辅助层30对应所述间隙处靠近所述薄膜晶体管层的表面到所述衬底10表面的第二距离。可以理解的，结合上文论述，第一辅助层30上还设有多个晶体管，本实施例中限定第一距离大于第二距离，以对第一辅助层30靠近薄膜晶体管层的一侧进行了平坦化处理，可以便于后期形成稳固的多个晶体管，提高制程的良率，进一步的，第一辅助层30靠近薄膜晶体管层的一侧可以平行于衬底10。
在一实施例中，所述第一辅助层30的厚度小于10埃。可以理解的，由于第一辅助层30的作用为降低衬底10中的极化电荷对有源层201中电荷移动的影响，而本不希望第一辅助层30的厚度较大，故本实施例中限定第一辅助层30的厚度小于10埃，可以在维持第一辅助层30的作用的同时，避免第一辅助层30的厚度过大而增加显示面板100的厚度或者影响显示面板100的应力。当然，辅助部401的厚度也可以大于第一辅助层30的厚度。
在一实施例中，如图2所示，所述第二辅助层40还位于所述第一辅助层30远离所述衬底10的一侧，位于所述第一辅助层30远离所述衬底10的一侧的所述第二辅助层40中的多个所述辅助部401、位于所述第一辅助层30靠近所述衬底10的一侧的另一所述第二辅助层40中的多个所述辅助部401一一对应，且一一对应的两所述辅助部401相对设置。
具体的，形成第一辅助层30后，可以通过但不限于黄光制程以形成多个凹槽，多个凹槽可以与位于第一辅助层30靠近衬底10的一侧的第二辅助层40中的多个辅助部401一一对应，再于多个凹槽内通过但不限于物理气相沉积的方式形成多个辅助部401，以构成位于第一辅助层30靠近衬底10的一侧的另一第二辅助层40。可以理解的，在第一辅助层30的厚度大于靠近衬底10的一侧的第二辅助层40的厚度时，可以形成远离衬底10的一侧的多个辅助部401，以进一步作用于第一辅助层30中的极化电荷，从而进一步减小对于有源层201中电荷移动的影响，同时由于一一对应的两所述辅助部401相对设置，也避免了额外减小显示面板100的透光率。
在一实施例中，所述第一辅助层30的组成材料包括极化材料。其中，极化可以理解为电流的移动而最终导致电位偏离电极开路电位的现象，此处的“极化材料”可以理解为具有极化特性的材料，例如可以对衬底10产生极化作用，也可以第一辅助层30本身被极化。具体的，第一辅助层30的组成材料可以包括非晶硅。其中，非晶硅与衬底10之间的吸附力较大，有利于第一辅助层30的形成，提高了辅助层和衬底10之间的稳固性。具体的，非晶硅可以由天然的硅的氧化物制取，成本较低，且非晶硅为半导体，可以实现降低衬底10中的极化电荷对于有源层201的电荷移动的影响的作用。
在一实施例中，如图1和图2所示，所述显示面板100还包括：缓冲层50，位于所述辅助层靠近所述薄膜晶体管层的一侧，所述缓冲层50的组成材料包括氮化硅、氧化硅中的至少一者。需要注意的是，采用化学气相沉积工艺、物理气相沉积工艺形成的辅助层靠近薄膜晶体管层的一侧会较为粗糙，本实施例中可以采用但不限于化学气相沉积工艺形成具有一定厚度的缓冲层50，即可以理解为缓冲层50靠近薄膜晶体管层的一侧会较为平坦，有利于形成薄膜晶体管层。
其中，采用氮化硅、氧化硅中的至少一者形成的缓冲层50可以具有吸水的作用以防止外界水汽浸入以损伤发光器件，也可以具有保温的作用以防止制程工艺中强烈的温度变化以降低有源层201的可靠性。具体的，缓冲层50可以包括第二缓冲层501、位于第二缓冲层501上的第三缓冲层502，第二缓冲层501、第三缓冲层502中的一者的组成材料可以包括氮氧化硅、第二缓冲层501、第三缓冲层502中的另一者的组成材料可以包括氧化硅；再进一步的，缓冲层50还可以包括采用氮氧化硅制作的第三缓冲层。进一步的，缓冲层50和薄膜晶体管层之间还可以设置介电层，介电层用于绝缘有源层201和其它膜层，介电层的组成材料可以参考上文关于缓冲层50的组成材料的相关说明。
本申请还提供显示面板的制作方法，所述方法包括但不限于以下实施例以及以下实施例之间的组合。
在一实施例中，结合图3和图4所示，所述显示面板的制作方法包括但不限于如下步骤。
S10，提供一衬底。
具体的，结合图1至图4所示，衬底10可以包括第一衬底101、位于第一衬底101靠近薄膜晶体管层的第二衬底102、位于第一衬底101和第二衬底102之间的第一缓冲层103，第一衬底101的组成材料和第二衬底102的组成材料可以包括聚酰亚胺，第一缓冲层103的组成材料可以包括氧化硅、氮化硅中的至少一者，例如采用氧化硅制作的第一缓冲层103具有吸水、保温的作用，可以延长显示面板100的寿命。
S20，在所述衬底上形成辅助层，所述辅助层包括第一辅助层、至少位于所述第一辅助层靠近所述衬底的一侧的第二辅助层，所述第二辅助层包括多个辅助部，相邻两所述辅助部之间具有间隙，所述第一辅助层的组成材料的介电常数小于所述衬底的介电常数，且大于所述第二辅助层的组成材料的介电常数，所述第一辅助层的透光率大于所述第二辅助层的透光率。
需要注意的是，结合上文论述，若未设置辅助层，衬底10中大量可极化电荷极被极化形成大量的极化电荷后，会对有源层201产生极化作用，造成有源层201中的电荷移动受到影响。
其中，结合图1至图4所示，第二辅助层40至少位于第一辅助层30靠近衬底10的一侧，即可以在形成第一辅助层30之前形成第二辅助层40。具体的，可以至少在第二衬底102上通过物理气相沉积的方式形成第二辅助层40，例如将第二辅助层40的组成材料的材料源表面气化成气态原子或分子，或部分电离成离子，并通过等离子体过程，在第二衬底102表面沉积以形成第二辅助层40。需要注意的是，用于沉积第二辅助层40的能量可以较小，以避免第二辅助层40的组成材料溅入至衬底10内，甚至造成衬底10翘起。
在此基础上，进一步的，可以通过具有多个开口的掩模版，结合物理气相沉积的方式以在第二衬底102表面沉积形成与多个开口一一对应的多个辅助部401，以构成第二辅助层40。具体的，此处对多个辅助部401的数量、排布方式不作限制，可以参考上文关于辅助部401的相关描述。
其中，结合图1至图4所示，在形成第二辅助层40之后，可以通过化学沉积的方式于第二辅助层40上形成第一辅助层30，第一辅助层30可以覆盖第二辅助层40的部分或者全部。具体的，如图1、图2和图4所示，此处以第二辅助层40包括间隔设置的多个辅助部401为例进行说明，可以与衬底10和多个辅助部401上沉积第一辅助层30的组成材料，以形成第一辅助层30。其中，第一辅助层30的厚度可以小于10埃。
可以理解的，本实施例中的第一辅助层30的组成材料的介电常数小于衬底10的介电常数，由“介电常数越大，越容易产生极化”这一规律可知，第一辅助层30相对于衬底10被极化的难度较大，因此即使衬底10中形成有大量的极化电荷以及显示面板100内部存在电场影响，位于衬底10和晶体管20之间的第一辅助层30被极化形成的极化电荷的数量还是可以远小于未设置第一辅助层30时衬底10被极化形成的极化电荷的数量，因此有源层201中的电荷移动的影响可以减小，提高了晶体管20工作的可靠性。
进一步的，本实施例中的第二辅助层40的组成材料的介电常数小于第一辅助层30的组成材料的介电常数，同理，根据上文分析，至少位于第一辅助层30靠近衬底10的一侧的第二辅助层40被极化形成的极化电荷的数量还是可以远小于未设置第二辅助层40时第一辅助层30被极化形成的极化电荷的数量，因此有源层201中的电荷移动的影响可以进一步减小，进一步提高了晶体管20工作的可靠性。
需要注意的是，第二辅助层40的介电常数虽然较小，但是透光率相对于第一辅助层30而言较大，即第二辅助层40虽然可以更大地弱化有源层201内的极化现象，但存在透光率较小的劣势。可以理解的，本实施例中的通过将第二辅助层40设置为由间隔排列的多个辅助部401构成，可以避免第二辅助层40完全覆盖于衬底10，当显示面板100包括位于辅助层下方或者衬底10下方的感光器件、显示面板100为底发光显示器件两者中至少一者情况存在时，第二辅助层40的设置方式可以保证显示面板100的透光率，以避免遮挡较多的光线，提高了显示面板100的亮度、感光器件的工作的可靠性两者中的至少一者。其中，本实施例对于辅助部401的形状和尺寸不作限制。
S30，在所述辅助层远离所述衬底的一侧形成薄膜晶体管层，所述薄膜晶体管层包括多个晶体管。
其中，结合图1、图2和图4所示，晶体管20可以包括有源层201、位于有源层201远离衬底10的一侧的栅极层202、位于栅极层202远离衬底10的一侧的源漏极层，源漏极层包括与有源层201的一端部相对设置且电性连接的源极部203，与有源层201的一端部相对设置且电性连接的漏极部204。进一步的，显示面板100还包括位于有源层201和栅极层202之间且覆盖有源层201的第一绝缘层205、覆盖于栅极层202远离衬底10的一侧的第二绝缘层206、位于第二绝缘层206远离衬底10的一侧的金属层207、位于金属层207和源漏极层之间且覆盖金属层207的层间介质层208。具体的，关于晶体管20中具体结构的相关描述可以参考上文中关于晶体管20中具体结构的相关描述。
进一步的，结合图1、图2和图4以及上文论述，在形成薄膜晶体管层之前，可以于辅助层远离衬底10的一侧形成缓冲层50，例如可以先于辅助层远离衬底10的一侧形成第二缓冲层501、再于第二缓冲层501远离衬底10的一侧形成第三缓冲层502，第二缓冲层501的组成材料和第三缓冲层502的组成材料可以参考上文的相关描述。
具体的，例如有源层201的组成材料包括非晶硅时，可以直接于缓冲层50远离衬底10的一侧采用非晶硅材料形成有源层201，当然，也可以采用准分子激光退火工艺处理非晶硅薄膜以形成多晶硅薄膜，再通过图案化形成有源层201。具体的，对于采用非晶硅制作的有源层201而言，可以向有源层201的两端注入掺杂粒子以形成两个参杂区域后，再形成覆盖有源层201的第一绝缘层205；也可以先形成覆盖有源层201的第一绝缘层205，再通过向第一绝缘层205中注入掺杂粒子以间接流入至有源层201的两端以形成两个参杂区域。具体的，可以于第一绝缘层205远离衬底10的一侧通过但不限于蒸镀工艺或者物理气相沉积工艺，并且结合图案化以形成栅极层202，进一步的，栅极层202在有源层201所在平面上的正投影可以位于有源层201的边界之内，可以以栅极层202为阻挡部，向有源层201超出于栅极层202的部分注入掺杂粒子以促进两个参杂区域的形成，本次掺杂的浓度可以高于前一次掺杂的浓度。具体的，可以形成覆盖栅极层202的第二绝缘层206，再于第二绝缘层206上通过但不限于蒸镀工艺或者物理气相沉积工艺，并且结合图案化以形成金属层207，金属层207和栅极层202相对设置以形成电容。具体的，可以形成覆盖金属层207的层间介质层208，再形成贯穿于层间介质层208、第二绝缘层206和部分第一绝缘层205的两过孔，两过孔连通于有源层201的两端和层间介质层208远离衬底10的一侧，再于过孔内填充源漏极层的组成材料并延伸至层间介质层208远离衬底10的一侧，结合图案化以形成源极部203和漏极部204。再进一步的，可以于层间介质层208远离衬底10的一侧、源漏极层远离衬底10的一侧形成发光层、像素定义层、封装层等膜层。
本申请提供了显示面板，包括：衬底；薄膜晶体管层，位于所述衬底上，所述薄膜晶体管层包括多个晶体管；辅助层，位于所述衬底和所述薄膜晶体管层之间，所述辅助层包括第一辅助层、至少位于所述第一辅助层靠近所述衬底的一侧的第二辅助层，所述第二辅助层包括多个辅助部，相邻两所述辅助部之间具有间隙；其中，所述第一辅助层的组成材料的介电常数小于所述衬底的组成材料的介电常数，且大于所述第二辅助层的组成材料的介电常数。其中，本申请通过设置介电常数小于所述衬底的介电常数的第一辅助层，减少了对有源层中的电荷移动的影响，以及通过设置介电常数更小的第二辅助层，但第二辅助层包括间隔排布的多个辅助部，可以进一步减少对有源层中的电荷移动的影响。
以上对本申请实施例所提供的显示面板的结构进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其中，包括：
    衬底；
    薄膜晶体管层，位于所述衬底上，所述薄膜晶体管层包括多个晶体管；
    辅助层，位于所述衬底和所述薄膜晶体管层之间，所述辅助层包括第一辅助层、至少位于所述第一辅助层靠近所述衬底的一侧的第二辅助层，所述第二辅助层包括多个辅助部，相邻两所述辅助部之间具有间隙；
    其中，所述第一辅助层的组成材料的介电常数小于所述衬底的组成材料介电常数，且大于所述第二辅助层的组成材料的介电常数；
    其中，所述第一辅助层包括极化材料，所述第二辅助层包括导电材料；
    其中，多个所述辅助部在所述衬底上均匀排布，并与所述衬底表面直接接触。
  2. 如权利要求1所述的显示面板，其中，所述第一辅助层的透光率大于所述辅助部的透光率。
  3. 如权利要求1所述的显示面板，其中，所述第一辅助层包括非晶硅，所述第二辅助层包括金属导体。
  4. 如权利要求1所述的显示面板，其中，所述第一辅助层覆盖多个所述辅助部并填充相邻两所述辅助部之间的间隙，且所述第一辅助层还与所述衬底表面直接接触。
  5. 如权利要求4所述的显示面板，其中，所述第一辅助层的厚度小于或等于10埃。
  6. 如权利要求4所述的显示面板，其中，所述辅助部靠近所述第一辅助层的一侧包括凸起部、凹陷部中的至少一者。
  7. 如权利要求4所述的显示面板，其中，所述第一辅助层对应所述辅助部处靠近所述薄膜晶体管层的表面到所述衬底表面的第一距离，大于所述第一辅助层对应所述间隙处靠近所述薄膜晶体管层的表面到所述衬底表面的第二距离。
  8. 如权利要求1所述的显示面板，其中，所述第二辅助层还位于所述第一辅助层远离所述衬底的一侧，位于所述第一辅助层远离所述衬底的一侧的所述第二辅助层中的多个所述辅助部、位于所述第一辅助层靠近所述衬底的一侧的另一所述第二辅助层中的多个所述辅助部一一对应，且一一对应的两所述辅助部相对设置。
  9. 一种显示面板，其中，包括：
    衬底；
    薄膜晶体管层，位于所述衬底上，所述薄膜晶体管层包括多个晶体管；
    辅助层，位于所述衬底和所述薄膜晶体管层之间，所述辅助层包括第一辅助层、至少位于所述第一辅助层靠近所述衬底的一侧的第二辅助层，所述第二辅助层包括多个辅助部，相邻两所述辅助部之间具有间隙；
    其中，所述第一辅助层的组成材料的介电常数小于所述衬底的组成材料介电常数，且大于所述第二辅助层的组成材料的介电常数；
    其中，所述第一辅助层包括极化材料，所述第二辅助层包括导电材料；
    其中，所述第二辅助层还位于所述第一辅助层远离所述衬底的一侧，位于所述第一辅助层远离所述衬底的一侧的所述第二辅助层中的多个所述辅助部、位于所述第一辅助层靠近所述衬底的一侧的另一所述第二辅助层中的多个所述辅助部一一对应，且一一对应的两所述辅助部相对设置。
  10. 如权利要求9所述的显示面板，其中，所述第一辅助层的透光率大于所述辅助部的透光率。
  11. 一种显示面板，其中，包括：
    衬底；
    薄膜晶体管层，位于所述衬底上，所述薄膜晶体管层包括多个晶体管；
    辅助层，位于所述衬底和所述薄膜晶体管层之间，所述辅助层包括第一辅助层、至少位于所述第一辅助层靠近所述衬底的一侧的第二辅助层，所述第二辅助层包括多个辅助部，相邻两所述辅助部之间具有间隙；
    其中，所述第一辅助层的组成材料的介电常数小于所述衬底的组成材料介电常数，且大于所述第二辅助层的组成材料的介电常数。
  12. 如权利要求11所述的显示面板，其中，所述第一辅助层包括极化材料，所述第二辅助层包括导电材料。
  13. 如权利要求12所述的显示面板，其中，所述第一辅助层的透光率大于所述辅助部的透光率。
  14. 如权利要求12所述的显示面板，其中，所述第一辅助层包括非晶硅，所述第二辅助层包括金属导体。
  15. 如权利要求11所述的显示面板，其中，多个所述辅助部在所述衬底上均匀排布，并与所述衬底表面直接接触。
  16. 如权利要求15所述的显示面板，其中，所述第一辅助层覆盖多个所述辅助部并填充相邻两所述辅助部之间的间隙，且所述第一辅助层还与所述衬底表面直接接触。
  17. 如权利要求16所述的显示面板，其中，所述第一辅助层的厚度小于或等于10埃。
  18. 如权利要求16所述的显示面板，其中，所述辅助部靠近所述第一辅助层的一侧包括凸起部、凹陷部中的至少一者。
  19. 如权利要求16所述的显示面板，其中，所述第一辅助层对应所述辅助部处靠近所述薄膜晶体管层的表面到所述衬底表面的第一距离，大于所述第一辅助层对应所述间隙处靠近所述薄膜晶体管层的表面到所述衬底表面的第二距离。
  20. 如权利要求11所述的显示面板，其中，所述第二辅助层还位于所述第一辅助层远离所述衬底的一侧，位于所述第一辅助层远离所述衬底的一侧的所述第二辅助层中的多个所述辅助部、位于所述第一辅助层靠近所述衬底的一侧的另一所述第二辅助层中的多个所述辅助部一一对应，且一一对应的两所述辅助部相对设置。
PCT/CN2022/088551 2022-04-07 2022-04-22 显示面板 WO2023193311A1 (zh)

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CN108493198A (zh) * 2018-04-11 2018-09-04 京东方科技集团股份有限公司 阵列基板及其制作方法、有机发光二极管显示装置
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CN112002712A (zh) * 2020-08-24 2020-11-27 武汉天马微电子有限公司 一种显示面板、显示装置及制作方法
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