WO2023178775A1 - 时钟信号调理电路、方法及显示面板、显示设备 - Google Patents

时钟信号调理电路、方法及显示面板、显示设备 Download PDF

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Publication number
WO2023178775A1
WO2023178775A1 PCT/CN2022/087609 CN2022087609W WO2023178775A1 WO 2023178775 A1 WO2023178775 A1 WO 2023178775A1 CN 2022087609 W CN2022087609 W CN 2022087609W WO 2023178775 A1 WO2023178775 A1 WO 2023178775A1
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Prior art keywords
clock signal
flip
flop
circuit
output terminal
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PCT/CN2022/087609
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English (en)
French (fr)
Inventor
钟钊贤
Original Assignee
惠州华星光电显示有限公司
Tcl华星光电技术有限公司
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Priority to US17/756,663 priority Critical patent/US20240161711A1/en
Publication of WO2023178775A1 publication Critical patent/WO2023178775A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of display processing technology, and in particular to a clock signal conditioning circuit, method, display panel, and display device.
  • LCD panels are widely used in various consumer electronics such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers due to their advantages of high image quality, power saving, thin body, and wide range of applications. products, becoming the mainstream in display panels.
  • the driving of horizontal scanning lines of active liquid crystal display panels is mainly completed by the IC (Integrated Circuit, integrated circuit) external to the panel.
  • the external IC can control the step-by-step charging and discharging of horizontal scanning lines at all levels.
  • the GOA (Gate On Array) technology uses the TFT (Thin Film Transistor, thin film transistor) liquid crystal display array process to fabricate the Gate line scanning driving signal circuit on the array substrate, thereby realizing the driving method of Gate progressive scanning. Therefore, it can Using the original process of the liquid crystal display panel, the driving circuit of the horizontal scanning line is fabricated on the substrate around the display area.
  • GOA technology can reduce the bonding process of external ICs, improve production capacity and reduce product costs, and make LCD panels more suitable for producing narrow-frame or frame-less display products.
  • GOA level transmission is used as a line scan driver.
  • multiple CK clock signals are set as signals to start line scan, if one of the multiple CK clock signals has no signal, that is, The abnormal output condition causes the GOA level to transmit an abnormality, and then displays an abnormality.
  • a clock signal conditioning circuit including:
  • the input end of the signal conversion circuit is used to connect to the N+1th clock signal output end, the output end of the signal conversion circuit is used to output the converted electrical signal; the N+1th clock signal output end is used to connect to the N+1th clock signal output end N+1 level GOA drive circuit;
  • the delay processing circuit is configured to obtain the converted electrical signal transmitted by the signal conversion circuit; the delay processing circuit is also configured to receive the third electrical signal when the voltage amplitude of the converted electrical signal falls into the conduction threshold range.
  • the Nth clock signal is transmitted from the N clock signal output terminals, and based on the preset interval clock signal, the Nth clock signal is delayed to obtain a delayed clock signal, and the delayed clock signal is transmitted to the Nth +1-level GOA drive circuit; the timing of the delayed clock signal is the same as the timing of the N+1 clock signal output by the N+1 clock signal output terminal.
  • a clock signal conditioning method includes the following steps:
  • the Nth clock signal transmitted from the Nth clock signal output terminal is received, and the Nth clock signal is delayed based on the preset interval clock signal. time processing to obtain the delayed clock signal;
  • the delayed clock signal is transmitted to the N+1th stage GOA driving circuit; the timing of the delayed clock signal is the same as the timing of the N+1th clock signal output by the N+1th clock signal output terminal.
  • a display panel includes a pixel unit, a GOA circuit and a clock signal conditioning circuit; the clock signal conditioning circuit is connected to the GOA circuit, and the GOA circuit is connected to the pixel unit;
  • the clock signal conditioning circuit includes:
  • the input end of the signal conversion circuit is used to connect to the N+1th clock signal output end, the output end of the signal conversion circuit is used to output the converted electrical signal; the N+1th clock signal output end is used to connect to the N+1th clock signal output end N+1 level GOA drive circuit;
  • the delay processing circuit is configured to obtain the converted electrical signal transmitted by the signal conversion circuit; the delay processing circuit is also configured to receive the third electrical signal when the voltage amplitude of the converted electrical signal falls into the conduction threshold range.
  • the Nth clock signal is transmitted from the N clock signal output terminals, and based on the preset interval clock signal, the Nth clock signal is delayed to obtain a delayed clock signal, and the delayed clock signal is transmitted to the Nth +1-level GOA drive circuit; the timing of the delayed clock signal is the same as the timing of the N+1 clock signal output by the N+1 clock signal output terminal.
  • a display device including a display panel
  • the display panel includes a pixel unit, a GOA circuit and a clock signal conditioning circuit; the clock signal conditioning circuit is connected to the GOA circuit, and the GOA circuit is connected to the pixel unit;
  • the clock signal conditioning circuit includes:
  • the input end of the signal conversion circuit is used to connect to the N+1th clock signal output end, the output end of the signal conversion circuit is used to output the converted electrical signal; the N+1th clock signal output end is used to connect to the N+1th clock signal output end N+1 level GOA drive circuit;
  • the delay processing circuit is configured to obtain the converted electrical signal transmitted by the signal conversion circuit; the delay processing circuit is also configured to receive the third electrical signal when the voltage amplitude of the converted electrical signal falls into the conduction threshold range.
  • the Nth clock signal is transmitted from the N clock signal output terminals, and based on the preset interval clock signal, the Nth clock signal is delayed to obtain a delayed clock signal, and the delayed clock signal is transmitted to the Nth +1-level GOA drive circuit; the timing of the delayed clock signal is the same as the timing of the N+1 clock signal output by the N+1 clock signal output terminal.
  • the input terminal of the signal conversion circuit is used to connect to the N+1th clock signal output terminal, and the output terminal of the signal conversion circuit is used to output the converted electrical signal; the N+1th clock signal output The terminal is used to connect the N+1th level GOA drive circuit; the delay processing circuit is configured to obtain the converted electrical signal transmitted by the signal conversion circuit; the delay processing circuit is also configured so that the voltage amplitude of the converted electrical signal falls into Within the conduction threshold range, the Nth clock signal transmitted from the Nth clock signal output terminal is received, and based on the preset interval clock signal, the Nth clock signal is delayed to obtain a delayed clock signal, and The delayed clock signal is transmitted to the N+1th stage GOA drive circuit, and the timing of the delayed clock signal is the same as the timing of the N+1th clock signal output by the N+1th clock signal output terminal, and then the stage of the GOA circuit It is said that there will be no abnormality due to no signal output from the N+1 level GOA drive circuit, which enhances the display stability.
  • This application uses a delay processing circuit to detect the voltage amplitude of the converted electrical signal transmitted by the signal conversion circuit.
  • the voltage amplitude of the converted electrical signal reaches the conduction threshold, it is determined that the output of the N+1 clock signal output terminal is abnormal. , that is, there is no signal output at the N+1th clock signal output terminal, then the Nth clock signal that controls the output of the Nth clock signal output terminal will be output in the same timing sequence as the normal N+1th clock signal after delay processing.
  • the same delayed clock signal is connected to the N+1 level GOA drive circuit to avoid the problem that when a CK clock signal has an abnormal condition of no signal, the GOA level transmission will be abnormal, and then the abnormal display will occur. , enhances display stability and improves product quality.
  • FIG. 1 is a first structural schematic diagram of a clock signal conditioning circuit in an embodiment of the present application.
  • FIG. 2 is a second structural schematic diagram of a clock signal conditioning circuit in an embodiment of the present application.
  • FIG. 3 is a third structural schematic diagram of the clock signal conditioning circuit in the embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a clock signal conditioning method in an embodiment of the present application.
  • the clock signal conditioning circuit 10 includes a signal conversion circuit 110 and a delay processing circuit 120.
  • the input terminal of the signal conversion circuit 110 is used to connect to the N+1th clock signal output terminal, the output terminal of the signal conversion circuit 110 is used to output the converted electrical signal; the N+1th clock signal output terminal is used to connect to the N+th clock signal output terminal.
  • 1-level GOA driving circuit the delay processing circuit 120 is configured to obtain the converted electrical signal transmitted by the signal conversion circuit 110; the delay processing circuit 120 is also configured so that the voltage amplitude of the converted electrical signal falls into the conduction threshold range
  • the Nth clock signal transmitted from the Nth clock signal output terminal is received, and based on the preset interval clock signal, the Nth clock signal is delayed to obtain a delayed clock signal, and the delayed clock signal is Transmitted to the N+1th level GOA drive circuit; the timing of the delayed clock signal is the same as the timing of the N+1th clock signal output by the N+1th clock signal output terminal.
  • the GOA circuit may include multiple GOA drive circuits.
  • the N+1th GOA circuit when the N+1th GOA circuit is connected to the corresponding clock signal, it can be used to scan and drive the corresponding pixel unit to work.
  • the N+1th GOA circuit is connected to the corresponding clock signal.
  • the corresponding clock signal or delayed clock signal When the N+1 clock signal or delayed clock signal is input, the corresponding pixel unit can be scanned and driven normally. It should be noted that N is a natural number.
  • the converted electrical signal may be a level signal, and the signal conversion circuit 110 may be used to convert the incoming clock signal into a level signal. For example, when the N+1th clock signal output terminal outputs the N+1th clock signal, when the signal conversion circuit 110 receives the N+1th clock signal, the signal conversion circuit 110 outputs a high level signal; when the N+th When there is no signal output from one clock signal output terminal, the signal conversion circuit 110 outputs a low-level signal.
  • the delay processing circuit 120 can be used to obtain the converted electrical signal transmitted by the signal conversion circuit 110, and perform judgment processing on the obtained converted electrical signal. For example, the delay processing circuit 120 can compare the converted electrical signal with a preset conductor.
  • the delay processing circuit 120 If the voltage amplitude of the converted electrical signal is not within the conduction threshold range, it is determined that the converted signal received by the delay processing circuit 120 is a high-level signal, and the Nth clock signal is turned off.
  • the delay processing circuit 120 has no output, and the N+1th clock signal output terminal transmits the N+1th clock signal to the N+1th GOA drive circuit normally. .
  • the delay processing circuit 120 compares the converted electrical signal with a preset conduction threshold. If the voltage amplitude of the converted electrical signal falls within the conduction threshold range, it determines that the converted signal received by the delay processing circuit 120 is a low-level signal, turning on the signal transmission channel between the Nth clock signal output terminal and the delay processing circuit 120, and then the delay processing circuit 120 receives the Nth clock signal, and pairs the clock signals based on the preset interval.
  • the timing of the delayed clock signal after delay processing is the same as the timing of the N+1th clock signal output by the N+1th clock signal output terminal, and then the delayed clock signal is
  • the clock signal is transmitted to the N+1-level GOA drive circuit, so that the N+1-level GOA drive circuit works normally, and avoids an abnormal situation of no signal output due to a CK clock signal, causing an abnormality in the GOA level transmission, and then displaying An unusual problem occurred.
  • the input terminal of the signal conversion circuit 110 is used to connect the N+1th clock signal output terminal, and the output terminal of the signal conversion circuit 110 is used to output the converted electrical signal; the N+1th clock signal output The terminal is used to connect the N+1th level GOA driving circuit; the delay processing circuit 120 is configured to obtain the converted electrical signal transmitted by the signal conversion circuit 110; the delay processing circuit 120 is also configured to calculate the voltage amplitude of the converted electrical signal.
  • the Nth clock signal transmitted from the Nth clock signal output terminal is received, and based on the preset interval clock signal, the Nth clock signal is delayed to obtain a delayed clock signal.
  • the delay processing circuit 120 detects the voltage amplitude of the converted electrical signal transmitted by the signal conversion circuit 110. When the voltage amplitude of the converted electrical signal falls within the conduction threshold range, the N+1 clock signal output terminal is determined.
  • the N clock signal that controls the output of the N clock signal output terminal will be output with the normal N+1 clock signal after delay processing.
  • the delayed clock signal with the same timing is connected to the N+1-level GOA drive circuit to avoid that when a CK clock signal has an abnormal condition of no signal, causing an abnormality in the GOA level transmission, and then displaying an abnormality. problems, enhanced display stability, and improved product quality.
  • the delay processing circuit 120 includes a switch circuit 122 and a delay circuit 124 .
  • the control end of the switch circuit 122 is used to receive the converted electrical signal, and the input end of the switch circuit 122 is used to connect the Nth clock signal output end; the first input end of the delay circuit 124 is connected to the output end of the switch circuit 122, delaying The second input terminal of the circuit 124 is used to input and access the preset interval clock signal; the output terminal of the delay circuit 124 is used to connect to the N+1-th level GOA driving circuit.
  • the voltage amplitude of the converted electrical signal falls into the conduction threshold range of the switch circuit 122, so that the delay circuit 124 receives the Nth clock signal output terminal.
  • the Nth clock signal is transmitted, and the Nth clock signal is delayed based on the interval clock signal to obtain a delayed clock signal, and the delayed clock signal is transmitted to the N+1-th level GOA driving circuit.
  • the switch circuit 122 can control the signal path from the input end to the output end of the switch circuit 122 according to the voltage amplitude of the received converted electrical signal. For example, when the voltage amplitude of the converted electrical signal received by the switch circuit 122 falls within the conduction threshold range of the switch circuit 122, it is determined that the N+1 clock signal output terminal has no signal output, and the input terminal of the switch circuit 122 is turned on. The signal path between the Nth clock signal output terminal and the delay circuit 124 is to conduct the signal path between the Nth clock signal output terminal and the delay circuit 124, and then the Nth clock signal output terminal transmits the Nth clock signal to the Nth clock signal through the switch circuit 122.
  • the delay circuit 124 allows the delay circuit 124 to receive the Nth clock signal and perform delay processing on the Nth clock signal based on the interval clock signal to obtain the delayed clock signal and transmit it to the N+1 level GOA drive circuit Delaying the clock signal allows the N+1 level GOA drive circuit to work normally, and avoids the problem of abnormal GOA level transmission and subsequent display abnormality due to an abnormal situation of no signal output in a CK clock signal.
  • the N+1th clock signal output terminal normally outputs the N+1th clock signal, and the N+1th clock signal output terminal is turned off. Open the signal channel between the input end and the output end of the switch circuit 122, that is, disconnect the signal channel between the Nth clock signal output end and the delay circuit 124.
  • the delay circuit 124 has no output, and the N+1th clock The signal output terminal normally transmits the N+1 clock signal to the N+1 GOA drive circuit.
  • the switch circuit 122 controls the on/off of the signal channel between the Nth clock signal output terminal and the delay circuit 124 according to the voltage amplitude of the converted electrical signal.
  • the voltage of the converted electrical signal When the amplitude falls within the conduction threshold range, it is determined that the output of the N+1 clock signal output terminal is abnormal, that is, there is no signal output at the N+1 clock signal output terminal, and the Nth clock signal output terminal output of the N+1 clock signal output terminal is controlled.
  • a delayed clock signal with the same timing as the normal N+1 clock signal is output, and is connected to the N+1 level GOA drive circuit, thereby avoiding the need for a CK clock signal when there is a CK clock signal.
  • the GOA level transmission When there is an abnormal situation of no signal in the signal, the GOA level transmission will be abnormal, and then the abnormal problem will be displayed, which will enhance the display stability and improve the product quality.
  • the signal conversion circuit 110 includes a Schmitt trigger 112 ; the input terminal of the Schmitt trigger 112 is connected to the N+1 clock signal output terminal, and the Schmitt trigger 112 The output terminal is connected to the control terminal of the switch circuit 122 .
  • the output terminal of the Schmitt trigger 112 is connected to the control terminal of the switch circuit 122, and then the N+1th clock signal output terminal is normal In the output state, the N+1 clock signal output terminal transmits the N+1 clock signal (ie, CK (N+1) signal) to the Schmitt trigger 112, causing the Schmitt trigger 112 to output a high level. Signal.
  • the N+1 clock signal ie, CK (N+1) signal
  • the N+1 clock signal output terminal transmits the RMS value (effective voltage value) of the N+1 clock signal to the Schmitt trigger 112 is 5V, then the Schmitt trigger 112 transmits a high voltage to the switch circuit 122 level signal, so that the switch circuit 122 is not conductive.
  • the Schmitt trigger 112 outputs a low-level signal, thereby causing the switch circuit 122 to be turned on.
  • the switching circuit 122 includes a PMOS tube 222 ; the gate of the PMOS tube 222 is connected to the output terminal of the Schmitt trigger 112 , and the source of the PMOS tube 222 is connected to the Nth clock signal output terminal. , the drain of the PMOS tube 222 is connected to the first input terminal of the delay circuit 124 .
  • the gate of the PMOS tube 222 is connected to the output terminal of the Schmitt trigger 112
  • the source of the PMOS tube 222 is connected to the Nth clock signal output terminal
  • the drain of the PMOS tube 222 is connected to the first input terminal of the delay circuit 124
  • the gate of the PMOS tube 222 receives the high-level signal transmitted by the Schmitt trigger 112
  • the PMOS tube 222 does not conduct, that is, the signal path between the Nth clock signal output terminal and the delay circuit 124 is disconnected. , causing the delay circuit 124 to have no output, and the N+1th clock signal output terminal transmits the N+1th clock signal to the N+1th GOA driving circuit normally.
  • the gate of the PMOS tube 222 When the gate of the PMOS tube 222 receives the low-level signal transmitted by the Schmitt trigger 112, it is determined that the N+1th clock signal output terminal has no signal output, and the PMOS tube 222 is turned on, that is, the Nth clock is turned on.
  • the signal channel between the signal output terminal and the delay circuit 124, and then the Nth clock signal output terminal transmits the Nth clock signal to the delay circuit 124 through the switch circuit 122, so that the delay circuit 124 receives the Nth clock signal , and perform delay processing on the Nth clock signal based on the interval clock signal to obtain a delayed clock signal with the same timing sequence as the normally output N+1th clock signal, and transmit the delay to the N+1th level GOA drive circuit
  • the clock signal enables the N+1 level GOA drive circuit to work normally, and avoids the problem of abnormal GOA level transmission and further display abnormality due to an abnormal situation of no signal output due to a CK clock signal.
  • the delay circuit 124 includes a first D flip-flop 322 , a second D flip-flop 324 , a third D flip-flop 326 , a fourth D flip-flop 328 , and a fifth D flip-flop 332 , the first AND gate 334, the second AND gate 336, the third AND gate 338, and the fourth AND gate 342.
  • the input terminal of the first D flip-flop 322 is connected to the drain of the PMOS tube 222, the output terminal of the first D flip-flop 322 is connected to the input terminal of the second D flip-flop 324, and the output terminal of the second D flip-flop 324 is connected to the third D flip-flop 322.
  • the input terminal of the flip-flop 326 and the output terminal of the third D flip-flop 326 are connected to the input terminal of the fourth D flip-flop 328 , and the output terminal of the fourth D flip-flop 328 is connected to the input terminal of the fifth D flip-flop 332 .
  • the clock terminal of the first D flip-flop 322, the clock terminal of the second D flip-flop 324, the clock terminal of the third D flip-flop 326, the clock terminal of the fourth D flip-flop 328, and the clock terminal of the fifth D flip-flop 332 are respectively Used to access the interval clock signal.
  • the first input terminal of the first AND gate 334 is connected to the output terminal of the first D flip-flop 322 .
  • the second input terminal of the first AND gate 334 is connected to the output terminal of the second D flip-flop 324 .
  • the output terminal of the first AND gate 334 The first input terminal of the third AND gate 338 is connected; the first input terminal of the second AND gate 336 is connected to the output terminal of the third D flip-flop 326, and the second input terminal of the second AND gate 336 is connected to the fourth D flip-flop 328.
  • the output terminal of the second AND gate 336 is connected to the second input terminal of the third AND gate 338; the first input terminal of the fourth AND gate 342 is connected to the output terminal of the third AND gate 338, and the fourth AND gate 342 is connected to the output terminal of the third AND gate 338.
  • the second input terminal is connected to the output terminal of the fifth D flip-flop 332, and the output terminal of the fourth AND gate 342 is connected to the N+1-th stage GOA driving circuit.
  • the delay circuit 124 receives the Nth clock signal, and the Nth clock signal is logically processed by 5 D flip-flops and 4 AND gates to obtain the same timing sequence as the normally output N+1 clock signal.
  • the delayed clock signal is transmitted to the N+1-level GOA drive circuit, so that the N+1-level GOA drive circuit can operate normally and avoid the abnormal situation of no signal output due to a CK clock signal. This causes GOA-level transmission to be abnormal, and then the display to be abnormal, which enhances display stability and improves product quality.
  • interval clock signal of the access delay circuit 124 may be determined by the specific interval time between the Nth clock signal and the N+1th clock signal.
  • the clock signal conditioning circuit 10 further includes a clock signal generator; the clock signal generator includes an interval clock output terminal and a plurality of clock signal output terminals; the interval clock output terminal is used to output a preset interval clock signal.
  • the clock signal generator can be used to output multiple clock signals.
  • the Nth clock signal output terminal of the clock signal generator can be used to output the Nth clock signal
  • the N+1th clock signal output terminal of the clock signal generator can be used to output the Nth clock signal.
  • the interval clock output terminal of the clock signal generator can be used to output a preset interval clock signal. It should be noted that the preset duty cycle of the interval clock signal is obtained based on the duty cycle of the Nth clock signal and the duty cycle of the N+1th clock signal.
  • a clock signal conditioning method is provided. This method is explained by taking the method applied to the delay processing circuit in Figure 1 as an example, and includes the following steps:
  • Step S410 Obtain the converted electrical signal transmitted by the signal conversion circuit.
  • the signal conversion circuit when the N+1th clock signal output terminal outputs the N+1th clock signal, the signal conversion circuit outputs a high-level signal according to the received N+1th clock signal; when the N+1th clock signal When there is no signal output at the clock signal output terminal, the signal conversion circuit outputs a low-level signal.
  • Step S420 When the voltage amplitude of the converted electrical signal falls into the conduction threshold range, receive the Nth clock signal transmitted from the Nth clock signal output end, and based on the preset interval clock signal, The signal is delayed and processed to obtain a delayed clock signal.
  • the delay processing circuit can perform judgment processing on the converted electrical signal transmitted by the acquisition signal conversion circuit. If the voltage amplitude of the converted electrical signal is not within the conduction threshold range, then it is judged that the converted electrical signal received by the delay processing circuit. The last signal is a high-level signal, thereby disconnecting the signal transmission channel between the Nth clock signal output terminal and the delay processing circuit.
  • the delay processing circuit has no output, and the N+1th clock signal output terminal is connected to the N+th clock signal output terminal.
  • a GOA drive circuit transmits the N+1 clock signal normally.
  • the delay processing circuit determines that the converted signal received by the delay processing circuit is a low-level signal, and the connection between the Nth clock signal output terminal and the delay processing circuit is controlled.
  • the signal transmission channel is turned on, and then the delay processing circuit receives the Nth clock signal, and delays the Nth clock signal based on the preset interval clock signal, so that the timing of the delayed clock signal after delay processing is The timing of the N+1 clock signal output by the N+1 clock signal output terminal is the same,
  • Step S430 transmit the delayed clock signal to the N+1th stage GOA driving circuit; the timing of the delayed clock signal is the same as the timing of the N+1th clock signal output by the N+1th clock signal output terminal.
  • the delay processing circuit can transmit the delayed clock signal obtained by the delay processing to the N+1-th level GOA driving circuit, so that the N+1-th level GOA driving circuit can work normally and avoid the problem of no signal output due to a CK clock signal.
  • the GOA level transmission will be abnormal, and then the abnormal problem will be displayed.
  • the preset duty cycle of the interval clock signal is obtained based on the duty cycle of the Nth clock signal and the duty cycle of the N+1th clock signal.
  • the delay processing circuit is used to detect the voltage amplitude of the converted electrical signal transmitted by the signal conversion circuit.
  • the N+1th If the output of the clock signal output terminal is abnormal, that is, the N+1 clock signal output terminal has no signal output, then the Nth clock signal that controls the output of the Nth clock signal output terminal will be outputted with the normal N+th clock signal after delay processing.
  • a delayed clock signal with the same timing sequence is connected to the N+1-th level GOA drive circuit, thereby preventing an abnormality in the GOA level transmission when a CK clock signal has no signal abnormality. Then abnormal problems are displayed, display stability is enhanced, and product quality is improved.
  • steps in the flowchart of FIG. 4 are shown in sequence as indicated by arrows, these steps are not necessarily executed in the order indicated by arrows. Unless explicitly stated in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in Figure 4 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but may be executed at different times. The execution of these sub-steps or stages The sequence is not necessarily sequential, but may be performed in turn or alternately with other steps or sub-steps of other steps or at least part of the stages.
  • a display panel in one embodiment, includes a pixel unit, a GOA circuit and any one of the above clock signal conditioning circuits; the clock signal conditioning circuit is connected to the GOA circuit, and the GOA circuit is connected to the pixel unit.
  • the pixel unit is composed of multiple sub-pixels arranged in an array, and each sub-pixel is connected to a vertical data line and a horizontal scanning line.
  • the GOA circuit includes a plurality of cascaded GOA drive circuits, and each level of GOA drive circuit drives a level of horizontal scanning line.
  • the main structure of the GOA drive circuit includes a pull-up circuit, a pull-up control circuit, a pull-down circuit and a pull-down sustaining circuit, as well as a bootstrap capacitor responsible for raising the potential.
  • the pull-up control circuit can also be called a precharge circuit; the pull-up circuit mainly responsible for outputting the clock signal as a gate signal; the pull-up control circuit is responsible for controlling the opening time of the pull-up circuit, and is generally connected to the stage signal or gate signal transmitted from the previous stage GOA drive circuit; the pull-down circuit is responsible for turning the gate on at the first time
  • the pull-down sustain circuit is responsible for maintaining the gate output signal and the gate signal of the pull-up circuit (usually called the Q point) in the off state (ie, negative potential); since The lifting capacitor is responsible for the secondary rise of the Q point, which is beneficial to the G(N) output of the pull-up circuit.
  • the display panel is an AMOLED display panel, AM Micro LED display panel, AM Mini LED display panel or LCD display panel.
  • the clock signal conditioning circuit can control the output of the Nth clock signal output terminal when the N+1th clock signal output terminal has no signal output.
  • the Nth clock signal undergoes delay processing, and after the delay processing, a delayed clock signal with the same timing sequence as the normal N+1th clock signal is output, and is connected to the N+1th level GOA drive circuit.
  • a display device is provided, and the display device includes the above-mentioned display panel.
  • Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory.
  • Volatile memory may include random access memory (RAM) or external cache memory.
  • RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous chain Synchlink DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.
  • SRAM static RAM
  • DRAM dynamic RAM
  • SDRAM synchronous DRAM
  • DDRSDRAM double data rate SDRAM
  • ESDRAM enhanced SDRAM
  • SLDRAM synchronous chain Synchlink DRAM
  • Rambus direct RAM
  • DRAM direct memory bus dynamic RAM
  • RDRAM memory bus dynamic RAM

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Abstract

本申请涉及一种时钟信号调理电路、方法及显示面板。所述电路包括信号转换电路和延时处理电路；延时处理电路在转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，对第N个时钟信号进行延时处理，避免当有一个CK时钟信号出现无信号的异常状况时，导致GOA级传出现异常。

Description

时钟信号调理电路、方法及显示面板、显示设备 技术领域
本申请涉及显示处理技术领域，特别是涉及一种时钟信号调理电路、方法及显示面板、显示设备。
 背景技术
液晶显示面板因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示面板中的主流。
目前，主动式液晶显示面板水平扫描线的驱动，主要由面板外接的IC(Integrated Circuit，集成电路)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA（Gate On Array）技术就是利用TFT(Thin Film Transistor，薄膜晶体管)液晶显示器阵列制程将Gate行扫描驱动信号电路制作在阵列基板上，从而实现对Gate逐行扫描的驱动方式，因此，可以运用液晶显示面板的原有制程，将水平扫描线的驱动电路制作在显示区域周围的基板上。GOA技术能减少外接IC的绑定(Bonding)工序，可提升产能并降低产品成本，并使液晶显示面板更适合制作窄边框或无边框的显示产品。
 技术问题
现有的液晶面板显示技术中，使用到GOA级传作为行扫描驱动，当设置了多个CK时钟信号作为开启行扫描的信号，若多个CK时钟信号中有一个信号出现无信号的状况即输出异常的状况，导致GOA级传出现异常，进而显示发生异常。
 技术解决方案
基于此，有必要针对上述技术问题，提供一种时钟信号调理电路、方法及显示面板、显示设备。
一种时钟信号调理电路，包括：
信号转换电路，信号转换电路的输入端用于连接第N+1个时钟信号输出端，信号转换电路的输出端用于输出转换后电信号；第N+1个时钟信号输出端用于连接第N+1级GOA驱动电路；
延时处理电路，延时处理电路被配置为获取信号转换电路传输的转换后电信号；延时处理电路还被配置为在转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对第N个时钟信号进行延时处理，得到延时时钟信号，并将延时时钟信号传输给第N+1级GOA驱动电路；延时时钟信号的时序与第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同。
一种时钟信号调理方法，包括以下步骤：
获取信号转换电路传输的转换后电信号；
在转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对第N个时钟信号进行延时处理，得到延时时钟信号；
将延时时钟信号传输给第N+1级GOA驱动电路；延时时钟信号的时序与第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同。
一种显示面板，包括像素单元、GOA电路和时钟信号调理电路；时钟信号调理电路连接GOA电路，GOA电路连接像素单元；
时钟信号调理电路包括：
信号转换电路，信号转换电路的输入端用于连接第N+1个时钟信号输出端，信号转换电路的输出端用于输出转换后电信号；第N+1个时钟信号输出端用于连接第N+1级GOA驱动电路；
延时处理电路，延时处理电路被配置为获取信号转换电路传输的转换后电信号；延时处理电路还被配置为在转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对第N个时钟信号进行延时处理，得到延时时钟信号，并将延时时钟信号传输给第N+1级GOA驱动电路；延时时钟信号的时序与第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同。
一种显示设备，包括显示面板；
显示面板包括像素单元、GOA电路和时钟信号调理电路；时钟信号调理电路连接GOA电路，GOA电路连接像素单元；
时钟信号调理电路包括：
信号转换电路，信号转换电路的输入端用于连接第N+1个时钟信号输出端，信号转换电路的输出端用于输出转换后电信号；第N+1个时钟信号输出端用于连接第N+1级GOA驱动电路；
延时处理电路，延时处理电路被配置为获取信号转换电路传输的转换后电信号；延时处理电路还被配置为在转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对第N个时钟信号进行延时处理，得到延时时钟信号，并将延时时钟信号传输给第N+1级GOA驱动电路；延时时钟信号的时序与第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同。
 有益效果
上述的时钟信号调理电路中，通过信号转换电路的输入端用于连接第N+1个时钟信号输出端，信号转换电路的输出端用于输出转换后电信号；第N+1个时钟信号输出端用于连接第N+1级GOA驱动电路；延时处理电路被配置为获取信号转换电路传输的转换后电信号；延时处理电路还被配置为在转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对第N个时钟信号进行延时处理，得到延时时钟信号，并将延时时钟信号传输给第N+1级GOA驱动电路，且延时时钟信号的时序与第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同，进而GOA电路的级传就不会因为第N+1级GOA驱动电路无信号输出而出现异常，增强了显示稳定性。本申请通过延时处理电路检测信号转换电路传输的转换后电信号的电压幅值大小，在转换后电信号的电压幅值达到导通阈值时，判定第N+1个时钟信号输出端输出异常，即第N+1个时钟信号输出端无信号输出，则控制第N个时钟信号输出端输出的第N个时钟信号经过延时处理后，输出与正常的第N+1个时钟信号的时序一样的延时时钟信号，并接入到第N+1级GOA驱动电路中，进而避免当有一个CK时钟信号出现无信号的异常状况时，导致GOA级传出现异常，进而显示发生异常的问题，增强了显示稳定性，提高了产品质量。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例中时钟信号调理电路的第一结构示意图。
图2为本申请实施例中时钟信号调理电路的第二结构示意图。
图3为本申请实施例中时钟信号调理电路的第三结构示意图。
图4为本申请实施例中时钟信号调理方法的流程示意图。
附图标记说明：
10、时钟信号调理电路；110、信号转换电路；112、施密特触发器；120、延时处理电路；122、开关电路；222、PMOS管；124、延时电路；322、第一D触发器；324、第二D触发器；326、第三D触发器；328、第四D触发器；332、第五D触发器；334、第一与门；336、第二与门；338、第三与门；342、第四与门。
 本发明的实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
为了解决现有的液晶面板显示技术中，当有一个CK时钟信号出现无信号的异常状况时，导致GOA级传出现异常，进而显示发生异常的问题，在一个实施例中，如图1所示，提供了一种时钟信号调理电路，时钟信号调理电路10包括信号转换电路110和延时处理电路120。
信号转换电路110的输入端用于连接第N+1个时钟信号输出端，信号转换电路110的输出端用于输出转换后电信号；第N+1个时钟信号输出端用于连接第N+1级GOA驱动电路；延时处理电路120被配置为获取信号转换电路110传输的转换后电信号；延时处理电路120还被配置为在转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对第N个时钟信号进行延时处理，得到延时时钟信号，并将延时时钟信号传输给第N+1级GOA驱动电路；延时时钟信号的时序与第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同。
其中，GOA电路可包括多个GOA驱动电路，例如，第N+1个GOA电路在接入相应的时钟信号时，可用来扫描驱动相应的像素单元工作，如第N+1个GOA电路在接入第N+1个时钟信号或延时时钟信号时，可正常扫描驱动相应的像素单元工作。需要说明的是，N为自然数。
转换后电信号可以是电平信号，信号转换电路110可用来对接入的时钟信号转换为电平信号。例如，第N+1个时钟信号输出端输出第N+1个时钟信号时，信号转换电路110接收到第N+1个时钟信号时，信号转换电路110输出高电平信号；当第N+1个时钟信号输出端无信号输出时，信号转换电路110输出低电平信号。延时处理电路120可用来获取信号转换电路110传输的转换后电信号，并对获取到的转换后电信号进行判断处理，例如，延时处理电路120可对转换后电信号与预设的导通阈值范围进行比对，若转换后电信号的电压幅值不在导通阈值范围内，则判定延时处理电路120接收到的转换后信号为高电平信号，进而断开第N个时钟信号输出端与延时处理电路120之间的信号传输通道，延时处理电路120无输出，第N+1个时钟信号输出端向第N+1个GOA驱动电路正常传输第N+1个时钟信号。
延时处理电路120对转换后电信号与预设的导通阈值进行比对，若转换后电信号的电压幅值落入导通阈值范围，则判定延时处理电路120接收到的转换后信号为低电平信号，导通第N个时钟信号输出端与延时处理电路120之间的信号传输通道，进而延时处理电路120接收第N个时钟信号，并基于预设的间隔时钟信号对第N个时钟信号进行延时处理后，使得延时处理后的延时时钟信号的时序与第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同，进而将延时时钟信号传输给第N+1级GOA驱动电路，使得第N+1级GOA驱动电路正常工作，避免因有一个CK时钟信号出现无信号输出的异常状况时，导致GOA级传出现异常，进而显示发生异常的问题。
上述的实施例中，通过信号转换电路110的输入端用于连接第N+1个时钟信号输出端，信号转换电路110的输出端用于输出转换后电信号；第N+1个时钟信号输出端用于连接第N+1级GOA驱动电路；延时处理电路120被配置为获取信号转换电路110传输的转换后电信号；延时处理电路120还被配置为在转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对第N个时钟信号进行延时处理，得到延时时钟信号，并将延时时钟信号传输给第N+1级GOA驱动电路，且延时时钟信号的时序与第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同，进而GOA电路的级传就不会因为第N+1级GOA驱动电路无信号输出而出现异常，增强了显示稳定性。通过延时处理电路120检测信号转换电路110传输的转换后电信号的电压幅值大小，在转换后电信号的电压幅值落入导通阈值范围时，判定第N+1个时钟信号输出端输出异常，即第N+1个时钟信号输出端无信号输出，则控制第N个时钟信号输出端输出的第N个时钟信号经过延时处理后，输出与正常的第N+1个时钟信号的时序一样的延时时钟信号，并接入到第N+1级GOA驱动电路中，进而避免当有一个CK时钟信号出现无信号的异常状况时，导致GOA级传出现异常，进而显示发生异常的问题，增强了显示稳定性，提高了产品质量。
在一个示例中，如图2所示，延时处理电路120包括开关电路122和延时电路124。
开关电路122的控制端用于接收转换后电信号，开关电路122的输入端用于连接第N个时钟信号输出端；延时电路124的第一输入端连接开关电路122的输出端，延时电路124的第二输入端用于输入接入预设的间隔时钟信号；延时电路124的输出端用于连接第N+1级GOA驱动电路。其中，在第N+1个时钟信号输出端无信号输出时，转换后电信号的电压幅值落入开关电路122的导通阈值范围，以使延时电路124接收第N个时钟信号输出端传输的第N个时钟信号，并基于间隔时钟信号对第N个时钟信号进行延时处理，得到延时时钟信号，且向第N+1级GOA驱动电路传输延时时钟信号。
其中，开关电路122可根据接收到的转换后电信号的电压幅值大小，来控制开关电路122输入端至输出端的信号通道。例如，开关电路122接收到的转换后电信号的电压幅值落入开关电路122的导通阈值范围时，判定第N+1个时钟信号输出端无信号输出，导通开关电路122的输入端与输出端之间的信号通道，即导通第N个时钟信号输出端与延时电路124之间的信号通道，进而第N个时钟信号输出端将第N个时钟信号通过开关电路122传输给延时电路124，使得延时电路124接收第N个时钟信号，并基于间隔时钟信号对第N个时钟信号进行延时处理，得到延时时钟信号，且向第N+1级GOA驱动电路传输延时时钟信号，使得第N+1级GOA驱动电路正常工作，避免因有一个CK时钟信号出现无信号输出的异常状况时，导致GOA级传出现异常，进而显示发生异常的问题。
在开关电路122接收到的转换后电信号的电压幅值未落入开关电路122的导通阈值范围时，判定第N+1个时钟信号输出端正常输出第N+1个时钟信号，则断开开关电路122的输入端与输出端之间的信号通道，即断开第N个时钟信号输出端与延时电路124之间的信号通道，延时电路124无输出，第N+1个时钟信号输出端向第N+1个GOA驱动电路正常传输第N+1个时钟信号。
上述的实施例中，通过开关电路122根据转换后电信号的电压幅值大小，控制第N个时钟信号输出端与延时电路124之间的信号通道的通断，在转换后电信号的电压幅值落入导通阈值范围时，判定第N+1个时钟信号输出端输出异常，即第N+1个时钟信号输出端无信号输出，则控制第N个时钟信号输出端输出的第N个时钟信号经过延时处理后，输出与正常的第N+1个时钟信号的时序一样的延时时钟信号，并接入到第N+1级GOA驱动电路中，进而避免当有一个CK时钟信号出现无信号的异常状况时，导致GOA级传出现异常，进而显示发生异常的问题，增强了显示稳定性，提高了产品质量。
在一个示例中，如图3所示，信号转换电路110包括施密特触发器112；施密特触发器112的输入端连接第N+1个时钟信号输出端，施密特触发器112的输出端连接开关电路122的控制端。
基于施密特触发器112的输入端连接第N+1个时钟信号输出端，施密特触发器112的输出端连接开关电路122的控制端，进而在第N+1个时钟信号输出端正常输出状况下，第N+1个时钟信号输出端向施密特触发器112传输第N+1个时钟信号（即CK（N+1）信号），使得施密特触发器112输出高电平信号。例如，第N+1个时钟信号输出端向施密特触发器112传输第N+1个时钟信号的RMS值（有效电压值）为5V，则施密特触发器112向开关电路122传输高电平信号，以使开关电路122不导通。在第N+1个时钟信号输出端输出异常状况下，即第N+1个时钟信号输出端无信号输出，使得施密特触发器112输出低电平信号，进而使得开关电路122导通。
在一个示例中，如图3所示，开关电路122包括PMOS管222；PMOS管222的栅极连接施密特触发器112的输出端，PMOS管222的源极连接第N个时钟信号输出端，PMOS管222的漏极连接延时电路124的第一输入端。
基于PMOS管222的栅极连接施密特触发器112的输出端，PMOS管222的源极连接第N个时钟信号输出端，PMOS管222的漏极连接延时电路124的第一输入端，当PMOS管222的栅极接收到施密特触发器112传输的高电平信号时，PMOS管222不导通，即断开第N个时钟信号输出端与延时电路124之间的信号通道，使得延时电路124无输出，第N+1个时钟信号输出端向第N+1个GOA驱动电路正常传输第N+1个时钟信号。
当PMOS管222的栅极接收到施密特触发器112传输的低电平信号时，判定第N+1个时钟信号输出端无信号输出，PMOS管222导通，即导通第N个时钟信号输出端与延时电路124之间的信号通道，进而第N个时钟信号输出端将第N个时钟信号通过开关电路122传输给延时电路124，使得延时电路124接收第N个时钟信号，并基于间隔时钟信号对第N个时钟信号进行延时处理，得到与正常输出的第N+1时钟信号的时序一样的延时时钟信号，且向第N+1级GOA驱动电路传输延时时钟信号，使得第N+1级GOA驱动电路正常工作，避免因有一个CK时钟信号出现无信号输出的异常状况时，导致GOA级传出现异常，进而显示发生异常的问题。
在一个示例中，如图3所示，延时电路124包括第一D触发器322、第二D触发器324、第三D触发器326、第四D触发器328、第五D触发器332、第一与门334、第二与门336、第三与门338、第四与门342。
第一D触发器322的输入端连接PMOS管222的漏极，第一D触发器322的输出端连接第二D触发器324的输入端，第二D触发器324的输出端连接第三D触发器326的输入端，第三D触发器326的输出端连接第四D触发器328的输入端，第四D触发器328的输出端连接第五D触发器332的输入端。第一D触发器322的时钟端、第二D触发器324的时钟端、第三D触发器326的时钟端、第四D触发器328的时钟端、第五D触发器332的时钟端分别用于接入间隔时钟信号。
第一与门334的第一输入端连接第一D触发器322的输出端，第一与门334的第二输入端连接第二D触发器324的输出端，第一与门334的输出端连接第三与门338的第一输入端；第二与门336的第一输入端连接第三D触发器326的输出端，第二与门336的第二输入端连接第四D触发器328的输出端，第二与门336的输出端连接第三与门338的第二输入端；第四与门342的第一输入端连接第三与门338的输出端，第四与门342的第二输入端连接第五D触发器332的输出端，第四与门342的输出端连接第N+1级GOA驱动电路。
示例性的，延时电路124接收到第N个时钟信号，第N个时钟信号经过5个D触发器和4个与门的逻辑处理，得到与正常输出的第N+1时钟信号的时序一样的延时时钟信号，且向第N+1级GOA驱动电路传输延时时钟信号，使得第N+1级GOA驱动电路正常工作，避免因有一个CK时钟信号出现无信号输出的异常状况时，导致GOA级传出现异常，进而显示发生异常的问题，增强了显示稳定性，提高了产品质量。
需要说明的是，接入延时电路124的间隔时钟信号可由具体第N个时钟信号和第N+1个时钟信号的间隔时间所决定。
在一个示例中，时钟信号调理电路10还包括时钟信号发生器；时钟信号发生器包括间隔时钟输出端和多个时钟信号输出端；间隔时钟输出端用于输出预设的间隔时钟信号。
其中，时钟信号发生器可用来输出多个时钟信号，如时钟信号发生器的第N个时钟信号输出端可用来输出第N个时钟信号，时钟信号发生器的第N+1个时钟信号输出端可用来输出第N+1个时钟信号。时钟信号发生器的间隔时钟输出端可用来输出预设的间隔时钟信号。需要说明的是，预设的间隔时钟信号的占空比根据第N个时钟信号的占空比和第N+1个时钟信号的占空比得到。
在一个实施例中，如图4所示，提供了一种时钟信号调理方法，以该方法应用于图1中的延时处理电路为例进行说明，包括以下步骤：
步骤S410，获取信号转换电路传输的转换后电信号。
其中，关于信号转换电路和转换后电信号的具体内容过程可参考上文内容，此处不再赘述。
示例性的，在第N+1个时钟信号输出端输出第N+1个时钟信号时，信号转换电路根据接收到的第N+1个时钟信号，输出高电平信号；当第N+1个时钟信号输出端无信号输出时，信号转换电路输出低电平信号。
步骤S420，在转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对第N个时钟信号进行延时处理，得到延时时钟信号。
示例性的，延时处理电路可对获取信号转换电路传输的转换后电信号进行判断处理，在转换后电信号的电压幅值不在导通阈值范围内，则判定延时处理电路接收到的转换后信号为高电平信号，进而断开第N个时钟信号输出端与延时处理电路之间的信号传输通道，延时处理电路无输出，第N+1个时钟信号输出端向第N+1个GOA驱动电路正常传输第N+1个时钟信号。
若转换后电信号的电压幅值落入导通阈值范围，则判定延时处理电路接收到的转换后信号为低电平信号，控制第N个时钟信号输出端与延时处理电路之间的信号传输通道导通，进而延时处理电路接收第N个时钟信号，并基于预设的间隔时钟信号对第N个时钟信号进行延时处理后，使得延时处理后的延时时钟信号的时序与第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同，
步骤S430，将延时时钟信号传输给第N+1级GOA驱动电路；延时时钟信号的时序与第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同。
延时处理电路可将延时处理得到的延时时钟信号传输给第N+1级GOA驱动电路，使得第N+1级GOA驱动电路正常工作，避免因有一个CK时钟信号出现无信号输出的异常状况时，导致GOA级传出现异常，进而显示发生异常的问题。
需要说明的是，预设的间隔时钟信号的占空比根据第N个时钟信号的占空比和第N+1个时钟信号的占空比得到。
上述的实施例中，通过延时处理电路检测信号转换电路传输的转换后电信号的电压幅值大小，在转换后电信号的电压幅值落入导通阈值范围时，判定第N+1个时钟信号输出端输出异常，即第N+1个时钟信号输出端无信号输出，则控制第N个时钟信号输出端输出的第N个时钟信号经过延时处理后，输出与正常的第N+1个时钟信号的时序一样的延时时钟信号，并接入到第N+1级GOA驱动电路中，进而避免当有一个CK时钟信号出现无信号的异常状况时，导致GOA级传出现异常，进而显示发生异常的问题，增强了显示稳定性，提高了产品质量。
应该理解的是，虽然图4的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图4中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
在一个实施例中，提供一种显示面板，显示面板包括像素单元、GOA电路和上述任意一项的时钟信号调理电路；时钟信号调理电路连接GOA电路，GOA电路连接像素单元。
其中，关于时钟信号调理电路的具体内容过程可参考上文内容，此处不再赘述。
像素单元由呈阵列排布的多个子像素组成，每一个子像素连接一垂直数据线和一水平扫描线。GOA电路包括级联的多个GOA驱动电路，每一级GOA驱动电路对应驱动一级水平扫描线。GOA驱动电路的主要结构包括上拉电路，上拉控制电路，下拉电路和下拉维持电路，以及负责电位抬高的自举电容等，上拉控制电路也可以称为预充电路；上拉电路主要负责将时钟信号输出为栅极信号；上拉控制电路负责控制上拉电路的打开时间，一般连接前面级GOA驱动电路传递过来的级传信号或者栅极信号；下拉电路负责在第一时间将栅极信号拉低为低电位，即关闭栅极信号；下拉维持电路则负责将栅极输出信号和上拉电路的栅极信号(通常称为Q点)维持在关闭状态(即负电位)；自举电容则负责Q点的二次抬升，这样有利于上拉电路的G(N)输出。
示例性的，显示面板为AMOLED显示面板，AM Micro LED显示面板，AM Mini LED显示面板或LCD显示面板。
上述实施例中，基于时钟信号调理电路连接GOA电路，GOA电路连接像素单元，时钟信号调理电路能够在第N+1个时钟信号输出端无信号输出时，控制第N个时钟信号输出端输出的第N个时钟信号进行延时处理，并在延时处理后，输出与正常的第N+1个时钟信号的时序一样的延时时钟信号，并接入到第N+1级GOA驱动电路中，进而避免当有一个CK时钟信号出现无信号的异常状况时，导致GOA级传出现异常，进而显示发生异常的问题，增强了显示稳定性，提高了产品质量。
在一个实施例中，提供一种显示设备，显示设备包括如上述的显示面板。
其中，关于显示面板和时钟信号调理电路的具体内容过程可参考上文内容，此处不再赘述。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的计算机程序可存储于一非易失性计算机可读取存储介质中，该计算机程序在执行时，可包括如上述各方法的实施例的流程。其中，本申请所提供的各实施例中所使用的对存储器、存储、数据库或其它介质的任何引用，均可包括非易失性和/或易失性存储器。非易失性存储器可包括只读存储器（ROM）、可编程ROM（PROM）、电可编程ROM（EPROM）、电可擦除可编程ROM（EEPROM）或闪存。易失性存储器可包括随机存取存储器（RAM）或者外部高速缓冲存储器。作为说明而非局限，RAM以多种形式可得，诸如静态RAM（SRAM）、动态RAM（DRAM）、同步DRAM（SDRAM）、双数据率SDRAM（DDRSDRAM）、增强型SDRAM（ESDRAM）、同步链路（Synchlink） DRAM（SLDRAM）、存储器总线（Rambus）直接RAM（RDRAM）、直接存储器总线动态RAM（DRDRAM）、以及存储器总线动态RAM（RDRAM）等。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (20)

  1. 一种时钟信号调理电路，其中，包括：
    信号转换电路，所述信号转换电路的输入端用于连接第N+1个时钟信号输出端，所述信号转换电路的输出端用于输出转换后电信号；第N+1个时钟信号输出端用于连接第N+1级GOA驱动电路；
    延时处理电路，所述延时处理电路被配置为获取所述信号转换电路传输的转换后电信号；所述延时处理电路还被配置为在所述转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对所述第N个时钟信号进行延时处理，得到延时时钟信号，并将所述延时时钟信号传输给所述第N+1级GOA驱动电路；所述延时时钟信号的时序与所述第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同。
  2. 根据权利要求1所述的时钟信号调理电路，其中，所述延时处理电路包括：
    开关电路，所述开关电路的控制端用于接收所述转换后电信号，所述开关电路的输入端用于连接第N个时钟信号输出端；
    延时电路，所述延时电路的第一输入端连接所述开关电路的输出端，所述延时电路的第二输入端用于输入接入预设的间隔时钟信号；所述延时电路的输出端用于连接所述第N+1级GOA驱动电路；
    其中，在所述第N+1个时钟信号输出端无信号输出时，所述转换后电信号的电压幅值落入所述开关电路的导通阈值范围，以使所述延时电路接收所述第N个时钟信号输出端传输的第N个时钟信号，并基于所述间隔时钟信号对所述第N个时钟信号进行延时处理，得到延时时钟信号，且向所述第N+1级GOA驱动电路传输所述延时时钟信号。
  3. 根据权利要求2所述的时钟信号调理电路，其中，所述信号转换电路包括施密特触发器；
    所述施密特触发器的输入端连接所述第N+1个时钟信号输出端，所述施密特触发器的输出端连接所述开关电路的控制端。
  4. 根据权利要求3所述的时钟信号调理电路，其中，所述开关电路包括PMOS管；
    所述PMOS管的栅极连接所述施密特触发器的输出端，所述PMOS管的源极连接所述第N个时钟信号输出端，所述PMOS管的漏极连接所述延时电路的第一输入端。
  5. 根据权利要求4所述的时钟信号调理电路，其中，所述延时电路包括第一D触发器、第二D触发器、第三D触发器、第四D触发器、第五D触发器、第一与门、第二与门、第三与门、第四与门；
    所述第一D触发器的输入端连接所述PMOS管的漏极，所述第一D触发器的输出端连接所述第二D触发器的输入端，所述第二D触发器的输出端连接所述第三D触发器的输入端，所述第三D触发器的输出端连接所述第四D触发器的输入端，所述第四D触发器的输出端连接所述第五D触发器的输入端；
    所述第一D触发器的时钟端、所述第二D触发器的时钟端、所述第三D触发器的时钟端、所述第四D触发器的时钟端、所述第五D触发器的时钟端分别用于接入所述间隔时钟信号；
    所述第一与门的第一输入端连接所述第一D触发器的输出端，所述第一与门的第二输入端连接所述第二D触发器的输出端，所述第一与门的输出端连接所述第三与门的第一输入端；所述第二与门的第一输入端连接所述第三D触发器的输出端，所述第二与门的第二输入端连接所述第四D触发器的输出端，所述第二与门的输出端连接所述第三与门的第二输入端；所述第四与门的第一输入端连接所述第三与门的输出端，所述第四与门的第二输入端连接所述第五D触发器的输出端，所述第四与门的输出端连接第N+1级GOA驱动电路。
  6. 根据权利要求1所述的时钟信号调理电路，其中，还包括时钟信号发生器；所述时钟信号发生器包括间隔时钟输出端和多个时钟信号输出端；
    所述间隔时钟输出端用于输出所述预设的间隔时钟信号。
  7. 一种时钟信号调理方法，其中，包括以下步骤：
    获取信号转换电路传输的转换后电信号；
    在所述转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对所述第N个时钟信号进行延时处理，得到延时时钟信号；
    将所述延时时钟信号传输给第N+1级GOA驱动电路；所述延时时钟信号的时序与第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同。
  8. 根据权利要求7所述的时钟信号调理方法，其中，所述预设的间隔时钟信号的占空比根据所述第N个时钟信号的占空比和所述第N+1个时钟信号的占空比得到。
  9. 一种显示面板，其中，包括像素单元、GOA电路和时钟信号调理电路；所述时钟信号调理电路连接所述GOA电路，所述GOA电路连接所述像素单元；
    所述时钟信号调理电路包括：
    信号转换电路，所述信号转换电路的输入端用于连接第N+1个时钟信号输出端，所述信号转换电路的输出端用于输出转换后电信号；第N+1个时钟信号输出端用于连接第N+1级GOA驱动电路；
    延时处理电路，所述延时处理电路被配置为获取所述信号转换电路传输的转换后电信号；所述延时处理电路还被配置为在所述转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对所述第N个时钟信号进行延时处理，得到延时时钟信号，并将所述延时时钟信号传输给所述第N+1级GOA驱动电路；所述延时时钟信号的时序与所述第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同。
  10. 根据权利要求9所述的显示面板，其中，所述延时处理电路包括：
    开关电路，所述开关电路的控制端用于接收所述转换后电信号，所述开关电路的输入端用于连接第N个时钟信号输出端；
    延时电路，所述延时电路的第一输入端连接所述开关电路的输出端，所述延时电路的第二输入端用于输入接入预设的间隔时钟信号；所述延时电路的输出端用于连接所述第N+1级GOA驱动电路；
    其中，在所述第N+1个时钟信号输出端无信号输出时，所述转换后电信号的电压幅值落入所述开关电路的导通阈值范围，以使所述延时电路接收所述第N个时钟信号输出端传输的第N个时钟信号，并基于所述间隔时钟信号对所述第N个时钟信号进行延时处理，得到延时时钟信号，且向所述第N+1级GOA驱动电路传输所述延时时钟信号。
  11. 根据权利要求10所述的显示面板，其中，所述信号转换电路包括施密特触发器；
    所述施密特触发器的输入端连接所述第N+1个时钟信号输出端，所述施密特触发器的输出端连接所述开关电路的控制端。
  12. 根据权利要求11所述的显示面板，其中，所述开关电路包括PMOS管；
    所述PMOS管的栅极连接所述施密特触发器的输出端，所述PMOS管的源极连接所述第N个时钟信号输出端，所述PMOS管的漏极连接所述延时电路的第一输入端。
  13. 根据权利要求12所述的显示面板，其中，所述延时电路包括第一D触发器、第二D触发器、第三D触发器、第四D触发器、第五D触发器、第一与门、第二与门、第三与门、第四与门；
    所述第一D触发器的输入端连接所述PMOS管的漏极，所述第一D触发器的输出端连接所述第二D触发器的输入端，所述第二D触发器的输出端连接所述第三D触发器的输入端，所述第三D触发器的输出端连接所述第四D触发器的输入端，所述第四D触发器的输出端连接所述第五D触发器的输入端；
    所述第一D触发器的时钟端、所述第二D触发器的时钟端、所述第三D触发器的时钟端、所述第四D触发器的时钟端、所述第五D触发器的时钟端分别用于接入所述间隔时钟信号；
    所述第一与门的第一输入端连接所述第一D触发器的输出端，所述第一与门的第二输入端连接所述第二D触发器的输出端，所述第一与门的输出端连接所述第三与门的第一输入端；所述第二与门的第一输入端连接所述第三D触发器的输出端，所述第二与门的第二输入端连接所述第四D触发器的输出端，所述第二与门的输出端连接所述第三与门的第二输入端；所述第四与门的第一输入端连接所述第三与门的输出端，所述第四与门的第二输入端连接所述第五D触发器的输出端，所述第四与门的输出端连接第N+1级GOA驱动电路。
  14. 根据权利要求9所述的显示面板，其中，还包括时钟信号发生器；所述时钟信号发生器包括间隔时钟输出端和多个时钟信号输出端；
    所述间隔时钟输出端用于输出所述预设的间隔时钟信号。
  15. 一种显示设备，其中，包括显示面板；
    所述显示面板包括像素单元、GOA电路和时钟信号调理电路；所述时钟信号调理电路连接所述GOA电路，所述GOA电路连接所述像素单元；
    所述时钟信号调理电路包括：
    信号转换电路，所述信号转换电路的输入端用于连接第N+1个时钟信号输出端，所述信号转换电路的输出端用于输出转换后电信号；第N+1个时钟信号输出端用于连接第N+1级GOA驱动电路；
    延时处理电路，所述延时处理电路被配置为获取所述信号转换电路传输的转换后电信号；所述延时处理电路还被配置为在所述转换后电信号的电压幅值落入导通阈值范围时，接收第N个时钟信号输出端传输的第N个时钟信号，并基于预设的间隔时钟信号，对所述第N个时钟信号进行延时处理，得到延时时钟信号，并将所述延时时钟信号传输给所述第N+1级GOA驱动电路；所述延时时钟信号的时序与所述第N+1个时钟信号输出端输出的第N+1个时钟信号的时序相同。
  16. 根据权利要求15所述的显示设备，其中，所述延时处理电路包括：
    开关电路，所述开关电路的控制端用于接收所述转换后电信号，所述开关电路的输入端用于连接第N个时钟信号输出端；
    延时电路，所述延时电路的第一输入端连接所述开关电路的输出端，所述延时电路的第二输入端用于输入接入预设的间隔时钟信号；所述延时电路的输出端用于连接所述第N+1级GOA驱动电路；
    其中，在所述第N+1个时钟信号输出端无信号输出时，所述转换后电信号的电压幅值落入所述开关电路的导通阈值范围，以使所述延时电路接收所述第N个时钟信号输出端传输的第N个时钟信号，并基于所述间隔时钟信号对所述第N个时钟信号进行延时处理，得到延时时钟信号，且向所述第N+1级GOA驱动电路传输所述延时时钟信号。
  17. 根据权利要求16所述的显示设备，其中，所述信号转换电路包括施密特触发器；
    所述施密特触发器的输入端连接所述第N+1个时钟信号输出端，所述施密特触发器的输出端连接所述开关电路的控制端。
  18. 根据权利要求17所述的显示设备，其中，所述开关电路包括PMOS管；
    所述PMOS管的栅极连接所述施密特触发器的输出端，所述PMOS管的源极连接所述第N个时钟信号输出端，所述PMOS管的漏极连接所述延时电路的第一输入端。
  19. 根据权利要求18所述的显示设备，其中，所述延时电路包括第一D触发器、第二D触发器、第三D触发器、第四D触发器、第五D触发器、第一与门、第二与门、第三与门、第四与门；
    所述第一D触发器的输入端连接所述PMOS管的漏极，所述第一D触发器的输出端连接所述第二D触发器的输入端，所述第二D触发器的输出端连接所述第三D触发器的输入端，所述第三D触发器的输出端连接所述第四D触发器的输入端，所述第四D触发器的输出端连接所述第五D触发器的输入端；
    所述第一D触发器的时钟端、所述第二D触发器的时钟端、所述第三D触发器的时钟端、所述第四D触发器的时钟端、所述第五D触发器的时钟端分别用于接入所述间隔时钟信号；
    所述第一与门的第一输入端连接所述第一D触发器的输出端，所述第一与门的第二输入端连接所述第二D触发器的输出端，所述第一与门的输出端连接所述第三与门的第一输入端；所述第二与门的第一输入端连接所述第三D触发器的输出端，所述第二与门的第二输入端连接所述第四D触发器的输出端，所述第二与门的输出端连接所述第三与门的第二输入端；所述第四与门的第一输入端连接所述第三与门的输出端，所述第四与门的第二输入端连接所述第五D触发器的输出端，所述第四与门的输出端连接第N+1级GOA驱动电路。
  20. 根据权利要求15所述的显示设备，其中，还包括时钟信号发生器；所述时钟信号发生器包括间隔时钟输出端和多个时钟信号输出端；
    所述间隔时钟输出端用于输出所述预设的间隔时钟信号。
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