WO2023168850A1 - 偏置生成电路以及存储电路 - Google Patents

偏置生成电路以及存储电路 Download PDF

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Publication number
WO2023168850A1
WO2023168850A1 PCT/CN2022/099536 CN2022099536W WO2023168850A1 WO 2023168850 A1 WO2023168850 A1 WO 2023168850A1 CN 2022099536 W CN2022099536 W CN 2022099536W WO 2023168850 A1 WO2023168850 A1 WO 2023168850A1
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Prior art keywords
circuit
bias
mos transistor
coupled
voltage
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PCT/CN2022/099536
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English (en)
French (fr)
Inventor
刘忠来
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长鑫存储技术有限公司
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Priority to US18/154,937 priority Critical patent/US20230290385A1/en
Publication of WO2023168850A1 publication Critical patent/WO2023168850A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

Definitions

  • Embodiments of the present disclosure relate to a bias generation circuit and a storage circuit.
  • a power converter or operating power supply may be used to convert an operating voltage to a desired voltage to power one or more electronic devices.
  • an auxiliary bias power supply for powering various circuits of the working power supply itself can be generated based on the working power supply.
  • a bias generating circuit can be used to convert the working voltage into a bias voltage.
  • the bias voltage generated based on the bias generation circuit is easy to change due to changes in other voltages in the circuit, so that the bias voltage cannot be within a stable value range, which is not conducive to the stability of other circuits that receive bias voltages to operate. working status.
  • Embodiments of the present disclosure provide a bias generation circuit and a storage circuit.
  • embodiments of the present disclosure provide a bias generating circuit, including: a first load circuit coupled between an operating voltage and an adjustment node; a bias circuit receiving the working voltage and output a bias voltage according to the working voltage; a voltage stabilizing circuit, the voltage stabilizing circuit is coupled to the output end of the bias circuit and receives a reference voltage, and is used to output a bias voltage according to the bias voltage and the The reference voltage adjusts the voltage of the adjustment node; a second load circuit, one end of the second load circuit is coupled to the output end of the bias circuit, and the other end is coupled to the adjustment node.
  • the voltage stabilizing circuit includes: an operational amplifier, a first input terminal of the operational amplifier receives the reference voltage, and a second input terminal of the operational amplifier is coupled to the adjustment node; a driving circuit , the drive circuit is coupled to the output end of the operational amplifier and receives the bias voltage, and is used to adjust the voltage of the adjustment node according to the output of the operational amplifier and the bias voltage; the feedback circuit, The feedback circuit is coupled between the adjustment node and the ground terminal.
  • the feedback circuit includes a first resistor coupled between the adjustment node and the ground.
  • the driving circuit includes a first NMOS transistor, a control end of the first NMOS transistor is coupled to the output end of the operational amplifier, and a first end of the first NMOS transistor is coupled to the bias The output end of the setting circuit is coupled, and the second end of the first NMOS transistor is coupled to the adjustment node.
  • the first load circuit includes a second resistor coupled between the operating voltage and the regulation node.
  • the first load circuit includes: a first MOS transistor, a first end of the first MOS transistor is coupled to the operating voltage, and a second end of the first MOS transistor is coupled to the The adjustment node is coupled, and the first MOS transistor responds to the first control voltage signal to conduct the first end of the first MOS transistor and the second end of the first MOS transistor.
  • the first load circuit includes: a second resistor, one end of the second resistor is coupled to the operating voltage; a first MOS transistor, a first end of the first MOS transistor is coupled to the working voltage.
  • the other end of the second resistor is coupled, the second end of the first MOS transistor is coupled to the adjustment node, and the first MOS transistor responds to the first control voltage signal to turn on the first MOS transistor. the first end and the second end.
  • the second load circuit includes: a second MOS transistor, the control end of the second MOS transistor is coupled to the first end of the first MOS transistor, and the third MOS transistor of the second MOS transistor One end is coupled to the output end of the bias circuit, and a second end of the second MOS transistor is coupled to the adjustment node.
  • the second load circuit includes: a third resistor, one end of the third resistor is coupled to the output end of the bias circuit; a second MOS transistor, the control end of the second MOS transistor is coupled to the first end of the first MOS transistor, the first end of the second MOS transistor is coupled to the other end of the third resistor, and the second end of the second MOS transistor is coupled to the adjustment Node coupling.
  • the type of the first MOS transistor is one of N-type or P-type
  • the type of the second MOS transistor is the other one of N-type or P-type
  • the second load circuit includes: a third resistor coupled between the output end of the bias circuit and the adjustment node.
  • the bias circuit includes: a third MOS transistor, the control end of the third MOS transistor is coupled to the output end of the bias circuit, and the first end of the third MOS transistor is coupled to The working voltage is coupled, and the second terminal of the third MOS transistor is coupled with the output terminal of the bias circuit.
  • the bias circuit further includes: a fourth MOS transistor, the first end of the fourth MOS transistor is coupled to the second end of the third MOS transistor, and the fourth MOS transistor is The second end is coupled to the output end of the bias circuit, and the control end of the fourth MOS transistor conducts the first end and the second end of the fourth MOS transistor in response to the second control voltage signal.
  • the bias generating circuit further includes: a switch circuit configured to be turned on in response to an enable signal to couple the first load circuit to the operating voltage via the switch circuit, and The bias circuit is caused to receive the operating voltage via the switch circuit.
  • the switch circuit includes a sixth MOS transistor.
  • another aspect of the present disclosure provides a memory circuit, including: a bias generation circuit as described in any one of the foregoing; an input buffer circuit, the input buffer circuit and the bias circuit The output terminal is coupled.
  • Figure 1 is a circuit schematic diagram of a bias generation circuit
  • 2 to 10 are nine circuit schematic diagrams of a bias generation circuit provided by an embodiment of the present disclosure.
  • FIG. 11 is a circuit schematic diagram of a memory circuit provided by yet another embodiment of the present disclosure.
  • FIG. 1 is a schematic circuit diagram of a bias generation circuit.
  • the bias generation circuit includes: a load circuit 10, which is coupled between the operating voltage VDD and the connection node 11; a bias circuit 12 that receives the working voltage. voltage VDD and outputs the bias voltage Vbias according to the operating voltage VDD; the voltage stabilizing circuit 13 is coupled to the output end of the bias circuit 12 and receives the reference voltage Vref, for adjusting according to the reference voltage Vref and the voltage of the connection node 11 Bias voltage Vbias.
  • the operational amplifier 14 in the circuit 13 decreases the value of the voltage output by the output terminal of the operational amplifier 14. Then the voltage stabilized circuit 13 and the output terminal of the operational amplifier decrease.
  • the voltage received by the control terminal of the coupled NMOS transistor 15 decreases, which reduces the conduction degree of the NMOS transistor 15 or causes the NMOS transistor 15 to turn off.
  • the current I1 in the bias circuit 12 decreases or becomes zero, causing the PMOS transistor 15 to turn off.
  • the voltage at the control terminal 16 is close to the voltage at the end of the PMOS tube 16 coupled to the working voltage, that is, the bias voltage Vbias is close to the working voltage VDD.
  • the bias voltage Vbias output by the bias circuit 12 will increase with the increase of the operating voltage VDD, which is not conducive to ensuring that the bias voltage Vbias output by the bias circuit 12 is stable.
  • the bias voltage Vbias output by the bias circuit 12 will increase with the increase of the operating voltage VDD, which is not conducive to ensuring that the bias voltage Vbias output by the bias circuit 12 is stable.
  • the bias voltage Vbias to operate will not be able to work due to the increase in the received bias voltage Vbias. Therefore, there is an urgent need to design a bias generating circuit that can easily generate a numerically stable bias voltage.
  • the implementation of the present disclosure provides a bias generating circuit. Not only the voltage stabilizing circuit is coupled to the output end and the adjustment node of the bias circuit, but also one end of the second load circuit is also coupled to the output end and the adjustment node of the bias circuit. Therefore, it can The voltage stabilizing circuit and the second load circuit are used to jointly adjust the current through the bias circuit, so that the bias circuit outputs a bias voltage with a stable value range. When the working voltage is stable, the voltage stabilizing circuit can control the voltage of the adjustment node at a fixed voltage value, so that the current through the bias circuit is stable, thereby outputting a stable bias voltage.
  • the bias generation circuit of the second load circuit can increase the current in the bias circuit through the second load circuit.
  • An embodiment of the present disclosure provides a bias generating circuit.
  • the bias generating circuit provided by an embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • 2 to 10 are nine circuit schematic diagrams of a bias generation circuit provided by an embodiment of the present disclosure.
  • the bias generation circuit includes: a first load circuit 100, which is coupled between the working voltage VDD and the adjustment node 101; a bias circuit 102, which receives the working voltage VDD and outputs a bias according to the working voltage VDD. Set the voltage Vbias; the voltage stabilizing circuit 103, the voltage stabilizing circuit 103 is coupled to the output end of the bias circuit 102 and receives the reference voltage Vref, for adjusting the voltage of the adjustment node 101 according to the bias voltage Vbias and the reference voltage Vref; the second load circuit 104. One end of the second load circuit 104 is coupled to the output end of the bias circuit 102, and the other end is coupled to the adjustment node 101.
  • the voltage stabilizing circuit 103 is coupled to the output terminal of the bias circuit 102, and the voltage stabilizing circuit 103 can provide a conductive path between the output terminal of the bias circuit 102 and the adjustment node 101.
  • One end of the second load circuit 104 is coupled to the output end of the bias circuit 102, and the other end is coupled to the adjustment node 101.
  • the second load circuit 104 can provide another connection between the output end of the bias circuit 102 and the adjustment node 101. A conductable path.
  • the current in the bias circuit 102 is affected by both the voltage stabilizing circuit 103 and the second load circuit 104 .
  • the output end of the bias circuit 102 is only coupled to the adjustment node through the voltage stabilizing circuit, and the current in the bias circuit is only affected by the voltage stabilizing circuit.
  • the output end of the bias circuit 102 can be coupled to the adjustment node 101 via the voltage stabilizing circuit 103, or can be coupled to the adjustment node 101 via the second load circuit 104, then when the operating voltage VDD occurs
  • the second load circuit 104 can also be used to assist the voltage stabilizing circuit 103.
  • Adjusting the current flowing through the bias circuit 102 is beneficial to keeping the current flowing through the bias circuit 102 within a stable value range, so that the bias circuit 102 outputs a stable value range based on the stable current in the bias circuit 102
  • the bias voltage Vbias is thus conducive to other circuits that receive the bias voltage Vbias to operate in a stable operating state.
  • coupling the first load circuit 100 to the working voltage VDD means that the first load circuit 100 is directly electrically connected to the working voltage VDD, without the need for other circuits or electronic devices to indirectly connect the two. Electrical connection.
  • the bias generating circuit may further include: a switch circuit 105 for turning on in response to the enable signal EnN, so that the first load circuit 100 is coupled to the operating voltage VDD via the switch circuit 105 connection, and the bias circuit 102 receives the operating voltage VDD via the switch circuit 105.
  • the switch circuit 105 may include a sixth MOS transistor. It should be noted that in FIG. 3 , the switch circuit 105 includes only one sixth MOS transistor as an example. In practical applications, the switch circuit 105 may also be a circuit composed of multiple sixth MOS transistors connected in series, or may be composed of other circuits based on A circuit composed of a single electronic device or a combination of multiple electronic devices that enables signal conduction. The embodiment of the present disclosure does not limit the configuration of the switch circuit 105 , as long as it is turned on in response to the enable signal EnN. It should be noted that, in one example, the sixth MOS transistor may be a PMOS transistor; in another example, the sixth MOS transistor may be an NMOS transistor.
  • the voltage stabilizing circuit 103 may include: an operational amplifier 113 , a first input terminal of which receives the reference voltage Vref, and a second input terminal of which is coupled to the adjustment node 101 ; a driver Circuit 123, the driving circuit 123 is coupled to the output end of the operational amplifier 113 and receives the bias voltage Vbias, and is used to adjust the voltage of the node 101 according to the output of the operational amplifier 113 and the bias voltage Vbias; the feedback circuit 133, the feedback circuit 133 is coupled Connected between the adjustment node 101 and the ground.
  • coupling the second input end of the operational amplifier 113 to the adjustment node 101 means that the second input end of the operational amplifier 113 and the adjustment node 101 can be directly electrically connected; the driving circuit 123 and the output end of the operational amplifier 113 Coupling means that the output end of the driving circuit 123 and the operational amplifier 113 can be directly electrically connected; the coupling of the feedback circuit 133 between the adjustment node 101 and the ground means that the feedback circuit 133 is coupled between the adjustment node 101 and the ground. can be directly electrically connected.
  • the structure of the voltage stabilizing circuit 103 will be described in detail below.
  • the driving circuit 123 may include a first NMOS transistor, the control end of the first NMOS transistor is coupled to the output end of the operational amplifier 113 , and the first end of the first NMOS transistor is coupled to the bias circuit 102 The output end of the first NMOS transistor is coupled to the adjustment node 101 .
  • the voltage stabilizing circuit 103 is based on The reference voltage Vref and the increased voltage of the adjustment node 101 will output a smaller output voltage.
  • the first NMOS transistor receives the smaller output voltage, causing the first NMOS transistor to have a very low conduction degree or causing the first NMOS transistor to turn off. , the voltage of the adjustment node 101 cannot be effectively reduced, and thus the current flowing through the bias circuit 102 cannot be adjusted.
  • the second load circuit 104 can be used to adjust the current flowing through the bias circuit 102, and make the bias circuit 102
  • the current I1 is mainly affected by the current I3 in the second load circuit 104 to keep the current I1 flowing through the bias circuit 102 within a stable value range, so that the bias circuit 102 is based on the stable current in the bias circuit 102 I1 outputs a stable bias voltage Vbias within a numerical range.
  • the feedback circuit 133 may include a first resistor coupled between the adjustment node 101 and the ground.
  • the feedback circuit may be a plurality of first resistors connected in series, or may be at least one other electronic device such as a MOS transistor.
  • the first load circuit 100 may include: a second resistor 110 coupled between the operating voltage VDD and the adjustment node 101 .
  • the coupling between the second resistor 110 and the working voltage VDD may be: the second resistor 110 is electrically connected to the adjustment node 101 via the switch circuit 105 .
  • the coupling between the second resistor 110 and the working voltage VDD may be: the second resistor 110 is directly electrically connected to the working voltage VDD.
  • the second resistor 110 and the adjustment node 101 may be directly electrically connected.
  • the first load circuit 100 includes a second resistor 110 as an example. In actual applications, the first load circuit 100 may include at least two second resistors 110 connected in series.
  • the first load circuit 100 may include: a first MOS transistor 120 , a first end of the first MOS transistor 120 coupled to the operating voltage VDD, and a second end of the first MOS transistor 120 . Coupled with the adjustment node 101, the first MOS transistor 120 responds to the first control voltage signal 10a to conduct the first end of the first MOS transistor 120 and the second end of the first MOS transistor 120.
  • the first MOS transistor may be a PMOS transistor or an NMOS transistor.
  • the coupling of the first end of the first MOS transistor 120 to the operating voltage VDD may be: the first end of the first MOS transistor 120 is electrically connected to the adjustment node 101 via the switch circuit 105 .
  • coupling the first terminal of the first MOS transistor 120 to the working voltage VDD may be: the first terminal of the first MOS transistor 120 is directly electrically connected to the working voltage VDD.
  • the second end of the first MOS transistor 120 and the adjustment node 101 may be directly electrically connected.
  • the first load circuit 100 includes a first MOS transistor 120 as an example. In actual applications, the first load circuit 100 may include at least two first MOS transistors 120 connected in series.
  • the first load circuit 100 may include: a second resistor 110 , one end of the second resistor 110 is coupled to the working voltage VDD; a first MOS transistor 120 , and a first end of the first MOS transistor 120 .
  • the end is coupled to the other end of the second resistor 110, the second end of the first MOS transistor 120 is coupled to the adjustment node 101, and the first MOS transistor 120 responds to the first control voltage signal 10a to turn on the first MOS transistor 120.
  • the first end and the second end are examples of the first MOS transistor 120 .
  • coupling one end of the second resistor 110 to the operating voltage VDD may be: one end of the second resistor 110 is electrically connected to the adjustment node 101 via the switch circuit 105 .
  • coupling the second resistor to the working voltage VDD may be: the second resistor is directly electrically connected to the working voltage VDD.
  • the first end of the first MOS transistor 120 and the other end of the second resistor 110 may be directly electrically connected, and the second end of the first MOS transistor 120 may be directly electrically connected to the adjustment node 101 .
  • the first load circuit 100 includes a second resistor 110 and a first MOS transistor 120 as an example. In practical applications, the number of the second resistor 110 and the first MOS transistor 120 is not limited. The number of second resistors 110 and the number of first MOS transistors 120 can be appropriately set according to the specific requirements of the setting generation circuit.
  • the current flowing through the feedback circuit 133 remains unchanged, because the current flowing through the feedback circuit 133 is the current I1 flowing through the bias circuit 102. , the sum of the current I2 flowing through the first load circuit 100 and the current I3 flowing through the second load circuit 104.
  • the first load circuit 100 plays a role
  • the function of shunting is beneficial to reducing the current I1 flowing through the bias circuit 102, so that the bias circuit 102 outputs a larger bias voltage Vbias based on the smaller current I1. Therefore, a first load is added to the bias generating circuit.
  • the circuit 100 is conducive to causing the bias circuit 102 to output a larger bias voltage Vbias when the operating voltage VDD remains unchanged.
  • the output voltage output by the voltage stabilizing circuit 103 based on the reference voltage Vref and the voltage of the adjusting node 101 is smaller, so that the driving force in the voltage stabilizing circuit 103
  • the circuit 123 is almost in an off state, which reduces the ability of the voltage stabilizing circuit 103 to adjust the voltage of the node 101, and thus cannot adjust the current I1 flowing through the bias circuit 102, so that the current I1 in the bias circuit 102 is mainly affected by the third
  • the influence of the current I3 in the second load circuit 104 makes the current I1 in the bias circuit 102 larger than the current in the bias circuit in the currently commonly used bias generating circuit, thereby helping to avoid the output of the bias circuit 102.
  • the bias voltage Vbias is too large, and it is beneficial to keep the bias voltage Vbias within a stable value range; on the other hand, when the bias voltage Vbias needs to be at a certain specified value, the entire second load circuit 104 can be adjusted
  • the magnitude of the resistance value is used to control the magnitude of the current I3 in the second load circuit 104 to adjust the magnitude of the current I1 in the bias circuit 102, thereby controlling the magnitude of the bias voltage Vbias.
  • the structure of the second load circuit 104 will be described in detail below through three embodiments.
  • the second load circuit 104 may include: a third resistor 114 coupled between the output end of the bias circuit 102 and the adjustment node 101 .
  • the resistance value of the third resistor 114 may be 15k ⁇ ⁇ 25k ⁇ .
  • the second load circuit 104 includes a third resistor 114 as an example.
  • the second load circuit 104 may include at least two third resistors 114 connected in series, for example , according to the required magnitude of the bias voltage Vbias output by the bias circuit 102, the resistance value of the second load circuit 104 can be set. In this way, it is helpful to further ensure that the bias voltage Vbias output by the bias circuit 102 is within a stable value range. It is convenient for other circuits that receive bias voltage to operate in a stable operating state.
  • the overall resistance value of the second load circuit 104 can be 15k ⁇ ⁇ 25k ⁇ to avoid the resistance value of the second load circuit 104 being too small to avoid making the current I3 in the second load circuit 104 too large to avoid biasing the circuit.
  • the bias voltage Vbias output based on the current I1 in the bias circuit 102 is too small.
  • the second load circuit 104 may include: a second MOS transistor 124 , a second MOS transistor 120 , and a second MOS transistor 120 .
  • the control end of 124 is coupled to the first end of the first MOS transistor 120
  • the first end of the second MOS transistor 124 is coupled to the output end of the bias circuit 102
  • the second end of the second MOS transistor 124 is coupled to the adjustment node 101 coupling.
  • designing the second MOS transistor 124 in the second load circuit 104 to control the current I3 in the second load circuit 104 is beneficial to controlling the bias voltage Vbias within a stable value range, and is beneficial to saving circuit and layout. layout space to increase the integration density of the bias generation circuit.
  • one end of the second resistor 110 is coupled to the working voltage VDD; the first MOS transistor 120 is coupled to the first end of the first MOS transistor 120 and the other end of the second resistor 110.
  • the second end of the first MOS transistor 120 is coupled to the operating voltage VDD.
  • the adjustment node 101 is coupled, and the first MOS transistor 120 responds to the first control voltage signal 10a to conduct the first terminal and the second terminal of the first MOS transistor 120 .
  • control end of the second MOS transistor 124 can be directly electrically connected to the first end of the first MOS transistor 120, and the first end of the second MOS transistor 124 can be directly electrically connected to the output end of the bias circuit 102.
  • the second end of the second MOS transistor 124 may be directly electrically connected to the adjustment node 101 .
  • the type of the first MOS transistor 120 may be one of N-type or P-type, and the type of the second MOS transistor 120 may be the other one of N-type or P-type.
  • the first MOS transistor 120 may be a PMOS transistor
  • the second MOS transistor 124 may be an NMOS transistor.
  • the current I3 in the second load circuit 104 is increased to increase the current I1 in the bias circuit 102, which is beneficial to the bias circuit 102 to output a smaller bias voltage Vbias based on the larger current I1, that is, it is beneficial to reduce the bias voltage.
  • the bias voltage Vbias output by the circuit 102 is set to avoid the phenomenon that the bias voltage Vbias increases significantly with the increase of the operating voltage VDD and ensure that the bias voltage Vbias is within a stable value range.
  • the second load circuit 104 may include: a third resistor 114 , and one end of the third resistor 114 Coupled with the output end of the bias circuit 102; the second MOS transistor 124, the control end of the second MOS transistor 124 is coupled with the first end of the first MOS transistor 120, the first end of the second MOS transistor 124 is coupled with the third The other end of the resistor 114 is coupled, and the second end of the second MOS transistor 124 is coupled to the adjustment node 101 .
  • the second load circuit 104 is also provided with a third resistor 114.
  • the common resistance of the third resistor 114 and the second MOS transistor 124 is Control so that the overall resistance value of the second load circuit 104 is within an appropriate range, so that the current I3 in the second load circuit 104 is stabilized within an appropriate value range, and the current I3 in the second load circuit 104 is prevented from being too large or is too small to prevent the current I1 in the bias circuit 102 from being too large or too small, which is beneficial to stabilizing the bias voltage Vbias output by the bias circuit 102 based on the current I1 in the bias circuit 102 within an appropriate value range.
  • the size of the second MOS transistor 124 is smaller.
  • the overall resistance value of the second load circuit 104 is within a suitable range through both the third resistor 114 and the second MOS transistor 124, it is possible to This avoids the need for a third resistor 114 with a very large resistance value, thereby helping to prevent the third resistor 114 from occupying too much circuit and layout space, thereby ensuring that the overall resistance value of the second load circuit 104 is within an appropriate range. , saving circuit and layout space.
  • the resistance value of the third resistor 114 may be 5k ⁇ ⁇ 7k ⁇ .
  • one end of the second resistor 110 is coupled to the working voltage VDD; the first MOS transistor 120 is coupled to the first end of the first MOS transistor 120 and the other end of the second resistor 110.
  • the second end of the first MOS transistor 120 is coupled to the operating voltage VDD.
  • the adjustment node 101 is coupled, and the first MOS transistor 120 responds to the first control voltage signal 10a to conduct the first terminal and the second terminal of the first MOS transistor 120 .
  • one end of the third resistor 114 can be directly electrically connected to the output end of the bias circuit 102, and the control end of the second MOS transistor 124 can be directly electrically connected to the first end of the first MOS transistor 120.
  • the first end of 124 can be directly electrically connected to the other end of the third resistor 114, and the second end of the second MOS transistor 124 can be directly electrically connected to the adjustment node 101.
  • the type of the first MOS transistor 120 may be one of N-type or P-type, and the type of the second MOS transistor 124 may be the other one of N-type or P-type.
  • the first MOS transistor 120 may be a PMOS transistor
  • the second MOS transistor 124 may be an NMOS transistor.
  • the voltage received by the control terminal of the second MOS transistor 124 also increases, which is beneficial to increasing the conduction degree of the second MOS transistor 124, thereby increasing
  • the current I3 in the second load circuit 104 is increased to increase the current I1 in the bias circuit 102, which is beneficial to reducing the bias voltage Vbias output by the output terminal of the bias circuit 102, so as to avoid the bias voltage Vbias changing with the operation.
  • the phenomenon that the voltage VDD increases will ensure that the bias voltage Vbias is within a stable value range.
  • the bias circuit 102 may include: a third MOS transistor 112.
  • the control end of the third MOS transistor 112 is directly coupled to the output end of the bias circuit 102.
  • the first end of the third MOS transistor 112 is connected to the working end of the third MOS transistor 112.
  • the voltage VDD is coupled, and the second terminal of the third MOS transistor 112 is coupled with the output terminal of the bias circuit 102 .
  • the third MOS transistor 112 may be a PMOS transistor. In this way, when the operating voltage VDD becomes larger, the voltage stabilizing circuit 103's ability to adjust the voltage of the adjusting node 101 is reduced, making it impossible to adjust the voltage flowing through the bias circuit 102.
  • the current I1 flowing through the bias circuit 102 can be adjusted by the second load circuit 104, so that the current I1 in the bias circuit 102 is mainly affected by the current I3 in the second load circuit 104, so as to To keep the current I1 flowing through the bias circuit 102 within a stable value range, and to make the current I1 in the bias circuit 102 larger than the current in the bias circuit in the currently commonly used bias generating circuit, then the first The three MOS transistors 112 can reduce the voltage at the control terminal of the third MOS transistor 112 based on the larger current I1, that is, the voltage at the control terminal of the third MOS transistor 112 is prevented from increasing with the increase of the operating voltage VDD, so that the bias voltage Vbias is stable. within the numerical range.
  • the third MOS transistor 112 may also be an NMOS transistor.
  • the principle that the third MOS transistor 112 can reduce the voltage of the control terminal of the third MOS transistor 112 based on the larger current I1 is as follows:
  • I1 is the current flowing through the third MOS transistor 112
  • W is the width of the channel region in the third MOS transistor 112
  • L is the length of the channel region in the third MOS transistor 112
  • ⁇ n is the migration of carriers.
  • C ox is the thickness of the gate dielectric layer in the third MOS transistor 112
  • V GS is the voltage difference between the control end of the third MOS transistor 112 and the first end of the third MOS transistor 112
  • V TH is the third MOS transistor 112. threshold voltage of tube 112.
  • V GS is a negative value, and (V GS -V TH ) 2 needs to increase, and V GS needs to decrease. Since V GS is the voltage difference between the control end of the third MOS transistor 112 and the first end of the third MOS transistor 112 , when the voltage VS at the first end of the third MOS transistor 112 remains unchanged, V GS needs to be reduced. is small, the voltage V G at the control terminal of the third MOS transistor 112 needs to be reduced.
  • the bias voltage Vbias output by the bias circuit 102 can be reduced to prevent the bias voltage Vbias from increasing with the increase of the operating voltage VDD. , so that the bias voltage Vbias is within a stable value range.
  • the bias circuit 102 may also include: a fourth MOS transistor 122 .
  • the first end is coupled to the second end of the third MOS transistor 112, the second end of the fourth MOS transistor 122 is directly coupled to the output end of the bias circuit 102, and the control end of the fourth MOS transistor 122 responds to the second control
  • the voltage signal 10b conducts the first terminal and the second terminal of the fourth MOS transistor 122 .
  • the fourth MOS transistor 122 may be an NMOS transistor or a PMOS transistor.
  • the following takes the bias generation circuit provided in FIG. 7 as an example to explain in detail the principle that the bias voltage Vbias output by the bias circuit 102 does not change with the change of the operating voltage VDD.
  • the value of the current I2 flowing through the first load circuit 100 will become larger, causing the voltage of the adjustment node 101 to become larger. Then, in the early stage when the working voltage VDD becomes larger, the voltage of the adjustment node 101 will be different from the reference voltage.
  • the difference in voltage Vref is large, so that the operational amplifier 113 in the voltage stabilizing circuit 103 outputs a smaller output voltage, and the first NMOS transistor in the driving circuit 123 receives the smaller output voltage, so that the first NMOS transistor becomes conductive.
  • the current I1 in the bias circuit 102 is mainly affected by the current I3 in the second load circuit 104, so as to Compared with the bias generating circuit without the second load circuit, the current I1 flowing through the bias circuit 102 is larger, so that the third MOS transistor 112 in the bias circuit 102 controls the third MOS transistor 112 based on the larger current I1.
  • the voltage at the control terminal of the MOS transistor 112 is reduced to prevent the bias voltage Vbias from increasing as the operating voltage VDD increases, so that the bias circuit 102 outputs a bias voltage Vbias with a stable value range.
  • the voltage stabilizing circuit 103 can control the voltage of the adjustment node 101 at a fixed voltage value, so that the current through the bias circuit 102 is stable, thereby outputting a stable bias voltage.
  • the first control voltage signal 10a, the second control voltage signal 10b and the reference voltage Vref may be the same.
  • the voltage stabilizing circuit 103 can provide a conductive path between the output end of the bias circuit 102 and the adjustment node 101.
  • the second load circuit 104 can provide another conductive path between the output end of the bias circuit 102 and the adjustment node 101.
  • the operating voltage VDD increases, the potential of the adjustment node 101 also increases, and the voltage is stabilized.
  • the ability of the circuit 103 to adjust the voltage of the adjustment node 101 decreases, the ability of the voltage stabilizing circuit 103 to adjust the current flowing through the bias circuit 102 also becomes smaller.
  • the second load circuit 104 can be used to assist the voltage stabilizing circuit 103 in regulating the current flowing through the bias circuit 102 .
  • the current of the circuit 102 is set, which is beneficial to keeping the current flowing through the bias circuit 102 within a stable numerical range, so that the bias circuit 102 outputs a stable bias voltage Vbias in a numerical range based on the stable current I1, which is beneficial to other receivers.
  • the circuit that operates with a bias voltage Vbias is in a stable operating state.
  • FIG. 11 is a circuit schematic diagram of a memory circuit provided by yet another embodiment of the present disclosure.
  • the memory circuit includes: any bias generation circuit 106 provided in the previous embodiment; an input buffer circuit 107 , and the input buffer circuit 107 is coupled to the output end of the bias circuit 102 .
  • the bias generation circuit 106 is the same as the previous embodiment, and will not be described again. In FIG. 11 , only a circuit schematic diagram of the bias generating circuit 106 is used as an example for convenience of illustration.
  • the input buffer circuit 107 includes: a seventh MOS transistor 117.
  • the control terminal of the seventh MOS transistor 117 is coupled to the output terminal of the bias circuit 102 in the bias generating circuit 106, that is, the seventh MOS transistor 117
  • the control terminal receives the bias voltage Vbias.
  • the control terminal of the seventh MOS transistor 117 and the output terminal of the bias circuit 102 may be directly electrically connected.
  • the third MOS transistor 112 in the bias circuit 102 and the seventh MOS transistor 117 in the input buffer circuit 107 form a current mirror structure.
  • VDS1 is the voltage between the second end of the third MOS transistor 112 and the first end of the third MOS transistor 112
  • VGS1 is the voltage between the control end of the third MOS transistor 112 and the first end of the third MOS transistor 112.
  • the voltage of VT1 is the threshold voltage of the third MOS transistor 112 .
  • VDS2 is the voltage between the second terminal of the seventh MOS tube 117 and the first terminal of the seventh MOS tube 117
  • VGS2 is the voltage between the control terminal of the seventh MOS tube 117 and the first terminal of the seventh MOS tube 117
  • VT2 is the threshold voltage of the seventh MOS transistor 117.
  • I out is the current value output by the seventh MOS transistor 117
  • I ref is the current value provided by the third MOS transistor 112 to the seventh MOS transistor 117
  • W 1 is the width of the channel of the third MOS transistor 112
  • L 1 is the length of the channel of the third MOS transistor 112
  • V DS1 is the voltage between the second end of the third MOS transistor 112 and the first end of the third MOS transistor 112
  • W 2 is the channel of the seventh MOS transistor 117.
  • the width of L 2 is the length of the channel of the seventh MOS transistor 117
  • V DS2 is the voltage between the second end of the seventh MOS transistor 117 and the first end of the seventh MOS transistor 117
  • ⁇ is the current mirror coefficient.
  • Vbias Vbias-VS1
  • VDS1 Vbias-VS1
  • VDS1 VS3-VS1
  • VS1 is the voltage at the control end of the third MOS transistor 112
  • VS3 is the voltage at the control end of the fourth MOS transistor 122.
  • the absolute value of VDS1 after adding the fourth MOS transistor 122 is smaller than that without adding the fourth MOS transistor.
  • the absolute value of VDS1 at 122, in addition, for the PMOS tube ⁇ is a negative value, so the 1+ ⁇ V DS1 after adding the fourth MOS tube 122 is smaller than the 1+ ⁇ V DS1 without adding the fourth MOS tube 122. It can be seen that after adding the fourth MOS transistor 122, the fourth MOS transistor 122 can be provided to ensure the ratio of I out to I ref without increasing the channel width of the seventh MOS transistor 117 .
  • the storage circuit includes any of the bias generating circuits 106 provided in the previous embodiments, then the bias voltage Vbias output by the output terminal of the bias circuit 102 received by the input buffer circuit 107 will be a stable value, which is beneficial to the The input buffer circuit 107 is in a stable operating state.
  • Embodiments of the present disclosure provide a bias generation circuit and a storage circuit.
  • the voltage stabilizing circuit is coupled to the output end of the bias circuit and the adjustment node.
  • one end of the second load circuit is also connected to the output end of the bias circuit and the adjustment node.
  • the nodes are coupled, so both the voltage stabilizing circuit and the second load circuit can be used to jointly adjust the voltage of the adjusting node. In this way, when the working voltage is stable, the voltage stabilizing circuit can control the voltage of the adjustment node at a fixed voltage value, so that the current through the bias circuit is stable, thereby outputting a stable bias voltage.
  • the current in the bias circuit can be increased through the second load circuit, which is helpful to prevent the bias voltage output by the bias circuit from becoming too large or excessive as the operating voltage changes.
  • Small which is conducive to making the bias circuit output a bias voltage with a stable value range, so that other circuits that receive the bias voltage for work are in a stable operating state.

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Abstract

一种偏置生成电路以及存储电路，偏置生成电路包括：第一负载电路（100），第一负载电路（100）耦接于工作电压（VDD）和调整节点（101）之间；偏置电路（102），接收工作电压（VDD）并根据工作电压（VDD）输出偏置电压（Vbias）；稳压电路（103），稳压电路（103）耦接偏置电路（102）的输出端并接收基准电压（Vref），用于根据偏置电压（Vbias）和基准电压（Vref）调整节点（101）的电压；第二负载电路（104），第二负载电路（104）的一端与偏置电路（102）的输出端耦接，另一端与调整节点（101）耦接。

Description

偏置生成电路以及存储电路
相关申请的交叉引用
本公开基于申请号为202210238528.7、申请日为2022年03月11日、申请名称为“偏置生成电路以及存储电路”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及一种偏置生成电路以及存储电路。
背景技术
在半导体器件中，可以使用电源转换器或者工作电源以将工作电压转换为期望电压以对一个或者多个电子设备供电。其中，基于工作电源可以生成用于对工作电源本身的各种电路供电的辅助偏置电源，例如利用偏置生成电路可以将工作电压转换为偏置电压。
然后，基于偏置生成电路生成的偏置电压容易因电路中其他电压的变动而变动，使得偏置电压无法处于一个稳定的数值范围内，不利于其他接收偏置电压以进行工作的电路处于稳定工作状态。
发明内容
本公开实施例提供一种偏置生成电路以及存储电路。
根据本公开一些实施例，本公开实施例一方面提供一种偏置生成电路，包括：第一负载电路，所述第一负载电路耦接于工作电压和调整节点之间；偏置电路，接收所述工作电压并根据所述工作电压输出偏置电压；稳压电路，所述稳压电路耦接所述偏置电路的输出端并接收基准电压，用于根据所述偏置电压和所述基准电压调整所述调整节点的电压；第二负载电路，所述第二负载电路的一端与所述偏置电路的输出端耦接，另一端与所述调整节点耦接。
在一些实施例中，所述稳压电路包括：运算放大器，所述运算放大器的第一输入端接收所述基准电压，所述运算放大器的第二输入端与所述调整节点耦接；驱动电路，所述驱动电路与所述运算放大器的输出端耦接并接收所述偏置电压，用于根据所述运算放大器的输出和所述偏置电压调整所述调整节点的电压；反馈电路，所述反馈电路耦接在所述调整节点与地端之间。
在一些实施例中，所述反馈电路包括第一电阻，所述第一电阻耦接在所述调整节点与所述地端之间。
在一些实施例中，所述驱动电路包括第一NMOS管，所述第一NMOS管的控制端与所述运算放大器的输出端耦接，所述第一NMOS管的第一端与所述偏置电路的输出端耦接，所述第一NMOS管的第二端与所述调整节点耦接。
在一些实施例中，所述第一负载电路包括第二电阻，所述第二电阻耦接在所述工作 电压与所述调整节点之间。
在一些实施例中，所述第一负载电路包括：第一MOS管，所述第一MOS管的第一端与所述工作电压耦接，所述第一MOS管的第二端与所述调整节点耦接，所述第一MOS管响应于第一控制电压信号以导通所述第一MOS管的第一端与所述第一MOS管的第二端。
在一些实施例中，所述第一负载电路包括：第二电阻，所述第二电阻一端与所述工作电压耦接；第一MOS管，所述第一MOS管的第一端与所述第二电阻的另一端耦接，所述第一MOS管的第二端与所述调整节点耦接，所述第一MOS管响应于第一控制电压信号以导通所述第一MOS管的第一端与所述第二端。
在一些实施例中，所述第二负载电路包括：第二MOS管，所述第二MOS管的控制端与所述第一MOS管的第一端耦接，所述第二MOS管的第一端与所述偏置电路的输出端耦接，所述第二MOS管的第二端与所述调整节点耦接。
在一些实施例中，所述第二负载电路包括：第三电阻，所述第三电阻一端与所述偏置电路的输出端耦接；第二MOS管，所述第二MOS管的控制端与所述第一MOS管的第一端耦接，所述第二MOS管的第一端与所述第三电阻的另一端耦接，所述第二MOS管的第二端与所述调整节点耦接。
在一些实施例中，所述第一MOS管的类型为N型或者P型中的一者，所述第二MOS管的类型为N型或者P型中的另一者。
在一些实施例中，所述第二负载电路包括：第三电阻，所述第三电阻耦接在所述偏置电路的输出端与所述调整节点之间。
在一些实施例中，所述偏置电路包括：第三MOS管，所述第三MOS管的控制端与所述偏置电路的输出端耦接，所述第三MOS管的第一端与所述工作电压耦接，所述第三MOS管的第二端与所述偏置电路的输出端耦接。
在一些实施例中，所述偏置电路还包括：第四MOS管，所述第四MOS管的第一端与所述第三MOS管的第二端耦接，所述第四MOS管的第二端与所述偏置电路的输出端耦接，所述第四MOS管的控制端响应于第二控制电压信号导通所述第四MOS管的第一端与第二端。
在一些实施例中，所述偏置生成电路还包括：开关电路，用于响应于使能信号导通，以使所述第一负载电路经由所述开关电路与所述工作电压耦接，以及使所述偏置电路经由所述开关电路接收所述工作电压。
在一些实施例中，所述开关电路包括第六MOS管。
根据本公开一些实施例，本公开实施例另一方面提供一种存储电路，包括：如前述任一项所述的偏置生成电路；输入缓冲电路，所述输入缓冲电路与所述偏置电路的输出端耦接。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除 非有特别申明，附图中的图不构成比例限制；为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领缺普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种偏置生成电路的电路示意图；
图2至图10为本公开一实施例提供的偏置生成电路的九种电路示意图；
图11为本公开又一实施例提供的存储电路的一种电路示意图。
具体实施方式
由背景技术可知，目前偏置生成电路生成的偏置电压的数值不稳定。
图1为一种偏置生成电路的电路示意图，参考图1，偏置生成电路包括：负载电路10，负载电路10耦接于工作电压VDD和连接节点11之间；偏置电路12，接收工作电压VDD并根据工作电压VDD输出偏置电压Vbias；稳压电路13，稳压电路13耦接偏置电路12的输出端并接收基准电压Vref，用于根据基准电压Vref和连接节点11的电压调整偏置电压Vbias。
若工作电压VDD变高，流经负载电路10的电流I2的数值会变大，导致连接节点11的电压变大，则基准电压Vref与连接节点11的电压之间的差值增大，稳压电路13中的运算放大器14基于基准电压Vref与连接节点11的电压之间的差值的增大，运算放大器14输出端输出的电压的数值减小，则稳压电路13中与运算放大器输出端耦接的NMOS管15的控制端接收的电压降低，降低NMOS管15的导通程度或者使得NMOS管15关断，如此，会使得偏置电路12中的电流I1降低或者为零，使得PMOS管16控制端的电压趋近于PMOS管16与工作电压耦接的一端的电压，即使得偏置电压Vbias趋近于工作电压VDD。
经分析发现，目前的偏置生成电路中，偏置电路12输出的偏置电压Vbias会随工作电压VDD的增大而增大，从而不利于保证偏置电路12输出的偏置电压Vbias处于稳定的数值范围内，且其他接收偏置电压Vbias以进行工作的电路会由于接收的偏置电压Vbias增大而无法工作。因此，亟需设计便于生成一种数值稳定的偏置电压的偏置生成电路。
本公开实施提供一种偏置生成电路，不仅稳压电路耦接偏置电路的输出端和调整节点，而且第二负载电路的一端也与偏置电路的输出端和调整节点耦接，因此可以利用稳压电路和第二负载电路两者共同调节通过偏置电路的电流，从而使得偏置电路输出数值范围稳定的偏置电压。在工作电压稳定时，稳压电路可以将调整节点的电压控制在固定电压值，使得通过偏置电路的电流稳定，从而输出稳定的偏置电压，在工作电压过大时，相较于没有第二负载电路的偏置生成电路，可以通过第二负载电路增大偏置电路中的电流，通过上述两个方面有利于避免偏置电路输出的偏置电压随工作电压的变动而变得过大或过小，从而有利于使得偏置电路输出数值范围稳定的偏置电压，以使得其他接收偏置电压以进行工作的电路处于稳定工作状态。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例 中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
本公开一实施例提供一种偏置生成电路，以下将结合附图对本公开一实施例提供的偏置生成电路进行详细说明。图2至图10为本公开一实施例提供的偏置生成电路的九种电路示意图。
参考图2，偏置生成电路包括：第一负载电路100，第一负载电路100耦接于工作电压VDD和调整节点101之间；偏置电路102，接收工作电压VDD并根据工作电压VDD输出偏置电压Vbias；稳压电路103，稳压电路103耦接偏置电路102的输出端并接收基准电压Vref，用于根据偏置电压Vbias和基准电压Vref调整调整节点101的电压；第二负载电路104，第二负载电路104的一端与偏置电路102的输出端耦接，另一端与调整节点101耦接。
如此，一方面，稳压电路103耦接偏置电路102的输出端，稳压电路103可以给偏置电路102的输出端和调整节点101之间提供一条可导通的路径，另一方面，第二负载电路104的一端与偏置电路102的输出端耦接，另一端与调整节点101耦接，则第二负载电路104可以给偏置电路102的输出端和调整节点101之间提供另一条可导通的路径。
如此，偏置电路102中的电流受稳压电路103和第二负载电路104两者共同的影响。相较于目前常见的偏置生成电路中，偏置电路102的输出端仅仅经由稳压电路与调整节点耦接，偏置电路中的电流仅受稳压电路的影响，本公开一实施例中提供的偏置生成电路中，偏置电路102的输出端既可以经由稳压电路103与调整节点101耦接，又可以经由第二负载电路104与调整节点101耦接，则在工作电压VDD发生变动，使得稳压电路103对调整节点101的电压的调节能力降低，使得稳压电路103对流经偏置电路102的电流的调节能力降低时，也可以通过第二负载电路104辅助稳压电路103调节流经偏置电路102的电流，从而有利于保持流经偏置电路102中的电流处于稳定的数值范围内，使得偏置电路102基于偏置电路102中稳定的电流而输出数值范围稳定的偏置电压Vbias，从而有利于其他接收偏置电压Vbias以进行工作的电路处于稳定工作状态。
以下将结合附图对本公开一实施例提供的偏置生成电路进行详细的说明。
关于第一负载电路100耦接于工作电压VDD和调整节点101之间的具体情形，以下通过两种实施例进行详细说明。
在一些实施例中，参考图2，第一负载电路100与工作电压VDD耦接指的是：第一负载电路100与工作电压VDD直接电连接，两者之间无需其他的电路或电子器件间接电连接。
在另一些实施例中，参考图3，偏置生成电路还可以包括：开关电路105，用于响应于使能信号EnN导通，以使第一负载电路100经由开关电路105与工作电压VDD耦接，以及使偏置电路102经由开关电路105接收工作电压VDD。
其中，在一些实施例中，开关电路105可以包括第六MOS管。需要说明的是，图3中仅以开关电路105包括一个第六MOS管作为示例，实际应用中，开关电路105也可以是由多个串联的第六MOS管构成的电路，或者由其他能够基于使能信号导通的单 个电子器件或多个电子器件的组合构成的电路。本公开实施例对开关电路105的具有构成不做限制，只需满足用于响应于使能信号EnN导通即可。需要说明的是，在一个例子中，第六MOS管可以为PMOS管；在另一个例子中，第六MOS管可以为NMOS管。
在一些实施例中，参考图4，稳压电路103可以包括：运算放大器113，运算放大器113的第一输入端接收基准电压Vref，运算放大器113的第二输入端与调整节点101耦接；驱动电路123，驱动电路123与运算放大器113的输出端耦接并接收偏置电压Vbias，用于根据运算放大器113的输出和偏置电压Vbias调整调整节点101的电压；反馈电路133，反馈电路133耦接在调整节点101与地端之间。
需要说明的是，运算放大器113的第二输入端与调整节点101耦接指的是，运算放大器113的第二输入端与调整节点101可以直接电连接；驱动电路123与运算放大器113的输出端耦接指的是，驱动电路123与运算放大器113的输出端可以直接电连接；反馈电路133耦接在调整节点101与地端之间指的是，反馈电路133与调整节点101与地端之间均可以是直接电连接。
以下对稳压电路103的构成进行详细的说明。
在一些实施例中，参考图4，驱动电路123可以包括第一NMOS管，第一NMOS管的控制端与运算放大器113的输出端耦接，第一NMOS管的第一端与偏置电路102的输出端耦接，第一NMOS管的第二端与调整节点101耦接。
如此，在工作电压VDD变大时，流经第一负载电路100的电流I2的数值会变大，使得调整节点101的电压变大，则在工作电压VDD变大的初期，稳压电路103基于基准电压Vref和变大的调整节点101的电压会输出较小的输出电压，第一NMOS管接收该较小的输出电压使得第一NMOS管的导通程度十分低或者使得第一NMOS管关断，无法有效降低调整节点101的电压，从而无法调节流经偏置电路102的电流大小，此时可以通过第二负载电路104调节流经偏置电路102的电流大小，并使得偏置电路102中的电流I1主要受第二负载电路104中的电流I3的影响，以保持流经偏置电路102中的电流I1处于稳定的数值范围内，使得偏置电路102基于偏置电路102中稳定的电流I1而输出数值范围稳定的偏置电压Vbias。
在一些实施例中，参考图4，反馈电路133可以包括第一电阻，第一电阻耦接在调整节点101与地端之间。在其他实施例中，反馈电路可以是多个串联的第一电阻，也可以是MOS管等其他的至少一个电子器件。
关于第一负载电路的构成，以下通过三种实施例对其进行详细说明。
在一些实施例中，参考图4，第一负载电路100可以包括：第二电阻110，第二电阻110耦接在工作电压VDD与调整节点101之间。
需要说明的是，第二电阻110与工作电压VDD耦接可以是：第二电阻110经由开关电路105与调整节点101电连接。在其他实施例中，第二电阻110与工作电压VDD耦接可以是：第二电阻110与工作电压VDD直接电连接。第二电阻110与调整节点101可以直接电连接。图4中以第一负载电路100包括一第二电阻110为示例，实际应用中，第一负载电路100可以包括至少两个相串联的第二电阻110。
在另一些实施例中，参考图5，第一负载电路100可以包括：第一MOS管120，第 一MOS管120的第一端与工作电压VDD耦接，第一MOS管120的第二端与调整节点101耦接，第一MOS管120响应于第一控制电压信号10a以导通第一MOS管120的第一端与第一MOS管120的第二端。其中，第一MOS管可以是PMOS管，也可以是NMOS管。
需要说明的是，第一MOS管120的第一端与工作电压VDD耦接可以是：第一MOS管120的第一端经由开关电路105与调整节点101电连接。在其他实施例中，第一MOS管120的第一端与工作电压VDD耦接可以是：第一MOS管120的第一端与工作电压VDD直接电连接。第一MOS管120的第二端与调整节点101可以直接电连接。图5中以第一负载电路100包括一第一MOS管120为示例，实际应用中，第一负载电路100可以包括至少两个相串联的第一MOS管120。
在又一些实施例中，参考图6，第一负载电路100可以包括：第二电阻110，第二电阻110一端与工作电压VDD耦接；第一MOS管120，第一MOS管120的第一端与第二电阻110的另一端耦接，第一MOS管120的第二端与调整节点101耦接，第一MOS管120响应于第一控制电压信号10a以导通第一MOS管120的第一端与第二端。
需要说明的是，第二电阻110一端与工作电压VDD耦接可以是：第二电阻110一端经由开关电路105与调整节点101电连接。在其他实施例中，第二电阻与工作电压VDD耦接可以是：第二电阻与工作电压VDD直接电连接。第一MOS管120的第一端与第二电阻110的另一端可以直接电连接，第一MOS管120的第二端与调整节点101可以直接电连接。图6中以第一负载电路100包括一第二电阻110与一第一MOS管120为示例，实际应用中，对第二电阻110的数量以及第一MOS管120的数量不做限制，根据偏置生成电路的具体需求合理设置第二电阻110的数量以及第一MOS管120的数量即可。
在工作电压VDD不变，稳压电路103稳定控制调整节点101的电压时，流经反馈电路133处的电流不变，由于流经反馈电路133处的电流为流经偏置电路102的电流I1、流经第一负载电路100的电流I2以及流经第二负载电路104的电流I3之和，相较于没有第一负载电路100的偏置生成电路，此时的第一负载电路100起到分流的作用，有利于降低流经偏置电路102的电流I1，从而使得偏置电路102基于更小的电流I1输出更大的偏置电压Vbias，因此，在偏置生成电路中增设第一负载电路100，有利于在工作电压VDD不变的情况下，使得偏置电路102输出较大的偏置电压Vbias。
本公开实施例中，由于工作电压VDD增大，调整节点101的电压增大，稳压电路103基于基准电压Vref和调整节点101的电压输出的输出电压较小，使得稳压电路103中的驱动电路123几乎处于关断状态，使得稳压电路103对调整节点101的电压的调节能力降低，从而无法调整通过流经偏置电路102的电流I1，使得偏置电路102中的电流I1主要受第二负载电路104中的电流I3的影响，使得偏置电路102中的电流I1相较于目前常用的偏置生成电路中偏置电路中的电流更大，从而有利于避免偏置电路102输出的偏置电压Vbias过大，且有利于使得偏置电压Vbias处于稳定的数值范围内；另一方面，在需要偏置电压Vbias的大小处于某一指定值时，可以通过调整第二负载电路104整体呈现的电阻值的大小，以控制第二负载电路104中的电流I3的大小，以调节偏置 电路102中的电流I1的大小，从而控制偏置电压Vbias的大小。
关于第二负载电路104的构成，以下通过三种实施例对其进行详细说明。
在一些实施例中，参考图7，第二负载电路104可以包括：第三电阻114，第三电阻114耦接在偏置电路102的输出端与调整节点101之间。其中，第三电阻114的阻值可以为15kΩ～25kΩ。
需要说明的是，第三电阻114与偏置电路102的输出端以及调整节点101的耦接均可以是直接电连接。图7中以第二负载电路104包括一第三电阻114为示例，实际应用中，根据偏置生成电路的具体需求，第二负载电路104可以包括至少两个相串联的第三电阻114，例如，根据需要偏置电路102输出的偏置电压Vbias的大小，可以设置第二负载电路104的电阻值，如此，有利于进一步保证偏置电路102输出的偏置电压Vbias处于稳定的数值范围内，便于其他接收偏置电压以进行工作的电路处于稳定工作状态。其中，第二负载电路104整体呈现的电阻值可以为15kΩ～25kΩ，避免第二负载电路104的电阻值过小，以避免使得第二负载电路104中的电流I3过大，以避免偏置电路102基于偏置电路102中的电流I1输出的偏置电压Vbias过小。
在另一些实施例中，参考图8，在第一负载电路100包括第二电阻110和第一MOS管120的前提下，第二负载电路104可以包括：第二MOS管124，第二MOS管124的控制端与第一MOS管120的第一端耦接，第二MOS管124的第一端与偏置电路102的输出端耦接，第二MOS管124的第二端与调整节点101耦接。如此，在第二负载电路104中设计第二MOS管124以控制第二负载电路104中的电流I3，在有利于控制偏置电压Vbias处于稳定的数值范围内的同时，有利于节省电路以及版图的布局空间，以提高偏置生成电路的集成密度。
其中，第二电阻110一端与工作电压VDD耦接；第一MOS管120，第一MOS管120的第一端与第二电阻110的另一端耦接，第一MOS管120的第二端与调整节点101耦接，第一MOS管120响应于第一控制电压信号10a以导通第一MOS管120的第一端与第二端。
需要说明的是，第二MOS管124的控制端可以与第一MOS管120的第一端直接电连接，第二MOS管124的第一端可以与偏置电路102的输出端直接电连接，第二MOS管124的第二端可以与调整节点101直接电连接。
其中，第一MOS管120的类型可以为N型或者P型中的一者，第二MOS管的类型为N型或者P型中的另一者。
在一个例子中，第一MOS管120可以为PMOS管，第二MOS管124可以为NMOS管。如此，在工作电压VDD增大，调整节点101的电压随之增大时，第二MOS管124控制端接收的电压也增大，有利于增大第二MOS管124的导通程度，从而增大第二负载电路104中的电流I3，以增大偏置电路102中的电流I1，从而有利于偏置电路102基于更大的电流I1输出较小的偏置电压Vbias，即有利于降低偏置电路102输出的偏置电压Vbias，以实现避免偏置电压Vbias随工作电压VDD的增大而大幅增大的现象，保证偏置电压Vbias处于稳定的数值范围内。
在又一些实施例中，参考图9，在第一负载电路100包括第二电阻110和第一MOS 管120的前提下，第二负载电路104可以包括：第三电阻114，第三电阻114一端与偏置电路102的输出端耦接；第二MOS管124，第二MOS管124的控制端与第一MOS管120的第一端耦接，第二MOS管124的第一端与第三电阻114的另一端耦接，第二MOS管124的第二端与调整节点101耦接。
为避免第二负载电路104的电阻值过小，第二负载电路104中在设置第二MOS管124的基础上，还设置有第三电阻114，第三电阻114与第二MOS管124的共同控制，使得第二负载电路104整体呈现的电阻值处于合适的范围，以使得第二负载电路104中的电流I3稳定在合适的数值范围内，避免第二负载电路104中的电流I3过大或者过小，以避免偏置电路102中的电流I1过大或者过小，如此，有利于使得偏置电路102基于偏置电路102中的电流I1输出的偏置电压Vbias稳定在合适的数值范围内。此外，相较于电阻器件，第二MOS管124的尺寸较小，则通过第三电阻114与第二MOS管124两者使得第二负载电路104整体呈现的电阻值处于合适的范围时，可以避免需要电阻值非常大的第三电阻114，从而有利于避免第三电阻114占用过多的电路以及版图的布局空间，以在保证第二负载电路104整体呈现的电阻值处于合适的范围的同时，节省电路以及版图的布局空间。其中，第三电阻114的电阻值可以为5kΩ～7kΩ。
其中，第二电阻110一端与工作电压VDD耦接；第一MOS管120，第一MOS管120的第一端与第二电阻110的另一端耦接，第一MOS管120的第二端与调整节点101耦接，第一MOS管120响应于第一控制电压信号10a以导通第一MOS管120的第一端与第二端。
需要说明的是，第三电阻114一端与偏置电路102的输出端可以直接电连接，第二MOS管124的控制端与第一MOS管120的第一端可以直接电连接，第二MOS管124的第一端与第三电阻114的另一端可以直接电连接，第二MOS管124的第二端与调整节点101可以直接电连接。
其中，第一MOS管120的类型可以为N型或者P型中的一者，所述第二MOS管124的类型为N型或者P型中的另一者。
在一个例子中，第一MOS管120可以为PMOS管，第二MOS管124可以为NMOS管。如此，在工作电压VDD增大，调整节点101的电压随之增大时，第二MOS管124控制端接收的电压也增大，有利于增大第二MOS管124的导通程度，从而增大第二负载电路104中的电流I3，以增大偏置电路102中的电流I1，从而有利于降低偏置电路102的输出端输出的偏置电压Vbias，以实现避免偏置电压Vbias随工作电压VDD的增大而则增大的现象，保证偏置电压Vbias处于稳定的数值范围内。
在一些实施例中，偏置电路102可以包括：第三MOS管112，第三MOS管112的控制端与偏置电路102的输出端直接耦接，第三MOS管112的第一端与工作电压VDD耦接，第三MOS管112的第二端与偏置电路102的输出端耦接。
在一些实施例中，第三MOS管112可以为PMOS管，如此，在工作电压VDD变大，稳压电路103对调整节点101的电压的调节能力降低，从而无法调整通过流经偏置电路102的电流I1，此时可以通过第二负载电路104调节通过流经偏置电路102的电流I1，并使得偏置电路102中的电流I1主要受第二负载电路104中的电流I3的影响，以 保持流经偏置电路102中的电流I1处于稳定的数值范围内，且使得偏置电路102中的电流I1相较于目前常用的偏置生成电路中偏置电路中的电流更大，则第三MOS管112基于更大的电流I1可以降低第三MOS管112控制端的电压，即避免第三MOS管112控制端的电压随工作电压VDD的增大而增大，以使得偏置电压Vbias处于稳定的数值范围内。在其他实施例中，第三MOS管112也可以为NMOS管。
其中，第三MOS管112基于更大的电流I1可以降低第三MOS管112控制端的电压的原理如下：
Figure PCTCN2022099536-appb-000001
其中，I1为流经第三MOS管112的电流，W为第三MOS管112中沟道区的宽度，L为第三MOS管112中沟道区的长度，μ n为载流子的迁移率，C ox为第三MOS管112中栅介质层的厚度，V GS为第三MOS管112的控制端与第三MOS管112的第一端之间的电压差，V TH为第三MOS管112的阈值电压。由于偏置电路102中的电流I1增大，即流经第三MOS管112的电流I1增大，则(V GS-V TH) 2增大。当第三MOS管112为PMOS管时，V GS为负值，需要(V GS-V TH) 2增大，则需要V GS减小。由于V GS为第三MOS管112的控制端与第三MOS管112的第一端之间的电压差，在第三MOS管112的第一端的电压V S不变时，需要V GS减小，则需要第三MOS管112的控制端的电压V G减小，由于第三MOS管112的控制端的电压V G即为偏置电路102输出的偏置电压Vbias，因而，在流经第三MOS管112的电流I1增大时，通过增设第二负载电路104，可以会使得偏置电路102输出的偏置电压Vbias减小，以避免偏置电压Vbias随工作电压VDD的增大而增大，以使得偏置电压Vbias处于稳定的数值范围内。
在一些实施例中，继续参考图7至图9，在偏置电路102包括上述第三MOS管112的基础上，偏置电路102还可以包括：第四MOS管122，第四MOS管122的第一端与第三MOS管112的第二端耦接，第四MOS管122的第二端与偏置电路102的输出端直接耦接，第四MOS管122的控制端响应于第二控制电压信号10b导通第四MOS管122的第一端与第二端。
需要说明的是，第四MOS管122的第一端与第三MOS管112的第二端可以直接电连接。其中，第四MOS管122可以为NMOS管或者PMOS管。
以下以图7中提供的偏置生成电路为示例，对偏置电路102输出的偏置电压Vbias不随工作电压VDD的变动而变动的原理进行详细说明。
在工作电压VDD变大时，流经第一负载电路100的电流I2的数值会变大，使得调整节点101的电压变大，则在工作电压VDD变大的初期，调整节点101的电压与基准电压Vref的差值较大，使得稳压电路103中的运算放大器113输出较小的输出电压，驱动电路123中的第一NMOS管接收该较小的输出电压使得第一NMOS管的导通程度十分低或者使得第一NMOS管关断，以使通过驱动第一NMOS管的电流几乎为零，则偏置电路102中的电流I1主要由受第二负载电路104中的电流I3的影响，以使得相较于没有设置第二负载电路的偏置生成电路，流经偏置电路102中的电流I1更大，使得偏置电路102中的第三MOS管112基于更大的电流I1控制第三MOS管112的控制端的 电压降低，以避免偏置电压Vbias随工作电压VDD的增大而增大，以使得偏置电路102输出数值范围稳定的偏置电压Vbias。
工作电压VDD稳定时，稳压电路103能够将调整节点101的电压控制在固定电压值，使得通过偏置电路102的电流稳定，从而输出稳定的偏置电压。
在一些实施例中，第一控制电压信号10a、第二控制电压信号10b以及基准电压Vref可以相同。
综上所述，相较于目前常见的偏置生成电路，一方面，稳压电路103可以给偏置电路102的输出端和调整节点101之间提供一条可导通的路径，另一方面，第二负载电路104可以给偏置电路102的输出端和调整节点101之间提供另一条可导通的路径，则在工作电压VDD增大，调整节点101的电位也随之增大，稳压电路103对调整节点101的电压的调节能力降低时，稳压电路103对流经偏置电路102电流的调节能力也变小，此时可以通过第二负载电路104辅助稳压电路103调节流经偏置电路102电流，从而有利于保持流经偏置电路102中的电流处于稳定的数值范围内，使得偏置电路102基于稳定的电流I1输出数值范围稳定的偏置电压Vbias，从而有利于其他接收偏置电压Vbias以进行工作的电路处于稳定工作状态。
本公开又一实施例还提供一种存储电路，包括如前述实施例提供的任一种偏置生成电路。以下将结合附图对本公开又一实施例提供的存储电路进行详细说明。图11为本公开又一实施例提供的存储电路的一种电路示意图。
参考图11，存储电路包括：如前述实施例提供的任一种偏置生成电路106；输入缓冲电路107，输入缓冲电路107与偏置电路102的输出端耦接。需要说明的是，偏置生成电路106与前述实施例相同，在此不做赘述。图11中仅以偏置生成电路106的一种电路示意图为示例，以便于图示。
在一些实施例中，输入缓冲电路107包括：第七MOS管117，第七MOS管117的控制端与偏置生成电路106中的偏置电路102的输出端耦接，即第七MOS管117的控制端接收偏置电压Vbias。其中，第七MOS管117的控制端与偏置电路102的输出端可以直接电连接。
其中，偏置电路102中的第三MOS管112与输入缓冲电路107中的第七MOS管117构成电流镜结构。
在一个例子中，第三MOS管112和第七MOS管117均为PMOS管。由于第三MOS管112作输入管，第三MOS管112的控制端与第二端短接，VDS1＝VGS1<VGS1-VT1，而第三MOS管112总是工作在饱和区，而且由于第三MOS管112的控制端与第二端短接，第三MOS管112的输入电阻也较低。其中，VDS1为第三MOS管112的第二端与第三MOS管112的第一端之间的电压，VGS1为第三MOS管112的控制端与第三MOS管112的第一端之间的电压，VT1为第三MOS管112的阈值电压。
由于第七MOS管117工作在饱和区，则VDS2<VGS2-VT2，又由于VGS1＝VGS2，则VDS2<VGS1-VT2，又由于VGS1＝VDS1，则VDS2<VDS1-VT2，由于VDS2和VDS1均为负值，则VDS2的绝对值大于VDS1的绝对值。其中，VDS2为第七MOS管117的第二端与第七MOS管117的第一端之间的电压，，VGS2为第七MOS管117的控制 端与第七MOS管117的第一端之间的电压，VT2为第七MOS管117的阈值电压。
根据电流镜公式：
Figure PCTCN2022099536-appb-000002
其中，I out为第七MOS管117输出的电流值，I ref为第三MOS管112提供给第七MOS管117的电流值，W 1为第三MOS管112的沟道的宽度，L 1为第三MOS管112的沟道的长度，V DS1为第三MOS管112的第二端与第三MOS管112的第一端之间的电压，W 2为第七MOS管117的沟道的宽度，L 2为第七MOS管117的沟道的长度，V DS2为第七MOS管117的第二端与第七MOS管117的第一端之间的电压，λ为电流镜系数。
为使得电流镜的结果越准确，需要
Figure PCTCN2022099536-appb-000003
的影响越小，为了减小VDS1的影响，需要增大W2，即增大第七MOS管117的沟道的宽度，以保证I out与I ref的比例。
本公开实施例中，在增加第四MOS管122后，理想情况下，I ref不变，则偏置电压Vbias基本不变，由于在未增加第四MOS管122时，VDS1＝Vbias-VS1；在增加第四MOS管122后，VDS1＝VS3-VS1，其中，VS1为第三MOS管112控制端的电压，VS3为第四MOS管122控制端的电压。由于VS3大于偏置电压Vbias，且第三MOS管112和第七MOS管117均为PMOS管，VDS1为负值，则增加第四MOS管122后的VDS1的绝对值小于未增加第四MOS管122时的VDS1的绝对值，此外，对于PMOS管λ为负值，因而增加第四MOS管122后的1+λV DS1小于未增加第四MOS管122时的1+λV DS1。可见，经过增加第四MOS管122之后，无需增大第七MOS管117的沟道的宽度，即可提供第四MOS管122保证I out与I ref的比例。
综上所述，存储电路包括如前述实施例提供的任一种偏置生成电路106，则输入缓冲电路107接收的偏置电路102的输出端输出的偏置电压Vbias为稳定值，有利于使得输入缓冲电路107处于稳定工作状态。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。
工业实用性
本公开实施例提供了一种偏置生成电路以及存储电路。本公开实施例提供的偏置生成电路中，一方面，稳压电路耦接偏置电路的输出端和调整节点，另一方面，第二负载电路的一端也与偏置电路的输出端和调整节点耦接，因此可以利用稳压电路和第二负载电路两者共同调节调整节点的电压。如此，在工作电压稳定时，稳压电路可以将调整节点的电压控制在固定电压值，使得通过偏置电路的电流稳定，从而输出稳定的偏置电压，而在工作电压过大时，相较于没有第二负载电路的偏置生成电路，可以通过第二负载电路增大偏置电路中的电流，有利于避免偏置电路输出的偏置电压随工作电压的变动而变得过大或过小，从而有利于使得偏置电路输出数值范围稳定的偏置电压，以使得其他接 收偏置电压以进行工作的电路处于稳定工作状态。

Claims (16)

  1. 一种偏置生成电路，包括：
    第一负载电路，所述第一负载电路耦接于工作电压和调整节点之间；
    偏置电路，接收所述工作电压并根据所述工作电压输出偏置电压；
    稳压电路，所述稳压电路耦接所述偏置电路的输出端并接收基准电压，用于根据所述偏置电压和所述基准电压调整所述调整节点的电压；
    第二负载电路，所述第二负载电路的一端与所述偏置电路的输出端耦接，另一端与所述调整节点耦接。
  2. 如权利要求1所述的偏置生成电路，其中，所述稳压电路包括：
    运算放大器，所述运算放大器的第一输入端接收所述基准电压，所述运算放大器的第二输入端与所述调整节点耦接；
    驱动电路，所述驱动电路与所述运算放大器的输出端耦接并接收所述偏置电压，用于根据所述运算放大器的输出和所述偏置电压调整所述调整节点的电压；
    反馈电路，所述反馈电路耦接在所述调整节点与地端之间。
  3. 如权利要求2所述的偏置生成电路，其中，所述反馈电路包括第一电阻，所述第一电阻耦接在所述调整节点与所述地端之间。
  4. 如权利要求2所述的偏置生成电路，其中，所述驱动电路包括第一NMOS管，所述第一NMOS管的控制端与所述运算放大器的输出端耦接，所述第一NMOS管的第一端与所述偏置电路的输出端耦接，所述第一NMOS管的第二端与所述调整节点耦接。
  5. 如权利要求1所述的偏置生成电路，其中，所述第一负载电路包括第二电阻，所述第二电阻耦接在所述工作电压与所述调整节点之间。
  6. 如权利要求1所述的偏置生成电路，其中，所述第一负载电路包括：第一MOS管，所述第一MOS管的第一端与所述工作电压耦接，所述第一MOS管的第二端与所述调整节点耦接，所述第一MOS管响应于第一控制电压信号以导通所述第一MOS管的第一端与所述第一MOS管的第二端。
  7. 如权利要求1所述的偏置生成电路，其中，所述第一负载电路包括：
    第二电阻，所述第二电阻一端与所述工作电压耦接；
    第一MOS管，所述第一MOS管的第一端与所述第二电阻的另一端耦接，所述第一MOS管的第二端与所述调整节点耦接，所述第一MOS管响应于第一控制电压信号 以导通所述第一MOS管的第一端与所述第二端。
  8. 如权利要求7所述的偏置生成电路，其中，所述第二负载电路包括：第二MOS管，所述第二MOS管的控制端与所述第一MOS管的第一端耦接，所述第二MOS管的第一端与所述偏置电路的输出端耦接，所述第二MOS管的第二端与所述调整节点耦接。
  9. 如权利要求7所述的偏置生成电路，其中，所述第二负载电路包括：
    第三电阻，所述第三电阻一端与所述偏置电路的输出端耦接；
    第二MOS管，所述第二MOS管的控制端与所述第一MOS管的第一端耦接，所述第二MOS管的第一端与所述第三电阻的另一端耦接，所述第二MOS管的第二端与所述调整节点耦接。
  10. 如权利要求8或9所述的偏置生成电路，其中，所述第一MOS管的类型为N型或者P型中的一者，所述第二MOS管的类型为N型或者P型中的另一者。
  11. 如权利要求1所述的偏置生成电路，其中，所述第二负载电路包括：第三电阻，所述第三电阻耦接在所述偏置电路的输出端与所述调整节点之间。
  12. 如权利要求1所述的偏置生成电路，其中，所述偏置电路包括：第三MOS管，所述第三MOS管的控制端与所述偏置电路的输出端耦接，所述第三MOS管的第一端与所述工作电压耦接，所述第三MOS管的第二端与所述偏置电路的输出端耦接。
  13. 如权利要求12所述的偏置生成电路，其中，所述偏置电路还包括：第四MOS管，所述第四MOS管的第一端与所述第三MOS管的第二端耦接，所述第四MOS管的第二端与所述偏置电路的输出端耦接，所述第四MOS管的控制端响应于第二控制电压信号导通所述第四MOS管的第一端与第二端。
  14. 如权利要求1所述的偏置生成电路，其中，还包括：开关电路，用于响应于使能信号导通，以使所述第一负载电路经由所述开关电路与所述工作电压耦接，以及使所述偏置电路经由所述开关电路接收所述工作电压。
  15. 如权利要求14所述的偏置生成电路，其中，所述开关电路包括第六MOS管。
  16. 一种存储电路，包括：
    如权利要求1-15任一项所述的偏置生成电路；
    输入缓冲电路，所述输入缓冲电路与所述偏置电路的输出端耦接。
PCT/CN2022/099536 2022-03-11 2022-06-17 偏置生成电路以及存储电路 WO2023168850A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102103950A (zh) * 2011-02-28 2011-06-22 朱虹 有声光提醒的直流电源保险丝监测装置
US20110309808A1 (en) * 2010-06-16 2011-12-22 Aeroflex Colorado Springs Inc. Bias-starving circuit with precision monitoring loop for voltage regulators with enhanced stability
CN102386040A (zh) * 2011-11-17 2012-03-21 韩春龙 直流电源保险丝声光提醒电路
CN103455072A (zh) * 2012-06-05 2013-12-18 国民技术股份有限公司 一种自适应偏置电路以及稳压电路
CN110377088A (zh) * 2019-07-10 2019-10-25 深圳市锐能微科技有限公司 一种集成电路、低压差线性稳压电路及其控制方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110309808A1 (en) * 2010-06-16 2011-12-22 Aeroflex Colorado Springs Inc. Bias-starving circuit with precision monitoring loop for voltage regulators with enhanced stability
CN102103950A (zh) * 2011-02-28 2011-06-22 朱虹 有声光提醒的直流电源保险丝监测装置
CN102386040A (zh) * 2011-11-17 2012-03-21 韩春龙 直流电源保险丝声光提醒电路
CN103455072A (zh) * 2012-06-05 2013-12-18 国民技术股份有限公司 一种自适应偏置电路以及稳压电路
CN110377088A (zh) * 2019-07-10 2019-10-25 深圳市锐能微科技有限公司 一种集成电路、低压差线性稳压电路及其控制方法

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