WO2023142401A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2023142401A1
WO2023142401A1 PCT/CN2022/107279 CN2022107279W WO2023142401A1 WO 2023142401 A1 WO2023142401 A1 WO 2023142401A1 CN 2022107279 W CN2022107279 W CN 2022107279W WO 2023142401 A1 WO2023142401 A1 WO 2023142401A1
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WO
WIPO (PCT)
Prior art keywords
sub
pixel
display area
circuit
pixels
Prior art date
Application number
PCT/CN2022/107279
Other languages
English (en)
French (fr)
Inventor
王刚
解红军
刘雨生
丁立薇
米磊
Original Assignee
昆山国显光电有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昆山国显光电有限公司 filed Critical 昆山国显光电有限公司
Priority to KR1020237039046A priority Critical patent/KR20230163569A/ko
Priority to JP2023571223A priority patent/JP2024519027A/ja
Publication of WO2023142401A1 publication Critical patent/WO2023142401A1/zh
Priority to US18/488,465 priority patent/US20240065029A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/353—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels characterised by the geometrical arrangement of the RGB subpixels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/60—OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes
    • H10K59/65—OLEDs integrated with inorganic image sensors

Definitions

  • the present application relates to the display field, in particular to a display panel and a display device.
  • sub-pixels can be arranged in the photosensitive region where photosensitive components such as cameras are located, and pixel circuits corresponding to these sub-pixels can be arranged in other positions of the display region.
  • the pixel circuits close to the frame display area are arranged in other positions. All of the above will lead to uneven arrangement density of pixel circuits in the display area, resulting in display differences in the display panel.
  • Embodiments of the present application provide a display panel and a display device, aiming at improving the display effect of the display panel.
  • the embodiment of the first aspect of the present application provides a display panel, the display panel has a first display area and a second display area, the display panel includes: a plurality of pixel blocks, including a plurality of sub-pixels, each pixel block includes a plurality of sub-pixels a sub-pixels, the plurality of sub-pixels include a first sub-pixel located in the first display area and a second sub-pixel located in the second display area; a plurality of circuit blocks located in the second display area, each circuit block includes b pixel circuits, The b pixel circuits include a first circuit and a second circuit, at least part of the first circuit is used to drive the first sub-pixel, and the second circuit is used to drive the second sub-pixel; where a and b are both positive integers greater than 0, And a is smaller than b, in the second display area, the orthographic projection of each circuit block along the thickness direction of the display panel is located within the orthographic projection of each pixel block along the thickness direction.
  • the embodiment of the second aspect of the present application provides a display device, which includes the display panel of the above-mentioned embodiment of the first aspect.
  • the circuit block is located in the second display area, that is, the pixel circuits for driving the first sub-pixel and the second sub-pixel are both located in the second display area, which can make the first display
  • the light transmittance of the region is greater than the light transmittance of the second display region.
  • the display panel can integrate a photosensitive component on the back of the first display area, so as to realize the under-screen integration of the photosensitive component such as a camera.
  • a driving circuit such as a shift register of the display panel may be disposed in the first display area, so as to realize a narrow frame design of the display panel.
  • the circuit blocks are in the second display area, each pixel block includes b pixel circuits, and the pixel block in the second display area includes a second sub-pixels, and b is greater than a , so that the redundant first circuits in at least part of the circuit blocks can drive the first sub-pixels in the first display area.
  • the orthographic projection of each circuit block along the thickness direction of the display panel is located within the orthographic projection of each pixel block along the thickness direction. On the one hand, it can ensure that the arrangement of the circuit blocks in the second display area is the same as that of the pixel blocks.
  • the arrangement of the circuit blocks is more uniform, and the display effect of the second display area is improved, thereby improving the display effect of the display panel.
  • the distance between the second circuit in at least part of the circuit block and the second sub-pixel it drives can be reduced, the length of the wiring between at least part of the second circuit and the second sub-pixel can be reduced, and the stability of signal transmission can be ensured.
  • Fig. 1 is a schematic structural diagram of a display panel provided by an embodiment of the first aspect of the present application
  • FIG. 2 is a schematic diagram of sub-pixel arrangement structure in an example of the Q region in FIG. 1;
  • FIG. 3 is a schematic diagram of an arrangement structure of a pixel circuit in an example of the Q region in FIG. 1;
  • Fig. 4 is a schematic diagram of sub-pixel arrangement structure in an example of W region in Fig. 1;
  • FIG. 5 is a schematic diagram of an arrangement structure of a pixel circuit in an example of the W region in FIG. 1;
  • FIG. 6 is a schematic diagram of an arrangement structure of a pixel circuit in another example of the Q region in FIG. 1;
  • FIG. 7 is a schematic diagram of sub-pixel arrangement structure in an example of the P region in FIG. 1;
  • FIG. 8 is a schematic diagram of an arrangement structure of a pixel circuit in an example of the P region in FIG. 1;
  • FIG. 9 is a schematic diagram of an arrangement structure of a pixel circuit in another example of the P region in FIG. 1;
  • FIG. 10 is a schematic diagram of sub-pixel arrangement structure in an example of the I region in FIG. 1;
  • FIG. 11 is a schematic diagram of an arrangement structure of pixel circuits in an example of region I in FIG. 1;
  • Fig. 12 is a schematic diagram of sub-pixel arrangement structure in an example of region II in Fig. 1;
  • FIG. 13 is a schematic diagram of an arrangement structure of pixel circuits in an example of region II in FIG. 1;
  • Fig. 14 is a schematic diagram of the arrangement structure of the pixel circuit in another example of the I region in Fig. 1;
  • Fig. 15 is a partial cross-sectional view at C-C in Fig. 2 .
  • a light-transmitting display area may be provided on the above-mentioned electronic device, and a photosensitive component may be arranged on the back of the light-transmitting display area, so as to realize full-screen display of the electronic device while ensuring normal operation of the photosensitive component.
  • the driving circuit of the light-transmitting area is usually arranged in the non-light-transmitting area, which will lead to non-uniform display effect in the non-light-transmitting area of the display panel.
  • the embodiment of the present application provides a display panel 100, which may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel 100.
  • a display panel 100 which may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel 100.
  • OLED Organic Light Emitting Diode
  • FIG. 1 shows a schematic top view of a display panel 100 according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a partially enlarged structure of the Q region in FIG. 1 .
  • FIG. 3 is a schematic diagram of a partially enlarged structure of the Q region in FIG. 1 in another example.
  • Figure 3 and Figure 2 show different layer structures.
  • FIG. 2 shows the layout structure diagram of the sub-pixel 110a at Q in FIG. 1.
  • the difference between FIG. 3 and FIG. 2 is that the second display area AA2 at Q in FIG. 3 shows the layout structure of the pixel circuit 120a. , and retains a schematic diagram of the arrangement structure of the sub-pixels 110a in the first display area AA1.
  • the embodiment of the first aspect of the present application provides a display panel 100 having a first display area AA1 and a second display area AA2.
  • the display panel 100 includes: a plurality of sub-pixels, including The first sub-pixel 111 in the area AA1 and the second sub-pixel 112 in the second display area AA2; a plurality of pixel blocks 110, including a plurality of sub-pixels, each pixel block 110 includes a sub-pixels 110a in the plurality of sub-pixels, and a plurality of sub-pixels
  • the pixel 110a includes a first sub-pixel 111 located in the first display area AA1 and a second sub-pixel 112 located in the second display area AA2; a plurality of circuit blocks 120 are located in the second display area AA2, and each circuit block 120 includes b pixels Circuit 120a, the b pixel circuits 120a include a first circuit 121 and a second circuit 122, at least part of the first circuit 121 is
  • the structures of the pixel block 110 and the circuit block 120 are defined by rectangular frames in FIG. 2 and FIG. 3 , and the rectangular frames do not constitute a limitation on the structure of the display panel 100 of the present application.
  • the rectangular frame includes a small part of the sub-pixels 110a that do not belong to the same pixel block 110, and the sub-pixels 100a within the rectangular frame whose area is greater than 50% of its total area are sub-pixels in the pixel block 110 represented by the rectangular frame 110a.
  • the a sub-pixels 110 a of each pixel block 110 located in the first display area AA1 are all first sub-pixels 111
  • the a sub-pixels 110 a of each pixel block 110 located in the second display area AA2 are all second sub-pixels 112 .
  • the circuit block 120 is located in the second display area AA2, that is, the pixel circuits 120a for driving the first sub-pixel 111 and the second sub-pixel 112 are both located in the second display area AA2 may make the light transmittance of the first display area AA1 greater than the light transmittance of the second display area AA2.
  • the display panel 100 can integrate a photosensitive component on the back of the first display area AA1, so as to realize the under-screen integration of the photosensitive component such as a camera.
  • a driving circuit such as a shift register of the display panel 100 may be disposed in the first display area AA1 to realize a narrow frame design of the display panel 100 .
  • the circuit blocks 120 are in the second display area AA2, and each circuit block 120 includes b pixel circuits 120a, and the pixel block 110 includes a-th pixel circuits 120a located in the second display area AA2.
  • Two sub-pixels 112, b is greater than a
  • a second circuit 122 is set in the circuit block 120 to drive a second sub-pixel 112 in the pixel block 110
  • b-a first circuits 120 can be set in the circuit block 120
  • the circuit At least part of the first circuit 121 in the block 120 may drive the first sub-pixel 111 in the first display area AA1.
  • the orthographic projection of each circuit block 120 along the thickness direction of the display panel 100 is located within the orthographic projection of each pixel block 110 along the thickness direction.
  • the arrangement is the same as the arrangement of the plurality of second sub-pixels 112 in the pixel block 110 , and the arrangement of the circuit blocks 120 is more uniform, which improves the display effect of the second display area AA2 .
  • the distance between at least part of the second circuit 122 in the circuit block 120 and the second sub-pixel 112 it drives can be reduced, and the length of the wiring between at least part of the second circuit 122 and the second sub-pixel 112 can be reduced to ensure that the signal Transmission stability.
  • the pixel block 110 in the second display area AA2 includes a number of second sub-pixels 112
  • the pixel block 110 in the first display area AA1 includes a number of first sub-pixels 111 . If there is a part of the display area located between the first display area AA1 and the second display area AA2, the pixel block 110 between the first display area AA1 and the second display area AA2 may further include the first sub-pixel 111 and the second sub-pixel 111. There are two sub-pixels 112, and the sum of the numbers of the first sub-pixel 111 and the second sub-pixel 112 is a.
  • the circuit block 120 may include b first circuits 121 or b second circuits 122 .
  • the pixel circuit 120a may include both the first circuit 121 and the second circuit 122, and the sum of the numbers of the first circuit 121 and the second circuit 122 is b.
  • the orthographic projection area of each pixel block 110 along the thickness direction overlaps with the orthographic projection area of the circuit block 120 along the thickness direction, so that the area of the pixel circuit 120a in the pixel block 110 is relatively small. big.
  • the distribution areas of the first circuit 121 and the second circuit 122 are equal, which can further improve the display effect of the second display area AA2, and avoid the unequal distribution areas of the first circuit 121 and the second circuit 122 Instead, a display difference appears.
  • the first circuit 121 and the second circuit 122 have the same circuit structure, except that part of the first circuit 121 is used to drive the first sub-pixel 111 , and the second circuit 122 is used to drive the second sub-pixel 112 .
  • the orthographic projection of the circuit block 120 along the thickness direction of the display panel 100 is the orthographic projection of the circuit block 120 on the display surface of the display panel 100 .
  • the orthographic projection of the pixel block 110 along the thickness direction is the orthographic projection of the pixel block 110 on the display surface of the display panel 100 .
  • the orthographic projection of the pixel block 110 along the thickness direction of the display panel 100 is the area where the orthographic projection of the a sub-pixels 110a in the pixel block 110 along the thickness direction of the display panel 100 is located.
  • the area where the pixel block 110 is located is the arrangement area occupied by a sub-pixels 110a in the pixel arrangement structure.
  • the arrangement size of a single sub-pixel 110a is 1cm ⁇ 1cm, that is, a single sub-pixel 110a along the display
  • the dimension of the orthographic projection in the thickness direction of the panel 100 is 1cm ⁇ 1cm, and the area where the pixel block 110 is located is a region formed by a 1cm ⁇ 1cm. 1cm.
  • the a sub-pixels 110a in the pixel block 110 are adjacently arranged.
  • the 16 sub-pixels 110a in the pixel block 110 are arranged adjacently.
  • the 16 sub-pixels 110a may be located in the same row or in two or more adjacent rows.
  • the row direction may be the first direction X
  • the column direction may be the second direction Y.
  • the row direction may also be the second direction Y
  • the column direction may be the first direction X.
  • the sub-pixels 110a of the display panel 100 are arranged to form a pixel arrangement structure
  • the pixel arrangement structure includes a repeating unit
  • the repeating unit includes a plurality of sub-pixels 110a
  • the repeating unit is arranged along the row direction and the column direction
  • the repeated arrangement forms a pixel arrangement structure.
  • the number of sub-pixels 110a included in the pixel block 110 may be related to the number of sub-pixels 110a included in the repeating unit, for example, the number of sub-pixels 110a included in the pixel block 110 is an integer multiple of the number of sub-pixels 110a included in the repeating unit. For example, as shown in FIG.
  • the pixel block 110 when the repeating unit includes 4 sub-pixels 110a, the pixel block 110 includes 16 sub-pixels 110a, and the number of sub-pixels 110a included in the pixel block 110 is 4 times the number of sub-pixels 110a included in the repeating unit, That is, the pixel block 110 includes 4 repeating units, and the orthographic projection of the pixel block 110 along the thickness direction is the arrangement size occupied by the 4 repeating units.
  • the orthographic projection of the circuit block 120 along the thickness direction of the display panel 100 is the area where the orthographic projection of the b sub-pixel 110 a circuits in the circuit block 120 along the thickness direction is located.
  • the b pixel circuits 120a in the circuit block 120 are adjacently arranged.
  • b is equal to 25 and the circuit block 120 includes 25 pixel circuits 120a
  • these 25 pixel circuits 120a are arranged adjacently.
  • the 25 pixel circuits 120a may be located in the same row or in two or more rows.
  • b pixel circuits 120a in the circuit block 120 are arranged in a row.
  • the pixel circuits 120a in the circuit block 120 are compressed in the row direction, so that the orthographic projections of the b pixel circuits 120a along the thickness direction are within the orthographic projections of the a sub-pixels 110a along the thickness direction.
  • the pixel block 110 includes a plurality of sub-pixels 110a arranged in p rows and q columns, and the product of p and q is a;
  • the circuit block 120 includes a plurality of pixel circuits 120a arranged in e rows and f columns, The product of e and f is b, where p, q, e, and f are all positive integers greater than 1, e ⁇ p, f ⁇ q.
  • p, q, e, and f are all positive integers greater than 1, so the pixel block 110 includes sub-pixels 110a arranged in multiple rows and columns, and the circuit block 120 includes sub-pixels 110a arranged in multiple rows and columns.
  • the pixel circuit 120a enables the pixel circuit 120a to be compressed in both the row direction and the column direction, so as to avoid technical difficulties caused by the pixel circuit 120a being compressed in the same direction.
  • the pixel block 110 includes sub-pixels 110a in p rows and p columns
  • the circuit block 120 includes pixel circuits 120a in e rows and e columns, so that the arrangement of multiple sub-pixels 110a in the pixel block 110 is more regular, and the multiple pixel circuits in the circuit block 120
  • the arrangement of 120a is more regular, and it is easier to adjust the size of the pixel circuit 120a.
  • the pixel block 110 when a is equal to 16 and the pixel block 110 includes 16 sub-pixels 110 a, the pixel block 110 includes 4 rows and 4 columns of sub-pixels 110 a.
  • the circuit block 120 when b is equal to 25 and the circuit block 120 includes 25 pixel circuits 120a, the circuit block 120 includes pixel circuits 120a with 5 rows and 5 columns.
  • pixel circuits 120 of 5 rows and 5 columns are arranged in the area where the sub-pixels 110a of 4 rows and 4 columns are located.
  • the sub-pixel circuits 120 of 4 rows and 4 columns The number of pixel circuits 120a set in the area where the pixel 110a is located is greater than the number of sub-pixels 110a, and at least part of the redundant pixel circuits 120a in one row and one column in the area where the sub-pixels 110a in four rows and four columns are located can be used to drive the first display area The first sub-pixel 111 in AA1.
  • FIG. 4 is a schematic diagram of the arrangement structure of the sub-pixel 110 a at W in FIG. 1 ;
  • FIG. 5 is a schematic diagram of the arrangement structure of the pixel circuit 120 a at W in FIG. 1 .
  • the second display area AA2 includes a main display area ZA and a transitional display area TA, and the transitional display area TA is located between the main display area ZA and the first display area AA1 During this period, at least part of the first circuit 121 located in the transition display area TA is used to drive the first sub-pixel 111 . That is, the area where the first circuit 121 for driving the first sub-pixel 111 is located is the transitional display area TA, and the area where the first circuit 121 is not used for driving the first sub-pixel 111 is located is the main display area ZA.
  • the first circuit 121 for driving the first sub-pixel 111 is arranged in the transition display area TA that is closer to the first display area AA1, which can reduce the number of first circuits that are electrically connected to each other.
  • the distance between the first circuit 121 and the first sub-pixel 111 reduces the length of the connection between the first circuit 121 and the first sub-pixel 111 to ensure the stability of signal transmission.
  • each circuit block 120 in the main display area ZA is located within the orthographic projection of each pixel block 110 driven by it, and each circuit block 120 in the main display area ZA includes second circuits 122 in p rows and q columns and ( e-p) First circuit 121 of rows (f-q) columns.
  • the first circuit 121 in the (e-p) row (f-q) column refers to the (e-p) row (f-q) column in the circuit block 120 in the e row and f column.
  • each circuit block 120 in the main display area ZA includes second circuits 122 with 4 rows and 4 columns and first circuits 121 with 1 row and 1 column, and the first circuit 121 with 1 row and 1 column refers to pixels with 5 rows and 5 columns. 1 row and 1 column of first circuits 121 in the circuit 120a.
  • each circuit block 120 in the main display area ZA includes 16 second circuits 122 and 9 first circuits 121 .
  • the number of second circuits 122 included in the circuit block 120 in the main display area ZA is the same as the number of second sub-pixels 112 included in the pixel block 110, so the second circuits in each circuit block 120 122 may be used to drive the second sub-pixels 112 in each pixel block 110 .
  • Each circuit block 120 in the main display area ZA is located within the orthographic projection of each pixel block 110 driven by it, which can reduce the distance between the second circuit 122 and the second sub-pixel 112 driven by it, and reduce the second The length of the connection between the circuit 122 and the second sub-pixel 112 driven by it.
  • the relative positional relationship of the plurality of second circuits 122 in the circuit block 120 is the same as the relative positional relationship of the plurality of second sub-pixels 112 in the pixel block 110, so as to further reduce the number of second circuits 122
  • the distance between the second circuit 122 and the second sub-pixel 112 driven by it reduces the connection length between the second circuit 122 and the second sub-pixel 112 driven by it.
  • the relative positional relationship between the second circuit 122 and the second sub-pixel 112 driven by it in the main display area ZA can be arranged in various ways.
  • the orthographic projection of the second circuit 122 and the second sub-pixel 112 driven by it along the thickness direction is at least partially overlapped, which can further reduce the distance between the second circuit 122 and the second sub-pixel 112 driven by it. , reducing the length of the connection between the second circuit 122 and the second sub-pixel 112 driven by it.
  • the orthographic projection of the second circuit 122 and the second sub-pixel 112 driven by it along the thickness direction is misaligned, as long as the orthographic projection of the circuit block 120 where the second circuit 122 is located along the thickness direction is located in the second sub-pixel driven by it It only needs to be within the orthographic projection of the pixel block 110 where 112 is located along the thickness direction.
  • the first circuit 121 in the circuit block 120 is located on one side of the second circuit 122 in the row direction, or the first circuit 121 is located on one side of a plurality of second circuits 122 in the column direction. .
  • the first circuit 121 is located in the middle of the plurality of second circuits 122 in the row direction and/or the column direction. In order to reduce the dislocation size between the second circuit 122 and the second sub-pixel 112 driven by it, the length of the wiring between the second circuit 122 and the second sub-pixel 112 driven by it is reduced.
  • first circuit 121 and the second circuit 122 are many ways to arrange the first circuit 121 and the second circuit 122 in the transitional display area TA.
  • first circuit 121 in the transitional display area TA The arrangement of the first circuit 121 and the second circuit 122 in the main display area ZA is the same as that of the first circuit 121 and the second circuit 122 . That is, each circuit block 120 in the transition display area TA is located within the orthographic projection of each pixel block 110 driven by it, and the circuit block 120 in the transition display area TA includes the second circuit 122 of p row q column and (e-p) row (f-q ) column of the first circuit 121.
  • the display difference between the transition display area TA and the main display area ZA can be further improved, and the distance between the second circuit 122 in the transition display area TA and the second sub-pixel 112 driven by it can be reduced, reducing the second The length of the connection between the circuit 122 and the second sub-pixel 112 driven by it.
  • the relative positional relationship of the plurality of second circuits 122 in the circuit block 120 is the same as the relative positional relationship of the plurality of second sub-pixels 112 in the pixel block 110 .
  • the first circuits 121 include a plurality of row circuits 121a arranged side by side along the row direction and a plurality of row circuits 121a arranged side by side along the column direction.
  • the column circuit 121b, at least part of the row circuit 121a and/or the column circuit 121b are used to drive the first sub-pixel 111 .
  • the row circuit 121a refers to a plurality of first circuits 121 arranged in a row direction
  • the column circuit 121b refers to a plurality of first circuits 121 arranged in a column direction. There is an intersection between the row direction and the column direction, so the first circuit 121 at the intersection position can be either the row circuit 121a or the column circuit 121b.
  • no second circuit 122 is provided in the row where the row circuit 121a is located, and no second circuit 122 is provided in the column where the column circuit 121b is located.
  • the connection between the first sub-pixel 111 and the second circuit 122 and the connection between the second sub-pixel 112 and the second circuit 122 can be avoided. Wire crosstalk.
  • the distribution image of the first circuit 121 is grid-like and has a hollowed-out area, and a plurality of second circuits 122 are located in the hollowed-out area, that is, at least two first circuits 121 are arranged at intervals, and at least some of the second circuits 122 are located in adjacent Between the two first circuits 121 , the first circuits 121 are arranged around a plurality of second circuits 122 . That is, in the circuit block 120 , the first circuits 121 are concentrated in the same row and arranged in the same column, so that the arrangement of the plurality of second circuits 122 in the circuit block 120 is more concentrated.
  • the sub-pixels 111 are arranged in a row with at least part of the first sub-pixels 111 in the regular area.
  • the special-shaped area may include a corner area RA, and the corner area RA surrounds the second display area AA2 and is bent.
  • the first display area AA1 includes a corner area RA
  • the pixel circuit 120a corresponding to the first sub-pixel 111 in the corner area RA is located in the second display area AA2, and then drive circuits such as shift registers and drivers can be set in the corner area RA.
  • the signal lines can reduce the frame size of the display panel 100 .
  • the shaped area may also include a photosensitive area UDC
  • the second display area AA2 is arranged around at least part of the photosensitive area UDC.
  • the pixel circuit 120a corresponding to the first sub-pixel 111 in the photosensitive area UDC is located in the second display area AA2, which can improve the light transmittance of the photosensitive area UDC, and facilitate the photosensitive component to be placed in the photosensitive area. Realize off-screen integration in UDC.
  • the photosensitive area UDC can display pictures, increase the display area of the display panel 10010, and realize the full-screen design of the display device.
  • the first display area AA1 includes a frame display area BA
  • the frame display area BA is arranged around the second display area AA2
  • the frame display area BA includes at least one frame located in the second display area AA2 in the column direction.
  • the side end bezel display area BA1 and the side bezel display area BA2 located on at least one side of the second display area AA2 in the row direction.
  • the pixel circuit 120a corresponding to the first sub-pixel 111 in the border display area BA is located in the second display area AA2, and then a shift register or the like can be set in the border display area BA to drive
  • the circuit and the driving signal lines can reduce the size of the frame of the display panel 100 and realize the design of the display panel 100 with a narrow frame or even no frame.
  • the regular area may include the above-mentioned frame display area BA, and the regular area may also include part of the first display area AA1 located on at least one side of the photosensitive area UDC in the row direction.
  • the corner area RA may be connected between the adjacent end bezel display area BA1 and side bezel display area BA2.
  • the first sub-pixels 111 located in different regions can be driven by different first circuits 121 .
  • at least part of the row circuits 121a are used to drive the first sub-pixels 111 located in the deformed region.
  • the first sub-pixels 111 in the same row in the heterogeneous area can be driven by the row circuit 121a in the same row, which can simplify the wiring between the first sub-pixel 111 and the row circuit 121a.
  • the first sub-pixels 111 in the special-shaped area are driven by the row circuit 121a, only need to add row signal lines to transmit the driving signals to the row circuit 121a, without adding column signal lines, and can reduce the size of the second display area AA2. Number of wires for signal lines.
  • the first sub-pixels 111 in the photosensitive area UDC may be driven by the row circuit 121a.
  • each row of first subpixels 111 in the first display area AA1 may be driven by row circuits 121a of different rows, that is, the first subpixels 111 of different rows are driven by row circuits 121a of different rows. drive.
  • multiple rows of first sub-pixels 111 in the first display area AA1 can also be driven by row circuits 121 a of the same row, that is, more than two rows of first sub-pixels 111 can use The row circuits 121a of the same row are driven.
  • a row signal line may be added in the transition display area TA to transmit the driving signal to the row circuit 121a.
  • the display panel 100 further includes a first row of signal lines 131 and a second row of signal lines 132 , and the first row of signal lines 131 is connected to the row for driving the first sub-pixels 111
  • the circuit 121a is also used to transmit signals thereto
  • the second row signal line 132 is connected to the second circuit 122 and used to transmit signals thereto.
  • the addition of the first row signal line 131 can transmit the driving signal to the row circuit 121a, so that the row circuit 121a can drive the first sub-pixel 111 to display.
  • FIG. 7 is a schematic diagram of the arrangement result of the sub-pixel 110 a at P in FIG. 1
  • FIG. 8 is a schematic structural diagram of the pixel circuit 120 a at P in FIG. 1 .
  • the first sub-pixel 111 in the corner area RA is reserved in FIG. 8 .
  • the first sub-pixels 111 in the corner area RA may be driven by the row circuits 121 a of the second display area AA2 .
  • multiple rows of first sub-pixels 111 in the corner area RA may be driven by multiple rows of circuits 121a.
  • FIG. 9 multiple rows of first sub-pixels 111 in the corner area RA may be driven by row circuits 121 a of the same row.
  • the display panel 100 further includes column signal lines (not shown in the figure) extending along the column direction for transmitting driving signals to the first circuit 121 and/or the second circuit 122 arranged in the same column.
  • first row signal lines 131 and the second row signal lines 132 may be scanning signal lines, and the column signal lines may be data signal lines.
  • first row signal lines 131 and the second row signal lines 132 may also be data signal lines, and the column signal lines may be scan signal lines.
  • the display panel 100 further includes a line buffer (not shown in the figure), the line buffer is used to store the driving signal of the first sub-pixel 111 in the shaped area, and The driving signal of the pixel 111 is transmitted to the first row signal line 131 .
  • the row buffer stores the driving signal of the first sub-pixel 111 in the irregular area, and the row buffer can transmit the driving signal to the first row signal line 131, and then drive the row circuit 121a through the first row signal line 131 .
  • the display panel 100 includes a pixel jump reduction (PJR) processing module, and the PJR processing module has functions of copying and shifting images.
  • the PJR processing module has functions of copying and shifting images.
  • the first sub-pixel is added to the position of the row circuit 121a for driving the first sub-pixel 111 in the image data 111 corresponding to the data, and store these data in the row buffer.
  • the PJR processing module is connected to the digital-to-analog conversion module, so as to convert the image data into an analog voltage signal through the digital-to-analog conversion module.
  • the second display area can
  • the first circuit 121 of AA2 drives the first sub-pixel 111 to emit light.
  • FIG. 10 is a schematic diagram of the arrangement structure of the sub-pixel 110a at I in FIG. 1
  • FIG. 11 is a schematic diagram of the arrangement structure of the pixel circuit 120a at I in FIG.
  • the first sub-pixel 111 located in the end bezel display area BA1 is removed.
  • Fig. 12 is a schematic diagram of the arrangement structure of the sub-pixel 110a at II in Fig. 1
  • Fig. 13 is a schematic diagram of the arrangement structure of the pixel circuit 120a at II in Fig. sub-pixel 111 .
  • the first sub-pixels 111 in the frame display area BA are arranged in rows and columns.
  • the first sub-pixels 111 in the end bezel display area BA1 are arranged in multiple rows, and the number of first sub-pixels 111 arranged in one row in the end bezel display area BA1 is less than or equal to that in the transition display area
  • the number of row circuits 121a arranged in a row in TA is less than or equal to that in the transition display area.
  • the first sub-pixels 111 of the same row in the end bezel display area BA1 can be driven by the row circuits 121a arranged in the same row in the transition display area TA, and the original sub-pixels 111 used to drive the first sub-pixels of the same row in the end bezel display area BA1 can be driven.
  • the row signal line of the pixel 111 may be diverted to the transition display area TA to connect to the row circuit 121 a for driving the first sub-pixel 111 .
  • the first sub-pixels 111 in the side frame display area BA2 are arranged in multiple columns, and the number of first sub-pixels 111 arranged in the same column in the side frame display area BA2 is less than or equal to that of the transition display
  • the number of column circuits 121b arranged in the same column in the area TA Therefore, the first sub-pixels 111 in the same column in the side bezel display area BA2 can be driven by the row circuit 121a arranged in the same column in the transition display area TA, and the original sub-pixels 111 in the same column in the side bezel display area BA2 can be driven.
  • the column signal line of the pixel 111 may be diverted to the transition display area TA to connect to the column circuit 121b for driving the first sub-pixel 111 .
  • At least part of the row circuit 121a is used to drive the first sub-pixel 111 located in the end bezel display area BA1
  • at least part of the column circuit 121b is used to drive to drive the first sub-pixels 111 located in the side bezel display area BA2.
  • the wiring of the signal lines of the display panel 100 can be further simplified without adding row signal lines or column signal lines.
  • the above is how to use the first circuit 121 in the transition display area TA to drive the first sub-pixel 111 when the arrangement of the circuit blocks 120 in the transition display area TA and the circuit blocks 120 in the main display area ZA is the same.
  • the arrangement of the circuit blocks 120 in the transitional display area TA may be different from the arrangement of the circuit blocks 120 in the main display area ZA.
  • FIG. 14 is a schematic diagram of a pixel arrangement structure at position I in FIG. 1 in another embodiment.
  • the first circuits 121 in the transitional display area TA are all located on the side of the second circuit 122 close to the first sub-pixel 111 .
  • the first circuit 121 in the transitional display area TA is arranged closer to the first display area AA1 , which can reduce the distance between the first circuit 121 and the first sub-pixel 111 driven by it.
  • the positional relationship between the second circuit 122 for driving the second sub-pixel 112 in the transition display area TA and the first circuit 121 for driving the first sub-pixel 111 in the transition display area TA is the same as that in the transition display area TA.
  • the positional relationship between the second sub-pixel 112 and the first sub-pixel 111 in the first display area AA1 is the same.
  • Such setting can reduce the distance between the second circuit 122 and the second sub-pixel 112 driven by it, and the distance between the first circuit 121 and the first sub-pixel 111 driven by it in the transitional display area TA, Furthermore, crossing between the signal lines connecting the first circuit 121 and the first sub-pixel 111 and the signal lines connecting the second circuit 122 and the second sub-pixel 112 can be avoided, thereby simplifying the wiring of the signal lines.
  • the signal line for driving the first sub-pixel 111 is connected to the first circuit 121 for driving the first sub-pixel 111, that is, Can.
  • the plurality of first circuits 121 in the transition display area TA are arranged according to the arrangement of the plurality of first sub-pixels 111 driven by them, and the plurality of first circuits 121 are sequentially connected to the first sub-pixels 111 in a relay manner, that is, The lengths of the multiple signal lines for connecting the first circuit 121 and the first sub-pixel 111 can be made to be consistent, and the multiple signal lines can be prevented from intersecting each other.
  • FIG. 14 only schematically shows the connection relationship between the first sub-pixel 111 and the first circuit 121 in the end bezel display area BA1 .
  • the first display area AA1 may further include a corner area RA, a photosensitive area UDC, and a side frame display area BA2, for driving the first display area in the corner area RA, the photosensitive area UDC, and the side frame display area BA2.
  • the first circuit 121 of the sub-pixel 111 is located on a side of the second circuit 122 close to the corner area RA, the photosensitive area UDC and the side frame display area BA2. That is, the corner area RA, the photosensitive area UDC, and the first sub-pixel 111 in the side frame display area BA2 and the first circuit 121 in the transition display area TA can also be connected to each other in a relay manner.
  • the corner area RA, the photosensitive area UDC, and the side frame display area BA2 The relative positional relationship between the first sub-pixel 111 in the front frame display area BA2 and the second sub-pixel 112 in the transition display area TA is related to the relationship in the transition display area TA for driving the corner area RA, the photosensitive area UDC and the side frame display area BA2
  • the relative positions of the first circuit 121 and the second circuit 122 in the first sub-pixel 111 are the same.
  • FIG. 15 is a cross-sectional view at C-C in FIG. 3 .
  • the display panel 100 further includes: a signal line layer 103, including a first connection signal line 133, and the first connection signal line 133 is used to connect the first circuit 121 and the first sub-pixel 111 .
  • crosstalk between the first connection signal line 133 and other signal lines can be avoided by setting the signal line layer 103 .
  • the display panel 100 further includes a substrate 101 , an array substrate disposed on the substrate 101 , and a pixel definition layer 102 , and the pixel circuit 120a is disposed on the array substrate.
  • the pixel definition layer 102 includes a first pixel opening K1 located in the first display area AA1 and a second pixel opening K2 located in the second display area AA2.
  • the first sub-pixel 111 includes a first light emitting structure 111b located in the first pixel opening K1, a first electrode 111a located on the side of the first light emitting structure 111b facing the array substrate, and a first electrode 111a located on the side of the first light emitting structure 111b facing away from the array substrate.
  • the second sub-pixel 112 includes a second light emitting structure 121b located in the second pixel opening K2, a third electrode 121a located on the side of the second light emitting structure 121b facing the array substrate, and a third electrode 121a located on the side of the second light emitting structure 121b facing away from the array substrate.
  • the first electrode 111a and the third electrode 121a are, for example, pixel electrodes, and the second electrode 111c and the fourth electrode 121c may be interconnected as a common electrode.
  • the signal line layer 103 may be located between the array substrate and the light emitting layer.
  • the array substrate may include a first metal layer, a second metal layer and a third metal layer
  • the pixel circuit 120a includes a thin film transistor (TFT), which is divided into a switching thin film transistor and a driving thin film transistor.
  • TFT thin film transistor
  • a thin film transistor (TFT) includes a semiconductor layer, a gate and source-drain electrodes, the gate may be located on the first metal layer, and the source-drain electrodes may be located on the third metal layer.
  • One of the plates of the capacitor can be provided on the second metal layer, and the other plate of the capacitor can be located on the first metal layer or the third metal layer.
  • the row signal lines are scan lines, and the row signal lines may be located on the first metal layer and connected to the gates of the switching thin film transistors.
  • the display panel 100 further includes a column signal line located on the data line and on the third metal layer, and the column signal line may be connected to one of the source and drain electrodes of the switching thin film transistor.
  • the source and drain electrodes of the driving thin film transistors of part of the first circuit 121 are connected to the first electrode 111a of the first sub-pixel 111 through the first connection signal line 133 .
  • the first connection signal line 133 is extended along the second direction Y, and the part of the first connection signal line 133 extending along the second direction Y is located on the same film layer.
  • the arrangement size of the first connecting signal lines 133 in the first direction X is m, and the arrangement size of the first sub-pixels 111 adjacent to the second display area AA2 along the second direction Y is n in the first direction X.
  • One of the first direction X and the second direction Y is a row direction, and the other is a column direction. Referring to FIG. 14 , the embodiment of the present application is illustrated by taking the first direction X as the row direction and the second direction Y as the column direction for illustration.
  • the layout size of the first connection signal line 133 in the first direction X includes not only the extension size of the first connection signal line 133 itself in the first direction X, but also two adjacent first connections along the first direction X. A spacing dimension between signal lines 133 .
  • the arrangement size of the first sub-pixels 111 in the first direction X is the same as the average arrangement size of the first sub-pixels 111 in the first direction X. For example, there are i first sub-pixels 111 arranged in the first direction X, the occupied size of the i first sub-pixels 111 in the first direction X is j, and the arrangement size n of the first sub-pixels 111 is equal to j/i.
  • the first sub-pixel 111 adjacent to the second display area AA2 along the second direction Y is adjacent to the first sub-pixel 111'.
  • the first connection signal line 133 connected to the first sub-pixel 111 on the side away from the second display area AA2 adjacent to the first sub-pixel 111' must pass through the adjacent first sub-pixel 111', and the adjacent first sub-pixel 111'
  • the extension in the first direction X is limited.
  • the first display area AA1 includes an end bezel display area BA1
  • two end bezel display areas BA1 are separately arranged on both sides of the second display area AA2
  • one end bezel display area BA1 is in the second direction
  • the extension size of the end bezel display area BA1 in the second direction Y is smaller than or equal to the arrangement size of the k first sub-pixels 111 in the second direction Y.
  • the first display area AA1 is the side bezel display area BA2
  • the first direction X is the column direction
  • the second direction Y is the row direction
  • the two side bezel display areas BA2 are located on both sides of the second display area AA2 .
  • k first sub-pixels 111 are arranged in the first direction X in a side frame display area BA2, and the extension size of the side frame display area BA2 in the first direction X is smaller than or equal to k first sub-pixels 111 The arrangement size along the first direction X.
  • the radius of the photosensitive area UDC is less than or equal to the arrangement size of the k first sub-pixels 111 along the row direction.
  • the arrangement size of the first connection signal lines 133 in the column direction is 5 ⁇ m
  • the arrangement size of the adjacent first sub-pixel 111 in the column direction is 61.7 ⁇ m
  • the most adjacent first sub-pixels 111 can be arranged
  • the number of the first connecting signal lines 133 is 11, and the extension size of the first display area AA1 in the row direction is smaller than or equal to the arrangement size of the 11 first sub-pixels 111 in the row direction.
  • the first connecting signal line 133 includes a first segment 133a and a second segment 133b extending in different directions, the first segment 133a and the second segment 133b They are located in different film layers, so as to improve the short-circuit connection risk of different first connection signal lines 133 .
  • the signal line layer 103 further includes a second connection signal line 134 for connecting the second circuit 122 and the second sub-pixel 112 .
  • the arrangement of the first connection signal line 133 and the second connection signal line 134 in the same layer can reduce the thickness of the display panel 100 .
  • the multiple first circuits 121 for driving the first sub-pixels 111 in the same row are located in the same row, so that the multiple first circuits 121 for driving the first sub-pixels 111 in the same row can be connected on the same first row of signal lines 131 .
  • the first circuits 121 in the same row are used to drive the first sub-pixels 111 in more than two rows.
  • the first display area AA1 includes a special-shaped area
  • the first sub-pixels 111 in more than two rows in the special-shaped area can be driven by the row circuit 121a in the transitional display area TA that is closer to the special-shaped area, so as to reduce the number of first circuits 121 and The distance between the first sub-pixels 111 driven by them.
  • this application reserves the first display area AA1 by setting the pixel circuit 120a in the second display area AA2, which can improve the performance of the first display area AA1.
  • the light transmittance or other driving circuits and driving signal lines are arranged in the first display area AA1 to reduce the frame size of the display panel 100 .
  • the arrangement of the circuit blocks 120 and the pixel blocks 110 in the second display area AA2 is the same, which ensures uniform display effects at different positions in the second display area AA2.
  • the embodiment of the present application also provides two ways of arranging the pixel circuits 120 a and ways of driving the first sub-pixels 111 to display.
  • the circuit blocks 120 in the transitional display area TA are arranged in the same manner as the circuit blocks 120 in the main display area ZA, and the row circuits 121a in the transitional display area TA are used to drive the first sub-sections in the special-shaped area.
  • pixel 111 and transmit the driving signal to the row circuit 121a in the transitional display area TA by adding the first row signal line 131 and the row buffer.
  • this embodiment can ensure that the distance between the second circuit 122 in the transitional display area TA and the main display area ZA is relatively close to the second sub-pixel 112 it drives, and on the other hand, it only needs to add a row signal line to drive the first sub-pixel.
  • the sub-pixel 111 can simplify the wiring of the display panel 100 .
  • the pixel block 110 and the circuit block 120 in the main display area ZA are arranged correspondingly along the thickness direction, which can reduce the distance between the second circuit 122 in the main display area ZA and the second sub-pixel 112 driven by it. distance between.
  • the arrangement of the first circuit 121 and the second circuit 122 in the transition display area TA is the same as the arrangement of the second sub-pixel 112 in the transition display area TA and the first sub-pixel 111 in the first display area AA1, and the transition display
  • the circuit block 120 where the second circuit 122 in the area TA is located is misaligned with the pixel block 110 where the second sub-pixel 112 driven by the second circuit 122 is located, and multiple first circuits 121 are sequentially connected to the first sub-pixels in a relay manner.
  • the lengths of the multiple signal lines for connecting the first circuit 121 and the first sub-pixel 111 can be made to be consistent, and the multiple signal lines can be prevented from intersecting each other.
  • the pixel circuit 120a is placed in the second display area AA2.
  • the circuit structure of the first circuit 121 is any one of a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, or a 9T1C circuit.
  • 2T1C circuit refers to the pixel drive circuit including two thin film transistors (T) and one capacitor (C) in the pixel drive circuit, and other "7T1C circuits", “7T2C circuits”, “9T1C circuits” and so on .
  • the circuit structure of the second circuit 122 is any one of a 2T1C circuit, a 7T1C circuit, a 7T2C circuit, or a 9T1C circuit.
  • the size of the first sub-pixel 111 is smaller than the size of the second sub-pixel 112 of the same color, which can reduce the occupied space of the first sub-pixel 111 in the first display area AA1, so that in the first display area AA1
  • the area of the non-light-emitting area is larger, which is convenient for improving the light transmittance of the first display area AA1.
  • the first sub-pixels 111 and the first circuits 121 are arranged in a one-to-one correspondence. Each first sub-pixel 111 is driven by a corresponding first circuit 121 , which can improve the display effect of the display panel 100 .
  • more than two adjacent first sub-pixels 111 of the same color are connected to the same first circuit 121 , which facilitates the wiring of the display panel 100 .
  • the first sub-pixel 111 includes a first light emitting structure 111b, a first electrode 111a and a second electrode 111c.
  • the second sub-pixel 112 includes a second light emitting structure 121b, a third electrode 121a and a fourth electrode 121c.
  • the first electrode 111 a and the third electrode 121 a are anodes
  • the second electrode 111 c and the fourth electrode 121 c are cathodes as an example for description.
  • the first light-emitting structure 111b and the second light-emitting structure 121b can respectively include an OLED light-emitting layer, and according to the design requirements of the first light-emitting structure 111b and the second light-emitting structure 121b, each can also include a hole injection layer, a hole transport layer, an electron At least one of an injection layer or an electron transport layer.
  • the first electrode 111a is a light-transmitting electrode.
  • the first electrode 111a includes an indium tin oxide (Indium Tin Oxide, ITO) layer or an indium zinc oxide layer.
  • the first electrode 111a is a reflective electrode, including a first transparent conductive layer, a reflective layer on the first transparent conductive layer, and a second transparent conductive layer on the reflective layer.
  • the first light-transmitting conductive layer and the second light-transmitting conductive layer may be ITO, indium zinc oxide, etc.
  • the reflective layer may be a metal layer, such as made of silver.
  • the third electrode 121a may be configured to use the same material as the first electrode 111a.
  • the second electrode 111c includes a magnesium-silver alloy layer.
  • the fourth electrode 121c can be configured to use the same material as the second electrode 111c.
  • the orthographic projection of each first light-emitting structure 111b on the substrate 101 consists of one first graphic unit or more than two first graphic units spliced together.
  • the first graphic unit consists of a circle, a At least one selected from the group consisting of ellipse, dumbbell, gourd, and rectangle.
  • the orthographic projection of each first electrode 111a on the substrate 101 is composed of one second graphic unit or spliced by more than two second graphic units, and the second graphic unit consists of a circle, an ellipse At least one selected from the group consisting of shape, dumbbell shape, gourd shape, and rectangle.
  • the orthographic projection of each second light-emitting structure 121b on the substrate 101 consists of one third graphic unit or more than two third graphic units spliced together.
  • the third graphic unit consists of a circle, a At least one selected from the group consisting of ellipse, dumbbell, gourd, and rectangle.
  • the orthographic projection of each third electrode 121a on the substrate 101 is composed of one fourth graphic unit or spliced by more than two fourth graphic units, and the fourth graphic unit consists of a circle, an ellipse At least one selected from the group consisting of shape, dumbbell shape, gourd shape, and rectangle.
  • the display panel 100 may further include an encapsulation layer, a polarizer and a cover plate located above the encapsulation layer, or a cover plate may be provided directly above the encapsulation layer without a polarizer, or at least in the first display area AA1
  • a cover plate is directly arranged above the encapsulation layer without a polarizer, so as to prevent the polarizer from affecting the amount of light collected by the photosensitive element corresponding to the first display area AA1.
  • a polarizer can also be arranged above the encapsulation layer of the first display area AA1.
  • the embodiment of the second aspect of the present application further provides a display device, including the display panel 100 of any one of the above-mentioned embodiments of the first aspect. Since the display device provided in the embodiment of the second aspect of the present application includes the display panel 100 of any embodiment of the above-mentioned first aspect, the display device provided in the embodiment of the second aspect of the present application has the display panel of any embodiment of the above-mentioned first aspect The beneficial effects of 100 will not be repeated here.
  • the display devices in the embodiments of the present application include but are not limited to mobile phones, personal digital assistants (Personal Digital Assistant, PDA for short), tablet computers, e-books, televisions, access control, smart fixed phones, consoles and other devices with display functions .
  • PDA Personal Digital Assistant

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Abstract

本申请公开了一种显示面板及显示装置，显示面板具有第一显示区和第二显示区，显示面板包括：多个像素块，包括多个子像素，各像素块包括多个子像素中的a个子像素，多个子像素包括位于第一显示区的第一子像素和位于第二显示区的第二子像素；多个电路块，位于第二显示区，各电路块包括b个像素电路，b个像素电路包括第一电路和第二电路，至少部分第一电路用于驱动第一子像素，第二电路用于驱动第二子像素；其中，a和b均为大于0的正整数，且a小于b，在第二显示区内，各电路块沿显示面板的厚度方向的正投影位于各像素块沿厚度方向上的正投影之内。本申请能够提高显示面板的显示效果。

Description

显示面板及显示装置
相关申请的交叉引用
本申请要求享有于2022年01月29日提交的名称为“显示面板及显示装置”的中国专利申请第202210111313.9号的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请涉及显示领域，具体涉及一种显示面板及显示装置。
背景技术
随着电子设备的快速发展，用户对屏占比的要求越来越高，使得电子设备的全面屏显示受到业界越来越多的关注。
传统的电子设备如手机、平板电脑等需要集成诸如前置摄像头、听筒以及红外感应元件等。现有技术中，可以将摄像头等感光组件所在的感光区内设置子像素，并将这些子像素对应的像素电路设置于显示区的其他位置。此外，一些显示面板中为了实现窄边框设计，会将靠近边框显示区域的像素电路设置于其他位置。以上均会导致显示区内像素电路的排布密度不均，导致显示面板出现显示差异。
发明内容
本申请实施例提供一种显示面板及显示装置，旨在提高显示面板的显示效果。
本申请第一方面的实施例提供一种显示面板，显示面板具有第一显示区和第二显示区，显示面板包括：多个像素块，包括多个子像素，各像素块包括多个子像素中的a个子像素，多个子像素包括位于第一显示区的第一子像素和位于第二显示区的第二子像素；多个电路块，位于第二显示区，各电路块包括b个像素电路，b个像素电路包括第一电路和第二电路，至少部分第一电路用于驱动第一子像素，第二电路用于驱动第二子像素；其中，a和b均为大于0的正整数，且a小于b，在第二显示区内，各电路块沿显示面板的厚度方向的正投影位于各像素块沿厚度方向的正投影之内。
本申请第二方面的实施例提供一种显示装置，其包括上述第一方面实施例的显示面板。
在本申请第一方面实施例提供的显示面板中，电路块位于第二显示区，即用于驱动第一子像素和第二子像素的像素电路均位于第二显示区，可以使得第一显示区的透光率大于第二显示区的透光率。显示面板在第一显示区的背面可以集成感光组件，实现例如摄像头的感光组件的屏下集成。或者可以将显示面板的移位寄存器等驱动电路设置于第一显示区，以实现显示面板的窄边框设计。
在本申请第一方面实施例提供的显示面板中，电路块在第二显示区，各像素块包括b个像素电路，而第二显示区的像素块包括a个第二子像素，b大于a，使得至少部分电路块内多余的第一电 路可以驱动第一显示区内的第一子像素。各电路块沿显示面板的厚度方向的正投影位于各像素块沿厚度方向上的正投影之内，一方面能够保证第二显示区内电路块的排布方式与像素块的排布方式相同，电路块的排布更加均匀，提高第二显示区的显示效果，进而提高显示面板的显示效果。另一方面能够减小至少部分电路块内第二电路与其驱动的第二子像素的距离，减小至少部分第二电路和第二子像素之间的走线长度，保证信号传输的稳定性。
附图说明
图1本申请第一方面实施例提供的一种显示面板的结构示意图；
图2是图1中Q区域在一种示例中子像素排布结构示意图；
图3是图1中Q区域在一种示例中像素电路的排布结构示意图；
图4是图1中W区域在一种示例中子像素排布结构示意图；
图5是图1中W区域在一种示例中像素电路的排布结构示意图；
图6是图1中Q区域在另一种示例中像素电路的排布结构示意图；
图7是图1中P区域在一种示例中子像素排布结构示意图；
图8是图1中P区域在一种示例中像素电路的排布结构示意图；
图9是图1中P区域在另一种示例中像素电路的排布结构示意图；
图10是图1中I区域在一种示例中子像素排布结构示意图；
图11是图1中I区域在一种示例中像素电路的排布结构示意图；
图12是图1中II区域在一种示例中子像素排布结构示意图；
图13是图1中II区域在一种示例中像素电路的排布结构示意图；
图14是图1中I区域在另一种示例中像素电路的排布结构示意图；
图15是图2中C-C处的局部剖视图。
具体施方式
在诸如手机和平板电脑等电子设备上，需要在显示面板的一侧集成诸如前置摄像头、红外光传感器、接近光传感器等感光组件。在一些实施例中，可以在上述电子设备上设置透光显示区，将感光组件设置在透光显示区背面，在保证感光组件正常工作的情况下，实现电子设备的全面屏显示。
为提高透光显示区的透光率，往往将透光区域的驱动电路设置于非透光区域，这就会导致显示面板非透光区域显示效果的不均一。
为解决上述问题，本申请实施例提供了一种显示面板及显示装置，以下将结合附图对显示面板及显示装置的各实施例进行说明。
本申请实施例提供一种显示面板100，该显示面板100可以是有机发光二极管(Organic Light Emitting Diode，OLED)显示面板100。
请一并参阅图1至图3，图1示出根据本申请一种实施例的显示面板100的俯视示意图。请一并参阅图2，图2是图1中Q区域的局部放大结构示意图。图3是另一种示例中图1中Q区域的局部放大结构示意图。图3和图2展示了不同的层结构。图2中展示出了图1中Q处的子像素110a的排布结构图，图3与图2不同之处在于图3在Q处第二显示区AA2展示出了像素电路120a的排 布结构图，并保留了第一显示区AA1的子像素110a排布结构示意图。
如图1至图3所示，本申请第一方面的实施例提供一种显示面板100具有第一显示区AA1和第二显示区AA2，显示面板100包括：多个子像素，包括位于第一显示区AA1的第一子像素111和位于第二显示区AA2的第二子像素112；多个像素块110，包括多个子像素，各像素块110包括多个子像素中的a个子像素110a，多个子像素110a包括位于第一显示区AA1的第一子像素111和位于第二显示区AA2的第二子像素112；多个电路块120，位于第二显示区AA2，各电路块120包括b个像素电路120a，b个像素电路120a包括第一电路121和第二电路122，至少部分第一电路121用于驱动第一子像素111，第二电路122用于驱动第二子像素112；其中，a和b均为大于0的正整数，且a小于b，在第二显示区AA2内，各电路块120沿显示面板100的厚度方向的正投影位于各像素块110沿厚度方向的正投影之内。图2和图3中以矩形框限定出了像素块110和电路块120的结构，矩形框并不构成对本申请显示面板100结构上的限定。矩形框中包括了不属于同一像素块110的子像素110a的一小部分，位于矩形框内的面积大于其自身总面积50％的子像素100a为该矩形框表示的像素块110内的子像素110a。
位于第一显示区AA1的每个像素块110的a个子像素110a均为第一子像素111，位于第二显示区AA2的每个像素块110的a个子像素110a均为第二子像素112。
在本申请第一方面实施例提供的显示面板100中，电路块120位于第二显示区AA2，即用于驱动第一子像素111和第二子像素112的像素电路120a均位于第二显示区AA2，可以使得第一显示区AA1的透光率大于第二显示区AA2的透光率。显示面板100在第一显示区AA1的背面可以集成感光组件，实现例如摄像头的感光组件的屏下集成。或者可以将显示面板100的移位寄存器等驱动电路设置于第一显示区AA1，以实现显示面板100的窄边框设计。
在本申请第一方面实施例提供的显示面板100中，电路块120在第二显示区AA2，各电路块120包括b个像素电路120a，像素块110包括位于第二显示区AA2的a个第二子像素112，b大于a，电路块120内设置a个第二电路122即可驱动像素块110内的a个第二子像素112，电路块120内可以设置b-a个第一电路120，电路块120内的至少部分第一电路121可以驱动第一显示区AA1内的第一子像素111。各电路块120沿显示面板100的厚度方向的正投影位于各像素块110沿厚度方向上的正投影之内，一方面能够保证第二显示区AA2内电路块120内多个第二电路122的排布方式与像素块110内多个第二子像素112的排布方式相同，电路块120的排布更加均匀，提高第二显示区AA2的显示效果。另一方面能够减小至少部分电路块120内第二电路122与其驱动的第二子像素112的距离，减小至少部分第二电路122和第二子像素112之间的走线长度，保证信号传输的稳定性。
可选的，第二显示区AA2的像素块110包括a个第二子像素112，第一显示区AA1的像素块110包括a个第一子像素111。如果存在部分显示区位于第一显示区AA1和第二显示区AA2之间，那么介于第一显示区AA1和第二显示区AA2之间的像素块110还可以包括第一子像素111和第二子像素112，且第一子像素111和第二子像素112的个数和为a。
可选的，电路块120可以包括b个第一电路121或者b个第二电路122。在另一些实施例中，像素电路120a可以既包括第一电路121也包括第二电路122，且第一电路121和第二电路122的个数和为b。
在一些可选的实施例中，第二显示区AA2内，各像素块110沿厚度方向的正投影面积和电路 块120沿厚度方向的正投影重叠，使得像素块110内像素电路120a的面积较大。
可选的，请继续参阅图3，第一电路121和第二电路122的分布面积相等，能够进一步改善第二显示区AA2的显示效果，避免第一电路121和第二电路122分布面积不等而出现显示差异。可选的，第一电路121和第二电路122的电路结构相同，不同之处在于部分第一电路121用于驱动第一子像素111，第二电路122用于驱动第二子像素112。
电路块120沿显示面板100的厚度方向的正投影即电路块120在显示面板100的显示面上的正投影。像素块110沿厚度方向的正投影即像素块110在显示面板100的显示面上的正投影。
可选的，像素块110沿显示面板100厚度方向的正投影为该像素块110内的a个子像素110a沿显示面板100厚度方向的正投影所在的区域。例如当子像素110a排布形成像素排布结构时，像素块110所在的区域为a个子像素110a在像素排布结构内占据的排布区域。例如当像素排布结构的尺寸为10cm×10cm，像素排布结构内的子像素110a呈10行10列分布，那么单个子像素110a的排布尺寸为1cm×1cm，即单个子像素110a沿显示面板100的厚度方向的正投影尺寸为1cm×1cm，像素块110所在的区域为a个1cm×1cm形成的区域，此处仅为举例说明，不代表子像素110a的实际排布尺寸为1cm×1cm。
像素块110内的a个子像素110a相邻设置。例如如图2和图3所示，当a等于16，像素块110包括16个子像素110a时，像素块110内的这16个子像素110a相邻设置。该16个子像素110a可以位于同一行或者位于相邻的两行以上。
可选的，如图2和图3所示，当在行方向和/或列方向上相邻的两个子像素110a存在交叠时，a个子像素110a沿显示面板100厚度方向的正投影所在的区域为a个子像素110a的平均排布尺寸。行方向可以为第一方向X，列方向可以为第二方向Y。在另一些实施例中，行方向也可以为第二方向Y，列方向为第一方向X。
可选的，如图2所示，显示面板100的子像素110a排布形成像素排布结构，像素排布结构包括重复单元，重复单元包括多个子像素110a，且重复单元沿行方向和列方向重复排布形成像素排布结构。像素块110内包括的子像素110a的数量可以与重复单元包括的子像素110a的数量相关，例如像素块110内包括的子像素110a数量为重复单元包括的子像素110a数量的整数倍。例如，如图2所示，当重复单元包括4个子像素110a时，像素块110包括16个子像素110a，像素块110包括的子像素110a的数量为重复单元包括的子像素110a数量的4倍，即像素块110包括4个重复单元，像素块110沿厚度方向的正投影为4个重复单元所占据的排布尺寸。
可选的，电路块120沿显示面板100厚度方向的正投影为该电路块120内的b个子像素110a电路沿厚度方向的正投影所在的区域。电路块120内的b个像素电路120a相邻设置。例如当b等于25，电路块120包括25个像素电路120a时，这25个像素电路120a相邻设置。该25个像素电路120a可以位于同一行或者位于两行及以上。
可选的，当像素块110内的a个子像素110a同行设置时，电路块120内的b个像素电路120a同行设置。电路块120内的像素电路120a在行方向上压缩，以使b个像素电路120a沿厚度方向的正投影位于a个子像素110a沿厚度方向的正投影之内。
在一些可选的实施例中，像素块110包括p行q列排布的多个子像素110a，p和q的乘积为a；电路块120包括e行f列排布的多个像素电路120a，e和f的乘积为b，其中，p、q、e、f均为大于1的正整数，e≥p，f≥q。
在这些可选的实施例中，p、q、e、f均为大于1的正整数，因此像素块110包括多行多列排列的子像素110a，电路块120包括多行多列排布的像素电路120a，使得像素电路120a在行方向上和列方向上均进行压缩，避免像素电路120a在同一方向上压缩导致的技术难题。
p、q、e、f的设置方式有多种，在一些可选的实施例中，p和q相等，e和f相等，且e大于p。即像素块110包括p行p列的子像素110a，电路块120包括e行e列的像素电路120a，使得像素块110内多个子像素110a的排布更加规律，电路块120内多个像素电路120a的排布更加规律，更加容易对像素电路120a的尺寸进行调整。
如上所述，如图2和图3所示，例如当a等于16，像素块110包括16个子像素110a时，像素块110包括4行4列的子像素110a。当b等于25，电路块120包括25个像素电路120a时，电路块120包括5行5列的像素电路120a。
即在本申请实施例提供的显示面板100中，在第二显示区AA2内，4行4列的子像素110a所在的区域内设置有5行5列的像素电路120。4行4列的子像素110a所在区域内设置的像素电路120a数量大于子像素110a的数量，4行4列的子像素110a所在区域内多余的1行1列像素电路120a中的至少部分可以用于驱动第一显示区AA1内的第一子像素111。
请一并参阅图1至图5，图4是图1中W处的子像素110a的排布结构示意图；图5是图1中W处的像素电路120a排布结构示意图。
在一些可选的实施例中，如图1至图5所示，第二显示区AA2包括主显示区ZA和过渡显示区TA，过渡显示区TA位于主显示区ZA和第一显示区AA1之间，至少部分位于过渡显示区TA的第一电路121用于驱动第一子像素111。即用于驱动第一子像素111的第一电路121所在的区域为过渡显示区TA，未用于驱动第一子像素111的第一电路121所在的区域为主显示区ZA。
在这些可选的实施例中，将用于驱动第一子像素111的第一电路121设置于距离第一显示区AA1较近的过渡显示区TA内，能够减小相互电连接的第一电路121和第一子像素111之间的距离，减小第一电路121和第一子像素111之间连线的长度，保证信号传输的稳定性。
可选的，主显示区ZA内各电路块120位于被其驱动的各像素块110的正投影之内，且主显示区ZA的各电路块120包括p行q列的第二电路122和(e-p)行(f-q)列的第一电路121。其中，(e-p)行(f-q)列的第一电路121是指e行f列的电路块120中的(e-p)行(f-q)列。
例如，请继续参阅图4和图5，当像素块110包括4行4列的子像素110a，每行和每列均为4个子像素110a，而电路块120包括5行5列的像素电路120a时，主显示区ZA内的各电路块120包括4行4列的第二电路122和1行1列的第一电路121，该1行1列的第一电路121是指5行5列像素电路120a中的1行和1列的第一电路121。1行1列的第一电路121中，1行有5个第一电路121，1列也有5个第一电路121，且1行1列的第一电路121在交叉位置处存在1个第一电路121重复。因此主显示区ZA内各电路块120包括16个第二电路122和9个第一电路121。
在这些可选的实施例中，主显示区ZA内电路块120包括的第二电路122的数量和像素块110包括的第二子像素112的数量相同，因此各电路块120内的第二电路122可以用于驱动各像素块110内的第二子像素112。主显示区ZA内各电路块120位于被其驱动的各像素块110的正投影之内，能够减小第二电路122和被其驱动的第二子像素112之间的距离，减小第二电路122和被其驱动的第二子像素112之间的连线长度。
可选的，主显示区ZA内，电路块120内多个第二电路122的相对位置关系与像素块110内多 个第二子像素112的相对位置关系相同，以进一步减小第二电路122和被其驱动的第二子像素112之间的距离，减小第二电路122和被其驱动的第二子像素112之间的连线长度。
可选的，主显示区ZA内第二电路122和被其驱动的第二子像素112的相对位置关系可以有多种设置方式。
例如，第二电路122和被其驱动的第二子像素112沿厚度方向的正投影至少部分交叠设置，能够进一步减小第二电路122和被其驱动的第二子像素112之间的距离，减小第二电路122和被其驱动的第二子像素112之间的连线长度。
或者，第二电路122和被其驱动的第二子像素112沿厚度方向的正投影错位设置，只要第二电路122所在的电路块120沿厚度方向的正投影位于被其驱动的第二子像素112所在的像素块110沿厚度方向的正投影之内即可。
可选的，如图5所示，电路块120内的第一电路121位于第二电路122在行方向上的一则，或者第一电路121位于多个第二电路122在列方向上的一侧。
在另一些实施例中，主显示区ZA内，第一电路121位于多个第二电路122在行方向和/或列方向上的中间。以减小第二电路122和被其驱动的第二子像素112之间的错位尺寸，减小第二电路122和被其驱动的第二子像素112之间的走线长度。
过渡显示区TA内第一电路121和第二电路122的排布方式可以有多种，在一些可选的实施例中，请继续参阅图3至图5，过渡显示区TA内第一电路121和第二电路122的排布方式与主显示区ZA内第一电路121和第二电路122的排布方式相同。即过渡显示区TA内各电路块120位于被其驱动的各像素块110的正投影之内，过渡显示区TA的电路块120包括p行q列的第二电路122和(e-p)行(f-q)列的第一电路121。能够进一步改善过渡显示区TA和主显示区ZA之间的显示差异，且能够减小过渡显示区TA内第二电路122和被其驱动的第二子像素112之间的距离，减小第二电路122和被其驱动的第二子像素112之间的连线长度。
可选的，过渡显示区TA内，电路块120内多个第二电路122的相对位置关系与像素块110内多个第二子像素112的相对位置关系相同。以进一步减小过渡显示区TA内第二电路122和被其驱动的第二子像素112之间的距离，减小第二电路122和被其驱动的第二子像素112之间的连线长度。
过渡显示区TA内第一电路121的排布方式可以有多种，在一些可选的实施例中，第一电路121包括沿行方向并排设置的多个行电路121a和沿列方向并排设置的列电路121b，至少部分行电路121a和/或列电路121b用于驱动第一子像素111。行电路121a是指沿行方向排布的多个第一电路121，列电路121b是指沿列方向排布的多个第一电路121。行方向和列方向存在交叉，因此交叉位置处的第一电路121既可以是行电路121a，也可以是列电路121b。
在这些可选的实施例中，行电路121a所在的行内未设置第二电路122，列电路121b所在的列内未设置第二电路122。当利用行电路121a和/或列电路121b驱动第一子像素111时，能够避免第一子像素111和第二电路122之间的连线与第二子像素112和第二电路122之间的连线串扰。
例如，第一电路121的分布图像呈网格状并具有镂空区域，多个第二电路122位于镂空区域，即至少两个第一电路121间隔设置，且至少部分第二电路122位于相邻的两个第一电路121之间，第一电路121环绕多个第二电路122设置。即在电路块120内，第一电路121集中于同行同列排布，使得电路块120内多个第二电路122的排布更加集中。
第一显示区AA1的设置方式有多种，例如，请继续参阅图1，第一显示区AA1包括规则区和位于规则区在行方向至少一侧的异形区，至少部分异形区内的第一子像素111与至少部分规则区的第一子像素111同行设置。
异形区的设置方式可以有多种，请继续参阅图1，例如异形区可以包括拐角区RA，拐角区RA环绕第二显示区AA2并弯折设置。当第一显示区AA1包括拐角区RA时，拐角区RA内的第一子像素111对应的像素电路120a位于第二显示区AA2，进而可以在拐角区RA内设置移位寄存器等驱动电路和驱动信号线，能够减小显示面板100的边框尺寸。
可选的，请继续参阅图1，异形区还可以包括感光区UDC，第二显示区AA2环绕至少部分感光区UDC设置。当第一显示区AA1包括感光区UDC时，感光区UDC内的第一子像素111对应的像素电路120a位于第二显示区AA2，能够提高感光区UDC的透光率，便于感光组件在感光区UDC内实现屏下集成。同时感光区UDC能够显示画面，提高显示面板10010的显示面积，实现显示装置的全面屏设计。
可选的，请继续参阅图1，第一显示区AA1包括边框显示区BA，边框显示区BA环绕第二显示区AA2设置，且边框显示区BA包括位于第二显示区AA2在列方向至少一侧的端部边框显示区BA1和位于第二显示区AA2在行方向至少一侧的侧部边框显示区BA2。当第一显示区AA1包括边框显示区BA时，边框显示区BA内的第一子像素111对应的像素电路120a位于第二显示区AA2，进而可以在边框显示区BA内设置移位寄存器等驱动电路和驱动信号线，能够减小显示面板100的边框尺寸，实现显示面板100的窄边框甚至无边框设计。
可选的，规则区可以包括上述的边框显示区BA，规则区还可以包括位于感光区UDC在行方向至少一侧的部分第一显示区AA1。当异形区包括拐角区RA时，拐角区RA可以连接于相邻的端部边框显示区BA1和侧部边框显示区BA2之间。
位于不同区域的第一子像素111可以选用不同的第一电路121进行驱动。在一些可选的实施例中，请继续参阅图3，至少部分行电路121a用于驱动位于异形区内的第一子像素111。使得异形区内同一行的第一子像素111可以使用同一行的行电路121a进行驱动，能够简化第一子像素111和行电路121a之间的布线。此外，异形区内的第一子像素111使用行电路121a进行驱动，只需增设向行电路121a传输驱动信号的行信号线即可，无需增设列信号线，能够减小第二显示区AA2内信号线的布线数量。
如图2和图3所示，当第一显示区AA1包括感光区UDC时，感光区UDC内的第一子像素111可以被行电路121a驱动。可选的，如图3所示，第一显示区AA1内的各行第一子像素111可以使用不同行的行电路121a进行驱动，即不同行的第一子像素111被不同行的行电路121a驱动。在另一些实施例中，请参阅图6，第一显示区AA1内的多行第一子像素111还可以使用同一行的行电路121a进行驱动，即两行以上的第一子像素111可以使用同行的行电路121a进行驱动。
可选的，当使用过渡显示区TA内的行电路121a驱动异形区内的第一子像素111时，可以在过渡显示区TA内增设行信号线以向行电路121a传输驱动信号。
在一些可选的实施例中，请继续参阅图6，显示面板100还包括第一行信号线131和第二行信号线132，第一行信号线131连接于驱动第一子像素111的行电路121a并用向其传输信号，第二行信号线132连接于第二电路122并用向其传输信号。在这些可选的实施例中，通过增设第一行信号线131能够向行电路121a传输驱动信号，进而使得行电路121a能够驱动第一子像素111显示。
请参阅图1、图7和图8，图7是图1中P处的子像素110a排布结果示意图，图8是图1中P处的像素电路120a结构示意图。其中，图8中保留了拐角区RA内的第一子像素111。
如图7和图8所示，当第一显示区AA1包括拐角区RA时，拐角区RA内的第一子像素111可以被第二显示区AA2的行电路121a驱动。如图8所示，拐角区RA内的多行第一子像素111可以选用多行行电路121a进行驱动。或者，如图9所示，拐角区RA内的多行第一子像素111可以选用同一行的行电路121a进行驱动。
可选的，显示面板100还包括沿列方向延伸的列信号线(图中未示出)，用于向同列设置的第一电路121和/或第二电路122传输驱动信号。
可选的，第一行信号线131和第二行信号线132可以为扫描信号线，列信号线可以为数据信号线。在另一些可选的实施例中，第一行信号线131和第二行信号线132还可以为数据信号线，列信号线为扫描信号线。
在一些可选的实施例中，显示面板100还包括行缓存器(图中未示出)，行缓存器用于储存异形区内第一子像素111的驱动信号、并根据异形区内第一子像素111的驱动信号向第一行信号线131传输驱动信号。通过增设行缓存器，行缓存器存储有异形区内第一子像素111的驱动信号，行缓存器能够向第一行信号线131传输驱动信号，进而通过第一行信号线131驱动行电路121a。
可选的，显示面板100包括像素跳跃还原(pixel jump reduction；PJR)处理模块，PJR处理模块具有图像复制且挪移的功能。在按照第一子像素111和第二子像素112排布方式进行处理图像处理的图像数据基础上，在图像数据内用于驱动第一子像素111的行电路121a所在位置增加该第一子像素111对应的数据，并将这些数据存储至行缓存器。
可选的，PJR处理模块连接于数模转换模块，以通过数模转换模块将图像数据转换为模拟电压信号。
可选的，当多个第一子像素111形成一个发白光的显示单元，且相邻的两个显示单元共用一个第一子像素111时，可以根据显示单元的发光需求通过位于第二显示区AA2的第一电路121驱动该第一子像素111发光。
请参阅图1、图10至图13，图10是图1中I处的子像素110a排布结构示意图，图11是图1中I处的像素电路120a排布结构示意图，且图11中保留了位于端部边框显示区BA1的第一子像素111。图12是图1中II处的子像素110a排布结构示意图，图13是图1中II处的像素电路120a排布结构示意图，且图13中保留了位于侧部边框显示区BA2的第一子像素111。
边框显示区BA内的第一子像素111成行成列排布。例如，如图10所示，端部边框显示区BA1内的第一子像素111成多行排布，且端部边框显示区BA1内同行设置的第一子像素111数量小于或等于过渡显示区TA内同行设置的行电路121a数量。因此端部边框显示区BA1内同行的第一子像素111可以使用过渡显示区TA内的同行设置的行电路121a进行驱动，并将原有用于驱动端部边框显示区BA1内同行的第一子像素111的行信号线挪用至过渡显示区TA连接用于驱动该第一子像素111的行电路121a即可。
例如，如图12所示，侧部边框显示区BA2内的第一子像素111呈多列排布，且侧部边框显示区BA2内同列设置的第一子像素111的数量小于或等于过渡显示区TA内同列设置的列电路121b数量。因此侧部边框显示区BA2内同列的第一子像素111可以使用过渡显示区TA内的同列设置的行电路121a进行驱动，并将原有用于驱动侧部边框显示区BA2内同列的第一子像素111的列信号 线挪用至过渡显示区TA连接用于驱动该第一子像素111的列电路121b即可。
在一些可选的实施例中，如图10至图13所示，至少部分行电路121a用于驱动位于端部边框显示区BA1内的第一子像素111，和/或至少部分列电路121b用于驱动位于侧部边框显示区BA2内的第一子像素111。无需增设行信号线或列信号线，能够进一步简化显示面板100的信号线的布线。
以上为过渡显示区TA内电路块120和主显示区ZA内电路块120的设置方式相同时，如何利用过渡显示区TA内的第一电路121驱动第一子像素111的设置方式。
在另一些可选的实施例中，过渡显示区TA内的电路块120的设置方式还可以与主显示区ZA内电路块120的设置方式不同。
请参阅图14，图14是图1中I处在另一实施例中的像素排布结构示意图。
可选的，如图14所示，过渡显示区TA内的第一电路121均位于第二电路122靠近第一子像素111的一侧。在这些可选的实施例中，过渡显示区TA内的第一电路121更加靠近第一显示区AA1设置，能够减小第一电路121和被其驱动的第一子像素111之间的距离。
可选的，用于驱动过渡显示区TA内第二子像素112的第二电路122和过渡显示区TA内用于驱动第一子像素111的第一电路121的位置关系与过渡显示区TA内第二子像素112和第一显示区AA1内第一子像素111位置关系相同。如此设置，能减小过渡显示区TA内第二电路122和被其驱动的第二子像素112之间的距离、及第一电路121和被其驱动的第一子像素111之间的距离，且能够避免连接第一电路121和第一子像素111的信号线与连接第二电路122和第二子像素112的信号线之间出现交叉，简化信号线的布线。
此外，在这些可选的实施例中，无需增设行信号线或列信号线，只需将用于驱动第一子像素111的信号线连接于驱动该第一子像素111的第一电路121即可。过渡显示区TA内的多个第一电路121按照被其驱动的多个第一子像素111的排布方式排布，多个第一电路121按照接力的方式依次连接第一子像素111，既能够使得多个用于连接第一电路121和第一子像素111的信号线的长度趋于一致，也能够避免该多个信号线相互交叉。
图14中仅示意出了端部边框显示区BA1内第一子像素111与第一电路121的连接关系。
在另一些实施例中，第一显示区AA1还可以包括拐角区RA、感光区UDC和侧部边框显示区BA2，用于驱动拐角区RA、感光区UDC和侧部边框显示区BA2中第一子像素111的第一电路121位于第二电路122靠近拐角区RA、感光区UDC和侧部边框显示区BA2的一侧。即拐角区RA、感光区UDC和侧部边框显示区BA2内的第一子像素111和过渡显示区TA的第一电路121也可以采用接力的方式相互连接，拐角区RA、感光区UDC和侧部边框显示区BA2内的第一子像素111与过渡显示区TA内第二子像素112的相对位置关系与过渡显示区TA内用于驱动拐角区RA、感光区UDC和侧部边框显示区BA2内第一子像素111的第一电路121和第二电路122的相对位置关系相同。
请参阅图15，图15是图3中C-C处的剖视图。
在一些可选的实施例中，如图15所示，显示面板100还包括：信号线层103，包括第一连接信号线133，第一连接信号线133用于连接第一电路121和第一子像素111。
在这些可选的实施例中，通过设置信号线层103能够避免第一连接信号线133与其他信号线串扰。
可选的，请继续参阅图15，显示面板100还包括衬底101、设置于衬底101的阵列基板和像素定义层102，像素电路120a设置于阵列基板。像素定义层102包括位于第一显示区AA1的第一像素开口K1和位于第二显示区AA2的第二像素开口K2。第一子像素111包括位于第一像素开口K1内的第一发光结构111b、位于第一发光结构111b朝向阵列基板一侧的第一电极111a和位于第一发光结构111b背离阵列基板一侧的第二电极111c。第二子像素112包括位于第二像素开口K2内的第二发光结构121b、位于第二发光结构121b朝向阵列基板一侧的第三电极121a和位于第二发光结构121b背离阵列基板一侧的第四电极121c。第一电极111a和第三电极121a例如为像素电极，第二电极111c和第四电极121c可以互联为公共电极。
可选的，信号线层103可以位于阵列基板和发光层之间。阵列基板可以包括第一金属层、第二金属层和第三金属层，像素电路120a包括薄膜晶体管(TFT)，薄膜晶体管(TFT)分为开关薄膜晶体管和驱动薄膜晶体管。薄膜晶体管(TFT)包括半导体层、栅极和源漏电极，栅极可以位于第一金属层，源漏电极可以位于第三金属层。第二金属层可以设置电容的其中一个极板，电容的另一极板可以位于第一金属层或第三金属层。
可选的，行信号线为扫描线，行信号线可以位于第一金属层并与开关薄膜晶体管的栅极相互连接。可选的，显示面板100还包括列信号线，列信号线位于数据线并位于第三金属层，列信号线可以与开关薄膜晶体管的源漏电极中的一者相互连接。
可选的，部分第一电路121的驱动薄膜晶体管的源漏电极通过第一连接信号线133连接于第一子像素111的第一电极111a。
在一些可选的实施例中，请继续参阅图14，至少部分第一连接信号线133沿第二方向Y延伸成型，第一连接信号线133上沿第二方向Y上延伸的部分位于同一膜层。第一连接信号线133在第一方向X上的排布尺寸为m，与第二显示区AA2沿第二方向Y相邻的第一子像素111在第一方向X上的排布尺寸为n，第一显示区AA1在第二方向Y上排布有2k个第一子像素111，m和n满足n＝km+d，其中，k为正整数，d为小于m的正数，d为信号线间距的冗余量。第一方向X和第二方向Y中的一者为行方向，另一者为列方向。请参阅图14，本申请实施例以第一方向X为行方向，第二方向Y为列方向进行举例说明。
第一连接信号线133在第一方向X上的排布尺寸既包括第一连接信号线133自身在第一方向X上的延伸尺寸，还包括沿第一方向X相邻的两个第一连接信号线133之间的一个间隔尺寸。第一子像素111在第一方向X上的排布尺寸为同第一子像素111在第一方向X上的平均排布尺寸。例如，第一方向X上排布有i个第一子像素111，该i个第一子像素111在第一方向X上的占据的尺寸为j，第一子像素111的排布尺寸n等于j/i。
在这些可选的实施例中，如图14所示，例如与第二显示区AA2沿第二方向Y相邻的第一子像素111为邻接第一子像素111’。位于邻接第一子像素111’远离第二显示区AA2一侧的第一子像素111连接的第一连接信号线133均要经过该邻接第一子像素111’，而邻接第一子像素111’在第一方向X上的延伸尺寸有限。那么第一显示区AA1在第二方向Y上排布的第一子像素111的数量与该邻接第一子像素111’的尺寸有关，即n＝km+d。当第一显示区AA1在第二方向Y上排布的第一子像素111的数量满足上述关系式时，能够避免在第一方向X上相邻的第一连接信号线133距离过近或相互交叠而导致信号串扰。
可选的，当第一显示区AA1包括端部边框显示区BA1时，两个端部边框显示区BA1分设于第 二显示区AA2的两侧，那么一个端部边框显示区BA1内在第二方向Y上排布有k个第一子像素111。端部边框显示区BA1在第二方向Y上的延伸尺寸小于或等于k个第一子像素111沿第二方向Y的排布尺寸。
当第一显示区AA1为侧部边框显示区BA2时，第一方向X为列方向，第二方向Y为行方向，两个侧部边框显示区BA2分设于第二显示区AA2的两侧。那么一个侧部边框显示区BA2内在第一方向X上排布有k各第一子像素111，侧部边框显示区BA2在第一方向X上的延伸尺寸小于或等于k各第一子像素111沿第一方向X的排布尺寸。
可选的，当第一显示区AA1为感光区UDC，且感光区UDC为圆形时，感光区UDC的半径小于或等于k个第一子像素111沿行方向的排布尺寸。
例如，第一连接信号线133在列方向上的排布尺寸为5μm，邻接第一子像素111在列方向上的排布尺寸为61.7μm，那么邻接第一子像素111上最多可以排布的第一连接信号线133的数量为11根，第一显示区AA1在行方向上的延伸尺寸小于或等于11个第一子像素111在行方向上的排布尺寸。
在一些可选的实施例中，请继续参阅图14，第一连接信号线133包括沿不同方向延伸的第一分段133a和第二分段133b，第一分段133a和第二分段133b位于不同的膜层，以改善不同第一连接信号线133的短路连接风险。
在一些可选的实施例中，信号线层103还包括第二连接信号线134，第二连接信号线134用于连接第二电路122和第二子像素112。第一连接信号线133和第二连接信号线134同层设置能够减薄显示面板100的厚度。
在一些可选的实施例中，用于驱动同一行第一子像素111的多个第一电路121位于同一行，使得用于驱动同一行第一子像素111的多个第一电路121可以连接于同一第一行信号线131。
可选的，同一行的第一电路121用于驱动两行以上的第一子像素111。例如，当第一显示区AA1包括异形区，可以利用过渡显示区TA内距离异形区较近的行电路121a驱动异形区内两行以上的第一子像素111，以减小第一电路121和被其驱动的第一子像素111之间的距离。
综上，本申请在不改变原有子像素110a排布的基础上，通过将像素电路120a设置于第二显示区AA2从而预留出了第一显示区AA1，可以提高第一显示区AA1的透光率或在第一显示区AA1内设置其他驱动电路和驱动信号线以减小显示面板100的边框尺寸。本申请中第二显示区AA2内电路块120和像素块110的排布方式相同，保证了第二显示区AA2内不同位置的显示效果均一。
本申请实施例还提供了两种像素电路120a的排布方式及其驱动第一子像素111显示的方式。
在第一种实施方式中，过渡显示区TA内的电路块120和主显示区ZA内的电路块120的设置方式一致，利用过渡显示区TA内的行电路121a驱动异形区内的第一子像素111，并通过增设第一行信号线131和行缓存器向过渡显示区TA内的行电路121a传输驱动信号。该实施方式一方面能够保证过渡显示区TA和主显示区ZA内第二电路122与其驱动的第二子像素112距离均较近，另一方面仅需增设一种行信号线即可驱动第一子像素111，能够简化显示面板100的布线。
在第二种实施方式中，主显示区ZA内的像素块110和电路块120沿厚度方向对应设置，能够减小主显示区ZA内第二电路122和被其驱动的第二子像素112之间的距离。过渡显示区TA内的第一电路121和第二电路122的排布方式与过渡显示区TA内第二子像素112和第一显示区AA1内第一子像素111的排布方式相同，过渡显示区TA内的第二电路122所在的电路块120与被该第二 电路122驱动的第二子像素112所在的像素块110错位设置，多个第一电路121按照接力的方式依次连接第一子像素111，既能够使得多个用于连接第一电路121和第一子像素111的信号线的长度趋于一致，也能够避免该多个信号线相互交叉。
因此，本申请实施例通过缩减第一电路121和第二电路122的尺寸，使得相同面积内设置的像素电路120a的数量多于子像素110a的数量，能够将用于驱动第一子像素111的像素电路120a置于第二显示区AA2。且第一显示区AA1的宽度与邻接第一子像素111的排布尺寸内能够容纳的第一连接信号线133的数量相关，即第一显示区AA1同行内设置的第一子像素111的数量2k与邻接第一子像素111在行方向上的排布尺寸n、第一连接信号线133在行方向上的的排布尺寸m满足n＝km+d。
在一些实施例中，第一电路121的电路结构是2T1C电路、7T1C电路、7T2C电路、或9T1C电路中的任一种。本文中，“2T1C电路”指像素驱动电路中包括2个薄膜晶体管(T)和1个电容(C)的像素驱动电路，其它“7T1C电路”、“7T2C电路”、“9T1C电路”等依次类推。
可选的，第二电路122的电路结构是2T1C电路、7T1C电路、7T2C电路、或9T1C电路中的任一种。
可选的，第一子像素111的尺寸小于同种颜色的第二子像素112的尺寸，能够减小第一子像素111在第一显示区AA1内的占据空间，使得第一显示区AA1中的非发光区域面积更大，便于提高第一显示区AA1的透光率。
在一些可选的实施例中，第一子像素111和第一电路121一一对应设置。使得每一个第一子像素111均有对应的第一电路121进行驱动，能够提高显示面板100的显示效果。
可选的，相邻的两个以上相同颜色的第一子像素111连接于同一第一电路121，便于显示面板100的布线。
可选的，如上所述，第一子像素111包括第一发光结构111b、第一电极111a和第二电极111c。第二子像素112包括第二发光结构121b、第三电极121a和第四电极121c。本实施例中，以第一电极111a、第三电极121a是阳极、第二电极111c、第四电极121c是阴极为例进行说明。
第一发光结构111b、第二发光结构121b分别可以包括OLED发光层，根据第一发光结构111b、第二发光结构121b的设计需要，各自还可以分别包括空穴注入层、空穴传输层、电子注入层或电子传输层中的至少一种。
在一些实施例中，第一电极111a为透光电极。在一些实施例中，第一电极111a包括氧化铟锡(Indium Tin Oxide，ITO)层或氧化铟锌层。在一些实施例中，第一电极111a为反射电极，包括第一透光导电层、位于第一透光导电层上的反射层以及位于反射层上的第二透光导电层。其中第一透光导电层、第二透光导电层可以是ITO、氧化铟锌等，反射层可以是金属层，例如是银材质制成。第三电极121a可以配置为与第一电极111a采用相同的材质。
在一些实施例中，第二电极111c包括镁银合金层。第四电极121c可以配置为与第二电极111c采用相同的材质。
在一些实施例中，每个第一发光结构111b在衬底101上的正投影由一个第一图形单元组成或由两个以上第一图形单元拼接组成，第一图形单元包括从由圆形、椭圆形、哑铃形、葫芦形、矩形组成的群组中选择的至少一个。
在一些实施例中，每个第一电极111a在衬底101上的正投影由一个第二图形单元组成或由两 个以上第二图形单元拼接组成，第二图形单元包括从由圆形、椭圆形、哑铃形、葫芦形、矩形组成的群组中选择的至少一个。
在一些实施例中，每个第二发光结构121b在衬底101上的正投影由一个第三图形单元组成或由两个以上第三图形单元拼接组成，第三图形单元包括从由圆形、椭圆形、哑铃形、葫芦形、矩形组成的群组中选择的至少一个。
在一些实施例中，每个第三电极121a在衬底101上的正投影由一个第四图形单元组成或由两个以上第四图形单元拼接组成，第四图形单元包括从由圆形、椭圆形、哑铃形、葫芦形、矩形组成的群组中选择的至少一个。
示例性地，显示面板100还可以包括封装层和位于封装层上方的偏光片和盖板，也可以直接在封装层上方直接设置盖板，无需设置偏光片，或者至少在第一显示区AA1的封装层上方直接设置盖板，无需设置偏光片，避免偏光片影响对应第一显示区AA1下方设置的感光元件的光线采集量，当然，第一显示区AA1的封装层上方也可以设置偏光片。
本申请第二方面的实施例还提供一种显示装置，包括上述任一第一方面实施例的显示面板100。由于本申请第二方面实施例提供的显示装置包括上述第一方面任一实施例的显示面板100，因此本申请第二方面实施例提供的显示装置具有上述第一方面任一实施例的显示面板100具有的有益效果，在此不再赘述。
本申请实施例中的显示装置包括但不限于手机、个人数字助理(Personal Digital Assistant，简称：PDA)、平板电脑、电子书、电视机、门禁、智能固定电话、控制台等具有显示功能的设备。

Claims (20)

  1. 一种显示面板，具有第一显示区和第二显示区，所述显示面板包括：
    多个像素块，包括多个子像素，各所述像素块包括所述多个子像素中的a个子像素，所述多个子像素包括位于所述第一显示区的第一子像素和位于所述第二显示区的第二子像素；
    多个电路块，位于所述第二显示区，各所述电路块包括b个像素电路，所述b个像素电路包括第一电路和第二电路，至少部分所述第一电路用于驱动所述第一子像素，所述第二电路用于驱动所述第二子像素，
    其中，a和b均为大于0的正整数，且a小于b，在所述第二显示区内，各电路块沿所述显示面板的厚度方向的正投影位于各所述像素块沿所述厚度方向的正投影之内。
  2. 根据权利要求1所述的显示面板，其中，在所述第二显示区内，各所述电路块沿所述厚度方向的正投影和各所述像素块沿所述厚度方向的正投影重叠。
  3. 根据权利要求1所述的显示面板，其中，
    所述像素块包括p行q列排布的多个所述子像素，p和q的乘积为a；
    所述电路块包括e行f列排布的多个所述像素电路，e和f的乘积为b，其中，p、q、e、f均为大于1的正整数，且e≥p，f≥q。
  4. 根据权利要求3所述的显示面板，其中，p和q相等，e和f相等，且e大于p。
  5. 根据权利要求3所述的显示面板，其中，
    所述第二显示区包括主显示区和过渡显示区，所述过渡显示区位于所述主显示区和所述第一显示区之间，至少部分位于所述过渡显示区的所述第一电路用于驱动所述第一子像素；
    所述主显示区内各所述电路块位于被其驱动的各所述像素块的正投影之内，且所述主显示区的各所述电路块包括p行q列的所述第二电路和(e-p)行(f-q)列的所述第一电路。
  6. 根据权利要求5所述的显示面板，其中，所述主显示区内，所述电路块内多个所述第二电路的相对位置关系与所述像素块内多个所述第二子像素的相对位置关系相同。
  7. 根据权利要求5所述的显示面板，其中，所述过渡显示区内各所述电路块位于被其驱动的各所述像素块的正投影之内，所述过渡显示区的所述电路块包括p行q列的所述第二电路和(e-p)行(f-q)列的所述第一电路。
  8. 根据权利要求7所述的显示面板，其中，所述过渡显示区内，所述电路块内多个所述第二电路的相对位置关系与所述像素块内多个所述第二子像素的相对位置关系相同。
  9. 根据权利要求7所述的显示面板，其中，所述第一电路包括沿行方向并排设置的多个行电路和沿列方向并排设置的列电路，至少部分所述行电路和/或所述列电路用于驱动所述第一子像素。
  10. 根据权利要求9所述的显示面板，其中，所述第一显示区包括规则区和位于所述规则区在行方向至少一侧的异形区，至少部分所述异形区内的所述第一子像素与至少部分所述规则区的所述第一子像素同行设置，至少部分所述行电路用于驱动位于所述异形区内的所述第一子像素。
  11. 根据权利要求9所述的显示面板，还包括第一行信号线和第二行信号线，所述第一行信号线连接于驱动所述第一子像素的所述行电路并用于向其传输信号，所述第二扫描线连接于所述第二电路并用于向其传输信号。
  12. 根据权利要求11所述的显示面板，还包括行缓存器，所述行缓存器用于储存所述异形区内所述第一子像素的驱动信号、并根据所述异形区内所述第一子像素的驱动信号向所述第一行信号线传输驱动信号。
  13. 根据权利要求7所述的显示面板，其中，所述第一显示区包括边框显示区，所述边框显示区环绕所述第二显示区设置，且所述边框显示区包括位于所述第二显示区在列方向至少一侧的端部边框显示区和位于所述第二显示区在行方向至少一侧的侧部边框显示区；
    至少部分所述行电路用于驱动位于所述端部边框显示区内的所述第一子像素；
    和/或，至少部分所述列电路用于驱动位于所述侧部边框显示区内的所述第一子像素。
  14. 根据权利要求5所述的显示面板，其中，
    所述过渡显示区内的所述第一电路均位于所述第二电路靠近所述第一子像素的一侧。
  15. 根据权利要求14所述的显示面板，其中，用于驱动所述过渡显示区内所述第二子像素的所述第二电路和所述过渡显示区内用于驱动所述第一子像素的所述第一电路的位置关系与所述过渡显示区内所述第二子像素和所述第一显示区内所述第一子像素位置关系相同。
  16. 根据权利要求1所述的显示面板，其中，还包括：
    信号线层，包括第一连接信号线，所述第一连接信号线用于连接所述第一电路和所述第一子像素。
  17. 根据权利要求16所述的显示面板，其中，至少部分所述第一连接信号线沿第二方向延伸成型，所述第一连接信号线在第一方向上的排布尺寸为m，与所述第二显示区沿所述第二方向相邻的所述第一子像素在所述第一方向上的排布尺寸为n，所述第一显示区在所述第二方向上排布有2k个所述第一子像素，m和n满足n＝km+d，其中，k为正整数，d为小于m的正数。
  18. 根据权利要求16所述的显示面板，其中，所述第一连接信号线包括沿不同方向延伸的第一分段和第二分段，第一分段和第二分段位于不同的膜层。
  19. 根据权利要求1所述的显示面板，其中，
    用于驱动同一行所述第一子像素的多个所述第一电路位于同一行，和/或
    同一行的所述第一电路用于驱动两行以上的所述第一子像素。
  20. 一种显示装置，其中，包括权利要求1-19任一项所述的显示面板。
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