WO2023133977A1 - 一种半导体结构及一种半导体结构的制作方法 - Google Patents

一种半导体结构及一种半导体结构的制作方法 Download PDF

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Publication number
WO2023133977A1
WO2023133977A1 PCT/CN2022/078109 CN2022078109W WO2023133977A1 WO 2023133977 A1 WO2023133977 A1 WO 2023133977A1 CN 2022078109 W CN2022078109 W CN 2022078109W WO 2023133977 A1 WO2023133977 A1 WO 2023133977A1
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groove
conductive
substrate
semiconductor structure
electrical connection
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PCT/CN2022/078109
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English (en)
French (fr)
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王路广
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长鑫存储技术有限公司
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Priority to US17/826,222 priority Critical patent/US20230223367A1/en
Publication of WO2023133977A1 publication Critical patent/WO2023133977A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80801—Soldering or alloying

Definitions

  • Embodiments of the present disclosure relate to the field of semiconductors, and in particular, to a semiconductor structure and a manufacturing method of the semiconductor structure.
  • multi-layer stack packaging technology With the development of three-dimensional packaging technology, multi-layer stack packaging technology is widely used, but the multi-layer stack structure needs to use wafers of the same size for stacking, and the connection structure between wafers will occupy a certain part of the multi-layer stack structure.
  • the thickness will increase the overall thickness of the multi-layer stack structure, which is not suitable for the current demand for thinner and thinner terminals.
  • connection structure in the multilayer stack structure is getting smaller and smaller, and the distance between adjacent connection structures is getting smaller and smaller, which is likely to cause short circuits between adjacent connection structures and wafer-to-wafer Shedding between circles.
  • Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method of the semiconductor structure, which at least help to improve the reliability of the semiconductor structure.
  • an embodiment of the present disclosure provides a semiconductor structure on the one hand, including: a first substrate having a first surface, the first substrate has an electrical connection pillar protruding from the first surface, the There is a first groove at the top of the electrical connecting column; a second substrate with a second surface, the second substrate has a conductive column inside, and the second substrate also has a second groove, and the second groove exposes The top surface and at least part of the sides of the conductive column; the second surface is bonded to the first surface, and the electrical connection column is partially located in the second groove, and the conductive column is partially located in the In the first groove: a welding structure, at least part of the welding structure is filled in the second groove, and at least a part of the welding structure is also filled between the conductive pillar and the first groove.
  • the cross section of the portion of the conductive pillar exposed by the second groove is smaller than the cross section of the portion not exposed by the second groove.
  • the electrical connection column includes: a conductive main body, a first diffusion barrier layer located on the bottom and side surfaces of the conductive main body, and a first metal protection layer located on the side walls and bottom of the first groove, and the A portion of the conductive main body is located in the second groove.
  • the material of the conductive main body includes copper or aluminum; the material of the first diffusion barrier layer includes tantalum, titanium, titanium nitride or tantalum nitride.
  • the electrical connection column further includes: a first electroplating seed layer, the first electroplating seed layer is located between the conductive main body portion and the first diffusion barrier layer.
  • the ratio of the depth of the first groove to the depth of the second groove is in the range of 1:1 to 1:5 Inside.
  • the welding structure is also located between the electrical connecting column and the side wall of the second groove.
  • the material of the welding structure includes tin or tin-silver alloy and the like.
  • the second diffusion barrier layer is located on the bottom surface and the sidewall of the second groove, and is also located on the top of the conductive column exposed by the second groove. face and sides.
  • the width of the second groove is 2-3 times the width of the portion of the conductive pillar not exposed by the second groove.
  • an embodiment of the present disclosure further provides a method for fabricating a semiconductor structure, including: providing a first substrate having a first surface, and the first substrate has a structure protruding from the first surface.
  • the electrical connection post provide a second base with a second surface, the second base has a conductive post, and the second base also has a second groove, the second groove exposes the conductive post
  • the method for forming the electrical connection column includes: forming a first diffusion barrier layer; forming a conductive body part, the conductive body part is located on the top surface of the first diffusion barrier layer and the side of the first diffusion barrier layer A wall; forming a first metal protection layer, the first metal protection layer being located between the soldering structure in the second groove and the conductive main body portion.
  • the conductive body part before forming the conductive body part, it also includes forming a first electroplating seed layer, and the first electroplating seed layer is located between the conductive body part and the first diffusion barrier layer.
  • the method for forming the second groove includes: patterning the second substrate to form a second initial groove recessed from the second substrate from the second surface to the inside of the second substrate, so The second initial groove exposes the top surface and part of the sidewall of the initial conductive column; at least part of the width of the initial conductive column is removed along a direction perpendicular to the extending direction of the second initial groove to form the second groove, The remaining initial conductive pillars are used as the conductive pillars.
  • the width of the formed second groove is 2 to 3 times the width of the conductive pillar exposed by the second groove.
  • the ratio of the depth of the first groove to the depth of the second groove is 1:1 to 1: 5 range.
  • the second diffusion barrier layer before bonding the second surface and the first surface, it also includes: forming a second diffusion barrier layer, the second diffusion barrier layer is located on the bottom surface and the sidewall of the second groove, and further located on the top and side surfaces of the conductive pillar exposed by the second groove.
  • forming the welding structure includes: forming an initial welding structure, and the initial welding structure is located in the first groove; annealing to form the welded structure.
  • the technical solution provided by the embodiments of the present disclosure has at least the following advantages: by arranging the electrical connection column in the second groove and the conductive column in the first groove, the conductive column and the electrical connection column can be dislocated and overlapped, thereby It is beneficial to prevent the first base and the second base from sliding against each other, thereby improving the stability of bonding between the first base and the second base; In a groove, the height of the entire semiconductor structure can be reduced; while the connection between the electrical connection column and the conductive column can be realized through the welding structure, the contact area between the electrical connection column and the conductive column can be increased, thereby improving the heat dissipation of the entire semiconductor structure. Moreover, by increasing the contact area between the electrical connection pillar and the conductive pillar, the contact area between the first substrate and the second substrate can be increased, thereby reducing the contact resistance between the first substrate and the second substrate, and improving the performance of the semiconductor structure.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure
  • 2 to 13 are structural schematic diagrams corresponding to each step of a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure.
  • connection structure in the multilayer stack structure is getting smaller and smaller, and the distance between adjacent connection structures is getting smaller and smaller.
  • the small distance between the connection structures may cause Overlapping occurs between adjacent connection structures, resulting in a short circuit between adjacent connection structures.
  • TCB-NCF thermocompression bonding uses heating and pressure to make the bond between two adjacent substrates Welding is formed at the connection structure to realize the connection of adjacent substrates; NCF (non-conductive glue, Non Conduction Adhesive Film) cooperates with the TCB process, that is, by coating NCF between the two substrates, NCF is used as a filling material to fill the two The gap between the bases and wraps the connection structure protruding from the base.
  • NCF non-conductive glue, Non Conduction Adhesive Film
  • connection structure due to the special fluidity of the NCF material, it is impossible to give the connection structure a sufficient strength process, and the morphological force of the connection structure is prone to shift, making the connection between adjacent substrates unstable; moreover, the morphological force of the connection structure is prone to occur. Offset can easily make the shape of the connection structure abnormal, which may lead to dislocation of the connection between the substrates, reduce the signal transmission efficiency between adjacent substrates, and may also cause the adjacent connection structures to contact and cause a short circuit. In addition, since the NCF material is added between the substrates, the overall thickness of the stacked substrates is increased, which does not meet the current demand for thinner and thinner terminals.
  • the implementation of the present disclosure provides a semiconductor structure.
  • the electrical connection column in the second groove and the conductive column in the first groove By arranging the electrical connection column in the second groove and the conductive column in the first groove, the tightness of the connection between the first substrate and the second substrate can be improved. And the height of the entire semiconductor structure can be reduced.
  • the welding structure in the first groove and the second groove it can prevent the welding structure from flowing during the bonding process, resulting in interconnection of adjacent electrical connection columns or conductive columns.
  • the reliability of the semiconductor structure can be improved by arranging the welding structure in the first groove and the second groove, and by reducing the use of NCF materials, the consumption of materials can be reduced and the height of the entire semiconductor structure can be reduced, and It can also avoid the occurrence of a short circuit caused by the use of NCF material resulting in contact between adjacent connection structures.
  • FIG. 1 is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure.
  • the semiconductor structure includes: a first substrate 110 having a first surface 100, the first substrate 110 has an electrical connection column 120 protruding from the first surface 100, and the top of the electrical connection column 120 has a first groove 130;
  • the second substrate 150 on the second surface 140 has a conductive column 160 inside, and the second substrate 150 also has a second groove 170, and the second groove 170 exposes the top surface of the conductive column 160 and at least part of it.
  • the second surface 140 is bonded to the first surface 100, and the electrical connection column 120 is partly located in the second groove 170, and the conductive column 160 is partially located in the first groove 130; welding structure 180, at least part of the welding structure 180 The second groove 170 is filled, and at least part of the welding structure 180 is also filled between the conductive pillar 160 and the first groove 130 .
  • both the first substrate 110 and the second substrate 150 may be wafers, and the semiconductor structure may be a wafer stack structure. In some other embodiments, both the first substrate 110 and the second substrate 150 may be dies, and the semiconductor structure may be a die stack structure. Furthermore, in still some embodiments, one of the first substrate 110 and the second substrate 150 may be a wafer, and the other may be a chip.
  • the first base 110 may include: a passivation layer 111 , a conductive layer 112 and a substrate 113 .
  • the passivation layer 111 covers the surface of the substrate 113 facing the passivation layer 111, and the passivation layer 111 also covers part of the surface of the conductive layer 112, the passivation layer 111 is used to protect the conductive layer 112 and the substrate 113 , to prevent the conductive layer 112 and the substrate 113 from contacting with other structures, and improve the stability of the semiconductor structure; the conductive layer 112 is located in the substrate 113, and the substrate 113 exposes the surface of the conductive layer 112, and the conductive layer 112 is used to connect the electrical connection column 120 and other structures in the first substrate 110 are electrically connected.
  • the material of the passivation layer 111 can be an insulating material with a relatively high relative permittivity such as silicon nitride, silicon nitride, or silicon oxynitride
  • the material of the conductive layer 112 can be conductive such as aluminum, silver, or gold.
  • Material; the material type of the substrate 113 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material, and the elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanium, gallium arsenide or gallium Indium etc.
  • the electrical connection column 120 is located on the surface of the conductive layer 112 and is electrically connected to the conductive layer 112. The electrical signal of the conductive layer 112 is drawn out through the electrical connection column 120. In other embodiments, some of the electrical connection columns 120 can also be embedded in the conductive layer 112 , and in some other embodiments, the electrical connection column can also penetrate the conductive layer, and be electrically connected to the conductive layer through the sidewall of the electrical connection column.
  • the height of the semiconductor structure can be reduced by disposing the conductive column 160 in the first groove 130; by disposing the soldering structure 180 in the first groove 130 and the second groove
  • the welding structure 180 can be limited in 170 to prevent the flow of the welding structure 180 from causing overlap between adjacent electrical connection columns 120 or adjacent conductive columns 160, thereby reducing the possibility of short circuiting the semiconductor structure; Filling the welding structure 180 around the column 120 can make the connection between the first substrate 110 and the second substrate 150 tighter, thereby improving the connection tightness of the semiconductor structure, and in the process of bonding the first substrate 110 and the second substrate 150,
  • the conductive posts 160 and the electrical connection posts 120 will expand when heated, and the interaction force generated by the expansion will make the semiconductor structures more tightly connected.
  • the cross section of the portion of the conductive pillar 160 exposed by the second groove 170 may be smaller than the cross section of the portion not exposed by the second groove 170 .
  • the width of the exposed part of the conductive column 160 in the second groove 170 so that the electrical connection column 120 can be embedded in the second groove 170, while reserving a part of the conductive column for bonding the first substrate 110 and the second substrate 150 160 and the electrical connection column 120 thermal expansion space, so as to avoid direct contact between the conductive column 160 and the electrical connection column 120, avoid thermal expansion of the conductive column 160 and the electrical connection column 120 during the bonding process, and avoid causing the conductive column 160 and the electrical connection column 120 Mutual extrusion
  • the internal stress on the conductive post 160 and the electrical connection post 120 can be reduced, and by reserving the expansion between the conductive post 160 and the electrical connection post 120
  • the space can make the conductive post 160 and the electrical connection post 120 more tightly connected after thermal expansion; and correspondingly, the space volume of the second groove 170 can be increased, so that more welding structures 180 can be accommodated, thereby improving the first substrate
  • the electrical connection post 120 may include: a conductive body portion 121 , a first diffusion barrier layer 122 located on the bottom and side surfaces of the conductive body portion 121 , and a first metal protection layer located on the sidewall and bottom surface of the first groove 130 .
  • layer 123 , and part of the conductive body portion 121 is located in the second groove 170 .
  • the conductive body portion 121 can be used to implement signal transmission between the first substrate 110 and the second substrate 150 .
  • the first diffusion barrier layer 122 can be higher than the conductive body part 121, and the first diffusion barrier layer 122 can prevent the copper metal of the conductive body part 121 from entering the inside of the first substrate 110 when the ions diffuse, and prevent the conductive body part 121 from causing the first Substrate 110 is contaminated, thereby improving the performance of the overall semiconductor structure.
  • the first metal protection layer 123 is located on the surface of the conductive body part 121 facing the second groove 170, and the first metal protection layer 123 can also cover part of the inner wall of the first diffusion barrier layer 122 higher than the conductive body part 121, the first metal protection The layer 123 is used to protect the conductive body part 121 from being in contact with the air, to prevent part of the conductive body part 121 from reacting with the air, thereby preventing part of the conductive body part 121 from being oxidized, and the first metal protective layer 123 can isolate the conductive body part 121 from the air. In order to prevent the conductive main body 121 from being oxidized or corroded by water vapor, the first metal protection layer 123 can also be used to prevent the conductive main body 121 from contaminating the second substrate 150 during ion diffusion.
  • the electrical connection post 120 further includes: a first electroplating seed layer 124 , and the first electroplating seed layer 124 is located between the conductive body portion 121 and the first diffusion barrier layer 122 .
  • part of the first electroplating seed layer 124 may be higher than the surface of the conductive body portion 121, and the top surface of the first electroplating seed layer 124 may be flush with the top surface of the first diffusion barrier layer 122, and in other In an embodiment, the top surface of the first electroplating seed layer 124 may also be flush with the top surface of the conductive body portion 121 , and the height of the corresponding top surface of the first electroplating seed layer 124 may be selected according to requirements.
  • the material of the first electroplating seed layer 124 may be copper or aluminum, and the material of the first electroplating seed layer 124 may be the same as that of the conductive body portion 121 .
  • Forming the first electroplating seed layer 124 can help to guide the formation of the conductive body part 121, and the first electroplating seed layer 124 can improve the adhesion between the conductive body part 121 and the first diffusion barrier layer 122, thereby improving the conductive body part 121.
  • the stability of the connection with the first diffusion barrier layer 122, and the first electroplating seed layer 124 can also reduce the void defect inside the conductive body part 121, thereby improving the ability of the first diffusion barrier layer 122 to prevent the ion diffusion of the conductive body part 121 Effect.
  • the material of the conductive body portion 121 may include copper or aluminum; the material of the first diffusion barrier layer 122 may include tantalum, titanium, titanium nitride or tantalum nitride.
  • the copper material and aluminum material have good electrical conductivity, and the material itself is relatively cheap, which is beneficial to reduce the cost of the semiconductor structure while ensuring good electrical conductivity;
  • the material of the first diffusion barrier layer 122 is nitrogen Titanium nitride is used as an example.
  • a stacked structure of a titanium nitride layer and a tantalum layer can also be formed as the first diffusion barrier layer 122 , and the barrier properties of the first diffusion barrier layer 122 can be improved by the stacked structure of the titanium nitride layer and the tantalum layer.
  • the ratio of the depth of the first groove 130 to the depth of the second groove 170 ranges from 1:1 to 1:5.
  • the depth ratio is 1:2, 1:3.2 or 1:4, etc.
  • the ratio of the depth of the first groove 130 to the depth of the second groove 170 can be adjusted according to actual needs, and the sum of the depths of the first groove 130 and the second groove 170 needs to satisfy the welding structure 180
  • the first groove 130 and the second groove 170 need to be filled, and on the premise that the soldering structure 180 fills the first groove 130 and the second groove 170 , the deeper the depth of the second groove 170 is, the correspondingly the larger the contact area between the electrical connection column 120 and the conductive column 160 is, the larger the contact area is, the better the heat dissipation effect of the semiconductor structure is; when the first groove 130
  • the ratio of the depth of the second groove 170 to the depth of the second groove 170 is less than 1:10, the welding structure 180 may not be able to fill the entire first groove 130 and the second groove 170, resulting in low stability of the semiconductor structure.
  • the welding structure 180 is also located between the electrical connection post 120 and the sidewall of the second groove 170 .
  • the soldering structure 180 With the bonding of the first substrate 110 and the second substrate 150, the soldering structure 180 becomes molten and is squeezed by the conductive pillar 160, so that the soldering structure 180 in the molten state moves away from the conductive pillar 160 direction displacement, as the surfaces of the first surface 100 and the second surface 140 are attached, the welding structure 180 fills the remaining space of the first groove 130 and the second groove 170 under the action of gravity and the extrusion of the conductive pillar 160 , the tightness of the connection between the first substrate 110 and the second substrate 150 can be improved through the welding structure 180 .
  • the material of the welding structure 180 may include tin or tin-silver alloy or the like.
  • the melting point of tin or tin-silver alloy is low, and the freezing point is high. The speed is faster, thereby shortening the time of the entire semiconductor structure manufacturing process; tin or tin-silver alloy has a better affinity with metals such as copper, so that the connection effect between the soldered structure 180 and the electrical connection column 120 and the conductive column 160 is better. Tighter; tin or tin-silver alloy also has good conductivity, which is convenient for the electrical signal transmission of the electrical connection column 120 and the conductive column 160; tin or tin-silver alloy has good fluidity after heating, and is also convenient for connecting the electrical connection column 120 and the conductive column 160. Post 160 is bonded.
  • the semiconductor structure may further include: a second diffusion barrier layer 190, the second diffusion barrier layer 190 is located on the bottom surface and the sidewall of the second groove 170, and is also located on the conductive column 160 by the second groove. 170 exposed top and sides.
  • Setting the second diffusion barrier layer 190 can prevent the material of the conductive pillar 160 from entering the interior of the first substrate 110 when ion diffusion occurs, thereby reducing the possibility of causing contamination of the first substrate 110, thereby improving the performance of the semiconductor structure.
  • the grain boundaries and various defects of part of the conductive pillars 160 can be filled, thereby blocking the rapid diffusion path of atoms.
  • the second diffusion barrier layer 190 can be made of the same material as the first diffusion barrier layer 122, such as tantalum, titanium, titanium nitride or tantalum nitride, thereby reducing the types of materials used to produce semiconductor structures and facilitating the overall production. process control.
  • the width of the second groove 170 is 2-3 times the width of the portion of the conductive pillar 160 not exposed by the second groove 170 .
  • the width of the first groove 130 and the second groove 170 is 2 to 3 times the width of the conductive pillar 160, it is beneficial to connect the first groove 130 and the second groove 170 through the conductive pillar 160 and the electrical connection pillar 120. It can be understood that the ratio of the width of the first groove 130 and the second groove 170 to the width of the conductive column 160 can be based on the amount of space that the first groove 130 and the second groove 170 need to accommodate. The total volume of the conductive post 160 and the electrical connection post 120 is adjusted accordingly.
  • the electrical connection pillar 120 by disposing the electrical connection pillar 120 in the second groove 170 and disposing the conductive pillar 160 in the first groove 130, the conductive pillar 160 and the second substrate 150 are bonded together.
  • the electrical connection post 120 expands when heated, so that the conductive post 160 and the electrical connection post 120 engage with each other, thereby improving the tightness of the connection between the first substrate 110 and the second substrate 150;
  • the welding structure 180 in the first groove 130 and the second groove 170 can reduce the probability of a short circuit of the semiconductor structure caused by the electrical connection of the adjacent electrical connection column 120 or the adjacent conductive column 160 due to the flow of the solder structure 180; by making the electrical connection column 120 higher than the first substrate
  • the part of 110 disposed in the second groove 170 can reduce the height of the entire semiconductor structure, and can make the electrical connection column 120 and the conductive column 160 dislocated and overlapped, thereby improving the bonding strength between the first substrate 110 and the second substrate 150.
  • the connection between the electrical connection column 120 and the conductive column 160 can be improved.
  • the contact area of the conductive column 160 is conducive to reducing the contact resistance between the electrical connection column 120 and the conductive column 160, and is also conducive to improving the heat dissipation of the semiconductor structure;
  • the probability of short circuit of the semiconductor structure caused by the electrical connection of the adjacent electrical connection pillars 120 or the adjacent conductive pillars 160 can also be reduced, thereby improving the performance of the semiconductor structure.
  • an embodiment of the present disclosure also provides a method for fabricating a semiconductor structure, which can be used to fabricate the above-mentioned semiconductor structure.
  • a semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.
  • 2 to 13 are structural schematic diagrams corresponding to each step of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure.
  • a first substrate 110 having a first surface 100 is provided, and the first substrate 110 has electrical connection posts 120 protruding from the first surface 100 .
  • the method for forming the electrical connection column 120 may include: forming a first diffusion barrier layer 122; forming a conductive body portion 121, the conductive body portion 121 is located on the top surface of the first diffusion barrier layer 122 and the first diffusion barrier layer The sidewall of 122 ; forming the first metal protection layer 123 , the first metal protection layer 123 is located between the soldering structure in the second groove 170 and the conductive main body portion 121 .
  • the thickness of the first diffusion barrier layer 122 may be 10nm-200nm. It can be understood that when the thickness of the first diffusion barrier layer 122 is less than 10nm, the diffusion of copper metal ions in the conductive body part 121 will be blocked. The effect is not good. When the thickness of the first diffusion barrier layer 122 is higher than 200 nm, the resistance of the first diffusion barrier layer 122 may be too high, affecting the performance of the entire semiconductor structure.
  • the thickness of the first diffusion barrier layer 122 can be selected according to actual needs.
  • the first diffusion barrier layer 122 can prevent the copper metal of the conductive body part 121 from entering the interior of the first substrate 110 when the ions diffuse, causing contamination of the first substrate 110, thereby affecting the performance of the entire semiconductor structure; the first metal protective layer 123 It is used to protect the conductive body part 121 from being in contact with the air, avoiding part of the conductive body part 121 reacting with the air, resulting in oxidation of the part of the conductive body part 121, and the first metal protective layer 123 can separate the conductive body part 121 from the air, thereby To avoid oxidation or water vapor corrosion of the conductive body part 121 , and the first metal protection layer 123 can also be used to prevent the conductive body part 121 from polluting the second substrate 150 during ion diffusion.
  • the first diffusion barrier layer 122 may further include: referring to FIG. 2 , forming a mask layer 200 with a first pattern on the surface of the first surface 100 of the first substrate 110; The mask layer 200 is used as a mask to etch the passivation layer 111 of the first substrate 110 to form grooves.
  • the first base 110 includes a substrate 113 , a passivation layer 111 and a conductive layer 112 .
  • the groove of the passivation layer 111 exposes the top surface of the conductive layer 112; in other embodiments, part of the conductive layer 112 is also etched while the passivation layer 111 is etched, that is, part of the groove is also located in the conductive layer 112 ; In some other embodiments, the groove can also penetrate the conductive layer.
  • the method of etching the passivation layer 111 can be dry etching, for example, the plasma is accelerated and guided by an electric field, so that it has a certain energy, and the plasma is guided to bombard the passivation layer 111, thereby forming a concave cavity. groove.
  • a first diffusion barrier layer 122 is formed on the inner wall and the bottom surface of the groove.
  • the first diffusion barrier layer 122 may be formed by PVD (Physical Vapor Deposition).
  • the process steps of forming the first diffusion barrier layer 122 may include: forming an initial barrier layer on the surface of the mask layer 200 and the inner wall and bottom surface of the groove; forming a pattern layer, which exposes the initial barrier layer on the surface of the mask layer 200;
  • the graphic layer is a mask, and the initial barrier layer located on the surface of the mask layer 200 is removed by etching, leaving the initial barrier layer as the first diffusion barrier layer 122; the graphic layer is removed.
  • the conductive body portion 121 may further include: forming a first electroplating seed layer 124 , the first electroplating seed layer 124 is located between the conductive body portion 121 and the first diffusion barrier layer 122 .
  • the first electroplating seed layer 124 is formed by a PVD process.
  • the thickness of the first electroplating seed layer 124 may be 50 nm ⁇ 100 nm.
  • the material of the first electroplating seed layer 124 can be the same as the material of the conductive main body portion 121, the formation of the conductive main body portion 121 can be promoted by forming the first electroplating seed layer 124 first, and the subsequent formation of the first electroplating seed layer 124 can also be reduced.
  • the void defect inside the conductive body part 121, thereby improving the effect of the first diffusion barrier layer 122 to prevent the ion diffusion of the conductive body part 121, thereby improving the performance of the semiconductor structure, and the first electroplating seed layer 124 can also improve the conductive body part. 121 and the first diffusion barrier layer 122 , so as to improve the stability of the connection between the conductive body part 121 and the first diffusion barrier layer 122 .
  • the conductive body part 121 filling the groove is formed on the first diffusion barrier layer 122 , and the top of the conductive body part 121 has the groove.
  • an electroplating process may be used to form the conductive body portion 121 on the surface of the first electroplating seed layer 190 .
  • part of the conductive body portion 121 is lower than the passivation layer 111 , and the thickness difference between the thickness of the portion of the conductive body portion 121 lower than the passivation layer 111 and the passivation layer 111 may be the thickness of the mask layer 220 Between 1/10 and 1/5 times of that.
  • a process basis can be provided for the subsequent embedding of the electrical connection column 120 in the second substrate 150, and when the part of the conductive body part 121 lower than the passivation layer 111
  • the thickness difference between the passivation layer 111 and the thickness of the passivation layer 111 is less than 1/10 of the thickness of the mask layer 220
  • the first metal protective layer is subsequently formed, the first part of the top surface of the conductive body part 121 that is lower than the passivation layer 111
  • the metal protection layer may be higher than the passivation layer 111, which is not conducive to the embedding process between the electrical connection column 120 and the second substrate 150;
  • the thickness difference between them is greater than 1/5 of the thickness of the mask layer 220 , the thickness of this part of the conductive main body 121 lower than the passivation layer 111 is thinner, which reduces the conductivity of the electrical connection column 120 .
  • a first metal protection layer 123 is formed on the bottom surface and sidewalls of the groove at the top of the conductive body portion 121 , and the remaining groove is used as the first groove 130 .
  • the first metal protection layer 123 may be flush with the top surface of the first diffusion barrier layer 122 , and the thickness of the first metal protection layer 123 may be 5 nm ⁇ 50 nm.
  • the volume of the initial welded structure is related to the limiting space surrounded by the first metal protection layer 123, the thicker the first metal protection layer 123, the smaller the corresponding limiting space surrounded by the first metal protection layer 123, and the corresponding initial The volume of the welded structure is smaller.
  • the thickness of the first metal protection layer 123 can be selected according to the actual situation.
  • an initial soldering structure 210 filling the first groove 130 is also formed.
  • the initial soldering structure 210 provides a technical basis for the subsequent connection of the conductive pillar 160 and the electrical connecting pillar 120 .
  • the material of the initial welding structure 210 may be tin or tin-silver alloy.
  • the melting point and freezing point of tin or tin-silver alloy are relatively low, and the speed of forming the initial welding structure 210 is relatively fast, and the first metal protective layer
  • the limiting space formed by 123 can also limit the shape of the initial welding structure 210, and can prevent the initial welding structure 210 in the molten state from flowing to the surrounding during the formation of the initial welding structure 210, and can reduce the semiconductor structure caused by the flow of the initial welding structure 210.
  • the probability of electrical connection between adjacent conductive pillars 160 or adjacent electrical connecting pillars 120 is reduced, thereby reducing the risk of short circuits in the semiconductor structure.
  • the initial welded structure 210 in a molten state may be filled into the remaining space of the groove, and the initial welded structure 210 may be condensed into a solid state after the filling is completed.
  • the top surface of the initial welding structure 210 can be higher than the top surface of the first metal protection layer 123; The top surface is even; in some other embodiments, the top surface of the initial soldering structure 210 can also be lower than the first metal protection layer 123; it can be understood that when the first substrate 110 and the second substrate 150 are subsequently bonded , disposing the conductive post exposed in the second groove in the first groove 130 (refer to FIG. 7 ) will occupy part of the accommodation space of the first groove 130 (refer to FIG. 7 ), so the top surface of the initial soldering structure 210 is also It can be lower than the first metal protection layer 123, and the volume of the initial welding structure 210 can be adjusted according to actual needs.
  • the part of the initial welding structure 210 higher than the top surface of the first metal protection layer 123 is arc-shaped, and because the initial welding structure 210 has a relatively high condensation point, it is easy to solidify and form. It is relatively easy to form the top surface of the initial soldering structure 210 higher than the top surface of the first metal protection layer 123 .
  • the initial soldering structure 210 after forming the initial soldering structure 210 , it further includes: removing the mask layer 200 (refer to FIG. 8 ).
  • a second substrate 150 having a second surface 140 is provided, the second substrate 150 has a conductive column 160 therein, and the second substrate 150 also has a second groove 170, and the second groove 170 exposes the conductive column 160 and at least some of the sides.
  • the method for forming the second groove 170 includes: referring to FIG. 10 , patterning the second substrate 150 to form a second initial groove 171 recessed from the second substrate 150 from the second surface 140 to the inside of the second substrate 150 , the second initial groove 171 exposes the top surface and part of the sidewall of the initial conductive column 161; referring to FIG. In the slot 170 , the initial conductive pillar 161 (refer to FIG. 10 ) remains as the conductive pillar 160 .
  • the second initial groove 171 can be formed by dry etching, and the initial conductive pillar 161 can be etched with a mixed solution of hydrogen peroxide and ammonia water to form the second groove 170 and the conductive pillar 160, forming a conductive After the post 160, the surface of the conductive post 160 may also be cleaned with a gas containing hydrogen ions.
  • the internal stress on the conductive post 160 and the electrical connection post 120 can be reduced by reserving part of the space for the thermal expansion of the conductive post 160 and the electrical connection post 120, and by reserving a conductive
  • the expanded space between the post 160 and the electrical connection post 120 can make the connection between the conductive post 160 and the electrical connection post 120 more tightly after thermal expansion, and correspondingly can increase the space volume of the second groove 170, so that more welding can be accommodated.
  • the structure 180 can improve the tightness of the connection between the first substrate 110 and the second substrate 150 .
  • the width of the second groove 170 formed in the direction perpendicular to the extension of the conductive pillar 160 is 2-3 times the width of the exposed conductive pillar 160 of the second groove 170 .
  • the width of the second groove 170 By setting the width of the second groove 170 to be 2 to 3 times the width of the conductive column 160 exposed by the second groove 170, it is beneficial to realize the unoccupied space in the second groove 170 through the conductive column 160 and the electrical connection column 120. It can be understood that the ratio of the width of the second groove 170 to the width of the conductive pillar 160 can be adjusted according to the total volume of the conductive pillar 160 and the electrical connection pillar 120 to be accommodated in the first groove 130 and the second groove 170. Adjustment.
  • the ratio of the depth of the formed first groove 130 to the depth of the second groove 170 is in the range of 1:1 to 1:5, for example, the depth The ratio is 1:2, 1:3.2 or 1:4 etc.
  • the ratio of the depth of the first groove 130 to the depth of the second groove 170 can be adjusted according to actual needs, and the sum of the depths of the first groove 130 and the second groove 170 needs to satisfy the welding structure 180
  • the first groove 130 and the second groove 170 need to be filled, and on the premise that the soldering structure 180 fills the first groove 130 and the second groove 170 , the deeper the depth of the second groove 170 is, the correspondingly the larger the contact area between the electrical connection column 120 and the conductive column 160 is, the larger the contact area is, the better the heat dissipation effect of the semiconductor structure is; when the first groove 130
  • the ratio of the depth of the second groove 170 to the depth of the second groove 170 is less than 1:10, the welding structure 180 may not be able to fill the entire first groove 130 and the second groove 170, resulting in low stability of the semiconductor structure.
  • the surface of the conductive pillar 160 further includes a silicon oxide layer
  • the process of etching the first groove 130 and the second groove 170 also includes: removing the first groove The silicon oxide layer on the surface of the conductive pillar 160 exposed by the groove 130 and the second groove 170 .
  • the method for removing the silicon oxide layer may use hydrofluoric acid to etch the silicon oxide layer on the surface of the conductive pillar 160 exposed by the first groove 130 and the second groove 170 .
  • the second diffusion barrier layer 190 before bonding the second surface 140 and the first surface 100, it also includes: forming a second diffusion barrier layer 190, the second diffusion barrier layer 190 is located on the bottom surface of the second groove 170 and On the sidewall, and also on the top and side surfaces of the conductive pillar 160 exposed by the second groove 170 .
  • a layer of second diffusion barrier layer 190 can be formed on the surface of the second groove 170 by electroplating; in other embodiments, the second diffusion barrier layer can be formed by PVD, which can be The surface of the second substrate 150, the side walls and the bottom surface of the first groove 130 and the second groove 170 form a second initial barrier layer; The initial barrier layer; using the second pattern layer as a mask, etch and remove the second initial barrier layer located on the surface of the second substrate 150, leaving the second initial barrier layer as the second diffusion barrier layer 190; removing the second pattern layer.
  • Setting the second diffusion barrier layer 190 can prevent the material of the conductive pillar 160 from entering the interior of the first substrate 110 when ion diffusion occurs, thereby reducing the possibility of causing contamination of the first substrate 110, thereby improving the performance of the semiconductor structure.
  • the grain boundaries and various defects of part of the conductive pillars 160 can be filled, thereby blocking the rapid diffusion path of atoms.
  • a second electroplating seed layer before forming the second diffusion barrier layer, can also be formed on the bottom surface and sidewall of the second groove, and the second electroplating seed layer can improve the connection between the conductive column and the subsequently formed second electroplating seed layer. Adhesion between diffusion barrier layers.
  • the second surface 140 is bonded to the first surface 100, and the electrical connection column 120 is partially located in the second groove 170, the conductive column 160 is partially located in the first groove 130, and at least part of the conductive column 160 Displaced and overlapped with part of the electrical connection pillars 120 ; forming a welding structure 180 , at least part of the welding structure 180 is filled in the second groove 170 , and at least a part of the welding structure 180 is also filled between the conductive pillar 160 and the first groove 130 .
  • the initial welding structure 210 (refer to FIG. 9 ) is annealed to form the welding structure 180.
  • the initial welded structure 210 (refer to FIG. 9 ) is heated and becomes a molten state, and as the second surface 140 is attached to the surface of the first surface 100, the initial welded structure 210 (refer to FIG. 9 ) in the molten state is subjected to the second The positioning of a groove 130 and the second groove 170 and the extrusion of the electrical connection column 120 make the initial welding structure 210 (refer to FIG. 9 ) in the molten state move away from the electrical connection column 120.
  • annealing the semiconductor structure can condense the initial soldered structure 210 (refer to FIG. 9 ) in the molten state into the soldered structure 180 .
  • the electrical connection between the conductive posts 160 and the electrical connection posts 120 can be realized through the soldering structure 180 , and the connection between the first substrate 110 and the second substrate 150 can be strengthened through the soldering structure 180 , thereby improving the stability of the semiconductor structure.
  • the embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, by arranging the electrical connection column 120 in the second groove 170 and disposing the conductive column 160 in the first groove 130, so that the conductive column 160 can be electrically connected to the
  • the pillars 120 are misplaced and overlapped, so as to prevent the first substrate 110 and the second substrate 150 from sliding against each other, thereby improving the stability of bonding between the first substrate 110 and the second substrate 150; the conductive pillars 160 are arranged in the first concave In the groove 130, during the process of bonding the first substrate 110 and the second substrate 150, the conductive column 160 and the electrical connection column 120 undergo thermal expansion, so that the conductive column 160 and the electrical connection column 120 engage with each other, thereby improving the first substrate 110 and the second substrate 150.
  • the contact area between the first substrate 110 and the second substrate 150 can increase the contact area between the first substrate 110 and the second substrate 150 , thereby reducing the contact resistance between the first substrate 110 and the second substrate 150 and improving the performance of the semiconductor structure.

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Abstract

本公开实施例涉及半导体领域，提供一种半导体结构及一种半导体结构的制作方法，其中，一种半导体结构包括：具有第一面（100）的第一基底（110），第一基底（110）具有凸出于第一面（100）的电连接柱（120），电连接柱（120）顶部具有第一凹槽（130）；具有第二面（140）的第二基底（150），第二基底（150）内具有导电柱（160），且第二基底（150）还具有第二凹槽（170），第二凹槽（170）露出导电柱（160）的顶面以及至少部分侧面；且电连接柱（120）部分位于第二凹槽（170）内，导电柱（160）部分位于第一凹槽（130）内；焊接结构（180），至少部分焊接结构（180）填充于第二凹槽（170），且至少部分焊接结构（180）还填充于导电柱（160）与第一凹槽（130）之间。

Description

一种半导体结构及一种半导体结构的制作方法
交叉引用
本申请要求于2022年01月12日递交的名称为“一种半导体结构及一种半导体结构的制作方法”、申请号为202210033870.3的中国专利申请的优先权，其通过引用被全部并入本申请。
技术领域
本公开实施例涉及半导体领域，特别涉及一种半导体结构及一种半导体结构的制作方法。
背景技术
随着三维封装技术的发展，多层堆叠封装技术应用广泛，但是多层堆叠结构需要用到尺寸相同的晶圆来做堆叠，晶圆与晶圆间的连接结构会占据多层堆叠结构的一定厚度，会则增大多层堆叠结构整体的厚度，不适应现在终端越来越薄的需求。
此外，随着集成度的不断微缩，多层堆叠结构中连接结构的尺寸越来越小，相邻连接结构间的距离越来越小，容易引起相邻连接结构间的短路以及晶圆与晶圆间的脱落。
发明内容
本公开实施例提供一种半导体结构及一种半导体结构的制作方法，至少有利于提高半导体结构的可靠性。
根据本公开一些实施例，本公开实施例一方面提供一种半导体结构，包括：具有第一面的第一基底，所述第一基底具有凸出于所述第一面的电连接柱，所述电连接柱顶部具有第一凹槽；具有第二面的第二基底，所述第二基底内具有导电柱，且所述第二基底还具有第二凹槽，所述第二凹槽露出所述导电柱的顶面以及至少部分侧面；所述第二面与所述第一面相键合，且所述电连接柱部分位于所述第二凹槽内，所述导电柱部分位于所述第一凹槽内；焊接结构，至少部分所述焊接结构填充于所述第二凹槽，且至少部分所述焊接结构还填充于所述导电柱与所述第一凹槽之间。
另外，在平行于所述第二面的平面上，所述导电柱被所述第二凹槽暴露的部分的横截面比未被所述第二凹槽暴露的部分的横截面小。
另外，所述电连接柱包括：导电主体部、位于所述导电主体部底面和侧面的第一扩散阻挡层以及位于所述第一凹槽的侧壁和底面的第一金属保护层，且所述导电主体部的部分位于所述第二凹槽内。
另外，所述导电主体部的材料包括铜或铝；所述第一扩散阻挡层的材料包括钽、钛、氮化钛或者氮化钽。
另外，所述电连接柱还包括：第一电镀种子层，所述第一电镀种子层位于所述导电主体部与所述第一扩散阻挡层之间。
另外，在垂直于所述第一面或垂直于所述第二面的方向上，所述第一凹槽的深度与所述第二凹槽的深度之比在1:1～1:5范围内。
另外，所述焊接结构还位于所述电连接柱与所述第二凹槽的侧壁之间。
另外，所述焊接结构的材料包括锡或者锡银合金等。
另外，还包括：第二扩散阻挡层，所述第二扩散阻挡层位于所述第二凹槽的底面上以及侧壁上，以及还位于所述导电柱被所述第二凹槽暴露的顶面和侧面上。
另外，在平行于所述第二面的方向上，所述第二凹槽的宽度是所述导电柱未被所述第二凹槽暴露的部分的宽度的2～3倍。
根据本公开一些实施例，本公开实施例另一方面还提供一种半导体结构的制作方法，包括：提供具有第一面的第一基底，所述第一基底具有凸出于所述第一面的电连接柱；提供具有第二面的第二基底，所述第二基底内具有导电柱，且所述第二基底还具有第二凹槽，所述第二凹槽露出所述导电柱的顶面以及至少部分侧面；将所述第二面与所述第一面进行键合，且所述电连接柱部分位于所述第二凹槽内，所述导电柱部分位于所述第一凹槽内，且至少部分所述导电柱与部分所述电连接柱错位交叠；形成焊接结构，至少部分所述焊接结构填充于所述第二凹槽，且至少部分所述焊接结构还填充于所述导电柱与所述第一凹槽之间。
另外，形成所述电连接柱的方法包括：形成第一扩散阻挡层；形成导电 主体部，所述导电主体部位于所述第一扩散阻挡层的顶面及所述第一扩散阻挡层的侧壁；形成第一金属保护层，所述第一金属保护层位于所述第二凹槽内的所述焊接结构与所述导电主体部之间。
另外，在形成所述导电主体部之前还包括，形成第一电镀种子层，所述第一电镀种子层位于所述导电主体部与所述第一扩散阻挡层之间。
另外，形成所述第二凹槽的方法包括：图形化所述第二基底，以形成自所述第二基底自所述第二面向所述第二基底内部凹陷的第二初始凹槽，所述第二初始凹槽暴露初始导电柱的顶面及部分侧壁；至少沿垂直于所述第二初始凹槽延伸方向去除部分宽度的所述初始导电柱，以形成所述第二凹槽，剩余所述初始导电柱作为所述导电柱。
另外，在垂直于所述导电柱延伸的方向上，形成的所述第二凹槽的宽度是所述第二凹槽暴露的所述导电柱宽度的2～3倍。
另外，在垂直于所述第一面或者垂直于所述第二面的方向上，形成的所述第一凹槽的深度与所述第二凹槽的深度之比在1:1～1:5范围内。
另外，在键合所述第二面与所述第一面前还包括：形成第二扩散阻挡层，所述第二扩散阻挡层位于所述第二凹槽的底面上以及侧壁上，以及还位于所述导电柱被所述第二凹槽暴露的顶面和侧面上。
另外，形成所述焊接结构包括：形成初始焊接结构，所述初始焊接结构位于所述第一凹槽内；键合所述第二面与所述第一面的过程中对所述初始焊接结构退火处理，以形成所述焊接结构。
本公开实施例提供的技术方案至少具有以下优点：通过将电连接柱设置于第二凹槽内，将导电柱设置于第一凹槽内，可以使得导电柱与电连接柱错位交叠，从而有利于避免第一基底和第二基底相互滑动，进而提高第一基底及第二基底之间键合的稳定性；且通过将电连接柱设置于第二凹槽内，将导电柱设置与第一凹槽内，可以降低整个半导体结构的高度；通过焊接结构实现电连接柱及导电柱的连接的同时可以增加电连接柱与导电柱之间的接触面积，从而可以提高整个半导体结构的散热，且通过增加电连接柱与导电柱之间的接触面积可以提高第一基底与第二基底之间的接触面积，进而降低第一基底与第二基底之间的接触电阻，提高半导体结构的性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，除非有特别申明，附图中的图不构成比例限制。
图1为本公开一实施例提供一种半导体结构的结构示意图；
图2至图13为本公开一实施例提供的一种半导体结构的制作方法各步骤对应的结构示意图。
具体实施方式
由背景技术可知，随着集成度的不断微缩，多层堆叠结构中连接结构的尺寸越来越小，且相邻连接结构的间距越来越小，然而连接结构之间的间距小就可能带来相邻的连接结构之间出现搭接，导致相邻的连接结构之间出现短路的情况。
经分析发现，目前的堆叠基底封装技术中，通常采用TCB-NCF热压键合工艺，其中，TCB(热压焊，Thermo Compression Bonding)利用加热和加压力，使得相邻两个基底之间的连接结构处形成焊接，以实现相邻基底的连接；NCF(非导电性胶水，Non Conduction Adhesive Film)配合TCB工艺作业，即通过在两个基底之间涂覆NCF，NCF作为填充材料填充两个基底之间的间隙并包裹凸出于基底的连接结构。
然而，由于NCF材料特殊的流动性，无法给连接结构足够强度的制程，连接结构的形态受力容易发生偏移，使得相邻基底之间连接不稳定；而且，连接结构的形态受力容易发生偏移，容易使得连接结构的形态异常，可能导致基底之间的连接处发生错位，降低相邻基底间的信号传递效率，也可能到导致相邻连接结构接触而短路。此外，由于在基底之间增加了NCF材料，增大了堆叠基底的整体厚度，不适应现在终端越来越薄的需求。
本公开实施提供一种半导体结构，通过将电连接柱设置于第二凹槽内，将导电柱设置于第一凹槽内，可以提高第一基底及第二基底之间的连接的紧密性，且可以降低整个半导体结构的高度，通过将焊接结构设置于第一凹槽及第二凹槽内可以避免焊接结构在键合过程中出现流动，导致相邻的电连接柱或者导电柱出现互连的情况，通过将焊接结构设置于第一凹槽及第二凹槽内可以提 高半导体结构的可靠性，且通过减少NCF材料的使用可以减小材料的消耗以及可以降低整个半导体结构的高度，且还可以避免出现因为NCF材料的使用导致相邻连接结构接触而短路的情况的出现。
下面将结合附图对本公开的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本公开各实施例中，为了使读者更好地理解本公开实施例而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本公开实施例所要求保护的技术方案。
图1为本公开一实施例提供的半导体结构的结构示意图。
参考图1，半导体结构包括：具有第一面100的第一基底110，第一基底110具有凸出于第一面100的电连接柱120，电连接柱120顶部具有第一凹槽130；具有第二面140的第二基底150，所述第二基底150内具有导电柱160，且第二基底150还具有第二凹槽170，第二凹槽170露出导电柱160的顶面以及至少部分侧面；第二面140与第一面100相键合，且电连接柱120部分位于第二凹槽170内，导电柱160部分位于第一凹槽130内；焊接结构180，至少部分焊接结构180填充于第二凹槽170，且至少部分焊接结构180还填充于导电柱160与第一凹槽130之间。
在一些实施例中，第一基底110和第二基底150可以均为晶圆(wafer)，半导体结构可以为晶圆堆叠结构。在另一些实施例中，第一基底110和第二基底150也可以均为芯片(die)，半导体结构可以为芯片堆叠结构。此外，在又一些实施例中，第一基底110和第二基底150中的一者可以为晶圆，另一者可以为芯片。
具体的，在一些实施例中，第一基底110可以包括：钝化层111、导电层112及衬底113。
在一些实施例中，钝化层111覆盖衬底113朝向钝化层111的表面，且钝化层111还覆盖导电层112的部分表面，钝化层111用于保护导电层112及衬底113，避免导电层112及衬底113与其他结构接触，提高半导体结构的稳定性；导电层112位于衬底113内，且衬底113暴露导电层112的表面，导电层112用于将电连接柱120及第一基底110内的其他结构电连接。
在一些实施例中，钝化层111的材料可以是氮化硅、氮化硅或氮氧化硅 等相对介电常数较高的绝缘材料，导电层112的材料可以为铝、银或者金等导电材料；衬底113的材料类型可以为元素半导体材料或者晶态无机化合物半导体材料，元素半导体材料可以为硅或者锗；晶态无机化合物半导体材料可以为碳化硅、锗化硅、砷化镓或者镓化铟等。
在一些实施例中，电连接柱120位于导电层112的表面，且与导电层112电连接，通过电连接柱120将导电层112的电信号引出，在另一些实施例中，部分电连接柱120还可以嵌入导电层112内，在又一些实施例中，电连接柱还可以将导电层贯穿，通过电连接柱的侧壁与导电层电连接。
通过设置电连接柱120位于第二凹槽170内，将导电柱160设置于第一凹槽130内可以降低半导体结构的高度；通过将焊接结构180设置于第一凹槽130及第二凹槽170内可以对焊接结构180进行限位，避免焊接结构180流动导致相邻的电连接柱120或者相邻的导电柱160之间出现搭接，从而降低半导体结构短路的可能性；通过将电连接柱120周围填充焊接结构180可以使第一基底110及第二基底150之间的连接更紧密，从而提高半导体结构连接紧密性，且在键合第一基底110及第二基底150的过程中，导电柱160及电连接柱120会受热膨胀，膨胀产生的相互作用力会使半导体结构连接的更紧密。
在一些实施例中，在平行于第二面140的平面上，导电柱160被第二凹槽170暴露的部分的横截面可以比未被第二凹槽170暴露的部分的横截面小。
通过调整第二凹槽170暴露的部分导电柱160的宽度以使电连接柱120可以嵌入第二凹槽170内，同时为键合第一基底110及第二基底150的时候预留部分导电柱160及电连接柱120热膨胀的空间，从而避免导电柱160及电连接柱120直接接触，避免导电柱160及电连接柱120在键合过程中发生热膨胀，避免导致导电柱160及电连接柱120相互挤压，通过预留部分导电柱160及电连接柱120热膨胀的空间可以减小导电柱160及电连接柱120受到的内部应力，且通过预留导电柱160及电连接柱120之间膨胀的空间可以使得导电柱160及电连接柱120在热膨胀后连接更加紧密；且相应的可以增加第二凹槽170的空间体积，从而可以容纳更多的焊接结构180，从而可以提高第一基底110及第二基底150之间的连接的紧密性。
在一些实施例中，电连接柱120可以包括：导电主体部121、位于导电主 体部121底面和侧面的第一扩散阻挡层122以及位于第一凹槽130的侧壁和底面的第一金属保护层123，且导电主体部121的部分位于第二凹槽170内。
在一些实施例中，导电主体部121可以用于实现第一基底110及第二基底150之间信号传输。
第一扩散阻挡层122可以高于导电主体部121，第一扩散阻挡层122可以避免导电主体部121铜金属在离子扩散的时候部分离子进入第一基底110内部，避免导电主体部121造成第一基底110污染，从而提高整个半导体结构的性能。第一金属保护层123位于导电主体部121朝向第二凹槽170的表面，且第一金属保护层123还可以覆盖部分第一扩散阻挡层122高于导电主体部121的内壁，第一金属保护层123用于保护导电主体部121不与空气接触，避免部分导电主体部121与空气发生反应，从而防止部分导电主体部121氧化，通过第一金属保护层123可以将导电主体部121与空气隔开，从而避免导电主体部121出现氧化或者出现水汽腐蚀，且第一金属保护层123还可以用于防止导电主体部121在离子扩散的过程中污染第二基底150。
在一些实施例中，电连接柱120还包括：第一电镀种子层124，第一电镀种子层124位于导电主体部121与第一扩散阻挡层122之间。
在一些实施例中，部分第一电镀种子层124可以高于导电主体部121的表面，且第一电镀种子层124的顶面可以与第一扩散阻挡层122的顶面齐平，在另一些实施例中，第一电镀种子层124的顶面也可以与导电主体部121的顶面齐平，可以根据需求选择对应的第一电镀种子层124的顶面高度。
第一电镀种子层124的材料可以是铜或铝，第一电镀种子层124的材料可以与导电主体部121的材料相同。通过形成第一电镀种子层124可以有利于引导导电主体部121的形成，且通过第一电镀种子层124可以提高导电主体部121与第一扩散阻挡层122的附着性，进而提高导电主体部121与第一扩散阻挡层122连接的稳定性，且通过第一电镀种子层124还可以减少导电主体部121内部的空洞缺陷，从而提高第一扩散阻挡层122的防止导电主体部121的离子扩散的效果。
导电主体部121的材料可以包括铜或铝；第一扩散阻挡层122的材料可以包括钽、钛、氮化钛或者氮化钽。
可以理解的是，铜材料及铝材料的导电性能较好，且材料本身价格较低，有利于在保证良好的导电性的同时降低半导体结构的成本；以第一扩散阻挡层122的材料为氮化钛为例，通过在导电主体部121的表面形成氮化钛层，可以填充部分导电主体部121的晶粒间界及各种缺陷，从而阻断了原子的快速扩散途径，在一些实施例中，还可以形成氮化钛层及钽层的叠层结构作为第一扩散阻挡层122，通过氮化钛层及钽层的叠层结构可以提高第一扩散阻挡层122的阻挡特性。
在一些实施例中，在垂直于第一面100或垂直于第二面140的方向上，第一凹槽130的深度与第二凹槽170的深度之比在1:1～1:5范围内，例如深度之比为1:2、1:3.2或者1:4等。
可以理解的是，第一凹槽130的深度与第二凹槽170的深度之比可以根据实际的需求进行调整，第一凹槽130及第二凹槽170的深度之和需满足焊接结构180在键合第一基底110及第二基底150之后需要填充满第一凹槽130及第二凹槽170，且在满足焊接结构180填充满第一凹槽130及第二凹槽170的前提下，第二凹槽170的深度越深，相应的，电连接柱120及导电柱160之间的接触面积也就越大，接触面积越大半导体结构的散热效果越好；当第一凹槽130的深度与第二凹槽170的深度之比小于1:10后，可能出现焊接结构180无法填充满整个第一凹槽130与第二凹槽170，导致半导体结构的稳定性不高。
在一些实施例中，焊接结构180还位于电连接柱120与第二凹槽170的侧壁之间。
可以理解的是，随着第一基底110及第二基底150的键合，焊接结构180变为熔融状态，且被导电柱160挤压，以使熔融状态下的焊接结构180向远离导电柱160的方向位移，随着第一面100及第二面140的表面贴合，焊接结构180在重力的作用及导电柱160的挤压下填充满第一凹槽130与第二凹槽170剩余空间，通过焊接结构180可以提高第一基底110及第二基底150连接的紧密性。
在一些实施例中，焊接结构180的材料可以包括锡或者锡银合金等。
可以理解的是，锡或者锡银合金的熔点较低，冷凝点较高，在键合第一基底110及第二基底150的过程中焊接结构180变为液态的速度及从液态变为 固态的速度较快，从而可以缩短整个半导体结构制作过程的时间；锡或者锡银合金与铜等金属有较好的亲和力，使得焊接结构180与电连接柱120及导电柱160的连接效果较好，连接更紧密；锡或者锡银合金还具有良好的导电率，便于电连接柱120及导电柱160的电信号传输；锡或者锡银合金在加热后流动性好，也便于将电连接柱120及导电柱160键合。
在一些实施例中，半导体结构还可以包括：第二扩散阻挡层190，第二扩散阻挡层190位于第二凹槽170的底面上以及侧壁上，以及还位于导电柱160被第二凹槽170暴露的顶面和侧面上。
通过设置第二扩散阻挡层190可以避免导电柱160的材料在发生离子扩散的时候部分离子进入第一基底110内部，从而减小造成第一基底110污染的可能性，进而提高半导体结构的性能，通过设置第二扩散阻挡层190可以填充部分导电柱160的晶粒间界及各种缺陷，从而阻断原子的快速扩散途径。
在一些实施例中，第二扩散阻挡层190可以与第一扩散阻挡层122的材料相同，例如是钽、钛、氮化钛或者氮化钽，从而减少生产半导体结构的材料种类，便于整个生产工艺的管控。
在一些实施例中，在平行于第二面140的方向上，第二凹槽170的宽度是导电柱160未被第二凹槽170暴露的部分的宽度的2～3倍。通过设置第一凹槽130与第二凹槽170的宽度和是导电柱160宽度的2～3倍有利于通过导电柱160及电连接柱120将第一凹槽130及第二凹槽170中未被占用的空间进行填充，可以理解的是，第一凹槽130与第二凹槽170的宽度与导电柱160宽度的比值可以根据第一凹槽130与第二凹槽170需容纳内的导电柱160及电连接柱120的总体积进行相应调整。
本公开实施例通过将电连接柱120设置于第二凹槽170内，将导电柱160设置于第一凹槽130内，在键合第一基底110及第二基底150过程中导电柱160及电连接柱120发生受热膨胀，使得导电柱160及电连接柱120相互卡合，从而提高第一基底110及第二基底150之间连接的紧密性；通过将焊接结构180设置于第一凹槽130及第二凹槽170内可以降低因焊接结构180流动导致相邻的电连接柱120或者相邻的导电柱160电连接导致半导体结构短路的概率；通过将电连接柱120高于第一基底110的部分设置于第二凹槽170内可以降低整 个半导体结构的高度，且可以使得电连接柱120与导电柱160错位交叠，进而提高第一基底110及第二基底150之间键合的稳定性；通过将电连接柱120高于第一基底110的部分设置于第二凹槽170内，并通过焊接结构180实现电连接柱120与导电柱160的电连接可以提高电连接柱120与导电柱160的接触面积，有利于降低电连接柱120与导电柱160的接触电阻，还有利于提高半导体结构的散热；通过将电连接柱120高于第一基底110的部分设置于第二凹槽170内，还可以降低相邻的电连接柱120或者相邻的导电柱160电连接导致半导体结构短路的概率，从而提高半导体结构的性能。
相应的，本公开一实施例还提供一种半导体结构的制作方法，可以用于制作上述半导体结构，相同或者相应的部分可以参考图1所述的实施例，以下将不再赘述。以下将结合附图对本公开另一实施例提供的半导体结构进行详细说明。图2至图13为本公开一实施例提供的一种半导体结构的制造方法各步骤对应的结构示意图。
参考图2至图9，提供具有第一面100的第一基底110，第一基底110具有凸出于第一面100的电连接柱120。
在一些实施例中，形成电连接柱120的方法可以包括：形成第一扩散阻挡层122；形成导电主体部121，导电主体部121位于第一扩散阻挡层122的顶面及第一扩散阻挡层122的侧壁；形成第一金属保护层123，第一金属保护层123位于第二凹槽170内的焊接结构与导电主体部121之间。
在一些实施例中，第一扩散阻挡层122的厚度可以是10nm～200nm，可以理解的是，当第一扩散阻挡层122的厚度低于10nm，阻挡导电主体部121的铜金属的离子扩散的效果不佳，当第一扩散阻挡层122的厚度高于200nm时，可能会导致第一扩散阻挡层122的电阻太高，影响整个半导体结构的性能。
第一扩散阻挡层122的厚度可以根据实际需求进行选择对应的厚度。
第一扩散阻挡层122可以避免导电主体部121的铜金属在离子扩散的时候部分离子进入第一基底110内部，造成第一基底110污染，进而影响整个半导体结构的性能；第一金属保护层123用于保护导电主体部121不与空气接触，避免部分导电主体部121与空气发生反应，导致部分导电主体部121氧化，通过第一金属保护层123可以将导电主体部121与空气隔开，从而避免导电主体 部121出现氧化或者出现水汽腐蚀，且第一金属保护层123还可以用于防止导电主体部121在离子扩散的过程中污染第二基底150。
在一些实施例中，在形成第一扩散阻挡层122之前还可以包括：参考图2，在第一基底110的第一面100的表面形成具有第一图形的掩膜层200；参考图3以掩膜层200为掩膜刻蚀第一基底110的钝化层111，以形成凹槽。
在一些实施例中，第一基底110包括衬底113、钝化层111以及导电层112。钝化层111的凹槽暴露导电层112的顶面；在另一些实施例中，在刻蚀钝化层111的同时还刻蚀部分导电层112，即，部分凹槽还位于导电层112内；在又一些实施例中，凹槽还可以贯穿导电层。
在一些实施例中，刻蚀钝化层111的方法可以采用干法刻蚀，例如通过电场对等离子体进行加速引导，使其具备一定能量，并引导等离子体轰击钝化层111，进而形成凹槽。
参考图4，在凹槽的内壁以及底面形成第一扩散阻挡层122。
在一些实施例中，可以采用PVD(Physical Vapor Deposition物理气相沉积)的方式形成第一扩散阻挡层122。
形成第一扩散阻挡层122的工艺步骤可以包括：在掩膜层200表面以及凹槽内壁以及底面形成初始阻挡层；形成图形层，该图形层露出位于掩膜层200表面的初始阻挡层；以图形层为掩膜，刻蚀去除位于掩膜层200表面的初始阻挡层，剩余初始阻挡层作为第一扩散阻挡层122；去除图形层。
参考图5，在形成导电主体部121之前还可以包括：形成第一电镀种子层124，第一电镀种子层124位于导电主体部121与第一扩散阻挡层122之间。
在一些实施例中，采用PVD工艺形成第一电镀种子层124。
在一些实施例中，第一电镀种子层124的厚度可以是50nm～100nm。
第一电镀种子层124的材料可以与导电主体部121的材料相同，通过先形成第一电镀种子层124可以促进导电主体部121的形成，且通过第一电镀种子层124还可以减少后续形成的导电主体部121内部的空洞缺陷，从而提高第一扩散阻挡层122的防止导电主体部121的离子扩散的效果，进而提高半导体结构的性能，且通过第一电镀种子层124还可以提高导电主体部121与第一扩 散阻挡层122的附着性，从而提高导电主体部121与第一扩散阻挡层122连接的稳定性。
参考图6，在第一扩散阻挡层122上形成填充凹槽的导电主体部121，且导电主体部121的顶部具有凹槽。
在一些实施例中，可以采用电镀工艺，在第一电镀种子层190表面形成导电主体部121。
在一些实施例中，部分导电主体部121低于钝化层111，且低于钝化层111的部分导电主体部121的厚度与钝化层111之间的厚度差可以是掩膜层220厚度的1/10～1/5倍之间。
可以理解的是，通过设置部分导电主体部121低于钝化层111可以为后续将电连接柱120嵌入第二基底150提供工艺基础，且当低于钝化层111的部分导电主体部121的厚度与钝化层111之间的厚度差小于掩膜层220厚度的1/10时，后续形成第一金属保护层时，位于低于钝化层111的部分导电主体部121顶面的第一金属保护层可能会高于钝化层111，不利于电连接柱120与第二基底150之间的嵌入处理；当低于钝化层111的部分导电主体部121的厚度与钝化层111之间的厚度差大于掩膜层220厚度的1/5时，这部分低于钝化层111的导电主体部121厚度较薄，降低电连接柱120的导电性能。
参考图7，在导电主体部121的顶部的凹槽的底面及侧壁上形成第一金属保护层123，剩余凹槽作为第一凹槽130。
在一些实施例中，第一金属保护层123可以与第一扩散阻挡层122的顶面齐平，第一金属保护层123的厚度可以是5nm～50nm。
可以理解的是，第一金属保护层123的厚度低于5nm时，保护导电主体部121的效果不佳，第一金属保护层123的厚度大于50nm时，影响后续在形成初始焊接结构的体积，初始焊接结构的体积与第一金属保护层123围成的限位空间有关，第一金属保护层123越厚相应的第一金属保护层123围成的限位空间越小，相应的可容纳初始焊接结构的体积越小。
第一金属保护层123的厚度可以根据实际的情况进行选择对应的厚度。
参考图8，在一些实施例中，在形成第一金属保护层123后还形成填充第 一凹槽130(参考图7)的初始焊接结构210。
初始焊接结构210为后续连接导电柱160及电连接柱120提供工艺基础。
在一些实施例中，初始焊接结构210的材料可以是锡或者锡银合金，通过锡或者锡银合金的熔点及凝固点较低，形成初始焊接结构210的速度较快，且通过第一金属保护层123形成的限位空间还可以限制初始焊接结构210形状，且可以防止在形成初始焊接结构210的过程中熔融状态的初始焊接结构210向周围流动，可以减少半导体结构因为初始焊接结构210流动导致相邻的导电柱160或者相邻电连接柱120电连接的概率，从而减少半导体结构短路的风险。
在一些实施例中，可以通过将熔融状态下的初始焊接结构210填充至凹槽的剩余空间，填充完成后可以通过冷凝的方式使初始焊接结构210变为固态。
在一些实施例中，初始焊接结构210的顶面可以高于第一金属保护层123的顶面；在另一些实施例中，初始焊接结构210的顶面也可以与第一金属保护层123的顶面平齐；在又一些实施例中，初始焊接结构210的顶面也可以低于第一金属保护层123；可以理解的是，在后续键合第一基底110与第二基底150的时候，将第二凹槽暴露的导电柱设置于第一凹槽130(参考图7)内，会占用部分第一凹槽130(参考图7)的容纳空间，故初始焊接结构210的顶面也可以低于第一金属保护层123，初始焊接结构210的体积可以根据实际需求进行调整。
可以理解的是，由于液体表面张力的存在，故高于第一金属保护层123顶面的部分初始焊接结构210呈圆弧状，且由于初始焊接结构210的冷凝点较高，容易凝固成型故形成初始焊接结构210的顶面高于第一金属保护层123的顶面相对容易。
参考图9，形成初始焊接结构210后还包括：去除掩膜层200(参考图8)。
参考图10及图11，提供具有第二面140的第二基底150，第二基底150内具有导电柱160，且第二基底150还具有第二凹槽170，第二凹槽170露出导电柱160的顶面以及至少部分侧面。
具体的，形成第二凹槽170的方法包括：参考图10，图形化第二基底150，以形成自第二基底150自第二面140向第二基底150内部凹陷的第二初始凹槽171，第二初始凹槽171暴露初始导电柱161的顶面及部分侧壁；参考图11，至 少沿垂直于第二初始凹槽171延伸方向去除部分宽度的初始导电柱161，以形成第二凹槽170，剩余初始导电柱161(参考图10)作为导电柱160。
在一些实施例中，可以采用干法刻蚀的方法形成第二初始凹槽171，可以采用双氧水及氨水的混合溶液刻蚀初始导电柱161以形成第二凹槽170及导电柱160，形成导电柱160之后还可以采用含氢离子的气体清洗导电柱160的表面。
继续参考图10及图11，通过去除部分宽度的第二初始凹槽171暴露的初始导电柱161可以使具有第二凹槽170及导电柱160的第二基底150及具有第一凹槽130(参考图7)及电连接柱120(参考图9)的第一基底110(参考图9)相互嵌合，从而为在后续键合第一基底110(参考图9)及第二基底150的时候预留部分导电柱160及电连接柱120(参考图9)热膨胀的空间，从而避免导电柱160及电连接柱120直接接触，避免导电柱160及电连接柱120在键合过程中发生热膨胀，避免导致导电柱160及电连接柱120相互挤压，通过预留部分导电柱160及电连接柱120热膨胀的空间可以减小导电柱160及电连接柱120受到的内部应力，且通过预留导电柱160及电连接柱120之间膨胀的空间可以使得导电柱160及电连接柱120在热膨胀后连接更加紧密，且相应的可以增加第二凹槽170的空间体积，从而可以容纳更多的焊接结构180，从而可以提高第一基底110及第二基底150之间的连接的紧密性。
在一些实施例中，在垂直于导电柱160延伸的方向上，形成的第二凹槽170的宽度是第二凹槽170暴露的导电柱160宽度的2～3倍。
通过设置第二凹槽170的宽度是第二凹槽170暴露的导电柱160宽度的2～3倍有利于通过导电柱160及电连接柱120将第二凹槽170中未被占用的空间进行填充，可以理解的是，第二凹槽170的宽度与导电柱160宽度的比值可以根据第一凹槽130与第二凹槽170需容纳的导电柱160及电连接柱120的总体积进行相应调整。
在垂直于第一面100或者垂直于第二面140的方向上，形成的第一凹槽130的深度与第二凹槽170的深度之比在1:1～1:5范围内，例如深度之比为1:2、1:3.2或者1:4等。
可以理解的是，第一凹槽130的深度与第二凹槽170的深度之比可以根据实际的需求进行调整，第一凹槽130及第二凹槽170的深度之和需满足焊 接结构180在键合第一基底110及第二基底150之后需要填充满第一凹槽130及第二凹槽170，且在满足焊接结构180填充满第一凹槽130及第二凹槽170的前提下，第二凹槽170的深度越深，相应的，电连接柱120及导电柱160之间的接触面积也就越大，接触面积越大半导体结构的散热效果越好；当第一凹槽130的深度与第二凹槽170的深度之比小于1:10后，可能出现焊接结构180无法填充满整个第一凹槽130与第二凹槽170，导致半导体结构的稳定性不高。
继续参考图10及图11，在一些实施例中，导电柱160的表面还包括氧化硅层，在刻蚀形成第一凹槽130及第二凹槽170的过程中还包括：去除第一凹槽130及第二凹槽170暴露的导电柱160表面的氧化硅层。
在一些实施例中，去除氧化硅层方法可以采用氢氟酸的方法刻蚀第一凹槽130及第二凹槽170暴露的导电柱160表面的氧化硅层。
参考图12，在一些实施例中，在键合第二面140与第一面100前还包括：形成第二扩散阻挡层190，第二扩散阻挡层190位于第二凹槽170的底面上以及侧壁上，以及还位于导电柱160被第二凹槽170暴露的顶面和侧面上。
在一些实施例中，可以采用电镀的方式在第二凹槽170的表面形成一层第二扩散阻挡层190；在另一些实施例中，可以采用PVD的方式形成第二扩散阻挡层，可以第二基底150的表面、第一凹槽130及第二凹槽170的侧壁及底面形成第二初始阻挡层；形成第二图形层，该第二图形层露出位于第二基底150表面的第二初始阻挡层；以第二图形层为掩膜，刻蚀去除位于第二基底150表面的第二初始阻挡层，剩余第二初始阻挡层作为第二扩散阻挡层190；去除第二图形层。
通过设置第二扩散阻挡层190可以避免导电柱160的材料在发生离子扩散的时候部分离子进入第一基底110内部，从而减小造成第一基底110污染的可能性，进而提高半导体结构的性能，通过设置第二扩散阻挡层190可以填充部分导电柱160的晶粒间界及各种缺陷，从而阻断原子的快速扩散途径。
在一些实施例中，在形成第二扩散阻挡层之前还可以在第二凹槽的底面及侧壁上形成第二电镀种子层，通过第二电镀种子层可以提高导电柱与后续形成的第二扩散阻挡层之间的附着性。
参考图13，将第二面140与第一面100进行键合，且电连接柱120部 分位于第二凹槽170内，导电柱160部分位于第一凹槽130内，且至少部分导电柱160与部分电连接柱120错位交叠；形成焊接结构180，至少部分焊接结构180填充于第二凹槽170，且至少部分焊接结构180还填充于导电柱160与第一凹槽130之间。
在键合第二面140与第一面100的过程中对初始焊接结构210(参考图9)退火处理，以形成焊接结构180，可以理解的是，键合第二面140与第一面100的过程中，初始焊接结构210(参考图9)受热变成熔融状态，并随着第二面140与第一面100的表面贴合，熔融状态的初始焊接结构210(参考图9)受到第一凹槽130及第二凹槽170的限位以及电连接柱120的挤压，使得熔融状态的初始焊接结构210(参考图9)向远离电连接柱120的方向移动，当完成第二面140与第一面100的键合后，对半导体结构进行退火处理可以使熔融状态下的初始焊接结构210(参考图9)冷凝变为焊接结构180。
通过焊接结构180可以实现导电柱160及电连接柱120的电连接，且通过焊接结构180可以加固第一基底110及第二基底150之间的连接，从而提高半导体结构的稳定性。
本公开实施例通过提供一种半导体结构的制作方法，通过将电连接柱120设置于第二凹槽170内，将导电柱160设置于第一凹槽130内，可以使得导电柱160与电连接柱120错位交叠，从而有利于避免第一基底110和第二基底150相互滑动，进而提高第一基底110及第二基底150之间键合的稳定性；将导电柱160设置于第一凹槽130内，在键合第一基底110及第二基底150过程中导电柱160及电连接柱120发生受热膨胀，使得导电柱160及电连接柱120相互卡合，从而提高第一基底110及第二基底150之间连接的紧密性；通过将电连接柱120设置于第二凹槽170内，将导电柱160设置于第一凹槽130内，可以降低整个半导体结构的高度；通过焊接结构180实现电连接柱120及导电柱160的连接的同时可以增加电连接柱120与导电柱160之间的接触面积，从而可以提高整个半导体结构的散热，且通过增加电连接柱120与导电柱160之间的接触面积可以提高第一基底110与第二基底150之间的接触面积，进而降低第一基底110与第二基底150之间的接触电阻，提高半导体结构的性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本公开的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏 离本公开实施例的精神和范围。任何本领域技术人员，在不脱离本公开实施例的精神和范围内，均可作各自更动与修改，因此本公开实施例的保护范围应当以权利要求限定的范围为准。

Claims (18)

  1. 一种半导体结构，包括：
    具有第一面的第一基底，所述第一基底具有凸出于所述第一面的电连接柱，所述电连接柱顶部具有第一凹槽；
    具有第二面的第二基底，所述第二基底内具有导电柱，且所述第二基底还具有第二凹槽，所述第二凹槽露出所述导电柱的顶面以及至少部分侧面；
    所述第二面与所述第一面相键合，且所述电连接柱部分位于所述第二凹槽内，所述导电柱部分位于所述第一凹槽内；
    焊接结构，至少部分所述焊接结构填充于所述第二凹槽，且至少部分所述焊接结构还填充于所述导电柱与所述第一凹槽之间。
  2. 根据权利要求1所述的半导体结构，其中，在平行于所述第二面的平面上，所述导电柱被所述第二凹槽暴露的部分的横截面比未被所述第二凹槽暴露的部分的横截面小。
  3. 根据权利要求1所述的半导体结构，其中，所述电连接柱包括：导电主体部、位于所述导电主体部底面和侧面的第一扩散阻挡层以及位于所述第一凹槽的侧壁和底面的第一金属保护层，且所述导电主体部的部分位于所述第二凹槽内。
  4. 根据权利要求3所述的半导体结构，其中，所述导电主体部的材料包括铜或铝；所述第一扩散阻挡层的材料包括钽、钛、氮化钛或者氮化钽。
  5. 根据权利要求3所述的半导体结构，其中，所述电连接柱还包括：第一电镀种子层，所述第一电镀种子层位于所述导电主体部与所述第一扩散阻挡层之间。
  6. 根据权利要求1所述的半导体结构，其中，在垂直于所述第一面或垂直于所述第二面的方向上，所述第一凹槽的深度与所述第二凹槽的深度之比在1:1～1:5范围内。
  7. 根据权利要求1所述的半导体结构，其中，所述焊接结构还位于所述电连接柱与所述第二凹槽的侧壁之间。
  8. 根据权利要求1所述的半导体结构，其中，所述焊接结构的材料包括锡或者锡银合金等。
  9. 根据权利要求1所述的半导体结构，其中，还包括：第二扩散阻挡层，所述 第二扩散阻挡层位于所述第二凹槽的底面上以及侧壁上，以及还位于所述导电柱被所述第二凹槽暴露的顶面和侧面上。
  10. 根据权利要求1所述的半导体结构，其中，在平行于所述第二面的方向上，所述第二凹槽的宽度是所述导电柱未被所述第二凹槽暴露的部分的宽度的2～3倍。
  11. 一种半导体结构的制作方法，包括：
    提供具有第一面的第一基底，所述第一基底具有凸出于所述第一面的电连接柱，所述电连接柱顶部具有第一凹槽；
    提供具有第二面的第二基底，所述第二基底内具有导电柱，且所述第二基底还具有第二凹槽，所述第二凹槽露出所述导电柱的顶面以及至少部分侧面；
    将所述第二面与所述第一面进行键合，且所述电连接柱部分位于所述第二凹槽内，所述导电柱部分位于所述第一凹槽内，且至少部分所述导电柱与部分所述电连接柱错位交叠；
    形成焊接结构，至少部分所述焊接结构填充于所述第二凹槽，且至少部分所述焊接结构还填充于所述导电柱与所述第一凹槽之间。
  12. 根据权利要求11所述的半导体结构的制作方法，其中，形成所述电连接柱的方法包括：
    形成第一扩散阻挡层；
    形成导电主体部，所述导电主体部位于所述第一扩散阻挡层的顶面及所述第一扩散阻挡层的侧壁；
    形成第一金属保护层，所述第一金属保护层位于所述第二凹槽内的所述焊接结构与所述导电主体部之间。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，在形成所述导电主体部之前还包括，形成第一电镀种子层，所述第一电镀种子层位于所述导电主体部与所述第一扩散阻挡层之间。
  14. 根据权利要求11所述的半导体结构的制作方法，其中，形成所述第二凹槽的方法包括：
    图形化所述第二基底，以形成自所述第二基底自所述第二面向所述第二基底内部凹陷的第二初始凹槽，所述第二初始凹槽暴露初始导电柱的顶面及部分侧壁；
    至少沿垂直于所述第二初始凹槽延伸方向去除部分宽度的所述初始导电柱，以形成所述第二凹槽，剩余所述初始导电柱作为所述导电柱。
  15. 根据权利要求14所述的半导体结构的制作方法，其中，在垂直于所述导电柱延伸的方向上，形成的所述第二凹槽的宽度是所述第二凹槽暴露的所述导电柱宽度的2～3倍。
  16. 根据权利要求11所述的半导体结构的制作方法，其中，在垂直于所述第一面或者垂直于所述第二面的方向上，形成的所述第一凹槽的深度与所述第二凹槽的深度之比在1:1～1:5范围内。
  17. 根据权利要求11所述的半导体结构的制作方法，其中，在键合所述第二面与所述第一面前还包括：形成第二扩散阻挡层，所述第二扩散阻挡层位于所述第二凹槽的底面上以及侧壁上，以及还位于所述导电柱被所述第二凹槽暴露的顶面和侧面上。
  18. 根据权利要求11所述的半导体结构的制作方法，其中，形成所述焊接结构包括：形成初始焊接结构，所述初始焊接结构位于所述第一凹槽内；
    键合所述第二面与所述第一面的过程中对所述初始焊接结构退火处理，以形成所述焊接结构。
PCT/CN2022/078109 2022-01-12 2022-02-25 一种半导体结构及一种半导体结构的制作方法 WO2023133977A1 (zh)

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