WO2023092698A1 - 拼接屏驱动架构及驱动方法 - Google Patents

拼接屏驱动架构及驱动方法 Download PDF

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Publication number
WO2023092698A1
WO2023092698A1 PCT/CN2021/137160 CN2021137160W WO2023092698A1 WO 2023092698 A1 WO2023092698 A1 WO 2023092698A1 CN 2021137160 W CN2021137160 W CN 2021137160W WO 2023092698 A1 WO2023092698 A1 WO 2023092698A1
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Prior art keywords
signal
interface
driving
conversion unit
splicing screen
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PCT/CN2021/137160
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English (en)
French (fr)
Inventor
王凯
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Tcl华星光电技术有限公司
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Priority to US17/620,779 priority Critical patent/US20240028285A1/en
Publication of WO2023092698A1 publication Critical patent/WO2023092698A1/zh

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1446—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display display composed of modules, e.g. video walls
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements
    • G09F9/3026—Video wall, i.e. stackable semiconductor matrix display modules
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/1423—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display
    • G06F3/1438—Digital output to display device ; Cooperation and interconnection of the display device with other functional units controlling a plurality of local displays, e.g. CRT and flat panel display using more than one graphics controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/003—Details of a display terminal, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G5/006—Details of the interface to the display terminal
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/02—Composition of display devices
    • G09G2300/026—Video wall, i.e. juxtaposition of a plurality of screens to create a display screen of bigger dimensions
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

Definitions

  • the present application relates to the field of display panel driving, in particular to a splicing screen driving architecture.
  • 8K splicing screens With the wide application of 8K products, 8K splicing screens have gradually entered the field of view of the display industry. However, there are very few solutions for driving 8K splicing screens in the industry. Common circuit driving solutions can only support spliced pictures to display complete 4K or 8K resolution. Existing naked-eye 3D solutions mainly focus on resolutions of 8K and below; higher-resolution 3D image display cannot be achieved; and the driving architecture is complex and costly.
  • the present application aims to provide a splicing screen driving architecture and driving method, aiming to solve the problem of complex 3D8K picture driving architecture and high cost in the prior art.
  • the embodiment of the present application provides a splicing screen driving architecture
  • the splicing screen includes M*N sub-displays
  • the splicing screen driving architecture includes:
  • a plurality of signal conversion units and a plurality of interface conversion units for converting interfaces are electrically connected to the plurality of interface conversion units; each sub-display in the M*N sub-displays includes At least one sub-display drive circuit; wherein, both M and N are positive integers greater than or equal to one.
  • Each signal conversion unit in the plurality of signal conversion units is used to receive an external drive signal and send the drive signal to the interface conversion unit; the interface conversion unit is used to receive the external drive signal sent by the signal conversion unit. drive signal, and send the external drive signal to the sub-display drive circuit.
  • the interface conversion unit includes a signal input interface and a signal output interface, and the data transmission protocols corresponding to the signal input interface and the signal output interface of the interface conversion unit do not match.
  • the signal conversion unit includes signal input and signal output interfaces, the data transmission protocol corresponding to the signal input interface of the interface conversion unit, and the signal corresponding to the signal output interface of the signal conversion unit
  • the transport protocol matches.
  • the number of the interface converting units is the same as the number of the sub-display driving circuits.
  • the number of the signal conversion units is the same as the number of the interface conversion units.
  • any signal conversion unit is connected to any interface conversion unit through its own multiple signal output interfaces.
  • the number of the signal conversion units is smaller than the number of the interface conversion units.
  • any signal conversion unit is simultaneously connected to multiple interface conversion units through its own multiple signal output interfaces.
  • an even number of signal output interfaces in one signal conversion unit is connected to one interface conversion circuit at the same time.
  • the splicing screen driving architecture further includes a synchronization module, configured to synchronize the driving signals output by the plurality of signal conversion units.
  • the multiple interface conversion units implement timing synchronization by using a coaxial line.
  • the signal output interface in the signal converting unit is a DP interface.
  • the two DP interfaces when the transmission rate of the DP interfaces is 8.1Gbps, the two DP interfaces transmit 8K60HZ signals; when the transmission rate of the DP interfaces is 5.4Gbps, the four DP interfaces The interface transmits 8K60HZ signal.
  • the signal conversion unit is a P4000 graphics card.
  • the interface conversion unit is an Arria10 circuit.
  • the splicing screen driving architecture further includes a picture conversion module, the picture conversion module is used to convert the picture corresponding to the initial driving signal into a 3D picture, and generate a driving picture corresponding to the 3D picture. signal to send the driving signal to the plurality of signal converting units.
  • the embodiment of the present application also provides a splicing screen driving method, which is driven by using the splicing screen driving architecture described in any one of the above, and the splicing screen driving method includes:
  • the signal conversion unit receives an initial driving signal, and converts the initial driving signal into a driving signal that can be displayed by the splicing screen;
  • the signal conversion unit sends the driving signal to the interface conversion unit, so as to use the interface conversion unit to realize interface conversion;
  • the interface conversion unit sends the driving signal to the sub-display driving circuit, so as to use the sub-display driving circuit to control the splicing screen to display images.
  • the present application provides a splicing screen driving architecture and a driving method.
  • the splicing screen driving architecture only includes a plurality of signal conversion units, a plurality of interface conversion units for converting interfaces, and a plurality of sub-display drive circuits; the plurality of signal Each signal conversion unit in the conversion unit is used to receive an external drive signal and send the drive signal to the interface conversion unit; the interface conversion unit is used to receive the external drive signal sent by the signal conversion unit, and send the drive signal to the interface conversion unit.
  • the external driving signal is sent to the sub-display driving circuit, so that the sub-display displays images.
  • the entire splicing screen driving architecture only includes signal conversion unit, interface conversion unit, sub-display driving circuit and sub-display.
  • the driving structure is simple, and the driving of the splicing screen can be realized with a small number of circuit boards, which greatly reduces the cost.
  • FIG. 1 is a schematic diagram of an embodiment of a splicing screen driving framework provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of another embodiment of the splicing screen driving architecture provided by the embodiment of the present application.
  • first and second are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, features defined as “first” and “second” may explicitly or implicitly include one or more features. In the description of the present application, “plurality” means two or more, unless otherwise specifically defined.
  • Embodiments of the present application provide a splicing screen driving architecture and a driving method, which will be described in detail below.
  • FIG. 1 is a schematic diagram of an embodiment of a splicing screen driving architecture provided by an embodiment of the present application.
  • the splicing screen includes M*N sub-display screens 10 , and the pictures displayed on the M*N sub-display screens are spliced to form a complete picture.
  • the splicing screen drive architecture can include a plurality of signal conversion units 20, a plurality of interface conversion units 30 for converting interfaces, and a plurality of signal conversion units 20 are electrically connected to a plurality of interface conversion units 30; and M*N sub-display screens
  • Each sub-display screen 10 in 10 includes at least one sub-display screen driving circuit 40 .
  • Each signal conversion unit 20 in the plurality of signal conversion units 20 is used for receiving an external driving signal and sending the driving signal to the interface conversion unit 30 .
  • the interface converting unit 30 is used for receiving the external driving signal sent by the signal converting unit, and sending the external driving signal to the sub-display driving circuit 40 .
  • the present application provides a splicing screen driving architecture, which only includes a plurality of signal conversion units, a plurality of interface conversion units for converting interfaces, and a plurality of sub-display drive circuits; among the plurality of signal conversion units Each signal conversion unit is used to receive an external drive signal and send the drive signal to the interface conversion unit; the interface conversion unit is used to receive the external drive signal sent by the signal conversion unit, and send the external drive signal to the interface conversion unit.
  • the driving signal is sent to the sub-display driving circuit, so that the sub-display displays images.
  • the entire splicing screen driving architecture only includes signal conversion unit, interface conversion unit, sub-display driving circuit and sub-display.
  • the driving structure is simple, and the driving of the splicing screen can be realized with a small number of circuit boards, which greatly reduces the cost.
  • the signal conversion unit 20 mainly converts the external driving signal into a driving signal that can be displayed on the display screen.
  • the interface conversion unit actually considers the actual driving scenario, and different hardware devices include multiple different hardware interfaces (hardware interface), where the hardware interface refers to the connection method between two hardware devices; the hardware interface includes both the physical interface and the logical data transmission protocol.
  • the hardware device may include multiple signal input interfaces and multiple signal output interfaces at the same time, and the corresponding data transmission protocols of the multiple signal input interfaces and the multiple signal output interfaces may not match.
  • the interface conversion unit 30 provided in the embodiment of the present application also includes a signal input interface and a signal output interface, and the data transmission protocols corresponding to the signal input interface and the signal output interface in the interface conversion unit 30 do not match.
  • the data transmission protocol corresponding to the signal input interface of the interface conversion unit 30 matches with the signal transmission protocol corresponding to the signal output interface of the signal conversion unit 20; the signal conversion unit 20 can utilize the signal output interface of itself to send the signal to the interface conversion unit 30 signal input interface.
  • the data transmission protocol corresponding to the signal output interface of the interface conversion unit 30 in the embodiment of the present application matches the transmission protocol corresponding to the signal input interface of the sub-display display drive circuit 40; the interface conversion unit 30 can use its own signal output interface The signal is sent to the signal input interface of the sub display screen driving circuit 40 .
  • the signal transmission protocol corresponding to the signal output interface of the signal conversion unit 20 does not match the transmission protocol corresponding to the signal input interface of the sub display screen drive circuit 40; the signal cannot be directly output from the signal conversion unit 20.
  • the interface is sent to the signal input interface of the sub-display driving circuit 40 . Therefore, the interface conversion unit 30 is required to convert the interface; the interface conversion unit 30 mainly plays the role of interface transfer.
  • the matching of signal transmission protocols may be that the signal transmission protocols are the same, or may be that the signal transmission protocols are different. For some signal transmission protocols, even if the signal transmission protocols corresponding to two hardware interfaces are different, signals can still be transmitted between the two; this is the characteristic of the signal transmission protocol itself.
  • the number of multiple interface conversion units 30 and multiple sub-display display drive circuits 40 may be the same; one interface conversion unit 30 is connected to only one determined sub-display display drive circuit 40 . That is, one interface conversion unit 30 is connected to only one determined sub-display screen.
  • the number of the multiple signal conversion units 20 may also be the same as the number of the multiple interface conversion units 30 .
  • one interface conversion unit 30 is connected to a uniquely determined signal conversion unit 20 .
  • the number of multiple signal conversion units 20, multiple interface conversion units 30 and multiple sub-display display drive circuits 40 is the same; and one signal conversion unit 20 is connected to a uniquely determined interface conversion unit 30, and one interface conversion The unit 30 is connected to a uniquely determined sub-display driving circuit 40 .
  • any signal conversion unit 20 includes a plurality of signal input interfaces and a plurality of signal output interfaces; Unit 30 is connected. That is, one signal conversion unit 20 is only connected to one interface conversion unit 30 .
  • the number of multiple signal conversion units 20 may be smaller than the number of multiple interface conversion units 30 .
  • any signal conversion unit 20 is connected to multiple interface conversion circuits 30 through its multiple signal output interfaces at the same time. That is, one signal conversion unit 20 is connected to multiple interface conversion units 30 at the same time.
  • one signal conversion unit 20 is connected to multiple interface conversion units 30 at the same time, so that the driving function can also be realized and the cost can be saved.
  • the splicing screen driving architecture may further include a synchronization module 50 ; and the synchronization module 50 is mainly used to synchronize the driving signals output by multiple signal conversion units 20 . That is, since the pictures displayed on the M*N sub-displays need to be spliced into a complete picture, it is necessary to ensure that the pictures input into each sub-display are kept synchronized.
  • the synchronization module 50 usually controls multiple signal conversion units 20 at the same time, so as to control the driving signals output by the multiple signal conversion units 20 to maintain synchronization. And when there are multiple synchronization modules 50 , the multiple synchronization modules 50 also need to maintain synchronization. In an actual driving scenario, if there are multiple synchronization modules 50, the multiple synchronization modules 50 are usually physically connected by network cables to maintain synchronization.
  • multiple interface conversion units 30 may use coaxial cables to achieve timing synchronization; that is, multiple interface conversion units 30 may also be physically connected by network cables to maintain synchronization.
  • the splicing screen driving architecture may also include a picture conversion module, which is mainly used to convert the picture corresponding to the initial driving signal into a 3D picture, and generate a driving signal corresponding to the 3D picture to convert the picture into a 3D picture.
  • the driving signal is sent to a plurality of signal converting units.
  • each sub-display displays a part of the display screen
  • the display images corresponding to all sub-displays are combined to form a complete 3D image, so it is necessary to splice the display images corresponding to all sub-displays. Therefore, in the embodiment of the present application, it is necessary to process the picture at the seam to avoid problems such as dislocation and blurring of the picture at the seam.
  • the splicing screen driving framework provided by the embodiment of the present application also includes a picture fusion module, which is mainly used to process the picture at the joint to ensure uniform transition of the picture at the joint.
  • the initial driving signal line is input to the picture conversion module, and after the picture is converted into a 3D picture, it is then input to the picture fusion module.
  • the picture fusion module processes the driving signal to ensure that the picture transition at the splicing seam on the splicing screen is uniform.
  • the driving signal processed by the picture fusion module is continuously input to the signal conversion unit 20; the signal conversion unit 20 mainly converts the driving signal into a signal that can be displayed on the display screen.
  • the image conversion module can be a software tool loaded in hardware devices such as computers, such as 3D conversion software; the image fusion module can be a software tool loaded in hardware devices such as computers, such as image processing software.
  • the multiple sub-displays in the splicing screen are usually V-By-One (VBO) interfaces, and the VBO interface is a commonly used interface between the display screen and the system chip.
  • VBO V-By-One
  • the sub-display uses the VBO interface to receive the driving signal, and realizes 3D display by displaying the 3D picture corresponding to the driving signal. Therefore, in the embodiment of the present application, the module physically connected to the VBO interface of the sub-display screen also needs to be a VBO interface.
  • the actual sub-display usually includes a plurality of different unit modules in order to receive external signals to realize image display.
  • the sub-display driving circuit in the embodiment of the present application is actually a circuit module inside the sub-display, that is, the display actually includes multiple different circuits; Multiple circuits in the circuit receive external driving signals, and the external driving signals drive the circuits to work normally to drive structures such as thin film transistors in the circuits to emit light, thereby displaying images.
  • the driving signal input to the sub-display is actually input into the sub-display driving circuit 40 in the sub-display; interface.
  • the output interface of the interface conversion unit is also a VBO interface.
  • the VBO output interface corresponding to the interface conversion unit can be connected to the VBO input interface of the sub-display driving circuit 40 .
  • the signal conversion unit 20 may be a graphics card in a hardware device such as a computer,
  • the graphics card converts the received image signal and outputs it to the display screen for display. Therefore, in the embodiment of the present application, the external drive signal is actually processed by the graphics card first, and then sent to the interface conversion unit 30 by the graphics card, and then sent to the sub-display drive circuit 40 by the interface conversion unit 30 .
  • the output interface corresponding to the graphics card is usually a Display Port (DP) interface
  • the signal conversion unit 20 that is, the graphics card
  • DP Display Port
  • FIG. 2 it is a schematic diagram of another embodiment of the splicing screen driving architecture provided by the embodiment of the present application.
  • the PC is the computer
  • the P4000 graphics card is the signal conversion unit 20
  • the A10 is the Arria10 circuit, which is the interface conversion unit 30 ;
  • the P4000 graphics card is a structure set inside the computer PC, while the A10 circuit and the CB circuit may be set inside the sub-display.
  • each computer PC is also loaded with 3D software and image fusion software, both of which are software tools for processing external initial driving signals.
  • the splicing screen can have a 3*3 structure; and since the CB circuit board is usually a part of the circuit structure of the sub-display, CB is used to directly represent the sub-display in FIG. 2 .
  • each computer PC includes a 3D software for image processing and image fusion software; and each computer PC includes a P4000 graphics card.
  • each sub-display includes an A10 circuit and a CB circuit; and an A10 circuit and a CB circuit in the same sub-display are connected.
  • the number of signal conversion units 20 is less than the number of interface conversion units 30 (ie A10 circuit);
  • the number of drive circuits 40 is the same.
  • one signal conversion unit 20 can be connected to multiple interface conversion units 30 at the same time, that is, one signal conversion unit 20 can control multiple different sub-display screens at the same time.
  • one signal conversion unit 20 may include four DP interfaces (ie, 4DP), and any two DP interfaces (ie, 2DP) in the four DP interfaces are respectively connected to two different interface conversion units 30; such a signal conversion
  • the unit 20 can simultaneously control multiple different sub-display screens, saving hardware costs.
  • the four DP interfaces in one signal conversion unit 20 may also be any three DP interfaces connected to one interface conversion unit 30 . Or all four DP interfaces in one signal conversion unit 20 are connected to the same interface conversion unit.
  • the splicing screen displays 3D pictures with a resolution of 8K or above, and how many signal output interfaces need to be used in the signal conversion unit 20 depends on the bandwidth of the video picture and the signal transmission rate of the signal output interfaces. .
  • DP interfaces when the transmission rate of DP interfaces is 8.1Gbps, two DP interfaces can transmit 8K60HZ signals; and when the transmission rate of DP interfaces is 5.4Gbps, four DP interfaces can transmit 8K60HZ signal.
  • the larger the bandwidth of the video picture the more DP interfaces are required to transmit the video signal.
  • the lower the transmission rate of the DP interface the more DP interfaces are required to transmit the video signal.
  • the graphics card of the signal conversion unit 20 (that is, P4000) includes four DP output interfaces, and the signal transmission rate of each DP output interface is 8.1Gbps. At this time, any two DP output interfaces and the same Only one interface conversion unit 30 can be connected.
  • the same interface conversion unit 30 (that is, the A10 circuit) includes two second signal input interfaces, that is, two DP input interfaces.
  • the two DP output interfaces in the signal conversion unit 20 are connected to the two DP input interfaces in the same interface conversion unit 30 at the same time; the signal transmission rate of the two DP input interfaces in the same interface conversion unit 30 is also 8.1Gbps .
  • the output of the interface conversion unit 30 (that is, the A10 circuit) is a 32 lane V-by-One interface, each lane
  • the signal transmission rate of the V-by-One interface is 2.97Gbps.
  • the input interface of the interface conversion unit ie, the A10 circuit
  • the input interface of the corresponding sub-display drive circuit 40 ie, the CB circuit
  • the CB circuit is also a 32 lane V-by-One interface.
  • DP interface and 32 lane V-by-One are common interfaces in actual driving scenarios; 8.1Gbps, 5.4Gbps, and 2.97Gbps are also relatively conventional signal transmission rates.
  • the splicing screen driver architecture also includes 3D software (that is, the picture conversion module), and the 3D software is mainly used to encode and decode video data and convert video signals into 3D video signals. .
  • the splicing screen driver architecture also includes picture fusion software (that is, the picture fusion module).
  • the picture fusion software will process the original RGB data after encoding and decoding by 3D software, and process the patchwork data of any sub-display and other sub-displays around to ensure data The transition is uniform at the seams to avoid blurred dislocations and other phenomena.
  • the picture conversion module and the picture fusion module can be software tools such as the 3D software and picture fusion software described in the above-mentioned embodiments respectively loaded in the computer; they can also be other software tools that can A hardware module that implements the same function.
  • software tools such as type 3D software and screen fusion software are usually used to realize functions such as screen conversion and fusion.
  • the splicing screen driving architecture further includes a synchronization module.
  • the synchronization module can be NVIDIA SYNC II card, and the NVIDIA SYNC II card is a part of the functional modules in the P4000 graphics card; therefore, the NVIDIA SYNC II card controls the drive signal output by the P4000 graphics card.
  • the synchronization module is connected to the signal conversion module, and the synchronization module controls the driving signal output by the signal conversion module to achieve synchronization.
  • synchronization modules i.e. NVIDIA SYNC II cards
  • one synchronization module controls PC1-PC4, that is, one synchronization module simultaneously controls multiple signal conversion modules 20 ;
  • another synchronous module controls PC5 alone. Since there are multiple synchronization modules, it is also necessary to control the synchronization between the multiple synchronization modules.
  • a network cable may be used to connect multiple synchronization modules, and a physical method may be used to maintain synchronization between the multiple synchronization modules.
  • the embodiment of the present application also provides a splicing screen driving method, which is driven by using the splicing screen driving architecture described in any one of the above items.
  • the splicing screen includes M*N sub-display screens
  • the splicing screen drive architecture includes: a plurality of signal conversion units and a plurality of interface conversion units for converting interfaces, and a plurality of signal conversion units are electrically connected to a plurality of interface conversion units ;
  • Each sub-display in M*N blocks of sub-displays includes at least one sub-display drive circuit;
  • Each signal conversion unit in the plurality of signal conversion units is used to receive an external drive signal, and send the drive signal to the interface conversion unit; the interface conversion unit is used to receive the external drive signal sent by the signal conversion unit, and send the external drive signal Send to the sub-display drive circuit.
  • both M and N are positive integers greater than or equal to one.
  • the signal conversion unit receives an initial driving signal, and converts the initial driving signal into a driving signal that can be displayed by the splicing screen;
  • the signal conversion unit sends the driving signal to the interface conversion unit, so as to use the interface conversion unit to realize interface conversion;
  • the interface conversion unit sends the driving signal to the sub-display driving circuit, so as to use the sub-display driving circuit to control the splicing screen to display images.
  • the splicing screen driving architecture only includes a plurality of signal conversion units, a plurality of interface conversion units for converting interfaces, and a plurality of sub-display drive circuits; among the plurality of signal conversion units Each signal conversion unit is used to receive an external drive signal and send the drive signal to the interface conversion unit; the interface conversion unit is used to receive the external drive signal sent by the signal conversion unit, and send the external drive signal to the interface conversion unit.
  • the driving signal is sent to the sub-display driving circuit, so that the sub-display displays images.
  • the entire splicing screen driving architecture only includes signal conversion unit, interface conversion unit, sub-display driving circuit and sub-display.
  • the driving structure is simple, and the driving of the splicing screen can be realized with a small number of circuit boards, which greatly reduces the cost.
  • the drive architecture of the splicing screen also includes a screen conversion module, which is mainly used to convert the screen corresponding to the initial driving signal into a 3D screen. Therefore, the splicing screen driving method may further include: the picture conversion module receives the initial driving signal, generates a driving signal corresponding to the 3D picture, and sends the driving signal to the signal conversion unit.
  • the splicing screen driving framework provided in the embodiment of the present application also includes a fusion module, so the splicing screen driving method provided in the embodiment of the present application may also include: the fusion module receives the driving signal from the picture conversion module, and the picture corresponding to the driving signal Fusion processing is carried out to make the picture transition evenly at the seam and avoid the problem of misalignment and blur.
  • the external driving signal is first sent to the image conversion module to be converted into a 3D image, and then fusion processing is performed.
  • the splicing screen driving method in the embodiment of the present application will be specifically described below with reference to FIG. 2 .
  • the splicing screen driver architecture shown in Figure 2 includes five computer devices PC1-PC5, and each PC includes a P4000 graphics card, 3D software, and fusion software.
  • 3*3 sub-displays (not shown in the figure) are included, and each sub-display includes an A10 circuit and a CB circuit, which are respectively A101-A109 and CB1-CB9.
  • any computer equipment such as PC5 is additionally equipped with two SYNC II synchronization cards for synchronization, and the two SYNC II synchronization cards are connected by network cable; two SYNC Synchronization is also achieved between II syncs.
  • the 3D software receives an external initial drive signal and converts the initial drive signal into 3D RGB original video data.
  • the fusion software receives and processes the original RGB video data sent by the 3D software, and processes the data information at the seams between the CB1 splicing screen and other surrounding displays to ensure that the video data transitions evenly at the seams.
  • the driving signal after fusion processing is sent to the P4000 graphics card, and the P4000 graphics card processes the driving signal and converts the driving signal into a driving signal that can be displayed on the splicing screen.
  • the converted drive signal is output to the A10 circuit through the two DP interfaces in the P4000 graphics card.
  • the A101 circuit receives the drive signal output by the P4000 graphics card through its own DP interface, and sends it to the CB1 circuit through its own VBO interface.
  • the A10 circuit itself does not process the driving signal, and the A10 circuit mainly plays the role of interface conversion.
  • CB1 receives the driving signal of the A101 circuit through its own VBO interface, it outputs the driving signal to the sub-display for display.
  • the driving signals received by PC1-PC5 usually need to be kept synchronous. And utilize two NVIDIA The SYNC II card further controls the drive signals to keep them in sync.
  • NVIDIA SYNC II Card1 simultaneously controls the driving signals output by PC1-PC4 to keep synchronously, and NVIDIA SYNC II Card2 controls the signal output by PC5 alone; and because NVIDIA SYNC II Card1 and NVIDIA The SYNC II Card2 maintains synchronization, so that the drive signals output by PC1-PC5 can all be synchronized.
  • the foregoing embodiments only ensure that the drive signals output by different graphics cards are kept in sync, and the drive signals still need to be kept in sync during the subsequent transmission of the drive signals. Specifically, the drive signals output by A101-A109 need to be synchronized.
  • the A101 circuit can output a synchronous signal
  • A102-A109 receives the synchronous signal sent by A101, and adjusts the timing of its own driving signal according to the synchronous signal, so that the driving signals in different A10 circuits remain synchronous .
  • the A101 circuit outputs the Vsync signal
  • A102-A109 receives the Vsync signal sent by A101 for frame synchronization
  • A101-A109 regenerates and outputs the current frame based on the non-display period (Vblank area) of the Vsync signal in a frame
  • the timing signal DE of the picture, and the video signal is aligned with the new training signal DE and output at the same time.
  • the splicing screen not only displays 3D pictures, but also can display 3D pictures with a resolution of 8K or above.
  • the received external drive signals are two 8K60HZ signals, That is, the 3D software processes the signal of 2*8K60HZ.
  • the same 2*8K60HZ signal is sent to the fusion software; the fusion software sends the processed 2*8K60HZ signal to the P4000 graphics card. Since one P4000 graphics card controls two sub-display screens at the same time, the signal of 2*8K60HZ is respectively input into two interface conversion units 30, and the signal received by each interface conversion unit 30 is an 8k60HZ signal.
  • each sub-display can receive and display an 8K signal, in fact the sub-display receives and displays an image with a resolution of 8K4K.
  • the splicing screen has a structure of 3*3
  • the number of sub-displays in the horizontal and vertical directions of the entire splicing screen is 3, and the overall display screen of the splicing screen is (8k*3)(4K*3), that is, after splicing
  • the overall resolution of the screen is 24K12K.
  • each video link since each video link only drives one 8K4K signal, a total of 9 video links in 3x3 are output at the same time, and a total of (8k*3) (4K*3) 24K12K data can be output. And if there are other numbers of M*N sub-displays, other 3D images with different resolutions can also be displayed correspondingly.
  • each PC can only support up to 2 SYNC II synchronization cards, if the number of sub-displays exceeds two SYNC
  • the system supported by the II sync card needs to add additional SYNC on other PCs II sync card and video card.
  • each of the above units or structures can be implemented as an independent entity, or can be combined arbitrarily as the same or several entities.
  • each of the above units or structures please refer to the previous method embodiments, here No longer.

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Abstract

本申请提供一种拼接屏驱动架构及驱动方法，整个拼接屏驱动架构仅包括信号转换单元、接口转换单元、子显示屏驱动电路和子显示屏，驱动架构简单，用少量的电路板即可实现拼接屏的驱动，大大降低成本。

Description

拼接屏驱动架构及驱动方法 技术领域
本申请涉及显示面板驱动领域，具体涉及一种拼接屏驱动架构。
 背景技术
在显示面板行业中，商用拼接屏越来越受欢迎，拼接屏广泛应用于会场，商场等场所，其灵活的拼接方式，可以满足不同大小会议场所对高清显示的需求。裸眼3D作为近些年发展起来的潮流技术，给观众带来更加真实震撼的视觉效果，吸引了大众对裸眼3D的热情。
 技术问题
随着8K产品的广泛应用，8K拼接屏逐渐进入显示行业视野，但目前业界驱动8K拼接屏的方案少之又少，常见的电路驱动方案仅可以支持到拼接后的图片显示完整的4K或者8K分辨率。现有的裸眼3D方案也主要集中在8K及以下分辨率；无法实现更高分辨率的3D画面显示；且驱动架构复杂，成本较高。
 技术解决方案
本申请旨在提供一种拼接屏驱动架构及驱动方法，旨在解决现有技术中的3D8K画面驱动架构复杂，成本较高的问题。
第一方面，本申请实施例提供一种拼接屏驱动架构，所述拼接屏包括M*N块子显示屏，所述拼接屏驱动架构包括：
多个信号转换单元和多个用于转换接口的接口转换单元，所述多个信号转换单元与所述多个接口转换单元电连接；所述M*N块子显示屏中每个子显示屏包括至少一个子显示屏驱动电路；其中，所述M和N均为大于或等于一的正整数。
所述多个信号转换单元中每个信号转换单元用于接收外部驱动信号，且将所述驱动信号发送至所述接口转换单元；所述接口转换单元用于接收所述信号转换单元发出的外部驱动信号，且将所述外部驱动信号发送至所述子显示屏驱动电路。
在一种可能的实施例中，所述接口转换单元包括信号输入接口和信号输出接口，所述接口转换单元的信号输入接口和信号输出接口对应的数据传输协议不匹配。
在一种可能的实施例中，所述信号转换单元包括信号输入和信号输出接口，所述接口转换单元的信号输入接口对应的数据传输协议，与所述信号转换单元的信号输出接口对应的信号传输协议匹配。
在一种可能的实施例中，所述接口转换单元的数量和所述子显示屏驱动电路的数量相同。
在一种可能的实施例中，所述信号转换单元的数量与所述接口转换单元的数量相同。
在一种可能的实施例中，任意一个信号转换单元通过自身的多个信号输出接口与任意一个接口转换单元连接。
在一种可能的实施例中，所述信号转换单元的数量小于所述接口转换单元的数量。
在一种可能的实施例中，任意一个信号转换单元通过自身的多个信号输出接口同时与多个接口转换单元连接。
在一种可能的实施例中，一个信号转换单元中的偶数个信号输出接口同时与一个接口转换电路连接。
在一种可能的实施例中，所述拼接屏驱动架构还包括同步模块，所述同步模块用于同步所述多个信号转换单元输出的驱动信号。
在一种可能的实施例中，所述同步模块为多个，多个所述同步模块之间利用网络实现物理连接而保持同步。
在一种可能的实施例中，所述多个接口转换单元利用同轴线实现时序同步。
在一种可能的实施例中，所述信号转换单元中的信号输出接口为DP接口。
在一种可能的实施例中，视频画面的带宽越大，传输视频信号所需的DP接口越多。
在一种可能的实施例中，所述DP接口的传输速率越低，传输视频信号所需的DP接口越多。
在一种可能的实施例中，当所述DP接口的传输速率为8.1Gbps时，两个所述DP接口传输8K60HZ信号；当所述DP接口的传输速率为5.4Gbps时，四个所述DP接口传输8K60HZ信号。
在一种可能的实施例中，所述信号转换单元为P4000显卡。
在一种可能的实施例中，所述接口转换单元为Arria10电路。
在一种可能的实施例中，所述拼接屏驱动架构还包括画面转换模块，所述画面转换模块用于将初始驱动信号对应的画面转换为3D画面，并生成与所述3D画面对应的驱动信号以将所述驱动信号发送给所述多个信号转换单元。
第二方面，本申请实施例还提供一种拼接屏驱动方法，利用如上任一项所述的拼接屏驱动架构进行驱动，所述拼接屏驱动方法包括：
所述信号转换单元接收初始驱动信号，并将所述初始驱动信号转换为所述拼接屏可以显示的驱动信号；
所述信号转换单元将所述驱动信号发送至所述接口转换单元，以利用所述接口转换单元实现接口转换；
所述接口转换单元将所述驱动信号发送至所述子显示屏驱动电路，以利用所述子显示屏驱动线路控制所述拼接屏显示画面。
 有益效果
本申请提供一种拼接屏驱动架构及驱动方法，该拼接屏驱动架构仅包括多个信号转换单元和多个用于转换接口的接口转换单元，以及多个子显示屏驱动电路；所述多个信号转换单元中每个信号转换单元用于接收外部驱动信号，且将所述驱动信号发送至所述接口转换单元；所述接口转换单元用于接收所述信号转换单元发出的外部驱动信号，且将所述外部驱动信号发送至所述子显示屏驱动电路，使得子显示屏显示画面。整个拼接屏驱动架构仅包括信号转换单元、接口转换单元、子显示屏驱动电路和子显示屏，驱动架构简单，用少量的电路板即可实现拼接屏的驱动，大大降低成本。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例所提供的拼接屏驱动架构一实施例示意图；
图2为本申请实施例所提供的拼接屏驱动架构另一实施例示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请中，“示例性”一词用来表示“用作例子、例证或说明”。本申请中被描述为“示例性”的任何实施例不一定被解释为比其它实施例更优选或更具优势。为了使本领域任何技术人员能够实现和使用本申请，给出了以下描述。在以下描述中，为了解释的目的而列出了细节。应当明白的是，本领域普通技术人员可以认识到，在不使用这些特定细节的情况下也可以实现本申请。在其它实例中，不会对公知的结构和过程进行详细阐述，以避免不必要的细节使本申请的描述变得晦涩。因此，本申请并非旨在限于所示的实施例，而是与符合本申请所公开的原理和特征的最广范围相一致。
需要说明的是，本申请实施例方法由于是在电子设备中执行，各电子设备的处理对象均以数据或信息的形式存在，例如时间，实质为时间信息，可以理解的是，后续实施例中若提及尺寸、数量、位置等，均为对应的数据存在，以便电子设备进行处理，具体此处不作赘述。
本申请实施例提供一种拼接屏驱动架构及驱动方法，以下分别进行详细说明。
请参阅图1，图1为本申请实施例提供的拼接屏驱动架构一实施例示意图。在图1中，拼接屏包括M*N块子显示屏10，M*N块子显示屏各自显示的画面拼接后形成一个完整的画面。而拼接屏驱动架构可以包括多个信号转换单元20、多个用于转换接口的接口转换单元30，多个信号转换单元20与多个接口转换单元30电连接；而M*N块子显示屏10中每个子显示屏10中包括至少一个子显示屏驱动电路40。
而多个信号转换单元20中每个信号转换单元20用于接收外部驱动信号，且将驱动信号发送至接口转换单元30。接口转换单元30用于接收信号转换单元发出的外部驱动信号，且将外部驱动信号发送至子显示屏驱动电路40。
本申请提供一种拼接屏驱动架构，该拼接屏驱动架构仅包括多个信号转换单元和多个用于转换接口的接口转换单元，以及多个子显示屏驱动电路；所述多个信号转换单元中每个信号转换单元用于接收外部驱动信号，且将所述驱动信号发送至所述接口转换单元；所述接口转换单元用于接收所述信号转换单元发出的外部驱动信号，且将所述外部驱动信号发送至所述子显示屏驱动电路，使得子显示屏显示画面。整个拼接屏驱动架构仅包括信号转换单元、接口转换单元、子显示屏驱动电路和子显示屏，驱动架构简单，用少量的电路板即可实现拼接屏的驱动，大大降低成本。
在本申请的实施例中，信号转换单元20主要是将外部驱动信号转换为显示屏可以显示的驱动信号。而接口转换单元实际上是考虑到实际的驱动场景，不同的硬件设备包括多个不同的硬件接口（hardware interface），其中硬件接口指的是两个硬件设备之间的连接方式；硬件接口既包括物理上的接口，还包括逻辑上的数据传输协议。
因此不同的硬件接口之间既需要物理连接，还需要两个接口对应的数据传输协议匹配，才能够利用物理接口传输数据。而硬件设备可以同时包括多个信号输入接口和多个信号输出接口，多个信号输入接口和多个信号输出接口的对应的数据传输协议可以不匹配。本申请实施例中提供的接口转换单元30也包括信号输入接口和信号输出接口，且接口转换单元30中的信号输入接口和信号输出接口对应的数据传输协议不匹配。而接口转换单元30的信号输入接口对应的数据传输协议，与信号转换单元20的信号输出接口对应的信号传输协议匹配；信号转换单元20可以利用自身的信号输出接口将信号发送给接口转换单元30的信号输入接口。
同理，本申请实施例中接口转换单元30的信号输出接口对应的数据传输协议，与子显示屏驱动电路40的信号输入接口对应的传输协议匹配；接口转换单元30可以利用自身的信号输出接口将信号发送给子显示屏驱动电路40的信号输入接口。而本申请实施例中，信号转换单元20的信号输出接口对应的信号传输协议，与子显示屏驱动电路40的信号输入接口对应的传输协议不匹配；信号无法直接从信号转换单元20的信号输出接口发送到子显示屏驱动电路40的信号输入接口。因此需要接口转换单元30进行接口的转换；接口转换单路30主要起到接口中转的作用。
需要说明的是，在上述实施例中，信号传输协议匹配可以是信号传输协议相同，也可以是信号传输协议不同。对于某些信号传输协议来说，即使两个硬件接口对应的信号传输协议不同，两者之间同样可以传输信号；这是信号传输协议本身的特性。
在本申请的一些实施例中，当M*N块子显示屏为多个时，多个子显示屏对应的子显示屏驱动电路40也同样为多个。而在一些实施例中，多个接口转换单元30和多个子显示屏驱动电路40的数量可以相同；一个接口转换单元30与唯一一个确定的子显示屏驱动电路40连接。即一个接口转换单路30与唯一一个确定的子显示屏连接。
而当多个接口转换单元30和多个子显示屏驱动电路40的数量相同时，多个信号转换单元20的数量也可以与多个接口转换单元30的数量相同。同样地，一个接口转换单元30与唯一确定的信号转换单元20连接。
在上述实施例中，多个信号转换单元20、多个接口转换单元30和多个子显示屏驱动电路40的数量均相同；且一个信号转换单元20连接唯一确定的接口转换单元30，一个接口转换单元30连接唯一确定的子显示屏驱动电路40。
需要说明的是，在实际的驱动场景中，包括但不限于信号转换单元20、接口转换单元30和子显示屏驱动电路40等硬件设备中，通常均包括多个输入与输出接口。例如，在本申请的实施例中，任意一个信号转换单元20均包括多个信号输入接口和多个信号输出接口；而任意一个信号转换单元20通过自身的多个信号输出接口与任意一个接口转换单元30连接。即一个信号转换单元20仅与一个接口转换单元30连接。
在另一些实施例中，多个信号转换单元20的数量可以小于多个接口转换单元30的数量。此时，任意一个信号转换单元20通过自身的多个信号输出接口同时与多个接口转化电路30连接。即一个信号转换单元20同时连接多个接口转换单元30。
而考虑到实际的成本等问题，通常情况下也是一个信号转换单元20同时连接多个接口转换单元30，这样同样可以实现驱动功能，且节省成本。
请参考图1，在图1所示的实施例中，该拼接屏驱动架构还可以包括同步模块50；而同步模块50主要是用于同步多个信号转换单元20输出的驱动信号。即由于需要保持M*N个子显示屏上显示的画面可以拼接为一个完整的画面，因此需要保证输入每个子显示屏中的画面保持同步。
而在本申请的实施例中，同步模块50通常同时控制多个信号转换单元20，以控制多个信号转换单元20输出的驱动信号保持同步。而当有多个同步模块50时，多个同步模块50之间也需要保持同步。在实际的驱动场景中，若是有多个同步模块50，则多个同步模块50之间通常利用网线实现物理连接而保持同步。
需要说明的是，不仅多个信号转换单元20输出的驱动信号需要保持同步，多个接口转换单元30输出的驱动信号也需要保持同步。在本申请的一些实施例中，多个接口转换单元30之间可以利用同轴线实现时序同步；即多个接口转换单元30之间也利用网线等实现物理连接而保持同步。
由于本申请实施例中的拼接屏显示的通常为3D画面，需要将普通的2D画面进行处理转换为3D画面，才能在拼接屏上显示为3D画面。因此在本申请的一些实施例中，拼接屏驱动架构还可以包括画面转换模块，画转换模块主要用于将初始驱动信号对应的画面转换为3D画面，并生成与3D画面对应的驱动信号以将驱动信号发送给多个信号转换单元。
又由于本申请中拼接屏中每个子显示屏显示画面的一部分，所有子显示屏对应的显示画面结合在一起才是一个完整的3D画面，因此需要将所有子显示屏对应的显示画面进行拼接。因此在本申请的实施例中，需要对拼缝处的画面进行处理，避免在拼缝处出现画面错位模糊等问题。
即本申请实施例所提供的拼接屏驱动架构还包括画面融合模块，画面融合模块主要用于对拼缝处的画面进行处理，保证画面在拼缝处过渡均匀。且在本申请的实施例中，初始驱动信号线输入至画面转换模块，将画面转换为3D画面后，再输入至画面融合模块中。画面融合模块接收到3D画面对应的驱动信号后，对驱动信号进行处理，保证拼接屏上拼缝处的画面过渡均匀。而经画面融合模块处理过的驱动信号继续输入至信号转换单元20；信号转换单元20主要是将驱动信号转换为显示屏可以显示的信号。
在实际的拼接屏驱动场景中，通常是利用计算机等硬件设备来控制多个子显示屏的画面；因此信号转换单元20、接口转换单元30和子显示屏驱动电路40等可以为安装在计算机设备或子显示屏中的硬件设备。而画面转换模块可以为装载在计算机等硬件设备内部的软件工具，如3D转换软件等；画面融合模块可以为装载在计算机等硬件设备内部的软件工具，如画面处理软件等。
在实际的拼接屏驱动场景中，拼接屏中的多个子显示屏中通常为V-By-One（VBO）接口，VBO接口是显示屏和***芯片之间普遍应用的接口。子显示屏利用VBO接口接收驱动信号，以显示驱动信号对应的3D画面实现3D显示。因此，在本申请的实施例中，与子显示屏VBO接口物理连接的模块也需要是VBO接口。
实际的子显示屏通常包括多个不同的单元模块，才能接收外部信号实现画面显示。而本申请实施例中的子显示屏驱动电路实际上是子显示屏内部的一个电路模块，即显示屏实际上也是包括多个不同的电路的；显示屏想要显示画面，实际上是利用自身的多个电路接收外部驱动信号，外部驱动信号驱动电路正常工作以驱动电路中的薄膜晶体管等结构发光，从而显示画面。
因此，驱动信号输入子显示屏，实际上是输入子显示屏中的子显示屏驱动电路40中；且子显示屏的输入接口为VBO接口，实际上也是子显示驱动电路40的输入接口为VBO接口。
又由于接口转换单元30与子显示屏驱动电路40连接，同样类型的接口才能连接，因此接口转换单元的输出接口同样为VBO接口。这样接口转换单元对应的VBO输出接口，才能和子显示屏驱动电路40的VBO输入接口连接。
在本申请的实施例中，信号转换单元20可以为计算机等硬件设备中的显卡，
主要用于处理计算机接收的图像；即显卡将接收到的图像信号经过转换后输出到显示屏上实现显示。因此本申请实施例中，外部的驱动信号实际上是先经过显卡处理后，再由显卡发送到接口转换单元30，再由接口转换单元30发送到子显示屏驱动电路40中。
由于显卡对应的输出接口通常为Display Port（DP）接口，若是信号转换单元20（即显卡）通过信号输入输出接口与接口转换单元30连接，则接口转换单元30对应的信号输入接口与信号转换单元20对应的信号输出接口匹配。即接口转换单元30对应的信号输入接口也为DP输入接口；此时本申请实施例中提供的接口转换单元30对应的信号输入接口为DP输入接口，而对应的信号输出接口为VBO输出接口。
如图2所示，为本申请实施例提供的拼接屏驱动架构另一实施例示意图。在图2中，PC即为计算机，而P4000显卡即为信号转换单元20；而A10为Arria10电路，即为接口转换单元30；CB为Control Board电路板，即为子显示屏驱动电路40。
在图2中，P4000显卡是设置在计算机PC内部的架构，而A10电路和CB电路可以为设置在子显示屏内部的架构。且在图2中，每个计算机PC上还装载有3D软件和画面融合软件，3D软件和画面融合软件均是对外部初始驱动信号进行处理的软件工具。同时在图2所示的实施例中，拼接屏可以为3*3的结构；且由于CB电路板通常为子显示屏的部分电路结构，因此图2中利用CB直接代表子显示屏。
在图2中，计算机可以为五个，分别为PC1-PC5，而每个计算机PC中均包括一个对画面进行处理的3D软件和画面融合软件；且每个计算机PC中均包括一个P4000显卡。而3*3块子显示屏中，每个子显示屏均包括一个A10电路和一个CB电路；且相同子显示屏中的一个A10电路和一个CB电路连接。
在图2所示的实施例中，信号转换单元20（即P4000显卡）的数量小于接口转换单元30（即A10电路）的数量；而接口转换单元30（即A10电路）的数量与子显示屏驱动电路40（即CB）的数量相同。此时，一个信号转换单元20可以同时与多个接口转换单元30连接，即一个信号转换单元20可以同时控制多个不同的子显示屏。
具体地，一个信号转换单元20可以包括四个DP接口（即4DP），而四个DP接口中任意两个DP接口（即2DP）分别与两个不同的接口转换单元30连接；这样一个信号转换单元20可以同时控制多个不同的子显示屏，节省硬件成本。
在本申请的一些实施例中，一个信号转换单元20中的四个DP接口也可以为任意三个DP接口与一个接口转换单元30连接。或是一个信号转换单元20中的四个DP接口全都与同一个接口转换单元连接。
需要说明的是，考虑到实际硬件接口的信息传输速率，在本申请的实施例中，对于同一个信号转换单元20来说，信号转换单元20上至少有两个信号输出接口（即两个DP接口）同时与一个接口转换单元30连接。且在本申请的实施例中，一个信号转换单元20通常为偶数个信号输出接口（即DP接口）同时与同一个接口转换单元30连接。
且在上述实施例中，在偶数个信号输出接口（即DP接口）同时与同一个接口转换单元30连接的同时，还需要保证7680/接口数能够整除。这是因为本申请实施例拼接屏显示的是8K及以上分辨率的3D画面，而7680则是8K画面对应的像素数量。
在本申请的实施例中，拼接屏显示的是8K及以上分辨率的3D画面，信号转换单元20中具体需要利用多少个信号输出接口，取决于视频画面的带宽以及信号输出接口的信号传输速率。
在一个具体实施例中，一般来说，当DP接口的传输速率为8.1Gbps时，两个DP接口就可以传输8K60HZ信号；而当DP接口的传输速率为5.4Gbps时，四个DP接口才能传输8K60HZ信号。
通常来说，视频画面的带宽越大，传输视频信号所需的DP接口越多。而DP接口的传输速率越低，传输视频信号所需的DP接口越多。
在本申请的一个具体实施例中，信号转换单元20（即P4000）显卡包括四个DP输出接口，且每个DP输出接口的信号传输速率为8.1Gbps，此时任意两个DP输出接口与同一个接口转换单元30连接即可。
而同一个接口转换单元30（即A10电路）中包括两个第二信号输入接口，即两个DP输入接口。信号转换单元20中的两个DP输出接口，同时与同一个接口转换单元30中的两个DP输入接口连接；同一个接口转换单元30中的两个DP输入接口的信号传输速率同样为8.1Gbps。
而接口转换单元30（即A10电路）的输出为32 lane V-by-One接口，每个lane V-by-One接口的信号传输速率为2.97Gbps。当接口转换单元（即A10电路）的输入接口为32 lane V-by-One接口时，对应的子显示屏驱动电路40（即CB电路）的输入接口也为32 lane V-by-One接口。
需要说明的是，在上述实施例中，DP接口、32 lane V-by-One是实际的驱动场景中常见的接口；而8.1Gbps、5.4Gbps、2.97Gbps也是比较常规的信号传输速率。
在图2所示的拼接屏驱动架构中，拼接屏驱动架构还包括有3D软件（即画面转换模块），而3D软件主要是用于对视频数据进行编解码，将视频信号转换为3D视频信号。同时还包括画面融合软件（即画面融合模块），画面融合软件将进行3D软件编解码之后的RGB原始数据进行处理，对任意子显示屏与周围其他子显示屏的拼缝数据进行处理，保证数据在拼缝处过渡均匀，避免出现模糊错位等现象。
需要说明的是，在本申请的一些实施例中，画面转换模块和画面融合模块可以分别为上述实施例所述的3D软件和画面融合软件等装载在计算机内部的软件工具；也可以为其他可以实现相同功能的硬件模块。而为了节省硬件成本，通常利用类型3D软件和画面融合软件等软件工具实现画面转换和融合等功能，
在图2所示的实施例中，拼接屏驱动架构还包括同步模块。具体的，同步模块可以为NVIDIA SYNC II卡，而NVIDIA SYNC II卡是P4000显卡中的一部分功能模块；因此NVIDIA SYNC II卡控制的是P4000显卡输出的驱动信号。
即在本申请的实施例中，同步模块与信号转换模块连接，同步模块控制信号转换模块输出的驱动信号实现同步。
在图2所示的实施例中，同步模块（即NVIDIA SYNC II卡）为两个，而两个同步模块中，一个同步模块控制PC1-PC4，即一个同步模块同时控制多个信号转换模块20；而另一个同步模块控制单独控制PC5。由于同步模块为多个，因此还需要控制多个同步模块之间保持同步。具体地，可以利用网线连接多个同步模块，利用物理方法使得多个同步模块之间保持同步。
本申请实施例还提供一种拼接屏驱动方法，利用如上任一项所述的拼接屏驱动架构进行驱动。具体的，拼接屏包括M*N块子显示屏，拼接屏驱动架构包括：多个信号转换单元和多个用于转换接口的接口转换单元，多个信号转换单元与多个接口转换单元电连接；M*N块子显示屏中每个子显示屏包括至少一个子显示屏驱动电路；
多个信号转换单元中每个信号转换单元用于接收外部驱动信号，且将驱动信号发送至所述接口转换单元；接口转换单元用于接收信号转换单元发出的外部驱动信号，且将外部驱动信号发送至子显示屏驱动电路。
其中，M和N均为大于或等于一的正整数。
本申请实施例提供的拼接屏驱动方法包括：
所述信号转换单元接收初始驱动信号，并将所述初始驱动信号转换为所述拼接屏可以显示的驱动信号；
所述信号转换单元将所述驱动信号发送至所述接口转换单元，以利用所述接口转换单元实现接口转换；
所述接口转换单元将所述驱动信号发送至所述子显示屏驱动电路，以利用所述子显示屏驱动线路控制所述拼接屏显示画面。
本申请实施例提供的拼接屏驱动方法，拼接屏驱动架构仅包括多个信号转换单元和多个用于转换接口的接口转换单元，以及多个子显示屏驱动电路；所述多个信号转换单元中每个信号转换单元用于接收外部驱动信号，且将所述驱动信号发送至所述接口转换单元；所述接口转换单元用于接收所述信号转换单元发出的外部驱动信号，且将所述外部驱动信号发送至所述子显示屏驱动电路，使得子显示屏显示画面。整个拼接屏驱动架构仅包括信号转换单元、接口转换单元、子显示屏驱动电路和子显示屏，驱动架构简单，用少量的电路板即可实现拼接屏的驱动，大大降低成本。
在本申请的实施例中，由于拼接屏主要显示的是3D画面，所以拼接屏驱动架构还包括画面转换模块，画面转换模块主要用于将初始驱动信号对应的画面转换为3D画面。因此该拼接屏驱动方法还可以包括：画面转换模块接收初始驱动信号，并生成与3D画面对应的驱动信号以将驱动信号发送至信号转换单元。
在本申请的另一些实施例中，由于拼接屏是由M*N块子显示屏拼接而成，每一个子显示屏显示的画面拼接后才是完整的画面，因此需要对拼缝处的图像进行处理，使得拼缝处的图像过渡更均匀。本申请实施例提供的拼接屏驱动架构还包括融合模块，因此本申请实施例提供的拼接屏驱动方法还可以包括：融合模块接收来自画面转换模块的驱动信号，并对所述驱动信号对应的画面进行融合处理，使得拼缝处画面过渡均匀，避免出现错位模糊的问题。
需要说明的是，外部的驱动信号先发送到画面转换模块转换为3D画面后，再进行融合处理。
以下结合图2具体描述本申请实施例中的拼接屏驱动方法。在图2所示的拼接屏驱动架构中包括五个计算机设备PC1-PC5，而每个PC中均包括一个P4000显卡、3D软件、融合软件。此外还包括3*3块子显示屏（图中未示出），而每个子显示屏中均包括一个A10电路和CB电路，分别为A101-A109以及CB1-CB9。
且任意一个计算机设备例如PC5中还额外装有两个SYNC II同步卡用于同步，且两个SYNC II同步卡利用网线连接；两个SYNC II同步之间也实现同步。
对于图2所示的拼接屏驱动架构来说，以CB1对应的显示屏为例，3D软件接收外部的初始驱动信号，并将初始驱动信号转换为3D的RGB的视频原始数据。而融合软件接收3D软件发出的RGB视频原始数据并进行处理，对CB1拼接屏与周围其他显示屏的拼缝处的数据信息处理，保证视频数据在拼缝处过渡均匀。
而融合处理完成后的驱动信号发送至P4000显卡，P4000显卡对驱动信号进行处理，将驱动信号转换为拼接屏可以显示的驱动信号。而转换后的驱动信号通过P4000显卡中的两个DP接口输出到A10电路中。
而A101电路的通过自身的DP接口接收到P4000显卡输出的驱动信号，又通过自身的VBO接口发送给CB1电路。A10电路本身并不处理驱动信号，A10电路主要是起到接口转换的作用。而CB1通过自身的VBO接口接收到A101电路驱动信号后，将驱动信号输出到子显示屏中实现显示。
对于CB2-CB9来说，均利用上述方法接收到驱动信号并实现显示。
需要说明的是，在本申请的实施例中，PC1-PC5接收到的驱动信号通常需要保持同步。且利用两个NVIDIA SYNC II卡进一步控制驱动信号保持同步。
在本申请的实施例中，NVIDIA SYNC II Card1同时控制PC1-PC4输出的驱动信号保持同步，而NVIDIA SYNC II Card2单独控制PC5输出的信号；又由于NVIDIA SYNC II Card1和NVIDIA SYNC II Card2之间保持同步，因此使得PC1-PC5输出的驱动信号均可以保持同步。
上述实施例仅仅是保证了不同显卡输出的驱动信号之间保持同步，在驱动信号后续传输的过程中仍要保持同步。具体的，需要A101-A109输出的驱动信号之间保持同步。
在本申请的实施例中，可以为A101电路输出同步信号，而A102-A109接收A101发出的同步信号，并根据该同步信号调整自身的驱动信号的时序，使得不同A10电路中的驱动信号保持同步。
具体的，A101电路输出Vsync信号，而A102-A109接收A101发出的Vsync信号用于帧同步；A101-A109基于Vsync信号在一帧画面中的非显示时段（Vblank区域），重新生成并输出当前帧画面的时序信号DE，而视频信号与新的实训信号DE对齐并同时输出。
在本申请的实施例中，拼接屏不仅显示3D画面，还可以显示8K及以上分辨率的3D画面。请结合图2，对于图2所示的拼接屏驱动架构来说，若3*3的子显示屏均显示8K3D画面，则对于PC1来说，接收到的外部驱动信号为两路8K60HZ的信号，即3D软件处理的是2*8K60HZ的信号。而3D软件处理后发给融合软件的同样为2*8K60HZ的信号；融合软件又将处理后的2*8K60HZ的信号发送给P4000显卡。由于一个P4000显卡同时控制两个子显示屏，此时2*8K60HZ的信号分别输入两个接口转换单元30中，每一个接口转换单元30接收到的信号为8k60HZ的信号。
对于本申请提供的实施例来说，若是每个子显示屏均可以接收并显示8K信号，实际上子显示屏接收并显示的8K4K分辨率的画面。而当拼接屏为3*3的结构时，整个拼接屏水平与垂直方向的子显示屏的数量各为3，拼接屏整体显示的画面为(8k*3)(4K*3)，即拼接后的画面整体分辨率为24K12K。
具体的，由于每条视频链路只驱动一个8K4K的信号，3x3共9条视频链路同时输出，就可以输出(8k*3)(4K*3)共24K12K的数据。而若是M*N块子显示屏为其他的数量，也可以对应显示其他不同分辨率的3D画面。
在上述实施例中，由于每个PC最多只能支持2个SYNC II同步卡，如果子显示屏的数量超过两个SYNC II同步卡支持的***，就需要在其他的PC上额外增加SYNC II同步卡和显卡。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见上文针对其他实施例的详细描述，此处不再赘述。
具体实施时，以上各个单元或结构可以作为独立的实体来实现，也可以进行任意组合，作为同一或若干个实体来实现，以上各个单元或结构的具体实施可参见前面的方法实施例，在此不再赘述。
以上各个操作的具体实施可参见前面的实施例，在此不再赘述。
以上对本申请实施例所提供的一种拼接屏驱动架构及驱动方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种拼接屏驱动架构，其中，所述拼接屏包括M*N块子显示屏，所述拼接屏驱动架构包括：
    多个信号转换单元和多个用于转换接口的接口转换单元，所述多个信号转换单元与所述多个接口转换单元电连接；所述M*N块子显示屏中每个子显示屏包括至少一个子显示屏驱动电路；其中，所述M和N均为大于或等于一的正整数；
    所述多个信号转换单元中每个信号转换单元用于接收外部驱动信号，且将所述驱动信号发送至所述接口转换单元；所述接口转换单元用于接收所述信号转换单元发出的外部驱动信号，且将所述外部驱动信号发送至所述子显示屏驱动电路。
  2. 根据权利要求1所述的拼接屏驱动架构，其中，所述接口转换单元包括信号输入接口和信号输出接口，所述接口转换单元的信号输入接口和信号输出接口对应的数据传输协议不匹配。
  3. 根据权利要求2所述的拼接屏驱动架构，其中，所述信号转换单元包括信号输入和信号输出接口，所述接口转换单元的信号输入接口对应的数据传输协议，与所述信号转换单元的信号输出接口对应的信号传输协议匹配。
  4. 根据权利要求1所述的拼接屏驱动架构，其中，所述接口转换单元的数量和所述子显示屏驱动电路的数量相同。
  5. 根据权利要求4所述的拼接屏驱动架构，其中，所述信号转换单元的数量与所述接口转换单元的数量相同。
  6. 根据权利要求5所述的拼接屏驱动架构，其中，任意一个信号转换单元通过自身的多个信号输出接口与任意一个接口转换单元连接。
  7. 根据权利要求1所述的拼接屏驱动架构，其中，所述信号转换单元的数量小于所述接口转换单元的数量。
  8. 根据权利要求6所述的拼接屏驱动架构，其中，任意一个信号转换单元通过自身的多个信号输出接口同时与多个接口转换单元连接。
  9. 根据权利要求8所述的拼接屏驱动架构，其中，一个信号转换单元中的偶数个信号输出接口同时与一个接口转换电路连接。
  10. 根据权利要求1所述的拼接屏驱动架构，其中，所述拼接屏驱动架构还包括同步模块，所述同步模块用于同步所述多个信号转换单元输出的驱动信号。
  11. 根据权利要求10所述的拼接屏驱动架构，其中，所述同步模块为多个，多个所述同步模块之间利用网络实现物理连接而保持同步。
  12. 根据权利要求1所述的拼接屏驱动架构，其中，所述多个接口转换单元利用同轴线实现时序同步。
  13. 根据权利要求1所述的拼接屏驱动架构，其中，所述信号转换单元中的信号输出接口为DP接口。
  14. 根据权利要求13所述的拼接屏驱动架构，其中，视频画面的带宽越大，传输视频信号所需的DP接口越多。
  15. 根据权利要求13所述的拼接屏驱动架构，其中，所述DP接口的传输速率越低，传输视频信号所需的DP接口越多。
  16. 根据权利要求15所述的拼接屏驱动架构，其中，当所述DP接口的传输速率为8.1Gbps时，两个所述DP接口传输8K60HZ信号；当所述DP接口的传输速率为5.4Gbps时，四个所述DP接口传输8K60HZ信号。
  17. 根据权利要求1所述的拼接屏驱动架构，其中，所述信号转换单元为P4000显卡。
  18. 根据权利要求1所述的拼接屏驱动架构，其中，所述接口转换单元为Arria10电路。
  19. 根据权利要求1所述的拼接屏驱动架构，其中，所述拼接屏驱动架构还包括画面转换模块，所述画面转换模块用于将初始驱动信号对应的画面转换为3D画面，并生成与所述3D画面对应的驱动信号以将所述驱动信号发送给所述多个信号转换单元。
  20. 一种拼接屏驱动方法，其中，利用如权利要求1-19任一项所述的拼接屏驱动结构进行驱动，所述拼接屏驱动方法包括：
    所述信号转换单元接收初始驱动信号，并将所述初始驱动信号转换为所述拼接屏可以显示的驱动信号；
    所述信号转换单元将所述驱动信号发送至所述接口转换单元，以利用所述接口转换单元实现接口转换；
    所述接口转换单元将所述驱动信号发送至所述子显示屏驱动电路，以利用所述子显示屏驱动线路控制所述拼接屏显示画面。
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