WO2023087373A1 - 显示面板及其制作方法、移动终端 - Google Patents

显示面板及其制作方法、移动终端 Download PDF

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Publication number
WO2023087373A1
WO2023087373A1 PCT/CN2021/133802 CN2021133802W WO2023087373A1 WO 2023087373 A1 WO2023087373 A1 WO 2023087373A1 CN 2021133802 W CN2021133802 W CN 2021133802W WO 2023087373 A1 WO2023087373 A1 WO 2023087373A1
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Prior art keywords
gate
layer
region
drain
diffusion region
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PCT/CN2021/133802
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English (en)
French (fr)
Inventor
丁玎
方亮
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武汉华星光电半导体显示技术有限公司
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Priority to US17/620,021 priority Critical patent/US20240107822A1/en
Publication of WO2023087373A1 publication Critical patent/WO2023087373A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present application relates to the display field, in particular to a display panel, a manufacturing method thereof, and a mobile terminal.
  • the quality requirements for display panels have become higher and higher.
  • the resistance of the active layer without special treatment is very high, which will affect the resistance of the source and drain regions, thereby affecting the mobility.
  • the source and drain regions are processed, such as using gate self-alignment to pattern the gate insulating layer so that the gate and the gate insulating layer have the same line width, and using plasma gas to treat the source and drain regions , reduce its resistance to make it conductive, but the plasma gas will diffuse in the source and drain regions along the channel layer to the channel region, resulting in shortening of the actual channel length, which will seriously affect the threshold voltage of the device, thereby affecting the display panel. quality.
  • the invention provides a display panel, a manufacturing method thereof, and a mobile terminal, which can alleviate the current technical problem that plasma gas diffuses along the channel layer to the channel region in the source and drain regions, resulting in shortening of the actual channel length.
  • An embodiment of the present application provides a display panel, including:
  • a driving circuit layer disposed on one side of the substrate comprising: a first active layer, a first gate insulating layer disposed on a side of the first active layer away from the substrate , a first gate disposed on a side of the first gate insulating layer far away from the substrate, a first interlayer insulating layer disposed on a side of the first gate far away from the substrate, and a first gate disposed on a side far away from the substrate, and disposed on The first interlayer insulating layer is away from the source-drain layer on the side of the substrate, and the source-drain layer includes a first source and a first drain;
  • the orthographic projection of the first gate insulating layer on the substrate is located within the range of the orthographic projection of the first active layer on the substrate, and the first gate is on the substrate
  • the orthographic projection on is located within the range of the orthographic projection of the first gate insulating layer on the substrate.
  • the first active layer includes: a first source conductor region, a first channel region, a first drain conductor region, a The first diffusion region between, and the second diffusion region located between the first drain conductor region and the first channel region, the first source is electrically connected to the first source conductor region , the first drain is electrically connected to the first drain conductor region; the first interlayer insulating layer covers at least the first channel region, the first diffusion region, and the second diffusion region .
  • the first gate insulating layer is completely overlapped with the first channel region, the first diffusion region, and the second diffusion region, and the The first gate overlaps with the first channel region.
  • the first active layer includes a plurality of oxygen vacancies; the concentration of oxygen vacancies in the first source conductor region and the first drain conductor region is higher than that in the first diffusion region and the first drain conductor region.
  • the oxygen vacancy concentrations of the two diffusion regions; the oxygen vacancy concentrations of the first diffusion region and the second diffusion region are both greater than the oxygen vacancy concentrations of the first channel region.
  • the first active layer further includes a third diffusion region located on the side of the first source conductor region away from the first channel region, and a third diffusion region located on the side of the first drain conductor region away from the first channel region.
  • the fourth diffusion region on the side of the first channel region; wherein, the oxygen vacancy concentration of the first source conductor region is greater than the oxygen vacancy concentration of the third diffusion region, and the oxygen vacancy concentration of the first drain conductor region The concentration is greater than the oxygen vacancy concentration of the fourth diffusion region.
  • the ratio of the sum of the width of the first diffusion region and the width of the second diffusion region to the width of the first channel region is less than 1:1.
  • the first gate insulating layer includes a first unit corresponding to the first gate, and a second unit located on the periphery of the first unit, the first unit is connected to the second unit Setting; wherein, the thickness of the second unit is smaller than the thickness of the first unit.
  • the driving circuit layer further includes a second gate corresponding to the first gate, and the second gate is located on a side of the first active layer away from the first gate;
  • the driving circuit layer further includes: a second active layer, a third gate, a fourth gate located between the second active layer and the third gate, and a second source and a second drain ;
  • the third gate and the second gate are arranged in the same layer, and the first source, the first drain, the second source and the second drain are arranged in the same layer .
  • the embodiment of the present application also provides a method for manufacturing a display panel, including:
  • the photoresist layer forms a second pattern that is continuously arranged, and the area of the second pattern is smaller than the area of the first pattern, so that part of the first gate film layer is exposed;
  • the exposed first gate film layer is removed to form a first gate and a first gate insulating layer.
  • the patterning process is used to form a first pattern on the first insulating film layer, the first gate film layer, and the photoresist layer, so that part of the first active layer is exposed.
  • the step includes: forming a first pattern on the first insulating film layer, the first gate film layer, and the photoresist layer by patterning process, so that the periphery of the first active layer is exposed.
  • the patterning process is used to form a first pattern on the first insulating film layer, the first gate film layer, and the photoresist layer, so that part of the first active layer is exposed.
  • the step includes: using a patterning process to form a first pattern on the first insulating film layer, the first gate film layer, and the photoresist layer, and the first pattern includes a plurality of openings; wherein, the The photoresist layer is arranged around the opening.
  • the manufacturing method of the display panel further includes: forming a first hole including a plurality of first openings on the first active layer, the first gate insulating layer, and the first gate.
  • the first opening exposes the first active layer; a first source and a first drain are formed on the first interlayer insulating layer.
  • the embodiment of the present application also provides a mobile terminal, including a display panel and a terminal body, where the terminal body is combined with the display panel;
  • the display panel includes:
  • a driving circuit layer disposed on one side of the substrate comprising: a first active layer, a first gate insulating layer disposed on a side of the first active layer away from the substrate , a first gate disposed on a side of the first gate insulating layer far away from the substrate, a first interlayer insulating layer disposed on a side of the first gate far away from the substrate, and a first gate disposed on a side far away from the substrate, and disposed on The first interlayer insulating layer is away from the source-drain layer on the side of the substrate, and the source-drain layer includes a first source and a first drain;
  • the orthographic projection of the first gate insulating layer on the substrate is located within the range of the orthographic projection of the first active layer on the substrate, and the first gate is on the substrate
  • the orthographic projection on is located within the range of the orthographic projection of the first gate insulating layer on the substrate.
  • the first active layer includes: a first source conductor region, a first channel region, a first drain conductor region, a The first diffusion region between, and the second diffusion region located between the first drain conductor region and the first channel region, the first source is electrically connected to the first source conductor region , the first drain is electrically connected to the first drain conductor region; the first interlayer insulating layer covers at least the first channel region, the first diffusion region, and the second diffusion region .
  • the first gate insulating layer is completely overlapped with the first channel region, the first diffusion region, and the second diffusion region, and the The first gate overlaps with the first channel region.
  • the first active layer includes a plurality of oxygen vacancies; the concentration of oxygen vacancies in the first source conductor region and the first drain conductor region is higher than that in the first diffusion region and the first drain conductor region.
  • the oxygen vacancy concentrations of the two diffusion regions; the oxygen vacancy concentrations of the first diffusion region and the second diffusion region are both greater than the oxygen vacancy concentrations of the first channel region.
  • the first active layer further includes a third diffusion region located on the side of the first source conductor region away from the first channel region, and a third diffusion region located on the side of the first drain conductor region away from the first channel region.
  • the fourth diffusion region on the side of the first channel region; wherein, the oxygen vacancy concentration of the first source conductor region is greater than the oxygen vacancy concentration of the third diffusion region, and the oxygen vacancy concentration of the first drain conductor region The concentration is greater than the oxygen vacancy concentration of the fourth diffusion region.
  • the ratio of the sum of the width of the first diffusion region and the width of the second diffusion region to the width of the first channel region is less than 1:1.
  • the first gate insulating layer includes a first unit corresponding to the first gate, and a second unit located on the periphery of the first unit, the first unit is connected to the second unit Setting; wherein, the thickness of the second unit is smaller than the thickness of the first unit.
  • the driving circuit layer further includes a second gate corresponding to the first gate, and the second gate is located on a side of the first active layer away from the first gate;
  • the driving circuit layer further includes: a second active layer, a third gate, a fourth gate located between the second active layer and the third gate, and a second source and a second drain ;
  • the third gate and the second gate are arranged in the same layer, and the first source, the first drain, the second source and the second drain are arranged in the same layer .
  • the size of the first gate is smaller than the size of the first gate insulating layer
  • the size of the first gate insulating layer is smaller than the size of the first active layer
  • the first gate and the first gate insulating layer are used to When the active layer is self-aligned and conductorized, the distance of the diffusion region of the plasma gas is reserved to effectively prevent the shortening of the channel region, ensure the effective length of the channel region, prevent threshold voltage drift, and improve the quality of the display panel.
  • FIG. 1 is a schematic structural diagram of a first structure of a display panel provided by an embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a second structure of a display panel provided by an embodiment of the present invention.
  • Fig. 3 is a schematic top view of Fig. 1 or Fig. 2;
  • FIG. 4 is a schematic structural diagram of a third structure of a display panel provided by an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a fourth structure of a display panel provided by an embodiment of the present invention.
  • FIG. 6 is a schematic structural diagram of a fifth structure of a display panel provided by an embodiment of the present invention.
  • Fig. 7 is a flow chart of the first step of the manufacturing method of the display panel provided by the embodiment of the present invention.
  • FIG. 8 is a flow chart of the second step of the manufacturing method of the display panel provided by the embodiment of the present invention.
  • FIGS. 9A to 9F are schematic flowcharts of the first method of manufacturing a display panel provided by an embodiment of the present invention.
  • FIG. 10 is a second schematic flowchart of a method for manufacturing a display panel provided by an embodiment of the present invention.
  • FIG. 11A and 11B are schematic flowcharts of a third method of manufacturing a display panel provided by an embodiment of the present invention.
  • Fig. 12 is a schematic structural diagram of a mobile terminal provided by an embodiment of the present invention.
  • the present application provides a display panel, a manufacturing method thereof, and a mobile terminal.
  • a display panel a manufacturing method thereof
  • a mobile terminal a mobile terminal
  • Embodiments of the present application provide a display panel, a manufacturing method thereof, and a mobile terminal. Each will be described in detail below. It should be noted that the description sequence of the following embodiments is not intended to limit the preferred sequence of the embodiments.
  • an embodiment of the present invention provides a display panel 100, including:
  • the driving circuit layer is arranged on one side of the substrate 200, and the driving circuit layer includes: a first active layer 310, a first active layer 310 arranged on a side away from the substrate 200.
  • the orthographic projection of the first gate insulating layer 320 on the substrate 200 is within the range of the orthographic projection of the first active layer 310 on the substrate 200, and the first gate 330 The orthographic projection on the substrate 200 is within the range of the orthographic projection of the first gate insulating layer 320 on the substrate 200 .
  • the size of the first gate is smaller than the size of the first gate insulating layer
  • the size of the first gate insulating layer is smaller than the size of the first active layer
  • the first gate and the first gate insulating layer are used to When the active layer is self-aligned and conductorized, the distance of the diffusion region of the plasma gas is reserved to effectively prevent the shortening of the channel region, ensure the effective length of the channel region, prevent threshold voltage drift, and improve the quality of the display panel.
  • the display panel 100 includes: a substrate 200; a driving circuit layer disposed on one side of the substrate 200, and the driving circuit layer includes: a first active layer 310 , the first gate insulating layer 320 disposed on the side of the first active layer 310 away from the substrate 200 , the first gate insulating layer 320 disposed on the side of the first gate insulating layer 320 away from the substrate 200
  • the source-drain layer includes a first source electrode 341 and a first drain electrode 342 .
  • the orthographic projection of the first gate insulating layer 320 on the substrate 200 is located within the range of the orthographic projection of the first active layer 310 on the substrate 200, and the first gate 330 is in the The orthographic projection on the substrate 200 is within the range of the orthographic projection of the first gate insulating layer 320 on the substrate 200 .
  • the orthographic projection of the first gate insulating layer 320 on the substrate 200 is located at Within the range of the orthographic projection of the first active layer 310 on the substrate 200, the distance of the diffusion region where the plasma gas acts can be reserved to effectively prevent the shortening of the channel.
  • the orthographic projection on the bottom 200 is within the range of the orthographic projection of the first gate insulating layer 320 on the substrate 200 , which can ensure the effective channel length, prevent threshold voltage drift, and improve the quality of the display panel 100 .
  • the first active layer includes: a first source conductor region 312, a first channel region 311, a first drain conductor region 313, a a first diffusion region 314 between the conductor region 312 and the first channel region 311, and a second diffusion region 315 between the first drain conductor region 313 and the first channel region 311,
  • the first source 341 is electrically connected to the first source conductor region 312, and the first drain 342 is electrically connected to the first drain conductor region 313;
  • the first interlayer insulating layer 360 is at least Covering the first channel region 311 , the first diffusion region 314 and the second diffusion region 315 .
  • the first channel region 311 corresponds to the channel region of the semiconductor; the first source conductor region 312 and the first drain conductor region 313 correspond to the source and drain regions, corresponding to the conductorized region, and have strong conductivity ;
  • the first diffusion area 314 and the second diffusion area 315 correspond to the diffusion area of the plasma gas action, the resistance is between the first channel area 311 and the conductorized area, and the plasma gas action is reserved. The distance of the diffusion region effectively prevents the shortening of the channel, ensures the effective channel length, prevents the threshold voltage from drifting, and improves the quality of the display panel 100 .
  • the first gate insulating layer 320 and the first channel region 311, the first diffusion region 314, and the second diffusion The region 315 is completely overlapped, and the first gate 330 is overlapped with the first channel region 311 .
  • a part of the first gate insulating layer 320 has the function of protecting the diffusion region, and the size of the first channel region 311 corresponding to the channel region corresponds to the first gate 330 to ensure the effective channel length and prevent threshold The voltage drift improves the quality of the display panel 100 .
  • the display panel further includes a plurality of The first interlayer insulating layer 360 of the first opening 361 , the first opening 361 exposes the first active layer 310 .
  • the insulating material between the first active layer 310 and the first source-drain unit 340 is a first interlayer insulating layer 360
  • the The material of the first interlayer insulating layer 360 is an insulating material.
  • the first gate insulating layer 320 includes a first unit 321 corresponding to the first gate 330 , and a first unit 321 located on the periphery of the first unit 321 .
  • Two units 322 , the first unit 321 is connected to the second unit 322 ; wherein, the thickness of the second unit 322 is smaller than the thickness of the first unit 321 .
  • the thickness of the second unit 322 will be smaller than the thickness of the first unit 321, and this structure can be used as an anti-counterfeiting mark.
  • the width of the second unit 322 may be equal to or different from the widths of the first diffusion region 314 and the second diffusion region 315 .
  • the ratio of the sum of the width of the first diffusion region 314 and the width of the second diffusion region 315 to the width of the first channel region 311 is less than 1:1.
  • the total length of the diffusion region should not exceed half of the sum of the diffusion region and the channel region, that is, the first The ratio of the sum of the width of the diffusion region 314 and the width of the second diffusion region 315 to the width of the first channel region 311 is less than 1:1, wherein the width of the first channel region 311 is represented by L It means that the width of the first diffusion region 314 and the width of the second diffusion region 315 are represented by ⁇ L1 and ⁇ L2 respectively, and the total length of the diffusion region is ⁇ L1+ ⁇ L2. Not only can the effective channel length be guaranteed, the threshold voltage drift can be prevented, but also the on-state current of the first thin film transistor can be increased, and the working efficiency of the first thin film transistor can be improved.
  • the first active layer 310 includes a plurality of oxygen vacancies; the oxygen vacancy concentrations of the first source conductor region 312 and the first drain conductor region 313 are both greater than the first The oxygen vacancy concentration of the diffusion region 314 and the second diffusion region 315; the oxygen vacancy concentration of the first diffusion region 314 and the second diffusion region 315 are all greater than the oxygen vacancy concentration of the first channel region 311 .
  • the first channel region 311 corresponds to the channel region of the semiconductor, and the concentration of oxygen vacancies is the smallest; the first source conductor region 312 .
  • the first drain conductor region 313 corresponds to the source and drain regions, and corresponds to the conductorized region, which has strong conductivity and the highest concentration of oxygen vacancies; the first diffusion region 314 and the second diffusion region 315 correspond to the plasma gas In the active diffusion region, the resistance is between the first channel region 311 and the conductorized region, and the concentration of oxygen vacancies is between the two, so as to ensure the effective channel length, prevent threshold voltage drift, and improve the display panel 100. the quality of.
  • the first active layer 310 further includes a third diffusion region 316 located on a side of the first source conductor region 312 away from the first channel region 311 , and The fourth diffusion region 317 located on the side of the first drain conductor region 313 away from the first channel region 311; wherein, the oxygen vacancy concentration of the first source conductor region 312 is greater than that of the third diffusion region 316 oxygen vacancy concentration, the oxygen vacancy concentration of the first drain conductor region 313 is greater than the oxygen vacancy concentration of the fourth diffusion region 317 .
  • the source and drain regions are treated with plasma gas to reduce their resistance and thereby
  • the opening 362 is used to diffuse the source and drain regions on both sides, which can further shorten the width of the control diffusion region, ensure the effective channel length, prevent threshold voltage drift, and improve the quality of the display panel 100 .
  • the oxygen vacancy concentration of the first diffusion region 314 is equal to the oxygen vacancy concentration of the third diffusion region 316
  • the oxygen vacancy concentration of the second diffusion region 315 is equal to that of the fourth diffusion region 317. Oxygen vacancy concentration.
  • the third diffusion region 316 as an example, that is, when the plasma gas diffuses, the plasma diffusion in the third diffusion region 316 does not reach the edge of the first active layer 310 or just diffuses to the first active layer 310 An edge of the active layer 310 .
  • the oxygen vacancy concentration of the first diffusion region 314 is lower than the oxygen vacancy concentration of the third diffusion region 316, and the oxygen vacancy concentration of the second diffusion region 315 is lower than that of the fourth diffusion region 317.
  • Oxygen vacancy concentration is lower than the third diffusion region 316.
  • the oxygen vacancy concentration of the third diffusion region 316 is equal to the oxygen vacancy concentration of the first source conductor region 312, and the oxygen vacancy concentration of the fourth diffusion region 317 is equal to the first drain concentration.
  • the oxygen vacancy concentration of the conductor region 313 The plasma gas diffuses to make the third diffusion region 316 and the fourth diffusion region 317 in a saturated state, which is the same as the state of the first source conductor region 312 and the first drain conductor region 313 .
  • the driving circuit layer further includes a second gate 350 corresponding to the first gate 330 , and the second gate 350 is located on the first active layer 310 A side away from the first gate 330; the driving circuit layer further includes: a second active layer 410, a third gate 420, and a second active layer 410 located between the third gate 420 Between the fourth gate 430, and the second source 441 and the second drain 442; wherein, the third gate 420 is set on the same layer as the second gate 350, and the first source 341, The first drain 342 , the second source 441 and the second drain 442 are arranged in the same layer.
  • the first gate 330, the second gate 350, and the first active layer 310 constitute the first thin film transistor
  • the third gate 420, the fourth gate 430, the The second active layer 410 constitutes the second thin film transistor.
  • the first gate 330 and the second gate 350 are designed as upper and lower double gates, the first gate 330 is a top gate, and the second gate 350 is a bottom gate, both of which control the first gate together.
  • the fourth gate 430 is used as a gate switching signal, and the fourth gate 430 and the third gate 420 form a capacitance to control the potential of the gate terminal.
  • the first active layer 310 includes metal oxide
  • the second active layer 410 includes low temperature polysilicon. Integrating low temperature polysilicon (LTPS) thin film transistors and metal oxide (Metal Oxide) thin film transistors on the same display panel 100 can combine the advantages of high mobility of low temperature polysilicon thin film transistors, fast charging of pixel capacitance, and metal oxide Thin film transistors have the advantage of low leakage.
  • LTPS low temperature polysilicon
  • Metal Oxide Metal Oxide
  • the display panel 100 further includes an insulating material filled between different types of components, the insulating material may be an organic insulating material, or an inorganic insulating material, the organic insulating material may be polyimide,
  • the inorganic insulating material can be any one of silicon-oxygen compound, silicon-nitride compound or silicon-oxygen-nitride compound, which is only used as an example here, and can be determined according to the actual process or actual situation, and is not specifically limited.
  • the materials of the first gate insulating layer 320 and all the insulating film layers may be organic insulating materials or inorganic insulating materials.
  • the organic insulating material can be polyimide, and the inorganic insulating material can be any one of silicon oxide compound, nitrogen silicon compound or silicon oxynitride compound. This is just an example, and the details can be determined according to the actual process or actual situation. Not specifically limited.
  • the display panel 100 may be a liquid crystal display panel or an organic light emitting display panel, and the following description will be made by taking the display panel 100 as an organic light emitting display panel as an example.
  • the display panel 100 further includes a planar layer 500 on the first source-drain unit 340 and the second source-drain unit 440 , the planar layer 500 includes a plurality of second openings 510 .
  • the display panel 100 further includes an anode layer 610 on the planar layer 500 , a pixel definition layer 620 on the anode layer 610 including a plurality of third openings, The luminescent material layer 630 located in the third opening, the cathode layer 640 located on the luminescent material layer 630 , and the spacer 650 located on the pixel definition layer 620 .
  • the anode layer 610 is electrically connected to the second source-drain unit 440 through the second opening 510 .
  • the display panel 100 further includes an encapsulation layer and a cover plate on the cathode layer 640 .
  • the size of the first gate is smaller than the size of the first gate insulating layer
  • the size of the first gate insulating layer is smaller than the size of the first active layer
  • the first gate and the first gate insulating layer are used to When the active layer is self-aligned and conductorized, the distance of the diffusion region of the plasma gas is reserved to effectively prevent the shortening of the channel region, ensure the effective length of the channel region, prevent threshold voltage drift, and improve the quality of the display panel.
  • the embodiment of the present invention also provides a method for manufacturing a display panel 100, including:
  • the size of the first gate is smaller than the size of the first gate insulating layer
  • the size of the first gate insulating layer is smaller than the size of the first active layer
  • the first gate and the first gate insulating layer are used to When the active layer is self-aligned and conductorized, the distance of the diffusion region of the plasma gas is reserved to effectively prevent the shortening of the channel region, ensure the effective length of the channel region, prevent threshold voltage drift, and improve the quality of the display panel.
  • step S100 includes:
  • the display panel 100 is filled with insulating materials between different types of components.
  • the insulating material can be an organic insulating material or an inorganic insulating material.
  • the organic insulating material can be polyimide, and the inorganic insulating material can be polyimide.
  • the material can be any one of silicon-oxygen compound, silicon-nitride compound or silicon-oxygen-nitride compound. This is just an example. The details can be determined according to the actual process or actual situation, and there is no specific limitation. The material composition of the insulating material is not the original The focus of the invention, so no precise distinction is made.
  • the first insulating film layer 301 and the first gate film layer 302 are subsequently uniformly patterned, and then aligned and conductorized, which can save photomasks and reduce production costs ,Increase productivity.
  • the material of the photoresist layer 303 is a photoresist material, and the composition of the material is not the focus of the present invention and is not specifically limited.
  • step S400 exposes part of the first active layer 310 , and the exposed area can be bombarded with plasma gas to be conductive.
  • step S400 may include:
  • step S400 may include:
  • the photoresist layer 303 is disposed around the opening 362 .
  • step S500 of step S410a please refer to FIG. 9E; for step S500 of step S410b, please refer to FIG. 11B.
  • the dotted arrow represents the plasma process.
  • it can be He, Ar, CF4, etc.
  • CF4 can measure the F content or oxygen hole content in the final product, while
  • He and Ar it is not easy to detect the content, so the oxygen vacancy concentration can be used as the distinction between different regions.
  • step S600 the periphery of the first gate film layer 302 is exposed, and the photoresist layer 303 is shrunk, so that the next step of shrinking the first gate film layer 302 can be performed to form a The first gate 330 corresponding to the first active layer 310 .
  • the photoresist layer 303 of the second pattern corresponds to the central position of the first active layer 310, and the photoresist layer 303 around the opening 362 in step S410b is removed, so that The peripheral area of the first active layer 310 is exposed.
  • the size of the first opening 361 can be reduced to avoid causing the first opening 361 to be too large.
  • the first source-drain unit 340 is collapsed or abnormally connected.
  • step S700 remove the first gate film layer 302 not covered by the photoresist layer 303, so as to form a gate corresponding to the first active layer 310. of the first gate 330 .
  • the first active layer includes: a first source conductor region 312, a first channel region 311, a first drain conductor region 313, and The first diffusion region 314 between the first source conductor region 312 and the first channel region 311 , and the first diffusion region 314 between the first drain conductor region 313 and the first channel region 311
  • the second diffusion region 315, the first source 341 is electrically connected to the first source conductor region 312, the first drain 342 is electrically connected to the first drain conductor region 313; the first The interlayer insulating layer 360 at least covers the first channel region 311 , the first diffusion region 314 and the second diffusion region 315 .
  • the first channel region 311 corresponds to the channel region of the semiconductor; the first source conductor region 312 and the first drain conductor region 313 correspond to the source and drain regions, corresponding to the conductorized region, and have strong conductivity ;
  • the first diffusion area 314 and the second diffusion area 315 correspond to the diffusion area of the plasma gas action, the resistance is between the first channel area 311 and the conductorized area, and the plasma gas action is reserved. The distance of the diffusion region effectively prevents the shortening of the channel, ensures the effective channel length, prevents the threshold voltage from drifting, and improves the quality of the display panel 100 .
  • the first gate insulating layer 320 includes a first unit 321 corresponding to the first gate 330 , and a first unit 321 located on the periphery of the first unit 321 .
  • Two units 322 , the first unit 321 is connected to the second unit 322 ; wherein, the thickness of the second unit 322 is smaller than the thickness of the first unit 321 .
  • the thickness of the second unit 322 will be smaller than the thickness of the first unit 321, and this structure can be used as an anti-counterfeiting mark.
  • the manufacturing method of the display panel 100 further includes:
  • the insulating material between the first active layer 310 and the first source-drain unit 340 is a first interlayer insulating layer 360, and the first interlayer insulating The material of layer 360 is an insulating material.
  • the first source 341 and the first drain 342 are electrically connected to the first active layer 310 through the first opening 361 .
  • the driving circuit layer further includes a second gate 350 corresponding to the first gate 330 , and the second gate 350 is located on the first active layer 310 A side away from the first gate 330; the driving circuit layer further includes: a second active layer 410, a third gate 420, and a second active layer 410 located between the third gate 420 Between the fourth gate 430, and the second source 441 and the second drain 442; wherein, the third gate 420 is set on the same layer as the second gate 350, and the first source 341, The first drain 342 , the second source 441 and the second drain 442 are arranged in the same layer.
  • the size of the first gate is smaller than the size of the first gate insulating layer
  • the size of the first gate insulating layer is smaller than the size of the first active layer
  • the first gate and the first gate insulating layer are used to When the active layer is self-aligned and conductorized, the distance of the diffusion region of the plasma gas is reserved to effectively prevent the shortening of the channel region, ensure the effective length of the channel region, prevent threshold voltage drift, and improve the quality of the display panel.
  • an embodiment of the present invention also provides a mobile terminal 10 , including any one of the above-mentioned display panels 100 and a terminal body 20 , where the terminal body 20 is combined with the display panel 100 .
  • the embodiment of the present invention discloses a display panel, a manufacturing method thereof, and a mobile terminal; the display panel substrate and a driving circuit layer, and the driving circuit layer includes: a first active layer, a first gate insulating layer, a first gate Pole, a first interlayer insulating layer, and a first source and a first drain, the orthographic projection of the first gate insulating layer on the substrate is located at the orthographic projection of the first active layer on the substrate Within the range, the orthographic projection of the first gate on the substrate is within the range of the orthographic projection of the first gate insulating layer on the substrate; the present invention makes the size of the first gate smaller than the first gate insulating layer The size of the layer, the size of the first gate insulating layer is smaller than the size of the first active layer, and when the first active layer is self-aligned and conductorized using the first gate and the first gate insulating layer, the plasma The distance of the gas diffusion region effectively prevents the shortening of the channel region, ensures the effective length of the

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Abstract

一种显示面板及其制作方法、移动终端;显示面板包括衬底及驱动电路层，驱动电路层包括第一有源层、第一栅极绝缘层、第一栅极、第一层间绝缘层、第一源极和第一漏极，第一栅极绝缘层在衬底上的正投影位于第一有源层在衬底上的正投影范围内，第一栅极在衬底上的正投影位于第一栅极绝缘层在衬底上的正投影范围内。

Description

显示面板及其制作方法、移动终端 技术领域
本申请涉及显示领域，尤其涉及一种显示面板及其制作方法、移动终端。
 背景技术
近些年，对于显示面板的质量要求越来越高，没有特殊处理过的有源层电阻很大，这会影响源漏极区的阻值，从而影响迁移率的大小，为了降低有源层电阻，通常会对源漏极区进行处理，如利用栅极自对准的方式使栅极绝缘层图案化，使栅极与栅极绝缘层具有相同线宽，利用等离子气体处理源漏极区，降低其电阻从而使其导体化，但等离子气体会在源漏区沿着沟道层向沟道区扩散，造成实际沟道长度缩短，这会严重影响器件的阈值电压，从而影响显示面板的质量。
因此，亟需一种显示面板及其制作方法、移动终端以解决上述技术问题。
 技术问题
本发明提供一种显示面板及其制作方法、移动终端，可以缓解目前等离子气体会在源漏区沿着沟道层向沟道区扩散，造成实际沟道长度缩短的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供了一种显示面板，包括：
衬底；
驱动电路层，设置在所述衬底的一侧，所述驱动电路层包括：第一有源层、设置在所述第一有源层远离所述衬底一侧的第一栅极绝缘层、设置在所述第一栅极绝缘层远离所述衬底一侧的第一栅极、设置在所述第一栅极远离所述衬底一侧的第一层间绝缘层、以及设置在所述第一层间绝缘层远离所述衬底一侧的源漏极层，所述源漏极层包括第一源极和第一漏极；
其中，所述第一栅极绝缘层在所述衬底上的正投影位于所述第一有源层在所述衬底上的正投影范围内，所述第一栅极在所述衬底上的正投影位于所述第一栅极绝缘层在所述衬底上的正投影范围内。
优选的，所述第一有源层包括：第一源极导体区、第一沟道区、第一漏极导体区、位于所述第一源极导体区和所述第一沟道区之间的第一扩散区、以及位于所述第一漏极导体区和所述第一沟道区之间的第二扩散区，所述第一源极与所述第一源极导体区电连接，所述第一漏极与所述第一漏极导体区电连接；所述第一层间绝缘层至少覆盖所述第一沟道区、所述第一扩散区、所述第二扩散区。
优选的，在所述显示面板的俯视图方向上，所述第一栅极绝缘层与所述第一沟道区、所述第一扩散区、及所述第二扩散区完全重叠设置，所述第一栅极与所述第一沟道区重叠设置。
优选的，所述第一有源层包括多个氧空位；所述第一源极导体区、所述第一漏极导体区的氧空位浓度，均大于所述第一扩散区、所述第二扩散区的氧空位浓度；所述第一扩散区、所述第二扩散区的氧空位浓度，均大于所述第一沟道区的氧空位浓度。
优选的，所述第一有源层还包括位于所述第一源极导体区远离所述第一沟道区一侧的第三扩散区、及位于所述第一漏极导体区远离所述第一沟道区一侧的第四扩散区；其中，所述第一源极导体区的氧空位浓度大于所述第三扩散区的氧空位浓度，所述第一漏极导体区的氧空位浓度大于所述第四扩散区的氧空位浓度。
优选的，所述第一扩散区的宽度与所述第二扩散区的宽度之和，与所述第一沟道区的宽度的比值小于1：1。
优选的，所述第一栅极绝缘层包括与所述第一栅极对应的第一单元、及位于所述第一单元***的第二单元，所述第一单元与所述第二单元连接设置；其中，所述第二单元的厚度小于所述第一单元的厚度。
优选的，所述驱动电路层还包括与所述第一栅极对应的第二栅极，所述第二栅极位于所述第一有源层远离所述第一栅极一侧；所述驱动电路层还包括：第二有源层、第三栅极、位于所述第二有源层与所述第三栅极之间的第四栅极、及第二源极和第二漏极；其中，所述第三栅极与所述第二栅极同层设置，所述第一源极、所述第一漏极、所述第二源极和所述第二漏极同层设置。
本申请实施例还提供了一种显示面板的制作方法，包括：
在衬底上形成第一有源层；
在所述第一有源层上依次形成第一绝缘膜层及第一栅极膜层；
在所述第一绝缘膜层及所述第一栅极膜层上形成光阻层；
利用图案化工艺，将所述第一绝缘膜层、所述第一栅极膜层、及所述光阻层形成第一图案，使部分所述第一有源层裸露；
利用等离子体工艺，对裸露的所述第一有源层进行导体化；
利用退光阻工艺，使所述光阻层形成连续设置的第二图案，所述第二图案的面积小于所述第一图案的面积，使部分所述第一栅极膜层裸露；
将裸露的所述第一栅极膜层去除，以形成第一栅极及第一栅极绝缘层。
优选的，所述利用图案化工艺，将所述第一绝缘膜层、所述第一栅极膜层、及所述光阻层形成第一图案，使部分所述第一有源层裸露的步骤包括：利用图案化工艺，将所述第一绝缘膜层、所述第一栅极膜层、及所述光阻层形成第一图案，使所述第一有源层的***裸露。
优选的，所述利用图案化工艺，将所述第一绝缘膜层、所述第一栅极膜层、及所述光阻层形成第一图案，使部分所述第一有源层裸露的步骤包括：利用图案化工艺，将所述第一绝缘膜层、所述第一栅极膜层、及所述光阻层形成第一图案，所述第一图案包括多个开口；其中，所述开口周围设置有所述光阻层。
优选的，所述显示面板的制作方法还包括：在所述第一有源层、所述第一栅极绝缘层、及所述第一栅极上形成包括多个第一开孔的第一层间绝缘层，所述第一开孔使所述第一有源层裸露；在所述第一层间绝缘层上形成第一源极和第一漏极。
本申请实施例还提供了一种移动终端，包括显示面板及终端主体，所述终端主体与所述显示面板组合为一体；
所述显示面板，包括：
衬底；
驱动电路层，设置在所述衬底的一侧，所述驱动电路层包括：第一有源层、设置在所述第一有源层远离所述衬底一侧的第一栅极绝缘层、设置在所述第一栅极绝缘层远离所述衬底一侧的第一栅极、设置在所述第一栅极远离所述衬底一侧的第一层间绝缘层、以及设置在所述第一层间绝缘层远离所述衬底一侧的源漏极层，所述源漏极层包括第一源极和第一漏极；
其中，所述第一栅极绝缘层在所述衬底上的正投影位于所述第一有源层在所述衬底上的正投影范围内，所述第一栅极在所述衬底上的正投影位于所述第一栅极绝缘层在所述衬底上的正投影范围内。
优选的，所述第一有源层包括：第一源极导体区、第一沟道区、第一漏极导体区、位于所述第一源极导体区和所述第一沟道区之间的第一扩散区、以及位于所述第一漏极导体区和所述第一沟道区之间的第二扩散区，所述第一源极与所述第一源极导体区电连接，所述第一漏极与所述第一漏极导体区电连接；所述第一层间绝缘层至少覆盖所述第一沟道区、所述第一扩散区、所述第二扩散区。
优选的，在所述显示面板的俯视图方向上，所述第一栅极绝缘层与所述第一沟道区、所述第一扩散区、及所述第二扩散区完全重叠设置，所述第一栅极与所述第一沟道区重叠设置。
优选的，所述第一有源层包括多个氧空位；所述第一源极导体区、所述第一漏极导体区的氧空位浓度，均大于所述第一扩散区、所述第二扩散区的氧空位浓度；所述第一扩散区、所述第二扩散区的氧空位浓度，均大于所述第一沟道区的氧空位浓度。
优选的，所述第一有源层还包括位于所述第一源极导体区远离所述第一沟道区一侧的第三扩散区、及位于所述第一漏极导体区远离所述第一沟道区一侧的第四扩散区；其中，所述第一源极导体区的氧空位浓度大于所述第三扩散区的氧空位浓度，所述第一漏极导体区的氧空位浓度大于所述第四扩散区的氧空位浓度。
优选的，所述第一扩散区的宽度与所述第二扩散区的宽度之和，与所述第一沟道区的宽度的比值小于1：1。
优选的，所述第一栅极绝缘层包括与所述第一栅极对应的第一单元、及位于所述第一单元***的第二单元，所述第一单元与所述第二单元连接设置；其中，所述第二单元的厚度小于所述第一单元的厚度。
优选的，所述驱动电路层还包括与所述第一栅极对应的第二栅极，所述第二栅极位于所述第一有源层远离所述第一栅极一侧；所述驱动电路层还包括：第二有源层、第三栅极、位于所述第二有源层与所述第三栅极之间的第四栅极、及第二源极和第二漏极；其中，所述第三栅极与所述第二栅极同层设置，所述第一源极、所述第一漏极、所述第二源极和所述第二漏极同层设置。
 有益效果
本发明通过使第一栅极的尺寸小于第一栅绝缘层的尺寸，第一栅绝缘层的尺寸小于第一有源层的尺寸，以及在利用第一栅极及第一栅绝缘层对第一有源层进行自对准导体化时，预留等离子气体的扩散区域的距离，有效防止沟道区缩短，保证有效沟道区长度，防止阈值电压漂移，提高了显示面板的质量。
 附图说明
图1是本发明实施例提供的显示面板的第一种结构的结构示意图；
图2是本发明实施例提供的显示面板的第二种结构的结构示意图；
图3是图1或图2的俯视示意图；
图4是本发明实施例提供的显示面板的第三种结构的结构示意图；
图5是本发明实施例提供的显示面板的第四种结构的结构示意图；
图6是本发明实施例提供的显示面板的第五种结构的结构示意图；
图7是本发明实施例提供的显示面板的制作方法的第一种步骤流程图；
图8是本发明实施例提供的显示面板的制作方法的第二种步骤流程图；
图9A至图9F是本发明实施例提供的显示面板的制作方法的第一种流程示意图；
图10是本发明实施例提供的显示面板的制作方法的第二种流程示意图；
图11A、图11B是本发明实施例提供的显示面板的制作方法的第三种流程示意图；
图12是本发明实施例提供的移动终端的结构示意图。
 本发明的实施方式
本申请提供一种显示面板及其制作方法、移动终端，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请实施例提供一种显示面板及其制作方法、移动终端。以下分别进行详细说明。需说明的是，以下实施例的描述顺序不作为对实施例优选顺序的限定。
请参阅图1至图6，本发明实施例提供一种显示面板100，包括：
衬底200；
驱动电路层，设置在所述衬底200的一侧，所述驱动电路层包括：第一有源层310、设置在所述第一有源层310远离所述衬底200一侧的第一栅极绝缘层320、设置在所述第一栅极绝缘层320远离所述衬底200一侧的第一栅极330、设置在所述第一栅极330远离所述衬底200一侧的第一层间绝缘层360、以及设置在所述第一层间绝缘层360远离所述衬底200一侧的源漏极层，所述源漏极层包括第一源极341和第一漏极342；
其中，所述第一栅极绝缘层320在所述衬底200上的正投影位于所述第一有源层310在所述衬底200上的正投影范围内，所述第一栅极330在所述衬底200上的正投影位于所述第一栅极绝缘层320在所述衬底200上的正投影范围内。
本发明通过使第一栅极的尺寸小于第一栅绝缘层的尺寸，第一栅绝缘层的尺寸小于第一有源层的尺寸，以及在利用第一栅极及第一栅绝缘层对第一有源层进行自对准导体化时，预留等离子气体的扩散区域的距离，有效防止沟道区缩短，保证有效沟道区长度，防止阈值电压漂移，提高了显示面板的质量。
现结合具体实施例对本发明的技术方案进行描述。
本实施例中，请参阅图1，所述显示面板100，包括：衬底200；驱动电路层，设置在所述衬底200的一侧，所述驱动电路层包括：第一有源层310、设置在所述第一有源层310远离所述衬底200一侧的第一栅极绝缘层320、设置在所述第一栅极绝缘层320远离所述衬底200一侧的第一栅极330、设置在所述第一栅极330远离所述衬底200一侧的第一层间绝缘层360、以及设置在所述第一层间绝缘层360远离所述衬底200一侧的源漏极层，所述源漏极层包括第一源极341和第一漏极342。
所述第一栅极绝缘层320在所述衬底200上的正投影位于所述第一有源层310在所述衬底200上的正投影范围内，所述第一栅极330在所述衬底200上的正投影位于所述第一栅极绝缘层320在所述衬底200上的正投影范围内。
在利用第一栅极330及第一栅极绝缘层320对第一有源层310进行自对准导体化时，所述第一栅极绝缘层320在所述衬底200上的正投影位于所述第一有源层310在所述衬底200上的正投影范围内，可以预留等离子气体作用的扩散区域的距离，有效防止沟道缩短，所述第一栅极330在所述衬底200上的正投影位于所述第一栅极绝缘层320在所述衬底200上的正投影范围内，可以保证有效沟道长度，防止阈值电压漂移，提高了显示面板100的质量。
在一些实施例中，请参阅图1，所述第一有源层包括：第一源极导体区312、第一沟道区311、第一漏极导体区313、位于所述第一源极导体区312和所述第一沟道区311之间的第一扩散区314、以及位于所述第一漏极导体区313和所述第一沟道区311之间的第二扩散区315，所述第一源极341与所述第一源极导体区312电连接，所述第一漏极342与所述第一漏极导体区313电连接；所述第一层间绝缘层360至少覆盖所述第一沟道区311、所述第一扩散区314、所述第二扩散区315。
所述第一沟道区311对应半导体的沟道区；所述第一源极导体区312、所述第一漏极导体区313对应源漏极区，对应导体化后的区域，导电性强；所述第一扩散区314、所述第二扩散区315对应等离子气体作用的扩散区，电阻介于所述第一沟道区311与导体化后的区域之间，预留等离子气体作用的扩散区域的距离，有效防止沟道缩短，可以保证有效沟道长度，防止阈值电压漂移，提高了显示面板100的质量。
在一些实施例中，在所述显示面板100的俯视图方向上，所述第一栅极绝缘层320与所述第一沟道区311、所述第一扩散区314、及所述第二扩散区315完全重叠设置，所述第一栅极330与所述第一沟道区311重叠设置。
所述第一栅极绝缘层320的一部分有保护扩散区的作用，将对应沟道区的所述第一沟道区311的尺寸与第一栅极330对应，保证有效沟道长度，防止阈值电压漂移，提高显示面板100的质量。
在一些实施例中，请参阅图1，所述显示面板还包括位于所述第一有源层310、所述第一栅极绝缘层320、及所述第一栅极330上形成包括多个第一开孔361的第一层间绝缘层360，所述第一开孔361使所述第一有源层310裸露。
在一些实施例中，请参阅图1，为方便描述，位于所述第一有源层310与所述第一源漏极单元340之间的绝缘材料为第一层间绝缘层360，所述第一层间绝缘层360的材料为绝缘材料。
在一些实施例中，请参阅图2、图3，所述第一栅极绝缘层320包括与所述第一栅极330对应的第一单元321、及位于所述第一单元321***的第二单元322，所述第一单元321与所述第二单元322连接设置；其中，所述第二单元322的厚度小于所述第一单元321的厚度。
在利用第一栅极330及第一栅极绝缘层320对第一有源层310进行自对准导体化后，预留等离子气体的扩散区域的距离，在所述第一有源层310的载流子迁移方向上，再将所述第一栅极330进行与等离子气体扩散距离对应的刻蚀后，也会对于未被第一栅极330覆盖的所述第一栅极绝缘层320有减薄效果，故，采用本发明中的方法进行制作的显示面板100中，所述第二单元322的厚度会小于所述第一单元321的厚度，可利用此结构作为防伪标识。
在一些实施例中，所述第二单元322的宽度与所述第一扩散区314、及所述第二扩散区315的宽度相比，可以相等，也可以不等。
在一些实施例中，所述第一扩散区314的宽度与所述第二扩散区315的宽度之和，与所述第一沟道区311的宽度的比值小于1：1。
请参阅图2、图3，根据不同的等离子气体工艺参数，或根据不同沟道区的长度设定，扩散区的总长度不应超过扩散区与沟道区总和的一半，即所述第一扩散区314的宽度与所述第二扩散区315的宽度之和，与所述第一沟道区311的宽度的比值小于1：1，其中，所述第一沟道区311的宽度用L表示，所述第一扩散区314的宽度与所述第二扩散区315的宽度分别用△L1、△L2表示，扩散区的总长度为△L1+△L2。既可以保证有效沟道长度，防止阈值电压漂移，又可以提高第一薄膜晶体管的开态电流，提高一薄膜晶体管的工作效率。
在一些实施例中，所述第一有源层310包括多个氧空位；所述第一源极导体区312、所述第一漏极导体区313的氧空位浓度，均大于所述第一扩散区314、所述第二扩散区315的氧空位浓度；所述第一扩散区314、所述第二扩散区315的氧空位浓度，均大于所述第一沟道区311的氧空位浓度。
对于利用等离子气体进行轰击降阻的工艺，例如可以是He、Ar、CF4等，CF4可以在最终的产品中测得F含量或氧空位含量，而对于He、Ar，将氧键轰击断裂，形成氧空位，只能检测氧空位含量，故可以氧空位浓度作为不同区的区分，所述第一沟道区311对应半导体的沟道区，氧空位浓度最小；所述第一源极导体区312、所述第一漏极导体区313对应源漏极区，对应导体化后的区域，导电性强，氧空位浓度最大；所述第一扩散区314、所述第二扩散区315对应等离子气体作用的扩散区，电阻介于所述第一沟道区311与导体化后的区域之间，氧空位浓度介于二者之间，保证有效沟道长度，防止阈值电压漂移，提高显示面板100的质量。
在一些实施例中，请参阅图4，所述第一有源层310还包括位于所述第一源极导体区312远离所述第一沟道区311一侧的第三扩散区316、及位于所述第一漏极导体区313远离所述第一沟道区311一侧的第四扩散区317；其中，所述第一源极导体区312的氧空位浓度大于所述第三扩散区316的氧空位浓度，所述第一漏极导体区313的氧空位浓度大于所述第四扩散区317的氧空位浓度。
在利用第一栅极330及第一栅极绝缘层320对第一有源层310进行自对准导体化时，在制作流程图中可见，利用等离子气体处理源漏极区，降低其电阻从而使其导体化时，利用开口362对源漏极区进行两侧扩散，可以进一步缩短控制扩散区的宽度，保证有效沟道长度，防止阈值电压漂移，提高显示面板100的质量。
在一些实施例中，所述第一扩散区314的氧空位浓度等于所述第三扩散区316的氧空位浓度，所述第二扩散区315的氧空位浓度等于所述第四扩散区317的氧空位浓度。以所述第三扩散区316为例，即在等离子气体作用扩散时，对于所述第三扩散区316中的等离子扩散没有到所述第一有源层310的边缘或正好扩散至所述第一有源层310的边缘。
在一些实施例中，所述第一扩散区314的氧空位浓度小于所述第三扩散区316的氧空位浓度，所述第二扩散区315的氧空位浓度小于所述第四扩散区317的氧空位浓度。以所述第三扩散区316为例，在等离子气体扩散时，对于第三扩散区316中的等离子扩至所述第一有源层310的边缘后产生了堆积。
在一些实施例中，所述第三扩散区316的氧空位浓度等于所述第一源极导体区312的氧空位浓度，所述第四扩散区317的氧空位浓度等于所述第一漏极导体区313的氧空位浓度。等离子气体扩散，使所述第三扩散区316、所述第四扩散区317处于饱和状态，与所述第一源极导体区312、所述第一漏极导体区313的状态相同。
在一些实施例中，请参阅图5，所述驱动电路层还包括与所述第一栅极330对应的第二栅极350，所述第二栅极350位于所述第一有源层310远离所述第一栅极330一侧；所述驱动电路层还包括：第二有源层410、第三栅极420、位于所述第二有源层410与所述第三栅极420之间的第四栅极430、及第二源极441和第二漏极442；其中，所述第三栅极420与所述第二栅极350同层设置，所述第一源极341、所述第一漏极342、所述第二源极441和所述第二漏极442同层设置。
所述第一栅极330、所述第二栅极350、所述第一有源层310构成所述第一薄膜晶体管，所述第三栅极420、所述第四栅极430、所述第二有源层410构成所述第二薄膜晶体管。所述第一栅极330与第二栅极350所述为上下双栅设计，所述第一栅极330为顶删，所述第二栅极350为底栅，两者一起控制所述第一薄膜晶体管的开关。所述第二薄膜晶体管中，所述第四栅极430作为栅极开关信号，所述第四栅极430与所述第三栅极420形成电容可以控制栅端电位。
在一些实施例中，所述第一有源层310包括金属氧化物，所述第二有源层410包括低温多晶硅。将低温多晶硅（LTPS）薄膜晶体管和金属氧化物（Metal Oxide）薄膜晶体管集成在同一显示面板100上，可以结合低温多晶硅薄膜晶体管的高迁移率、对像素电容的充电速度快的优点，和金属氧化物薄膜晶体管漏电低的优势。
在一些实施例中，所述显示面板100还包括填充于不同类别元器件之间的绝缘材料，绝缘材料可以为有机绝缘材料，也可以为无机绝缘材料，有机绝缘材料可以为聚酰亚胺，无机绝缘材料可以为硅氧化合物、氮硅化合物或硅氧氮化合物中的任一种，在此只做举例，具体可以根据实际工艺或实际情况而定，不做具体限定。
在一些实施例中，所述第一栅极绝缘层320及所有的绝缘膜层的材料可以为有机绝缘材料，也可以为无机绝缘材料。有机绝缘材料可以为聚酰亚胺，无机绝缘材料可以为硅氧化合物、氮硅化合物或硅氧氮化合物中的任一种，在此只做举例，具体可以根据实际工艺或实际情况而定，不做具体限定。
在一些实施例中，所述显示面板100可以为液晶显示面板或有机发光显示面板，以下以所述显示面板100为有机发光显示面板为例进行描述。
在一些实施例中，请参阅图6，所述显示面板100还包括位于所述第一源漏极单元340及所述第二源漏极单元440上的平坦层500，所述平坦层500包括多个第二开孔510。
在一些实施例中，请参阅图6，所述显示面板100还包括位于所述平坦层500上的阳极层610、位于所述阳极层610上包括多个第三开孔的像素定义层620、位于所述第三开孔内的发光材料层630、位于所述发光材料层630上的阴极层640、及位于所述像素定义层620上的隔垫物650。所述阳极层610通过所述第二开孔510与所述第二源漏极单元440电连接。
在一些实施例中，所述显示面板100还包括位于所述阴极层640上的封装层及盖板。
本发明通过使第一栅极的尺寸小于第一栅绝缘层的尺寸，第一栅绝缘层的尺寸小于第一有源层的尺寸，以及在利用第一栅极及第一栅绝缘层对第一有源层进行自对准导体化时，预留等离子气体的扩散区域的距离，有效防止沟道区缩短，保证有效沟道区长度，防止阈值电压漂移，提高了显示面板的质量。
请参阅图7，本发明实施例还提供了一种显示面板100的制作方法，包括：
S100、在衬底200上形成多个第一有源层310；
S200、在所述第一有源层310上依次形成第一绝缘膜层301及第一栅极膜层302；
S300、在所述第一绝缘膜层301及所述第一栅极膜层302上形成光阻层303；
S400、利用图案化工艺，将所述第一绝缘膜层301、所述第一栅极膜层302、及所述光阻层303形成第一图案，使部分所述第一有源层310裸露；
S500、利用等离子体工艺，对裸露的所述第一有源层310进行导体化；
S600、利用退光阻工艺，使所述光阻层303形成连续设置的第二图案，所述第二图案的面积小于所述第一图案的面积，使部分所述第一栅极膜层302裸露；
S700、将裸露的所述第一栅极膜层302去除，以形成第一栅极330及第一栅极绝缘层320。
本发明通过使第一栅极的尺寸小于第一栅绝缘层的尺寸，第一栅绝缘层的尺寸小于第一有源层的尺寸，以及在利用第一栅极及第一栅绝缘层对第一有源层进行自对准导体化时，预留等离子气体的扩散区域的距离，有效防止沟道区缩短，保证有效沟道区长度，防止阈值电压漂移，提高了显示面板的质量。
现结合具体实施例对本发明的技术方案进行描述。
S100、在衬底200上形成多个第一有源层310，请参阅图9A。
在一些实施例中，步骤S100包括：
S110、在所述衬底200上形成多个第二栅极350。
S120、在所述第二栅极350上形成绝缘材料。
S130、在绝缘材料上形成多个第一有源层310。
在一些实施例中，所述显示面板100在不同类别元器件之间填充有绝缘材料，绝缘材料可以为有机绝缘材料，也可以为无机绝缘材料，有机绝缘材料可以为聚酰亚胺，无机绝缘材料可以为硅氧化合物、氮硅化合物或硅氧氮化合物中的任一种，在此只做举例，具体可以根据实际工艺或实际情况而定，不做具体限定，绝缘材料的材料成分不是本发明的重点，故不做精确区分。
S200、在所述第一有源层310上依次形成第一绝缘膜层301及第一栅极膜层302，请参阅图9B。
在一些实施例中，对于步骤S200，将所述第一绝缘膜层301及所述第一栅极膜层302在后续统一图案化，再进行对准导体化，可以节省光罩，降低生产成本，提高生产效率。
S300、在所述第一绝缘膜层301及所述第一栅极膜层302上形成光阻层303，请参阅图9C。
在一些实施例中，所述光阻层303的材料为光阻材料，材料成分不是本发明的重点，不做具体限定。
S400、利用图案化工艺，将所述第一绝缘膜层301、所述第一栅极膜层302、及所述光阻层303形成第一图案，使部分所述第一有源层310裸露，请参阅图9D。
在一些实施例中，步骤S400使部分所述第一有源层310裸露，裸露的区域可以进行等离子气体轰击进行导体化。
在一些实施例中，请参阅图9D，步骤S400可以包括：
S410a、利用图案化工艺，将所述第一绝缘膜层301、所述第一栅极膜层302、及所述光阻层303形成第一图案，使所述第一有源层310的***裸露。
在一些实施例中，请参阅图11A，步骤S400可以包括：
S410b、利用图案化工艺，将所述第一绝缘膜层301、所述第一栅极膜层302、及所述光阻层303形成第一图案，所述第一图案包括多个开口362。
在一些实施例中，所述开口362周围设置有所述光阻层303。
S500、利用等离子体工艺，对裸露的所述第一有源层310进行导体化。
利用步骤S410a的步骤S500，请参阅图9E；利用步骤S410b的步骤S500，请参阅图11B。在图中，虚线箭头表示等离子体工艺，对于利用等离子气体进行轰击降阻的工艺，例如可以是He、Ar、CF4等，CF4可以在最终的产品中测得F含量或氧空穴含量，而对于He、Ar，不易检测含量，故可以氧空位浓度作为不同区的区分。
S600、利用退光阻工艺，使所述光阻层303形成连续设置的第二图案，所述第二图案的面积小于所述第一图案的面积，使部分所述第一栅极膜层302裸露，请参阅图9F。
在一些实施例中，步骤S600使所述第一栅极膜层302的***裸露，将光阻层303缩小，从而可以进行下一步对所述第一栅极膜层302的缩小，形成与所述第一有源层310对应的所述第一栅极330。
在一些实施例中，所述第二图案的光阻层303对应所述第一有源层310的中心位置，对于步骤S410b中的所述开口362周围的所述光阻层303去除，从而使所述第一有源层310的***区域均裸露，在步骤S800中，对于所述第一开孔361的尺寸可以缩小，避免因所述第一开孔361尺寸过大，避免导致使所述第一源漏极单元340塌陷或连接异常。
S700、将裸露的所述第一栅极膜层302去除，以形成第一栅极330及第一栅极绝缘层320。
为避免重复作图，步骤S700请参阅图1或图2，将不被所述光阻层303覆盖的所述第一栅极膜层302去除，从而形成与所述第一有源层310对应的所述第一栅极330。
在步骤S500的导体化步骤中，请参阅图1、图2，所述第一有源层包括：第一源极导体区312、第一沟道区311、第一漏极导体区313、位于所述第一源极导体区312和所述第一沟道区311之间的第一扩散区314、以及位于所述第一漏极导体区313和所述第一沟道区311之间的第二扩散区315，所述第一源极341与所述第一源极导体区312电连接，所述第一漏极342与所述第一漏极导体区313电连接；所述第一层间绝缘层360至少覆盖所述第一沟道区311、所述第一扩散区314、所述第二扩散区315。
所述第一沟道区311对应半导体的沟道区；所述第一源极导体区312、所述第一漏极导体区313对应源漏极区，对应导体化后的区域，导电性强；所述第一扩散区314、所述第二扩散区315对应等离子气体作用的扩散区，电阻介于所述第一沟道区311与导体化后的区域之间，预留等离子气体作用的扩散区域的距离，有效防止沟道缩短，可以保证有效沟道长度，防止阈值电压漂移，提高了显示面板100的质量。
在一些实施例中，请参阅图2、图3，所述第一栅极绝缘层320包括与所述第一栅极330对应的第一单元321、及位于所述第一单元321***的第二单元322，所述第一单元321与所述第二单元322连接设置；其中，所述第二单元322的厚度小于所述第一单元321的厚度。
在利用第一栅极330及第一栅极绝缘层320对第一有源层310进行自对准导体化后，预留等离子气体的扩散区域的距离，在所述第一有源层310的载流子迁移方向上，再将所述第一栅极330进行与等离子气体扩散距离对应的刻蚀后，也会对于未被第一栅极330覆盖的所述第一栅极绝缘层320有减薄效果，故，采用本发明中的方法进行制作的显示面板100中，所述第二单元322的厚度会小于所述第一单元321的厚度，可利用此结构作为防伪标识。
在一些实施例中，请参阅图8，所述显示面板100的制作方法还包括：
S800、在所述第一有源层310、所述第一栅极绝缘层320、及所述第一栅极330上形成包括多个第一开孔361的第一层间绝缘层360，所述第一开孔361使所述第一有源层310裸露，请参阅图10或图11A。
在一些实施例中，为方便描述，位于所述第一有源层310与所述第一源漏极单元340之间的绝缘材料为第一层间绝缘层360，所述第一层间绝缘层360的材料为绝缘材料。
S900、在所述第一层间绝缘层360上形成第一源极341和第一漏极342。
为避免重复作图，步骤S900请参阅图1，在一些实施例中，第一源极341和第一漏极342通过所述第一开孔361与所述第一有源层310电连接。
在一些实施例中，请参阅图5，所述驱动电路层还包括与所述第一栅极330对应的第二栅极350，所述第二栅极350位于所述第一有源层310远离所述第一栅极330一侧；所述驱动电路层还包括：第二有源层410、第三栅极420、位于所述第二有源层410与所述第三栅极420之间的第四栅极430、及第二源极441和第二漏极442；其中，所述第三栅极420与所述第二栅极350同层设置，所述第一源极341、所述第一漏极342、所述第二源极441和所述第二漏极442同层设置。
本发明通过使第一栅极的尺寸小于第一栅绝缘层的尺寸，第一栅绝缘层的尺寸小于第一有源层的尺寸，以及在利用第一栅极及第一栅绝缘层对第一有源层进行自对准导体化时，预留等离子气体的扩散区域的距离，有效防止沟道区缩短，保证有效沟道区长度，防止阈值电压漂移，提高了显示面板的质量。
请参阅图12，本发明实施例还提供了一种移动终端10，包括如任一上述的显示面板100及终端主体20，所述终端主体20与所述显示面板100组合为一体。
现结合具体实施例对本发明的技术方案进行描述。
所述显示面板100的具体结构请参阅任一上述显示面板100的实施例及图1至图6，在此不再赘述。
本发明实施例公开了一种显示面板及其制作方法、移动终端；该显示面板衬底及驱动电路层，该驱动电路层包括：第一有源层、第一栅极绝缘层、第一栅极、第一层间绝缘层、以及第一源极和第一漏极，该第一栅极绝缘层在该衬底上的正投影位于该第一有源层在该衬底上的正投影范围内，该第一栅极在该衬底上的正投影位于该第一栅极绝缘层在该衬底上的正投影范围内；本发明通过使第一栅极的尺寸小于第一栅绝缘层的尺寸，第一栅绝缘层的尺寸小于第一有源层的尺寸，以及在利用第一栅极及第一栅绝缘层对第一有源层进行自对准导体化时，预留等离子气体的扩散区域的距离，有效防止沟道区缩短，保证有效沟道区长度，防止阈值电压漂移，提高了显示面板的质量。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种显示面板，其中，包括：
    衬底；
    驱动电路层，设置在所述衬底的一侧，所述驱动电路层包括：第一有源层、设置在所述第一有源层远离所述衬底一侧的第一栅极绝缘层、设置在所述第一栅极绝缘层远离所述衬底一侧的第一栅极、设置在所述第一栅极远离所述衬底一侧的第一层间绝缘层、以及设置在所述第一层间绝缘层远离所述衬底一侧的源漏极层，所述源漏极层包括第一源极和第一漏极；
    其中，所述第一栅极绝缘层在所述衬底上的正投影位于所述第一有源层在所述衬底上的正投影范围内，所述第一栅极在所述衬底上的正投影位于所述第一栅极绝缘层在所述衬底上的正投影范围内。
  2. 根据权利要求1所述的显示面板，其中，所述第一有源层包括：第一源极导体区、第一沟道区、第一漏极导体区、位于所述第一源极导体区和所述第一沟道区之间的第一扩散区、以及位于所述第一漏极导体区和所述第一沟道区之间的第二扩散区，所述第一源极与所述第一源极导体区电连接，所述第一漏极与所述第一漏极导体区电连接；
    所述第一层间绝缘层至少覆盖所述第一沟道区、所述第一扩散区、所述第二扩散区。
  3. 根据权利要求2所述的显示面板，其中，在所述显示面板的俯视图方向上，所述第一栅极绝缘层与所述第一沟道区、所述第一扩散区、及所述第二扩散区完全重叠设置，所述第一栅极与所述第一沟道区重叠设置。
  4. 根据权利要求2所述的显示面板，其中，所述第一有源层包括多个氧空位；
    所述第一源极导体区、所述第一漏极导体区的氧空位浓度，均大于所述第一扩散区、所述第二扩散区的氧空位浓度；
    所述第一扩散区、所述第二扩散区的氧空位浓度，均大于所述第一沟道区的氧空位浓度。
  5. 根据权利要求4所述的显示面板，其中，所述第一有源层还包括位于所述第一源极导体区远离所述第一沟道区一侧的第三扩散区、及位于所述第一漏极导体区远离所述第一沟道区一侧的第四扩散区；
    其中，所述第一源极导体区的氧空位浓度大于所述第三扩散区的氧空位浓度，所述第一漏极导体区的氧空位浓度大于所述第四扩散区的氧空位浓度。
  6. 根据权利要求2所述的显示面板，其中，所述第一扩散区的宽度与所述第二扩散区的宽度之和，与所述第一沟道区的宽度的比值小于1：1。
  7. 根据权利要求1所述的显示面板，其中，所述第一栅极绝缘层包括与所述第一栅极对应的第一单元、及位于所述第一单元***的第二单元，所述第一单元与所述第二单元连接设置；
    其中，所述第二单元的厚度小于所述第一单元的厚度。
  8. 根据权利要求1所述的显示面板，其中，所述驱动电路层还包括与所述第一栅极对应的第二栅极，所述第二栅极位于所述第一有源层远离所述第一栅极一侧；
    所述驱动电路层还包括：第二有源层、第三栅极、位于所述第二有源层与所述第三栅极之间的第四栅极、及第二源极和第二漏极；
    其中，所述第三栅极与所述第二栅极同层设置，所述第一源极、所述第一漏极、所述第二源极和所述第二漏极同层设置。
  9. 一种显示面板的制作方法，其中，包括：
    在衬底上形成第一有源层；
    在所述第一有源层上依次形成第一绝缘膜层及第一栅极膜层；
    在所述第一绝缘膜层及所述第一栅极膜层上形成光阻层；
    利用图案化工艺，将所述第一绝缘膜层、所述第一栅极膜层、及所述光阻层形成第一图案，使部分所述第一有源层裸露；
    利用等离子体工艺，对裸露的所述第一有源层进行导体化；
    利用退光阻工艺，使所述光阻层形成连续设置的第二图案，所述第二图案的面积小于所述第一图案的面积，使部分所述第一栅极膜层裸露；
    将裸露的所述第一栅极膜层去除，以形成第一栅极及第一栅极绝缘层。
  10. 根据权利要求9所述的显示面板的制作方法，其中，所述利用图案化工艺，将所述第一绝缘膜层、所述第一栅极膜层、及所述光阻层形成第一图案，使部分所述第一有源层裸露的步骤包括：
    利用图案化工艺，将所述第一绝缘膜层、所述第一栅极膜层、及所述光阻层形成第一图案，使所述第一有源层的***裸露。
  11. 根据权利要求9所述的显示面板的制作方法，其中，所述利用图案化工艺，将所述第一绝缘膜层、所述第一栅极膜层、及所述光阻层形成第一图案，使部分所述第一有源层裸露的步骤包括：
    利用图案化工艺，将所述第一绝缘膜层、所述第一栅极膜层、及所述光阻层形成第一图案，所述第一图案包括多个开口；
    其中，所述开口周围设置有所述光阻层。
  12. 根据权利要求9所述的显示面板的制作方法，其中，所述显示面板的制作方法还包括：
    在所述第一有源层、所述第一栅极绝缘层、及所述第一栅极上形成包括多个第一开孔的第一层间绝缘层，所述第一开孔使所述第一有源层裸露；
    在所述第一层间绝缘层上形成第一源极和第一漏极。
  13. 一种移动终端，其中，包括显示面板及终端主体，所述终端主体与所述显示面板组合为一体；
    所述显示面板，包括：
    衬底；
    驱动电路层，设置在所述衬底的一侧，所述驱动电路层包括：第一有源层、设置在所述第一有源层远离所述衬底一侧的第一栅极绝缘层、设置在所述第一栅极绝缘层远离所述衬底一侧的第一栅极、设置在所述第一栅极远离所述衬底一侧的第一层间绝缘层、以及设置在所述第一层间绝缘层远离所述衬底一侧的源漏极层，所述源漏极层包括第一源极和第一漏极；
    其中，所述第一栅极绝缘层在所述衬底上的正投影位于所述第一有源层在所述衬底上的正投影范围内，所述第一栅极在所述衬底上的正投影位于所述第一栅极绝缘层在所述衬底上的正投影范围内。
  14. 根据权利要求13所述的移动终端，其中，所述第一有源层包括：第一源极导体区、第一沟道区、第一漏极导体区、位于所述第一源极导体区和所述第一沟道区之间的第一扩散区、以及位于所述第一漏极导体区和所述第一沟道区之间的第二扩散区，所述第一源极与所述第一源极导体区电连接，所述第一漏极与所述第一漏极导体区电连接；
    所述第一层间绝缘层至少覆盖所述第一沟道区、所述第一扩散区、所述第二扩散区。
  15. 根据权利要求14所述的移动终端，其中，在所述显示面板的俯视图方向上，所述第一栅极绝缘层与所述第一沟道区、所述第一扩散区、及所述第二扩散区完全重叠设置，所述第一栅极与所述第一沟道区重叠设置。
  16. 根据权利要求14所述的移动终端，其中，所述第一有源层包括多个氧空位；
    所述第一源极导体区、所述第一漏极导体区的氧空位浓度，均大于所述第一扩散区、所述第二扩散区的氧空位浓度；
    所述第一扩散区、所述第二扩散区的氧空位浓度，均大于所述第一沟道区的氧空位浓度。
  17. 根据权利要求16所述的移动终端，其中，所述第一有源层还包括位于所述第一源极导体区远离所述第一沟道区一侧的第三扩散区、及位于所述第一漏极导体区远离所述第一沟道区一侧的第四扩散区；
    其中，所述第一源极导体区的氧空位浓度大于所述第三扩散区的氧空位浓度，所述第一漏极导体区的氧空位浓度大于所述第四扩散区的氧空位浓度。
  18. 根据权利要求14所述的移动终端，其中，所述第一扩散区的宽度与所述第二扩散区的宽度之和，与所述第一沟道区的宽度的比值小于1：1。
  19. 根据权利要求14所述的移动终端，其中，所述第一栅极绝缘层包括与所述第一栅极对应的第一单元、及位于所述第一单元***的第二单元，所述第一单元与所述第二单元连接设置；
    其中，所述第二单元的厚度小于所述第一单元的厚度。
  20. 根据权利要求14所述的移动终端，其中，所述驱动电路层还包括与所述第一栅极对应的第二栅极，所述第二栅极位于所述第一有源层远离所述第一栅极一侧；
    所述驱动电路层还包括：第二有源层、第三栅极、位于所述第二有源层与所述第三栅极之间的第四栅极、及第二源极和第二漏极；
    其中，所述第三栅极与所述第二栅极同层设置，所述第一源极、所述第一漏极、所述第二源极和所述第二漏极同层设置。
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