WO2023077557A1 - 显示装置 - Google Patents

显示装置 Download PDF

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Publication number
WO2023077557A1
WO2023077557A1 PCT/CN2021/130787 CN2021130787W WO2023077557A1 WO 2023077557 A1 WO2023077557 A1 WO 2023077557A1 CN 2021130787 W CN2021130787 W CN 2021130787W WO 2023077557 A1 WO2023077557 A1 WO 2023077557A1
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WO
WIPO (PCT)
Prior art keywords
clock signal
signal line
circuit board
display device
grounding
Prior art date
Application number
PCT/CN2021/130787
Other languages
English (en)
French (fr)
Inventor
姚晓慧
傅华
徐志达
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/618,514 priority Critical patent/US20240038131A1/en
Publication of WO2023077557A1 publication Critical patent/WO2023077557A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects

Definitions

  • the present application relates to the field of display technology, and in particular to a display device.
  • TFT-LCD thin film transistor liquid crystal display
  • the existing ultra-high resolution display devices are prone to various display defects, such as black and white horizontal lines, image crosstalk, image sticking, and the like. These bad defects seriously affect the display quality of the display device and the viewing experience of customers.
  • the black and white horizontal lines are generated due to the large in-plane load of the ultra-high resolution display device.
  • the in-plane load also increases.
  • clock signal lines designed to be driven row-by-row within a plane of a display device such as a display plane of a display panel
  • the display device controls a plurality of pixels located in the plane to emit light to present a desired picture.
  • the difference in load between the clock signal lines will cause the difference in the potential of the pixel after charging, which will lead to the difference in brightness between different pixel rows. Therefore, there are dense black and white horizontal lines in the displayed picture.
  • an improvement solution for the above defects is to adjust the in-plane load difference between the clock signal lines by changing the manufacturing process.
  • this improvement solution cannot completely solve the load difference between the clock signal lines, and may easily lead to problems such as lower product yield, lower production capacity, and lower benefits.
  • the object of the present application is to provide a display device, which can improve the problem that the display device displays unexpected black and white horizontal lines.
  • the present application provides a display device, including: a processor configured to output a driving signal and a voltage; a timing controller connected to the processor and configured to generate a control signal based on the driving signal; a circuit The board is connected with the timing controller and is configured to generate an initial clock signal according to the voltage and the control signal, wherein the clock signal is a signal in which high level and low level appear alternately; the display panel is connected with the A circuit board connection, including a display area and a non-display area; a plurality of clock signal lines configured to transmit the initial clock signal, wherein each of the clock signal lines extends from the circuit board to the non-display area of the display panel display area; a plurality of grounding resistors, arranged on the circuit board, wherein each of the grounding resistors is connected to the corresponding clock signal line, configured to reduce the voltage value of the high level of the initial clock signal, Then obtain an adjusted clock signal; a gate driver, arranged in the non-display area of the display panel,
  • the plurality of clock signal lines are arranged sequentially from the display area of the display panel toward the non-display area, and two of the clock signal lines are correspondingly connected to each other.
  • the values of the grounding resistances are different.
  • the display device includes the M clock signal line, the M-1 clock signal line and the M-2 clock signal line arranged in sequence; and the M clock signal line and the M clock signal line
  • the value of the connected grounding resistor is R(M)
  • the value of the grounding resistor connected to the M-1th clock signal line is R(M-1)
  • the value of the M-2th clock signal line The value of the grounding resistance connected to the clock signal line is R(M-2), where R(M) ⁇ R(M-1) ⁇ R(M-2) or R(M)>R(M-1) > R (M-2).
  • the display device further includes a plurality of matching resistors disposed on the circuit board, and each of the matching resistors is connected to the corresponding clock signal line.
  • each of the clock signal lines includes a first segment and a second segment connected to the first segment, the first segment is set on the circuit board, and the second segment is set on the The non-display area of the display panel, and each of the grounding resistors is connected to the first segment of the corresponding clock signal line.
  • the circuit board includes a first circuit board and a second circuit board;
  • the first section of each clock signal line includes a first subsection and a second subsection, and the first subsection a segment is disposed on the first circuit board, and the second sub-segment is disposed on the second circuit board;
  • the second segment of each clock signal line includes a third sub-segment and a fourth sub-segment, respectively arranged on opposite sides of the display panel;
  • the gate driver includes a first gate driver and a second gate driver, the first gate driver is connected to the third subsection, and the second gate driver The gate driver is connected to the fourth subsection, and the first gate driver and the second gate driver are respectively connected to opposite ends of the gate line;
  • each of the grounding resistors includes a first grounding resistor resistor and a second grounding resistor, the first grounding resistor is set on the first circuit board and connected to the first subsection of the corresponding clock signal line, the second grounding resistor is set on the first circuit board
  • the two circuit boards are
  • the values of the first grounding resistor and the second grounding resistor connected to the same clock signal line are the same.
  • the values of the first grounding resistor and the second grounding resistor connected to the same clock signal line are different.
  • the same clock signal line, the RC circuit of the first ground resistor, the second ground resistor, and the corresponding RC circuit of the gate line form an electronic circuit.
  • the present application also provides a display device, including: a circuit board configured to output a clock signal, wherein the clock signal is a signal in which high levels and low levels appear alternately; a display panel is connected to the circuit board and includes a display area and a non-display area; a plurality of clock signal lines configured to transmit the clock signal, wherein each of the clock signal lines extends from the circuit board to the non-display area of the display panel; a plurality of grounding resistors, It is arranged on the circuit board, wherein each of the grounding resistors is connected to the corresponding clock signal line, configured to reduce the voltage value of the high level of the clock signal; the gate driver is arranged on the display The non-display area of the panel is connected to the clock signal line and is configured to generate a gate signal according to the clock signal that reduces the voltage value of the high level; and a gate line is provided on the display panel The display area is connected to the gate driver and configured to transmit the gate signal.
  • the plurality of clock signal lines are arranged sequentially from the display area of the display panel toward the non-display area, and two of the clock signal lines are correspondingly connected to each other.
  • the values of the grounding resistances are different.
  • the display device includes the M clock signal line, the M-1 clock signal line and the M-2 clock signal line arranged in sequence; and the M clock signal line and the M clock signal line
  • the value of the connected grounding resistor is R(M)
  • the value of the grounding resistor connected to the M-1th clock signal line is R(M-1)
  • the value of the M-2th clock signal line The value of the grounding resistance connected to the clock signal line is R(M-2), where R(M) ⁇ R(M-1) ⁇ R(M-2) or R(M)>R(M-1) > R (M-2).
  • the display device further includes a plurality of matching resistors disposed on the circuit board, and each of the matching resistors is connected to the corresponding clock signal line.
  • each of the clock signal lines includes a first segment and a second segment connected to the first segment, the first segment is set on the circuit board, and the second segment is set on the The non-display area of the display panel, and each of the grounding resistors is connected to the first segment of the corresponding clock signal line.
  • the circuit board includes a first circuit board and a second circuit board;
  • the first section of each clock signal line includes a first subsection and a second subsection, and the first subsection a segment is disposed on the first circuit board, and the second sub-segment is disposed on the second circuit board;
  • the second segment of each clock signal line includes a third sub-segment and a fourth sub-segment, respectively arranged on opposite sides of the display panel;
  • the gate driver includes a first gate driver and a second gate driver, the first gate driver is connected to the third subsection, and the second gate driver The gate driver is connected to the fourth subsection, and the first gate driver and the second gate driver are respectively connected to opposite ends of the gate line;
  • each of the grounding resistors includes a first grounding resistor resistor and a second grounding resistor, the first grounding resistor is set on the first circuit board and connected to the first subsection of the corresponding clock signal line, the second grounding resistor is set on the first circuit board
  • the two circuit boards are
  • the values of the first grounding resistor and the second grounding resistor connected to the same clock signal line are the same.
  • the values of the first grounding resistor and the second grounding resistor connected to the same clock signal line are different.
  • the same clock signal line, the RC circuit of the first ground resistor, the second ground resistor, and the corresponding RC circuit of the gate line form an electronic circuit.
  • this application can optimize the circuit design of the clock signal line and eliminate the load difference of the clock signal line by setting the grounding resistance and matching resistance connected to the clock signal line on the circuit board of the display device, thereby solving the problem of display screen
  • the problem of unexpected black and white horizontal lines appears, which greatly improves the product yield and product quality.
  • FIG. 1 shows a schematic diagram of a display device according to an embodiment of the present application.
  • FIG. 2 shows a partial circuit block diagram of the display device in FIG. 1 .
  • FIG. 3 is a schematic diagram of the wiring area of the non-display area of the display panel of the display device of FIG. 1 .
  • FIG. 4 shows a circuit diagram of a clock signal line according to an embodiment of the present application.
  • FIG. 5 shows a waveform diagram of a clock signal according to an embodiment of the present application.
  • FIG. 1 shows a schematic diagram of a display device 10 according to an embodiment of the application.
  • the display device 10 includes a processor 100, a timing controller 110, a first circuit board 121, a second circuit board 122, a flexible circuit board 130, a display panel 140, a first gate driver 151, a second gate driver 152 and a source driver.
  • the timing controller 110 is connected to the processor 100 .
  • the first circuit board 121 and the second circuit board 122 are connected to the timing controller 110 , and are respectively connected to the display panel 140 through corresponding flexible circuit boards 130 .
  • the display panel 140 includes a display area 141 and a non-display area 142 surrounding the display area 141 .
  • the first gate driver 151 and the second gate driver 152 are respectively disposed on opposite sides of the display panel 140 and disposed in the non-display area 142 between the outer periphery 143 of the display panel 140 and the display area 141 .
  • the source driver may be integrated in the first circuit board 121 and the second circuit board 122 , integrated in the flexible circuit board 130 , or disposed in the non-display area 142 of the display panel 140 , but is not limited thereto.
  • the display area 141 of the display panel 140 includes a plurality of gate lines GL, a plurality of data lines and a plurality of pixels, wherein each gate line GL can drive at least one row of pixels.
  • the first gate driver 151 and the second gate driver 152 are correspondingly connected to the gate line GL, and are respectively connected to opposite ends of the gate line GL.
  • the source driver is connected to the data line.
  • FIG. 2 shows a partial circuit block diagram of the display device in FIG. 1 .
  • the display device 10 further includes a voltage generation unit 101 and a timing generation unit 123 .
  • the voltage generation unit 101 may be disposed in the processor 100
  • the timing generation unit 123 may be disposed in the first circuit board 121 and the second circuit board 122 .
  • the timing generating unit 123 is connected to the voltage generating unit 101 and the timing controller 110 .
  • the timing generation unit 123 is connected to the first gate driver 151 and the second gate driver 152 through a plurality of signal lines, such as a clock signal line CLK, a scan start signal line, a scan sequence control signal line, and the like.
  • the signal lines between the timing generation unit 123 of the first circuit board 121 and the first gate driver 151 include 12 clock signal lines (CLK1 to CLK12), and the timing generation unit of the second circuit board 122
  • the signal lines between 123 and the second gate driver 152 also include 12 clock signal lines (CLK1 to CLK12 ). It should be understood that in other embodiments, other numbers of clock signal lines CLK can be used, but not limited thereto.
  • the processor 100 outputs driving signals such as an image signal, an enable signal, a vertical synchronization signal, a horizontal synchronization signal, and a clock signal.
  • the timing controller 110 receives the aforementioned driving signal from the processor 100 .
  • the timing controller 110 generates data control signals based on the driving signals.
  • the source driver generates a data signal according to the data control signal and outputs it to a corresponding data line.
  • the voltage generation unit 101 provides voltages to the timing generation unit 123 .
  • the timing controller 110 generates control signals based on the driving signals.
  • the timing generation unit 123 generates a gate control signal including a clock signal according to the voltage and the control signal, and controls the corresponding clock signal line CLK to transfer the clock signal to the first gate driver 151 and/or the second gate driver 152 .
  • the first gate driver 151 and the second gate driver 152 generate gate signals according to the gate control signals, and output them to corresponding gate lines.
  • the pixels in the display panel 140 display an image in response to the data signal and the gate signal.
  • the non-display area 142 of the display panel 140 includes a first wiring area 1421 and a second wiring area 1422 .
  • the first wiring region 1421 is located between the first gate driver 151 and the outer periphery 143 of the display panel 140
  • the second wiring region 1422 is located between the second gate driver 152 and the outer periphery 143 of the display panel 140 .
  • each clock signal line CLK extends from the circuit board 121 / 122 to the wiring area 1421 / 1422 of the non-display area 142 of the display panel 140 .
  • the same clock signal line CLK (such as the first clock signal line CLK1 ) includes a first segment disposed on the circuit board 121 / 122 and a second segment disposed on the display panel 140 . Since this embodiment adopts the dual gate driving technique, the same clock signal line CLK extends on opposite sides of the display device 10 .
  • the first section of the clock signal line CLK includes a first subsection 161 located on the first circuit board 121 and a second subsection 162 located on the second circuit board 122 .
  • the second section of the clock signal line CLK includes a third subsection 163 located in the first wiring area 1421 and a fourth subsection 164 located in the second wiring area 1422 .
  • the first subsection 161 and the second subsection 162 receive a clock signal generated based on the same signal from the timing controller 110 , that is, the first subsection 161 and the second subsection 162 are used to transmit the same clock signal.
  • the first subsection 161 is connected with the third subsection 163
  • the second subsection 162 is connected with the fourth subsection 164 .
  • the third subsection 163 is connected with the first gate driver 151
  • the fourth subsection 164 is connected with the second gate driver 152 .
  • the first gate driver 151 and the second gate driver 152 control the same gate line GL based on the same clock signal.
  • the different clock signal lines CLK will have load differences among different clock signal lines CLK due to differences in panel manufacturing process, thereby affecting the clock signal transmitted to the display panel 140 .
  • the process difference of the circuit board 121/122, and the design difference between the display panel 140 and the circuit board 121/122 (such as structural design, wiring layout design, etc.) will also cause the above-mentioned load difference problem.
  • FIG. 3 shows a schematic diagram of the wiring areas 1421 / 1422 of the non-display area 142 of the display panel 140 of the display device of FIG. 1 .
  • the clock signal of each clock signal line CLK is coupled with surrounding signal lines. Due to the influence of wiring design, different clock signals will have different coupling amounts, which in turn will cause different loads between different clock signal lines.
  • the display device of the present application further includes a grounding resistor connected to the clock signal lines, which will be described in detail as follows.
  • the grounding resistor R is disposed on the circuit board 121 / 122 and connected to the first segment of the corresponding clock signal line CLK.
  • FIG. 4 shows a circuit diagram of a clock signal line according to an embodiment of the present application.
  • the ground resistor 1 connected to the same clock signal line CLK includes a first ground resistor RL1 and a second ground resistor RR1 .
  • the first grounding resistor RL1 is disposed on the first circuit board 121 and connected to the first subsection 161 of the clock signal line CLK.
  • the second grounding resistor RR1 is disposed on the second circuit board 122 and connected to the second subsection 162 of the clock signal line CLK.
  • the third subsection 163 of the clock signal line CLK has a first load (including a first load resistor RL2 and a first load capacitor CL2 ) due to process differences and wiring layout effects.
  • the fourth subsection 164 of the clock signal line CLK has a second load (including a second load resistor RR2 and a second load capacitor CR2 ).
  • the gate line GL driven based on the same clock signal also has a third load (including a third load resistor R3 and a third load capacitor C3 ).
  • the same clock signal line CLK forms an electronic circuit with the RC circuits of the first grounding resistor RL1 and the second grounding resistor RR1 and the corresponding RC circuit of the gate line GL.
  • the current of the clock signal line CLK on the display panel is I1
  • the current of the clock signal line CLK on the first circuit board 121 is I2
  • the current of the clock signal line CLK on the second circuit board 122 is I3.
  • the total current I of the clock signal line CLK is I1+I2+I3.
  • FIG. 5 shows a waveform diagram of a clock signal according to an embodiment of the present application.
  • the timing generation unit 123 generates the initial clock signal W1 according to the received voltage and the control signal of the timing controller 110 , and transmits the initial clock signal W1 through a corresponding clock signal line CLK.
  • the initial clock signal W1 is a signal in which high level VGH and low level VGL appear alternately.
  • the grounding resistor R connected to the clock signal line CLK can reduce the high-level voltage value of the clock signal, so as to obtain the adjusted clock signal W2.
  • the total resistance of the circuit can be reduced, and the total current I can be increased, so that the voltage drop of the clock signal on the circuit board increases, thereby reducing the high voltage of the clock signal input to the display panel.
  • Level voltage value In some embodiments, the difference ⁇ V between the high level VGH of the initial clock signal W1 and the adjusted high level VGH' of the clock signal W2 is about 0.375V. According to the feed through effect, when the gate lines of row N are turned on, the gate lines of row N ⁇ 1 are turned off. At this time, the driving voltage of the pixel electrodes in the N-1 row will be reduced due to the influence of the parasitic capacitance, and then the brightness of the pixels in the N-1 row will be dimmed.
  • the driving voltage drop caused by the feedthrough effect can be reduced, thereby improving the brightness of the pixel corresponding to the dark area. Therefore, the problem of black and white horizontal lines caused by the load difference between the clock signal lines CLK is eliminated, thereby improving the picture quality.
  • the grounding resistor R is disposed on the circuit board 121 / 122 instead of the wiring area 1421 / 1422 of the display panel 140 . Therefore, it is possible to prevent the grounding resistor R from occupying the wiring space of the display panel 140 and avoid the grounding resistor R from increasing the load on the display panel 140 .
  • the value of the grounding resistance R is determined according to the wiring position of the clock signal line connected thereto. In this embodiment, considering the differences in wiring positions of different clock signal lines, the value of the grounding resistance R is between 1 and 500 kilo-ohms (K ⁇ ). It should be understood that if the value of the grounding resistance R exceeds this range, it will affect the normal display of the panel, or have little effect on eliminating black and white horizontal lines. If the value of the resistance is too large (for example greater than 500 K ⁇ ), due to the circuit principle, the influence on the clock signal in the display panel is small, and there is no improvement effect of eliminating black and white horizontal lines. On the other hand, if the value of the resistance is too small (for example, less than 1K ⁇ ), the clock signal line in the display panel will be short-circuited due to the circuit principle, thereby affecting the display.
  • K ⁇ kilo-ohms
  • the display device 10 includes a plurality of clock signal lines arranged sequentially from the non-display area 142 toward the display area 141 of the display panel 140 .
  • the display device 10 includes N clock signal lines arranged sequentially from the outer periphery 143 of the display panel 140 toward the display area 141 .
  • the value of the grounding resistor connected to the Nth clock signal line is R(N)
  • the value of the grounding resistor connected to the first clock signal line is R(1), wherein R(N) ⁇ R(1).
  • the display device 10 includes N clock signal lines arranged sequentially from the outer periphery 143 of the display panel 140 toward the display area 141 . Since the wiring difference between adjacent clock signal lines is small, the values of two adjacent grounding resistors R correspondingly connected to two adjacent clock signal lines are designed to be the same.
  • the display device 10 includes adjacent K th clock signal lines and K ⁇ 1 th clock signal lines, where N ⁇ K ⁇ 1.
  • the value of the grounding resistance connected to the Kth clock signal line is R(K)
  • R(K) ⁇ R(N) or R(K) ⁇ R(1) The part of the grounding resistor R adopts the same resistance design, which is beneficial to reduce the manufacturing complexity of the circuit board 121/122 and improve the yield rate and production capacity.
  • the display device 10 includes a plurality of clock signal lines arranged sequentially from the outer periphery 143 of the display panel 140 toward the display area 141 . Since there are different process differences between different clock signal lines, and different clock signals also have different coupling values due to the relationship between stages, the value of the grounding resistance R correspondingly connected to multiple clock signal lines can be designed as All or most of them are different. In response to the different values of the grounding resistance R, these values can be set in an orderly or disorderly manner, wherein the ordered arrangement includes gradual changes. Specifically, the values of the grounding resistors R gradually change from the outer periphery to the direction of the display area, such as increasing or decreasing gradually.
  • the display device 10 includes N clock signal lines arranged in sequence from the outer periphery 143 of the display panel 140 toward the direction of the display area 141, including the M clock signal line, the M ⁇ 1 clock signal line arranged in sequence, The clock signal line and the M-2th clock signal line, and N ⁇ M ⁇ 1.
  • the value of the grounding resistance connected to the Mth clock signal line is R(M)
  • the value of the grounding resistance connected to the M-1th clock signal line is R(M-1
  • the value of the grounding resistance connected to the M-2th clock signal line The value of the grounding resistance connected to the signal line is R(M-2), where R(M) ⁇ R(M-1) ⁇ R(M-2) or R(M)>R(M-1)>R( M-2).
  • the values of the grounding resistors R are arithmetic progressions with a tolerance of 1K ⁇ .
  • the grounding resistors R connected to the first clock signal line CLK1 to the twelfth clock signal line CLK12 are 1K ⁇ , 2K ⁇ , and 3K ⁇ respectively. , 4K ⁇ , 5K ⁇ , 6K ⁇ , 7K ⁇ , 8K ⁇ , 9K ⁇ , 10K ⁇ , 11K ⁇ , 12K ⁇ . All or most of the grounding resistors R are designed with different resistance values, which has a better effect on improving the black and white horizontal lines.
  • the first grounding resistor RL1 and the second grounding resistor RR1 of the grounding resistor R connected to the same clock signal line CLK can be designed to be the same (for example, the value of the above grounding resistor R is equal to the first grounding resistor RL1, and is equal to the second grounding resistance RR1).
  • the first grounding resistor RL1 and the second grounding resistor RR1 connected to the same clock signal line CLK with the same resistance value, it is beneficial to reduce manufacturing complexity and improve yield and productivity.
  • the first grounding resistor R connected to the same clock signal line CLK The first grounding resistor RL1 and the second grounding resistor RR1 can be designed differently. With this design, the load difference of the same clock signal line on different sides of the display device can be effectively improved.
  • the display device 10 further includes a plurality of matching resistors R_PCB disposed on the circuit board 121 / 122 , and each matching resistor R_PCB is connected in series with the corresponding first segment of the clock signal line CLK.
  • the matching resistor R_PCB connected to the same clock signal line CLK includes a first matching resistor RL_PCB and a second matching resistor RR_PCB.
  • the first matching resistor RL_PCB is disposed on the first circuit board 121 and connected to the first subsection 161 of the clock signal line CLK.
  • the second matching resistor RR_PCB is disposed on the second circuit board 122 and connected to the second subsection 162 of the clock signal line CLK.
  • the grounding resistor R is set first, and then the matching resistor R_PCB is set. Specifically, a lighting test is performed on the display device 10 to confirm the picture quality. If horizontal dense lines appear in the screen, all clock signals are measured to determine the load difference between the clock signal lines. Next, through the above-mentioned design scheme of the grounding resistor R, the voltage value corresponding to the high level of the clock signal is reduced. Therefore, the load difference between clock signal lines is eliminated, thereby eliminating black and white horizontal lines and improving display quality. Next, the resistance of the clock signal line CLK on the circuit board 121/122 is referenced to determine the clock signal line CLK that causes the dark line, and series resistance matching is performed on the clock signal line CLK.
  • the problem of black and white horizontal lines can be further solved by setting the matching resistor R_PCB. It can be seen from the above that the setting of the grounding resistor R and the matching resistor R_PCB can effectively reduce the charging difference of the clock signal of different clock signal lines CLK to the pixel row, thereby improving the brightness uniformity of each pixel row and eliminating the problem of black and white horizontal lines and improve picture quality.
  • this application can optimize the circuit design of the clock signal line and eliminate the load difference of the clock signal line by setting the grounding resistance and matching resistance connected to the clock signal line on the circuit board of the display device, and then solve the problem of the display screen.
  • the problem of unexpected black and white horizontal lines greatly improves product yield and product quality.

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Abstract

一种显示装置(10)，包括：电路板(121/122)、显示面板(140)、多条时钟信号线(CLK)和多个接地电阻(R)。每一时钟信号线(CLK)从电路板(121/122)延伸至显示面板(140)的非显示区(142)。多个接地电阻(R)设置在电路板(121/122)上。每一接地电阻(R)与对应的时钟信号线(CLK)连接，配置为降低时钟信号的高电平的电压值。

Description

显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示装置。
 背景技术
随着显示技术日趋成熟，现有薄膜电晶体液晶显示装置（thin film transistor liquid crystal display，TFT-LCD）已能实现窄边框和超高分辨率（如8K），并且朝着大尺寸、高分辨率、高对比等更高性能发展。
然而，现有的超高分辨率的显示装置容易出现多种显示不良缺陷，如黑白水平线、画面串扰、残影等。这些不良缺陷严重影响显示装置的显示质量和客户的观视体验。黑白水平线是由于超高分辨率的显示装置的面内负载较大而产生。并且，随着显示装置的尺寸增加，面内负载也随之增大。具体来说，对于设计在显示装置的面内（如显示面板的显示面）的逐行驱动的时钟信号线，位于不同行的时钟信号线之间存在明显的负载差异。显示装置通过控制位于面内的多个像素发光以呈现出所需画面。时钟信号线之间的负载差异会导致像素充电后的电位存在差异，进而导致不同像素行之间存在亮度差异。因此，显示出的画面中存在密集的黑白水平线。
目前，针对上述缺陷的一种改善方案为，通过改变制造工艺来调整时钟信号线之间的面内负载差异。然而，这种改善方案无法完全解决时钟信号线之间的负载差异，并且容易导致产品的良率降低、产能下降和效益降低等问题。
有鉴于此，有必要提出一种显示装置，以解决现有技术中存在的问题。
 技术问题
为解决上述现有技术的问题，本申请的目的在于提供一种显示装置，其能改善显示装置显示出非预期的黑白水平线的问题。
 技术解决方案
为达成上述目的，本申请提供一种显示装置，包括：处理器，配置为输出驱动信号和电压；时序控制器，与所述处理器连接，以及配置为基于所述驱动信号产生控制信号；电路板，与所述时序控制器连接，配置为根据所述电压和所述控制信号产生初始时钟信号，其中以及所述时钟信号为高电平和低电平交替出现的信号；显示面板，与所述电路板连接，包含显示区和非显示区；多条时钟信号线，配置为传递所述初始时钟信号，其中每一所述时钟信号线从所述电路板延伸至所述显示面板的所述非显示区；多个接地电阻，设置在所述电路板，其中每一所述接地电阻与对应的所述时钟信号线连接，配置为降低所述初始时钟信号的所述高电平的电压值，进而获得调整后的时钟信号；栅极驱动器，设置在所述显示面板的所述非显示区，且与所述时钟信号线连接，配置为根据所述调整后的时钟信号产生栅极信号；以及栅极线，设置在所述显示面板的所述显示区，且与所述栅极驱动器连接，配置为传递所述栅极信号。
在一些实施例中，所述多条时钟信号线从所述显示面板的所述显示区朝所述非显示区的方向依序排列，并且与其中两条所述时钟信号线对应连接的两个所述接地电阻的数值不同。
在一些实施例中，所述显示装置包含依序排列的第M条时钟信号线、第M-1条时钟信号线和第M-2条时钟信号线；以及与所述第M条时钟信号线连接的所述接地电阻的数值为R（M），与所述第M-1条时钟信号线连接的所述接地电阻的数值为R（M-1），以及与所述第M-2条时钟信号线连接的所述接地电阻的数值为R（M-2），其中R（M）<R（M-1）< R（M-2）或R（M）>R（M-1）> R（M-2）。
在一些实施例中，所述显示装置包含相邻的第K条时钟信号线和第K-1条时钟信号线；以及与所述第K条时钟信号线连接的所述接地电阻的数值为R（K），与所述第K-1条时钟信号线连接的所述接地电阻的数值为R（K-1），其中R（K）=R（K-1）。
在一些实施例中，所述显示装置还包括多个匹配电阻，设置在所述电路板，以及每一所述匹配电阻与对应的所述时钟信号线连接。
在一些实施例中，每一所述时钟信号线包含第一段和与所述第一段连接的第二段，所述第一段设置在所述电路板，所述第二段设置在所述显示面板的所述非显示区，以及每一所述接地电阻与对应的所述时钟信号线的所述第一段连接。
在一些实施例中，所述电路板包含第一电路板和第二电路板；每一所述时钟信号线的所述第一段包含第一子段和第二子段，所述第一子段设置在所述第一电路板，以及所述第二子段设置在所述第二电路板；每一所述时钟信号线的所述第二段包含第三子段和第四子段，分别设置在所述显示面板的相对两侧；所述栅极驱动器包含第一栅极驱动器和第二栅极驱动器，所述第一栅极驱动器与所述第三子段连接，所述第二栅极驱动器与所述第四子段连接，所述第一栅极驱动器和所述第二栅极驱动器分别与所述栅极线的相对两端连接；每一所述接地电阻包含第一接地电阻和第二接地电阻，所述第一接地电阻设置在所述第一电路板并且与对应的所述时钟信号线的所述第一子段连接，所述第二接地电阻设置在所述第二电路板并且与对应的所述时钟信号线的所述第二子段连接。
在一些实施例中，与同一所述时钟信号线连接的所述第一接地电阻和所述第二接地电阻的数值相同。
在一些实施例中，与同一所述时钟信号线连接的所述第一接地电阻和所述第二接地电阻的数值不同。
在一些实施例中，同一所述时钟信号线与所述第一接地电阻、所述第二接地电阻的RC电路和对应的所述栅极线的RC电路构成电子回路。
本申请还提供一种显示装置，包括：电路板，配置为输出时钟信号，其中所述时钟信号为高电平和低电平交替出现的信号；显示面板，与所述电路板连接，包含显示区和非显示区；多条时钟信号线，配置为传递所述时钟信号，其中每一所述时钟信号线从所述电路板延伸至所述显示面板的所述非显示区；多个接地电阻，设置在所述电路板，其中每一所述接地电阻与对应的所述时钟信号线连接，配置为降低所述时钟信号的所述高电平的电压值；栅极驱动器，设置在所述显示面板的所述非显示区，且与所述时钟信号线连接，配置为根据降低所述高电平的电压值的所述时钟信号产生栅极信号；以及栅极线，设置在所述显示面板的所述显示区，且与所述栅极驱动器连接，配置为传递所述栅极信号。
在一些实施例中，所述多条时钟信号线从所述显示面板的所述显示区朝所述非显示区的方向依序排列，并且与其中两条所述时钟信号线对应连接的两个所述接地电阻的数值不同。
在一些实施例中，所述显示装置包含依序排列的第M条时钟信号线、第M-1条时钟信号线和第M-2条时钟信号线；以及与所述第M条时钟信号线连接的所述接地电阻的数值为R（M），与所述第M-1条时钟信号线连接的所述接地电阻的数值为R（M-1），以及与所述第M-2条时钟信号线连接的所述接地电阻的数值为R（M-2），其中R（M）<R（M-1）< R（M-2）或R（M）>R（M-1）> R（M-2）。
在一些实施例中，所述显示装置包含相邻的第K条时钟信号线和第K-1条时钟信号线；以及与所述第K条时钟信号线连接的所述接地电阻的数值为R（K），与所述第K-1条时钟信号线连接的所述接地电阻的数值为R（K-1），其中R（K）=R（K-1）。
在一些实施例中，所述显示装置还包括多个匹配电阻，设置在所述电路板，以及每一所述匹配电阻与对应的所述时钟信号线连接。
在一些实施例中，每一所述时钟信号线包含第一段和与所述第一段连接的第二段，所述第一段设置在所述电路板，所述第二段设置在所述显示面板的所述非显示区，以及每一所述接地电阻与对应的所述时钟信号线的所述第一段连接。
在一些实施例中，所述电路板包含第一电路板和第二电路板；每一所述时钟信号线的所述第一段包含第一子段和第二子段，所述第一子段设置在所述第一电路板，以及所述第二子段设置在所述第二电路板；每一所述时钟信号线的所述第二段包含第三子段和第四子段，分别设置在所述显示面板的相对两侧；所述栅极驱动器包含第一栅极驱动器和第二栅极驱动器，所述第一栅极驱动器与所述第三子段连接，所述第二栅极驱动器与所述第四子段连接，所述第一栅极驱动器和所述第二栅极驱动器分别与所述栅极线的相对两端连接；每一所述接地电阻包含第一接地电阻和第二接地电阻，所述第一接地电阻设置在所述第一电路板并且与对应的所述时钟信号线的所述第一子段连接，所述第二接地电阻设置在所述第二电路板并且与对应的所述时钟信号线的所述第二子段连接。
在一些实施例中，与同一所述时钟信号线连接的所述第一接地电阻和所述第二接地电阻的数值相同。
在一些实施例中，与同一所述时钟信号线连接的所述第一接地电阻和所述第二接地电阻的数值不同。
在一些实施例中，同一所述时钟信号线与所述第一接地电阻、所述第二接地电阻的RC电路和对应的所述栅极线的RC电路构成电子回路。
 有益效果
相较于先前技术，本申请通过在显示装置的电路板上设置与时钟信号线连接的接地电阻和匹配电阻，可优化时钟信号线的电路设计和消除时钟信号线的负载差异，进而解决显示画面出现非预期的黑白水平线的问题，大幅提升产品的良率和产品质量。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1显示根据本申请的实施例的显示装置的示意图。
图2显示图1的显示装置的局部电路框图。
图3显示图1的显示装置的显示面板的非显示区的布线区的示意图。
图4显示根据本申请的实施例的时钟信号线的电路图。
图5显示根据本申请的实施例的时钟信号的波形图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参照图1，其显示根据本申请的实施例的显示装置10的示意图。显示装置10包括处理器100、时序控制器110、第一电路板121、第二电路板122、柔性电路板130、显示面板140、第一栅极驱动器151、第二栅极驱动器152和源极驱动器。时序控制器110与处理器100连接。第一电路板121和第二电路板122与时序控制器110连接，并且分别通过对应的柔性电路板130与显示面板140连接。显示面板140包括显示区141和围绕显示区141的非显示区142。第一栅极驱动器151和第二栅极驱动器152分别设置在显示面板140的相对两侧，并且设置在显示面板140的外周围143与显示区141之间的非显示区142。源极驱动器可集成在第一电路板121和第二电路板122中，集成在柔性电路板130中，或者是设置在显示面板140的非显示区142，不局限于此。显示面板140的显示区141包括多条栅极线GL、多条数据线和多个像素，其中每一栅极线GL可驱动至少一行像素。第一栅极驱动器151和第二栅极驱动器152与栅极线GL对应连接，并且分别连接栅极线GL的相对两端。源极驱动器与数据线连接。
请参照图1和图2，图2显示图1的显示装置的局部电路框图。显示装置10还包含电压产生单元101和时序产生单元123。在本实施例中，电压产生单元101可设置在处理器100中，以及时序产生单元123可设置在第一电路板121和第二电路板122中。时序产生单元123与电压产生单元101和时序控制器110连接。时序产生单元123通过多条信号线与第一栅极驱动器151和第二栅极驱动器152连接，如时钟信号线CLK、扫描开始信号线、扫描顺序控制信号线等。在本实施例中，第一电路板121的时序产生单元123与第一栅极驱动器151之间的信号线包含12条时钟信号线（CLK1至CLK12），以及第二电路板122的时序产生单元123与第二栅极驱动器152之间的信号线也包含12条时钟信号线（CLK1至CLK12）。应当理解的是，在其他实施例中可采用其他数量的时钟信号线CLK，不局限于此。
如图1和图2所示，在本实施例中，处理器100输出图像信号、使能信号、垂直同步信号、水平同步信号和时钟信号等驱动信号。时序控制器110从处理器100接收上述驱动信号。时序控制器110基于驱动信号产生数据控制信号。源极驱动器根据数据控制信号产生数据信号，并输出至对应的数据线。再者，电压产生单元101提供电压至时序产生单元123。时序控制器110基于驱动信号产生控制信号。时序产生单元123根据电压和控制信号产生包含时钟信号的栅极控制信号，并且控制对应的时钟信号线CLK传递所述时钟信号至第一栅极驱动器151和/或第二栅极驱动器152。第一栅极驱动器151和第二栅极驱动器152根据栅极控制信号产生栅极信号，并输出至对应的栅极线。显示面板140中的像素响应于数据信号和栅极信号显示图像。
如图1所示，显示面板140的非显示区142包含第一布线区1421和第二布线区1422。第一布线区1421位于第一栅极驱动器151与显示面板140的外周围143之间，以及第二布线区1422位于第二栅极驱动器152与显示面板140的外周围143之间。
如图1和图2所示，每一时钟信号线CLK从电路板121/122延伸至显示面板140的非显示区142的布线区1421/1422。具体来说，同一时钟信号线CLK（如第一时钟信号线CLK1）包含设置在电路板121/122的第一段和设置在显示面板140的第二段。由于本实施例是采用双栅极驱动技术，因此同一时钟信号线CLK会在显示装置10的相对两侧延伸。
如图1所示，在一条时钟信号线CLK中，时钟信号线CLK的第一段包含位于第一电路板121的第一子段161和位于第二电路板122的第二子段162。时钟信号线CLK的第二段包含位于第一布线区1421的第三子段163和位于第二布线区1422的第四子段164。第一子段161和第二子段162接收基于时序控制器110的同一信号而产生的时钟信号，即第一子段161和第二子段162用于传递相同的时钟信号。第一子段161与第三子段163连接，以及第二子段162与第四子段164连接。第三子段163与第一栅极驱动器151连接，以及第四子段164与第二栅极驱动器152连接。第一栅极驱动器151和第二栅极驱动器152基于相同的时钟信号控制同一条栅极线GL。
应当注意的是，不同的时钟信号线CLK之间会因为面板制程差异而导致不同的时钟信号线CLK之间存在负载差异，进而影响传递至显示面板140的时钟信号。其次，电路板121/122的制程差异、显示面板140和电路板121/122的设计差异（如结构设计、走线布局设计等）也会导致上述负载差异的问题。举例来说，请参照图3，其显示图1的显示装置的显示面板140的非显示区142的布线区1421/1422的示意图。在显示面板140的布线区1421/1422中，从显示面板140的非显示区142（或外周围143）朝显示区141的方向包含依序排列的彩膜基板的公共电极线CF_COM、DBS（data line bm less）公共电极线DBS、第十二时钟信号线CLK12至第一时钟信号线CLK1、第二下拉电路控制信号线LC2、第一下拉电路控制信号线LC1和基准电位线VSS。在显示面板140内，每一时钟信号线CLK的时钟信号会与周围信号线相互耦合。由于布线设计的影响，不同的时钟信号会产生不同的耦合量，进而使得不同时钟信号线之间具有不同的负载。为了改善时钟信号线之间的负载差异，本申请的显示装置还包含与时钟信号线连接的接地电阻，具体说明如下。
如图1和图2所示，接地电阻R设置在电路板121/122，且与对应的时钟信号线CLK的第一段连接。具体来说，请参照图4，其显示根据本申请的实施例的时钟信号线的电路图。与同一条时钟信号线CLK连接的接地电阻1包含第一接地电阻RL1和第二接地电阻RR1。第一接地电阻RL1设置在第一电路板121上，且与时钟信号线CLK的第一子段161连接。第二接地电阻RR1设置在第二电路板122上，且与时钟信号线CLK的第二子段162连接。时钟信号线CLK的第三子段163由于制程差异和走线布局影响而具有第一负载（包含第一负载电阻RL2和第一负载电容CL2）。同理，时钟信号线CLK的第四子段164具有第二负载（包含第二负载电阻RR2和第二负载电容CR2）。此外，基于同一时钟信号而驱动的栅极线GL也具有第三负载（包含第三负载电阻R3和第三负载电容C3）。同一条时钟信号线CLK与第一接地电阻RL1、第二接地电阻RR1的RC电路和对应的栅极线GL的RC电路构成电子回路。时钟信号线CLK在显示面板上的电流为I1，时钟信号线CLK在第一电路板121上的电流为I2，时钟信号线CLK在第二电路板122上的电流为I3。时钟信号线CLK的总电流I为I1+I2+I3。
在本实施例中，通过设置接地电阻R，可增强时钟信号的电压降，使得时钟信号的高电平的电压值降低。具体来说，请参照图5，其显示根据本申请的实施例的时钟信号的波形图。时序产生单元123根据接收电压和时序控制器110的控制信号产生初始时钟信号W1，通过一对应的时钟信号线CLK传递初始时钟信号W1。初始时钟信号W1为高电平VGH和低电平VGL交替出现的信号。与时钟信号线CLK连接的接地电阻R可降低时钟信号的高电平的电压值，进而获得调整后的时钟信号W2。具体来说，通过接地电阻R可使得电路的总电阻减小，并且使总电流I增大，使得时钟信号在电路板上的压降增大，进而降低输入到显示面板上的时钟信号的高电平的电压值。在一些实施例中，初始时钟信号W1的高电平VGH与调整后的时钟信号W2的高电平VGH’的差值ΔV约为0.375V。根据馈通（feed through）效应，当第N行的栅极线导通，第N-1行的栅极线关闭。此时，第N-1行的像素电极会因寄生电容影响而降低驱动电压，进而使得第N-1行的像素的亮度变暗。在本申请中，通过设置接地电阻R可减少因馈通效应而导致的驱动电压下降，进而使对应暗区像素的亮度提高。因此，消除了因时钟信号线CLK之间负载差异所造成的黑白水平线的问题，从而提升画面质量。
在本申请中，接地电阻R设置在电路板121/122上，而不是设置在显示面板140的布线区1421/1422。因此，可避免接地电阻R占用显示面板140的布线空间，以及避免接地电阻R增加显示面板140的负载。
应当注意的是，接地电阻R的数值根据与其连接的时钟信号线的布线位置决定。在本实施例中，考量不同时钟信号线的布线位置差异，接地电阻R的数值介于1至500千欧姆（KΩ）之间。应当理解的是，若接地电阻R的数值超出此范围会影响面板正常显示，或对消除黑白水平线的作用不大。若电阻的数值太大（如大于500 KΩ），由于电路原理使得对于显示面板内的时钟信号影响较小，进而无消除黑白水平线的改善效果。另一方面，若电阻的数值太小（如小于1KΩ），由于电路原理使得显示面板内的时钟信号线存在短路，从而影响显示。
在一些实施例中，显示装置10包含从显示面板140的非显示区142朝显示区141的方向依序排列的多条时钟信号线。通过将与其中至少两条时钟信号线对应连接的两个接地电阻的数值设计为不同，可消除因时钟信号线布线位置不同而造成的负载差异。举例来说，显示装置10包含从显示面板140的外周围143朝显示区141的方向依序排列的N条时钟信号线。与第N条时钟信号线连接的接地电阻的数值为R（N），以及与第一条时钟信号线连接的接地电阻的数值为R（1），其中R（N）≠R（1）。
在一些实施例中，显示装置10包含从显示面板140的外周围143朝显示区141的方向依序排列的N条时钟信号线。由于相邻近的时钟信号线之间的布线差异较小，因此将与其中两相邻的时钟信号线对应连接的两相邻的接地电阻R的数值设计为相同。举例来说，显示装置10包含相邻的第K条时钟信号线和第K-1条时钟信号线，其中N≤K<1。与第K条时钟信号线连接的接地电阻的数值为R（K），与第K-1条时钟信号线连接的接地电阻的数值为R（K-1），其中R（K）=R（K-1）。应当注意的是，R（K）≠R（N）或R（K）≠R（1）。通过部分的接地电阻R采用相同电阻值的设计，有利于降低电路板121/122的制造复杂性、提高良率和产能。
在一些实施例中，显示装置10包含从显示面板140的外周围143朝显示区141的方向依序排列的多条时钟信号线。由于不同的时钟信号线之间存在不同的制程差异，且不同的时钟信号也会因级传关系而存在不同的耦合值，因此与多条时钟信号线对应连接的接地电阻R的数值可设计为全部或大部分不同。响应于接地电阻R的数值不同，该些数值可采有序或无序的设置方案，其中有序的方案包含渐变。具体来说，该些接地电阻R的数值从外周围朝显示区的方向渐变，如渐增或渐减。举例来说，显示装置10包含从显示面板140的外周围143朝显示区141的方向依序排列的N条时钟信号线，其中包含依序排列的第M条时钟信号线、第M-1条时钟信号线和第M-2条时钟信号线，且N≤M<1。与第M条时钟信号线连接的接地电阻的数值为R（M），与第M-1条时钟信号线连接的接地电阻的数值为R（M-1），以及与第M-2条时钟信号线连接的接地电阻的数值为R（M-2），其中R（M）<R（M-1）< R（M-2）或R（M）>R（M-1）> R（M-2）。在一些实施例中，该些接地电阻R的数值为等差数列，公差为1KΩ，如与第一时钟信号线CLK1至第十二时钟信号线CLK12连接的接地电阻R分别为1KΩ、2KΩ、3KΩ、4KΩ、5KΩ、6KΩ、7KΩ、8KΩ、9KΩ、10KΩ、11KΩ、12KΩ。全部或大部分的接地电阻R采用不同电阻值的设计，对于改善黑白水平线的效果更佳。
在一些实施例中，与同一条时钟信号线CLK连接的接地电阻R的第一接地电阻RL1和第二接地电阻RR1可设计为相同（如上述的接地电阻R的数值等于第一接地电阻RL1，且等于第二接地电阻RR1）。通过将与同一条时钟信号线CLK连接的第一接地电阻RL1和第二接地电阻RR1采用相同电阻值的设计，有利于降低制造复杂性、提高良率和产能。
在一些实施例中，考量同一条时钟信号线CLK在显示装置10（包含电路板和显示面板）的两侧可能存在制程差异和布线差异，与同一条时钟信号线CLK连接的接地电阻R的第一接地电阻RL1和第二接地电阻RR1可设计为不同。藉此设计，可有效地改善同一条时钟信号线在显示装置的不同侧的负载差异。
如图2和图4所示，显示装置10还包括多个匹配电阻R_PCB，设置在电路板121/122，且每一匹配电阻R_PCB与对应的时钟信号线CLK的第一段串联连接。具体来说，与同一条时钟信号线CLK连接的匹配电阻R_PCB包含第一匹配电阻RL_PCB和第二匹配电阻RR_PCB。第一匹配电阻RL_PCB设置在第一电路板121上，且与时钟信号线CLK的第一子段161连接。第二匹配电阻RR_PCB设置在第二电路板122上，且与时钟信号线CLK的第二子段162连接。
在显示装置10的制造过程中，先设置接地电阻R，接着再设置匹配电阻R_PCB。具体来说，对显示装置10进行点灯测试以确认画面质量。若画面中出现的水平密集线则对所有时钟信号进行量测，以确定时钟信号线之间的负载差异。接着，通过上述的接地电阻R的设计方案，降低对应时钟信号的高电平的电压值。因此，消除了时钟信号线之间的负载差异，从而消除黑白水平线和提高显示质量。接着，对电路板121/122上的时钟信号线CLK的电阻进行基准定位以确认造成暗线的时钟信号线CLK，并且对该时钟信号线CLK进行串电阻匹配。因此，通过匹配电阻R_PCB的设置可进一步解决黑白水平线的问题。由上可知，通过接地电阻R和匹配电阻R_PCB的设置，可有效减小不同的时钟信号线CLK的时钟信号对像素行的充电差异，进而提升各像素行的亮度均一性，消除黑白水平线的问题以及提升画面质量。
上述实施例是以采用双栅极驱动技术的显示装置进行说明。应当理解的是，本申请的方案也适用于采用单栅极驱动技术的显示装置，其原理以及接地电阻与匹配电阻的设计方案皆相似于上述双栅极驱动技术的显示装置，在此不加以赘述。
综上所述，本申请通过在显示装置的电路板上设置与时钟信号线连接的接地电阻和匹配电阻，可优化时钟信号线的电路设计和消除时钟信号线的负载差异，进而解决显示画面出现非预期的黑白水平线的问题，大幅提升产品的良率和产品质量。
以上对本申请实施例所提供的一种显示装置进行了详细介绍。本文中应用了具体实施例对本申请的原理及实施方式进行了阐述。以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想。本领域的普通技术人员应当理解，其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示装置，包括：
    处理器，配置为输出驱动信号和电压；
    时序控制器，与所述处理器连接，以及配置为基于所述驱动信号产生控制信号；
    电路板，与所述时序控制器连接，配置为根据所述电压和所述控制信号产生初始时钟信号，其中以及所述时钟信号为高电平和低电平交替出现的信号；
    显示面板，与所述电路板连接，包含显示区和非显示区；
    多条时钟信号线，配置为传递所述初始时钟信号，其中每一所述时钟信号线从所述电路板延伸至所述显示面板的所述非显示区；
    多个接地电阻，设置在所述电路板，其中每一所述接地电阻与对应的所述时钟信号线连接，配置为降低所述初始时钟信号的所述高电平的电压值，进而获得调整后的时钟信号；
    栅极驱动器，设置在所述显示面板的所述非显示区，且与所述时钟信号线连接，配置为根据所述调整后的时钟信号产生栅极信号；以及
    栅极线，设置在所述显示面板的所述显示区，且与所述栅极驱动器连接，配置为传递所述栅极信号。
  2. 如权利要求1所述的显示装置，其中所述多条时钟信号线从所述显示面板的所述显示区朝所述非显示区的方向依序排列，并且与其中两条所述时钟信号线对应连接的两个所述接地电阻的数值不同。
  3. 如权利要求1所述的显示装置，其中所述显示装置包含依序排列的第M条时钟信号线、第M-1条时钟信号线和第M-2条时钟信号线；以及
    与所述第M条时钟信号线连接的所述接地电阻的数值为R（M），与所述第M-1条时钟信号线连接的所述接地电阻的数值为R（M-1），以及与所述第M-2条时钟信号线连接的所述接地电阻的数值为R（M-2），其中R（M）<R（M-1）< R（M-2）或R（M）>R（M-1）> R（M-2）。
  4. 如权利要求1所述的显示装置，其中所述显示装置包含相邻的第K条时钟信号线和第K-1条时钟信号线；以及
    与所述第K条时钟信号线连接的所述接地电阻的数值为R（K），与所述第K-1条时钟信号线连接的所述接地电阻的数值为R（K-1），其中R（K）=R（K-1）。
  5. 如权利要求1所述的显示装置，其中所述显示装置还包括多个匹配电阻，设置在所述电路板，以及每一所述匹配电阻与对应的所述时钟信号线连接。
  6. 如权利要求1所述的显示装置，其中每一所述时钟信号线包含第一段和与所述第一段连接的第二段，所述第一段设置在所述电路板，所述第二段设置在所述显示面板的所述非显示区，以及每一所述接地电阻与对应的所述时钟信号线的所述第一段连接。
  7. 如权利要求6所述的显示装置，其中所述电路板包含第一电路板和第二电路板；
    每一所述时钟信号线的所述第一段包含第一子段和第二子段，所述第一子段设置在所述第一电路板，以及所述第二子段设置在所述第二电路板；
    每一所述时钟信号线的所述第二段包含第三子段和第四子段，分别设置在所述显示面板的相对两侧；
    所述栅极驱动器包含第一栅极驱动器和第二栅极驱动器，所述第一栅极驱动器与所述第三子段连接，所述第二栅极驱动器与所述第四子段连接，所述第一栅极驱动器和所述第二栅极驱动器分别与所述栅极线的相对两端连接；
    每一所述接地电阻包含第一接地电阻和第二接地电阻，所述第一接地电阻设置在所述第一电路板并且与对应的所述时钟信号线的所述第一子段连接，所述第二接地电阻设置在所述第二电路板并且与对应的所述时钟信号线的所述第二子段连接。
  8. 如权利要求7所述的显示装置，其中与同一所述时钟信号线连接的所述第一接地电阻和所述第二接地电阻的数值相同。
  9. 如权利要求7所述的显示装置，其中与同一所述时钟信号线连接的所述第一接地电阻和所述第二接地电阻的数值不同。
  10. 如权利要求7所述的显示装置，其中同一所述时钟信号线与所述第一接地电阻、所述第二接地电阻的RC电路和对应的所述栅极线的RC电路构成电子回路。
  11. 一种显示装置，包括：
    电路板，配置为输出时钟信号，其中所述时钟信号为高电平和低电平交替出现的信号；
    显示面板，与所述电路板连接，包含显示区和非显示区；
    多条时钟信号线，配置为传递所述时钟信号，其中每一所述时钟信号线从所述电路板延伸至所述显示面板的所述非显示区；
    多个接地电阻，设置在所述电路板，其中每一所述接地电阻与对应的所述时钟信号线连接，配置为降低所述时钟信号的所述高电平的电压值；
    栅极驱动器，设置在所述显示面板的所述非显示区，且与所述时钟信号线连接，配置为根据降低所述高电平的电压值的所述时钟信号产生栅极信号；以及
    栅极线，设置在所述显示面板的所述显示区，且与所述栅极驱动器连接，配置为传递所述栅极信号。
  12. 如权利要求11所述的显示装置，其中所述多条时钟信号线从所述显示面板的所述显示区朝所述非显示区的方向依序排列，并且与其中两条所述时钟信号线对应连接的两个所述接地电阻的数值不同。
  13. 如权利要求11所述的显示装置，其中所述显示装置包含依序排列的第M条时钟信号线、第M-1条时钟信号线和第M-2条时钟信号线；以及
    与所述第M条时钟信号线连接的所述接地电阻的数值为R（M），与所述第M-1条时钟信号线连接的所述接地电阻的数值为R（M-1），以及与所述第M-2条时钟信号线连接的所述接地电阻的数值为R（M-2），其中R（M）<R（M-1）< R（M-2）或R（M）>R（M-1）> R（M-2）。
  14. 如权利要求11所述的显示装置，其中所述显示装置包含相邻的第K条时钟信号线和第K-1条时钟信号线；以及
    与所述第K条时钟信号线连接的所述接地电阻的数值为R（K），与所述第K-1条时钟信号线连接的所述接地电阻的数值为R（K-1），其中R（K）=R（K-1）。
  15. 如权利要求11所述的显示装置，其中所述显示装置还包括多个匹配电阻，设置在所述电路板，以及每一所述匹配电阻与对应的所述时钟信号线连接。
  16. 如权利要求11所述的显示装置，其中每一所述时钟信号线包含第一段和与所述第一段连接的第二段，所述第一段设置在所述电路板，所述第二段设置在所述显示面板的所述非显示区，以及每一所述接地电阻与对应的所述时钟信号线的所述第一段连接。
  17. 如权利要求16所述的显示装置，其中所述电路板包含第一电路板和第二电路板；
    每一所述时钟信号线的所述第一段包含第一子段和第二子段，所述第一子段设置在所述第一电路板，以及所述第二子段设置在所述第二电路板；
    每一所述时钟信号线的所述第二段包含第三子段和第四子段，分别设置在所述显示面板的相对两侧；
    所述栅极驱动器包含第一栅极驱动器和第二栅极驱动器，所述第一栅极驱动器与所述第三子段连接，所述第二栅极驱动器与所述第四子段连接，所述第一栅极驱动器和所述第二栅极驱动器分别与所述栅极线的相对两端连接；
    每一所述接地电阻包含第一接地电阻和第二接地电阻，所述第一接地电阻设置在所述第一电路板并且与对应的所述时钟信号线的所述第一子段连接，所述第二接地电阻设置在所述第二电路板并且与对应的所述时钟信号线的所述第二子段连接。
  18. 如权利要求17所述的显示装置，其中与同一所述时钟信号线连接的所述第一接地电阻和所述第二接地电阻的数值相同。
  19. 如权利要求17所述的显示装置，其中与同一所述时钟信号线连接的所述第一接地电阻和所述第二接地电阻的数值不同。
  20. 如权利要求17所述的显示装置，其中同一所述时钟信号线与所述第一接地电阻、所述第二接地电阻的RC电路和对应的所述栅极线的RC电路构成电子回路。
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