WO2023040474A1 - 一种射频功率放大器 - Google Patents

一种射频功率放大器 Download PDF

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Publication number
WO2023040474A1
WO2023040474A1 PCT/CN2022/108114 CN2022108114W WO2023040474A1 WO 2023040474 A1 WO2023040474 A1 WO 2023040474A1 CN 2022108114 W CN2022108114 W CN 2022108114W WO 2023040474 A1 WO2023040474 A1 WO 2023040474A1
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capacitor
transformer
transistor
output
input
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PCT/CN2022/108114
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English (en)
French (fr)
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谢志远
赵宇霆
郭嘉帅
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深圳飞骧科技股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the utility model relates to the technical field of power amplifiers, in particular to a radio frequency power amplifier.
  • the goal of 5G communication technology is high data throughput rate, low delay, low cost and energy saving, higher system capacity and large-scale device connection.
  • the download speed is 100 times that of 4G communication, the transmission delay is less than 1ms, and the channel bandwidth reaches 400MHz, and has a higher data transfer rate of 20Gbps.
  • the power amplifier PA
  • the power amplifier has a great influence on the performance of the entire transceiver. Its function is to amplify the output signal, and the amplified signal is sent by the antenna. Therefore, the power amplifier will directly determine the various performance indicators of the transceiver system, and then affect the various performance indicators of the entire 5G wireless communication system.
  • the output power of the power amplifier directly determines the strength of the signal transmitted to the space, that is, the effective coverage area of wireless communication.
  • High output power is the basic requirement for the design of RF power amplifiers, and the 5G communication system requires RF power amplifiers to have greater output power.
  • Increasing the output power of the RF power amplifier can be done by increasing its output current swing or output voltage swing, and increasing the output current swing can be achieved by increasing the area of a single transistor or connecting multiple transistors in parallel, but this will make the transistor The input and output impedances are reduced, making matching more difficult.
  • the embodiment of the utility model provides a radio frequency power amplifier, which can reduce the matching difficulty and improve the output power of the radio frequency power amplifier.
  • the utility model provides a radio frequency power amplifier on the one hand, including an input matching network, a first-stage two-way amplifier circuit, an inter-stage matching network, a second-stage two-way amplifier circuit and an output matching network;
  • the input matching network includes a first transformer T1
  • the interstage matching network includes a second transformer T2
  • the output matching network includes a third transformer T3, a first capacitor C1, a second capacitor C2, a second The third capacitor C3, the fourth capacitor C4, the fifth capacitor C5 and the first inductor L1;
  • the two input terminals of the first transformer T1 are respectively connected to the radio frequency input signal RFin and the ground terminal, and the two output terminals of the first transformer T1 are respectively connected to the two input terminals of the first-stage dual amplifier circuit, so as to The single-ended radio frequency input signal RFin is changed into a pair of differential signals, and the two output ends of the first-stage dual amplifying circuit are respectively connected to the two input ends of the second transformer T2, and the second transformer T2
  • the two output terminals of the second-stage dual-channel amplifier circuit are respectively connected to the two input terminals of the second-stage dual-channel amplifier circuit, and the two output terminals of the second-stage dual-channel amplifier circuit are respectively connected to the two input terminals of the third transformer T3, One end of the first capacitor C1 and the second capacitor C2 are respectively connected to the two input ends of the third transformer T3, the other end of the first capacitor C1 and the second capacitor C2 is grounded, and the third capacitor One end of C3 and one end of the fourth capacitor C4 are both connected to an
  • the input matching network further includes a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, and a second inductor L2;
  • One end of the sixth capacitor C6 and the seventh capacitor C7 are respectively connected to the two input ends of the first transformer T1, the other end of the sixth capacitor C6 and the seventh capacitor C7 are grounded, and the second inductor L2
  • the eighth capacitor C8 is connected in series between an output end of the first transformer T1 and the first-stage dual amplifier circuit.
  • the ninth capacitor C9 is connected in series between the other output terminal of the first transformer T1 and the other input terminal of the first-stage dual amplifier circuit.
  • the inter-stage matching network further includes a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a third inductor L3, and a fourth inductor L4;
  • the third inductor L3 is connected in series between an output end of the first-stage dual amplifier circuit and an input end of the second transformer T2, and one end of the tenth capacitor C10 is connected to the third inductor Between one end of L3 and the output end of the first stage dual amplifier circuit connected to the third inductor L3, the other end of the tenth capacitor C10 is grounded, and the fourth inductor L4 is connected in series with the first stage Between the other output end of the dual amplifier circuit and the other input end of the second transformer T2, one end of the eleventh capacitor C11 is connected to one end of the fourth inductance L4 and connected to the fourth inductance L4 The other end of the eleventh capacitor C11 is grounded between the output ends of the first-stage dual amplifier circuit connected, and the twelfth capacitor C12 is connected in series between one output end of the second transformer T2 and the first Between one input end of the second stage dual amplifier circuit, the thirteenth capacitor C13 is connected in series between the other output end of the second transformer T2 and the other input end of the
  • the first-stage dual amplifier circuit includes two first transistors Q1, and the second-stage dual amplifier circuit includes two second transistors Q2;
  • the bases of the two first transistors Q1 are respectively the two input terminals of the first-stage dual amplifier circuit, and the collectors of the two first transistors Q1 are respectively the two input terminals of the first-stage dual amplifier circuit.
  • the two output terminals of the two first transistors Q1 are grounded;
  • the bases of the two second transistors Q2 are respectively the two input terminals of the second-stage dual amplifier circuit, and the two The collectors of the two second transistors Q2 are respectively the two output terminals of the second-stage dual amplifier circuit, and the emitters of the two second transistors Q2 are grounded.
  • the bases of the first transistor Q1 and the second transistor Q2 are further connected with a bias circuit
  • the base and collector of the third transistor Q3, the base of the fourth transistor Q4, one end of the first resistor R1 and one end of the fourteenth capacitor C14 are connected; the first resistor R1
  • the other end of the second transistor Q5 is connected to the power supply voltage Vreg, the emitter of the third transistor Q3, the collector and the base of the fifth transistor Q5 are connected, and the emitter of the fifth transistor Q5 is connected to one end of the second resistor R2 , the other end of the second resistor R2 is grounded, the other end of the fourteenth capacitor C14 is grounded, the collector of the fourth transistor Q4 is connected to the supply voltage Vbat, the emitter of the fourth transistor Q4 is connected to the third One end of the resistor R3 is connected, and the other end of the third resistor R3 is connected to the base of the corresponding first transistor Q1 or the second transistor Q2.
  • first transformer T1 the second transformer T2 and the third transformer T3 are all symmetrical inter-wound transformers.
  • the radio frequency power amplifier of the present invention includes an input matching network, a first-stage two-way amplification circuit, an inter-stage matching network, a second-stage two-way amplifying circuit, and an output matching network; wherein, the input matching network includes A first transformer T1, the interstage matching network includes a second transformer T2, and the output matching network includes a third transformer T3, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4 , the fifth capacitor C5 and the first inductance L1; the two input terminals of the first transformer T1 are respectively connected to the radio frequency input signal RFin and the ground terminal, and the two output terminals of the first transformer T1 are respectively connected to the first stage
  • the two input terminals of the dual-channel amplifier circuit are used to change the single-ended radio frequency input signal RFin into a pair of differential signals, and the two output terminals of the first-stage dual-channel amplifier circuit are respectively connected to the second transformer T2 Two input terminals, the two output terminals of the first
  • Fig. 1 is the circuit diagram of the radio frequency power amplifier that the utility model embodiment provides;
  • Fig. 2 is the circuit diagram of the bias circuit that the utility model embodiment provides
  • Fig. 3 is the gain simulation waveform figure of radio frequency power amplifier of the present utility model
  • Fig. 4 is the gain of the radio frequency power amplifier of the present utility model and the comparison waveform diagram of gain compression
  • Fig. 5 is a simulation waveform diagram of the power added efficiency of the radio frequency power amplifier of the present invention.
  • the radio frequency power amplifier 100 that the embodiment of the present invention provides, comprise input matching network 11, the first stage two-way amplifier circuit 12, interstage matching network 13, the second stage two-way amplifier circuit 14 that are connected in series successively and an output matching network 15 .
  • the input matching network 11 includes a first transformer T1
  • the first-stage dual amplifier circuit 12 includes two input terminals and two output terminals, one input terminal and a corresponding output terminal form an amplifier circuit
  • the inter-stage matching network 13 includes a second transformer T2
  • the second-stage dual amplifying circuit 14 includes an input terminal and two output terminals, one input terminal and a corresponding output terminal form an amplifying circuit
  • the matching network 15 includes a third transformer T3, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5 and a first inductor L1.
  • the first to the third transformers are all symmetrical inter-winding transformers.
  • both the first-stage dual-channel amplifier circuit 12 and the second-stage dual-channel amplifier circuit 14 are implemented using HBT transistors, wherein the first-stage dual-channel amplifier circuit 12 includes two first transistors Q1, and the second-stage The dual amplifier circuit 14 includes two second transistors Q2.
  • the bases of the two first transistors Q1 are respectively the two input terminals of the first-stage dual amplifier circuit 12, and the collectors of the two first transistors Q1 are respectively the two input terminals of the first-stage dual amplifier circuit 12.
  • the first-stage dual-channel amplifier circuit and the second-stage dual-channel amplifier circuit may also be implemented by CMOS tubes or other power tubes.
  • the first transistor Q1 and the second transistor Q2 are HBT transistors as an example for description.
  • the two input terminals of the first transformer T1 are respectively connected to the radio frequency input signal RFin and the ground terminal, and the two output terminals of the first transformer T1 are respectively connected to the bases of the two first transistors Q1, so that the single-ended
  • the radio frequency input signal RFin becomes a pair of differential signals and is respectively output to the two first transistors Q1 for amplification, wherein the pair of differential signals have the same magnitude and a phase difference of 180°.
  • the collectors of the two first transistors Q1 are respectively connected to the two input terminals of the second transformer T2, and the emitters of the two first transistors Q1 are respectively grounded.
  • the two output terminals of the second transformer T2 are respectively connected to the bases of the two second transistors Q2, because the second transformer T2 has a double-input and double-output structure, so the two outputs of the first-stage dual-channel amplifier circuit 12 After the differential output signal passes through the second transformer T2, it continues to be input into the second-stage dual amplifier circuit 14 as two differential signals.
  • the collectors of the two second transistors Q2 are respectively connected to the input terminals of the third transformer T3, and the emitters of the two second transistors Q2 are respectively grounded.
  • One end of the first capacitor C1 and the second capacitor C2 are respectively connected to the two input ends of the third transformer T3, the other end of the first capacitor C1 and the second capacitor C2 is grounded, and the third capacitor One end of C3 and one end of the fourth capacitor C4 are both connected to an output end of the third transformer T3, the other end of the third capacitor C3 is grounded, the other end of the fourth capacitor C4, the first One end of the fifth capacitor C5 is connected to one end of the first inductor L1, the other end of the fifth capacitor C5 is grounded, the other end of the first inductor L1 outputs a radio frequency output signal RFout, and the third transformer T3 The other output is grounded.
  • the third transformer T3 is a transformer for converting a differential signal into a single-ended signal.
  • the two differential signals with a phase difference of 180° passing through the two second transistors Q2 will generate a phase difference of 180° again through the third transformer T3.
  • the phase difference is 360° or 0°, the two differential signals are converted into one single-ended signal to complete the power combination to obtain high output power.
  • the output matching network 15 is composed of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the first inductor L1 and the third transformer T3, which can realize high impedance matching to low impedance to complete the output matching function.
  • the first capacitor C1 and the second capacitor C2 can be realized by using the same capacitor element, and both have the same size.
  • 5 is the simulation waveform figure of the power added efficiency of the radio frequency power amplifier of the present utility model, shows by the simulation waveform figure in the figure, in the N77 operating frequency band, the radio frequency power amplifier of the present utility model
  • the gain is 34 ⁇ 36dBm
  • the output power 1dB compression point is 37dBm
  • the power added efficiency at the output power 1dB compression point is 52.5%
  • the power added efficiency at the output power back to 28.5dBm is 18.9%
  • the adjacent channel leakage ratio is -36.2dBc, with better performance.
  • the first-stage dual-channel amplifying circuit 12 uses two first transistors Q1 to respectively implement two-channel amplifying circuits.
  • each of the first-stage dual-channel amplifying circuits 12 One amplifying circuit can be realized by using a plurality of first transistors Q1 connected in parallel, the bases of the first transistors Q1 connected in parallel in each circuit are connected in parallel, the collectors are connected in parallel, and the emitters are grounded.
  • the second-stage dual-channel amplifier circuit 14 also uses two second transistors Q2 to realize the two-channel amplifier circuits respectively.
  • the second-stage dual-channel amplifier circuit 14 Each of the amplifying circuits can also be realized by a plurality of second transistors Q2 connected in parallel, the bases of the multiple second transistors Q2 connected in parallel in each amplifying circuit are connected in parallel, the collectors are connected in parallel, and the emitters are all grounded.
  • the input matching network 11 further includes a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9 and a second inductor L2.
  • One end of the sixth capacitor C6 and the seventh capacitor C7 are respectively connected to the two input ends of the first transformer T1, the other end of the sixth capacitor C6 and the seventh capacitor C7 are grounded, and the second inductor L2
  • the eighth capacitor C8 is connected in series between an output terminal of the first transformer T1 and a base of the first transistor Q1
  • the ninth capacitor C9 is connected in series between the other output terminal of the first transformer T1 and the base of another first transistor Q1.
  • the sixth capacitor C6, the seventh capacitor C7, the eighth capacitor C8, the ninth capacitor C9, the second inductor L2 and the second transformer T2 together form an input matching network 11, wherein the eighth capacitor C8 and the ninth capacitor C9 can adopt The same capacitive element is implemented, and the two have the same size, thereby ensuring that the two signals are equal in magnitude and out of phase, and the eighth capacitor C8 and the ninth capacitor C9 can adjust the gain trend of the first-stage dual amplifier circuit 12, and It functions as a DC blocking capacitor; while the sixth capacitor C6, the seventh capacitor C7 and the second inductor L2 can adjust and increase the bandwidth of the transformer and reduce its insertion loss.
  • the inter-stage matching network 13 further includes a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12, a thirteenth capacitor C13, a third inductor L3 and a fourth inductor L4.
  • the third inductor L3 is connected in series between the collector of the first transistor Q1 and an input terminal of the second transformer T2, one end of the tenth capacitor C10 is connected to the third inductor L3
  • the collector of the first transistor Q1 is connected, the other end of the tenth capacitor C10 is grounded, and the fourth inductor L4 is connected in series with the collector of the other first transistor Q1 and the other input of the second transformer T2
  • the eleventh capacitor C11 is connected to the collector of the first transistor Q1 connected to the fourth inductance L4
  • the other end of the eleventh capacitor C11 is grounded
  • the twelfth capacitor C12 The thirteenth capacitor C13 is connected in series between an output terminal of the second transformer T2 and the base of a second transistor Q
  • the tenth capacitor C10, the eleventh capacitor C11, the twelfth capacitor C12, the thirteenth capacitor C13, the third inductor L3, the fourth inductor L4 and the second transformer T2 together form an inter-stage matching network 13, similarly Ground, wherein the two capacitors C12 and C13 have the same size, which can ensure that the two signals are equal in magnitude and inverted, and the capacitors C12 and C13 can adjust the gain trend of the second-stage amplifier circuit 14, and play the role of a DC blocking capacitor; Capacitors C10, C11 and inductors L3, L4 can adjust and increase the bandwidth of the transformer and reduce its insertion loss.
  • the capacitor C10 and the capacitor C11 can be realized by using the same capacitor element, and both have the same size.
  • the bases of each of the first transistor Q1 and the second transistor Q2 are also connected with a bias circuit, as shown in FIG. 1 , the bases of the first transistor Q1 are connected with a first bias circuit circuit 161, the base of the second transistor Q2 is connected to a second bias circuit 162, wherein the structures of the first bias circuit 161 and the second bias circuit 162 may be the same or different, as long as a suitable bias voltage can be provided That's it.
  • the structure of the bias circuit specifically includes a third transistor Q3, a fourth transistor Q4, and a fifth transistor Q5. , a first resistor R1, a second resistor R2, a third resistor R3 and a fourteenth capacitor C14.
  • the base and collector of the third transistor Q3, the base of the fourth transistor Q4, one end of the first resistor R1 and one end of the fourteenth capacitor C14 are connected; the first resistor R1
  • the other end of the second transistor Q5 is connected to the power supply voltage Vreg, the emitter of the third transistor Q3, the collector and the base of the fifth transistor Q5 are connected, and the emitter of the fifth transistor Q5 is connected to one end of the second resistor R2 , the other end of the second resistor R2 is grounded, the other end of the fourteenth capacitor C14 is grounded, the collector of the fourth transistor Q4 is connected to the supply voltage Vbat, the emitter of the fourth transistor Q4 is connected to the third One end of the resistor R3 is connected, and the other end of the third resistor R3 is connected to the base of the corresponding first transistor Q1 or the second transistor Q2.
  • the first resistor R1 and the second resistor R2 are voltage dividing resistors
  • the third resistor R3 is a thermal effect suppressing resistor
  • I 1 and I 2 are currents
  • the fourteenth capacitor C14 is a filter capacitor.
  • the third transistor Q3 and the fifth transistor Q5 form a clamping voltage, so that the current I2 is a stable current, and the magnitude of I2 can be adjusted by adjusting the magnitude of the first resistor R1 and the second resistor R2.
  • the DC current of the first transistor Q1 or the second transistor Q2 increases. Due to the self-heating effect of the transistor and the rectification characteristics of the diode, the base of the first transistor Q1 or the second transistor Q2 The potential will drop and the signal on the RF line will leak into the bias circuit. Due to the existence of the fourteenth capacitor C14, the signal passes through the emitter and base of the fourth transistor Q4 and the fourteenth capacitor C14 to ground in sequence. Therefore, the base potential of the fourth transistor Q4 remains unchanged, so that the linearity of the power amplifier 100 is effectively improved.
  • the voltage between the base and the emitter of the fourth transistor Q4 decreases, and since the base potential of the fourth transistor Q4 remains unchanged, the first transistor Q1 or the second transistor
  • the reduction of the base voltage of Q2 is effectively compensated, so that the static operating point of the first transistor Q1 or the second transistor Q2 remains unchanged under the state of high input and output power, so that the gain compression is effectively suppressed.
  • the insertion return loss of inter-stage matching and overall matching can be optimized, the output power of the RF power amplifier can be improved, and the adjacent channel leakage of the RF power amplifier is better, at an output power of 28.5dBm At , the adjacent channel leakage ratio is less than -36.2dBc.

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Abstract

本实用新型实施例公开了一种射频功率放大器，包括依次串联的输入匹配网络、第一级双路放大电路、级间匹配网络、第二级双路放大电路以及输出匹配网络；其中，所述输入匹配网络包括一个第一变压器T1，所述级间匹配网络包括一个第二变压器T2，所述输出匹配网络包括一个第三变压器T3，所述第一变压器T1用于将单端的所述射频输入信号RFin变为一对差分信号并输入给第一级双路放大电路，所述第二变压器T2位于第一级双路放大电路和第二级双路放大电路之间，所述第三变压器T3用于将两路差分信号合成为一路射频信号输出，通过上述方式，能够降低匹配难度，提高射频功率放大器的输出功率。

Description

一种射频功率放大器 技术领域
本实用新型涉及功率放大器技术领域，尤其涉及一种射频功率放大器。
背景技术
5G通信技术目标是高数据吞吐率、低延时、低成本节能、更高的***容量和大规模的设备连接，其中下载速度是4G通信的100倍，传输时延低于1ms，信道带宽达到400MHz，并且有更高的数据传输速率，其速率为20Gbps。在5G通信的收发机中，功率放大器(PA)对整个收发机的性能影响非常大，其作用是将输出信号进行放大，由天线将被放大的信号发出。因此，功率放大器将直接决定了收发机***的各个性能指标，进而影响整个5G无线通信***的各项性能指标。现有的传统匹配结构多为由电容电感组合成的“Π型”、“T型”、“L型”匹配网络，可将功率放大器的输入输出端口与50欧姆端口连接时实现阻抗变化，根据不同设计指标的不同需求，可选择最适合的匹配结构和匹配器件。
功率放大器的输出功率直接决定了信号发射到空间的强度，即无线通信的有效覆盖面积，高输出功率是射频功率放大器设计的基本要求，而5G通信***需射频功率放大器有更大的输出功率。提高射频功率放大器的输出功率可通过提高其输出电流摆幅或者输出电压摆幅进行，而提高输出电流摆幅可通过增大单个晶体管面积或将多个晶体管并联来实现，然而这会使得晶体管的输入和输出阻抗减小，增加了匹配的难度。
实用新型内容
本实用新型实施例提供一种射频功率放大器，能够降低匹配难度，提高射频功率放大器的输出功率。
为了解决上述技术问题，本实用新型一方面提供一种种射频功率放大器，包括输入匹配网络、第一级双路放大电路、级间匹配网络、第二级双路放大电路以及输出匹配网络；
其中，所述输入匹配网络包括一个第一变压器T1，所述级间匹配网络包括 一个第二变压器T2，所述输出匹配网络包括一个第三变压器T3、第一电容C1、第二电容C2、第三电容C3、第四电容C4、第五电容C5以及第一电感L1；
所述第一变压器T1的两个输入端分别连接射频输入信号RFin和地端，所述第一变压器T1的两个输出端分别连接所述第一级双路放大电路的两个输入端，以将单端的所述射频输入信号RFin变为一对差分信号，所述第一级双路放大电路的两个输出端分别连接所述第二变压器T2的两个输入端，所述第二变压器T2的两个输出端分别连接所述第二级双路放大电路的两个输入端，所述第二级双路放大电路的两个输出端分别连接所述第三变压器T3的两个输入端，其中所述第一电容C1和第二电容C2的一端分别与所述第三变压器T3的两个输入端连接，所述第一电容C1和第二电容C2的另一端接地，所述第三电容C3的一端和所述第四电容C4的一端均与所述第三变压器T3的一个输出端连接，所述第三电容C3的另一端接地，所述第四电容C4的另一端、所述第五电容C5的一端以及所述第一电感L1的一端相连接，所述第五电容C5的另一端接地，所述第一电感L1的另一端输出射频输出信号RFout，所述第三变压器T3的另一个输出端接地。
更进一步地，所述输入匹配网络还包括第六电容C6、第七电容C7、第八电容C8、第九电容C9以及第二电感L2；
所述第六电容C6和第七电容C7的一端分别与所述第一变压器T1的两个输入端连接，所述第六电容C6和第七电容C7的另一端接地，所述第二电感L2串联在所述第一变压器T1的与地连接的输入端和地端之间，所述第八电容C8串联在所述第一变压器T1的一个输出端和所述第一级双路放大电路的一个输入端之间，所述第九电容C9串联在所述第一变压器T1的另一个输出端和所述第一级双路放大电路的另一个输入端之间。
更进一步地，所述级间匹配网络还包括第十电容C10、第十一电容C11、第十二电容C12、第十三电容C13、第三电感L3以及第四电感L4；
所述第三电感L3串联在所述第一级双路放大电路的一个输出端和所述第二变压器T2的一个输入端之间，所述第十电容C10的一端连接在所述第三电感L3的一端和与所述第三电感L3连接的第一级双路放大电路的输出端之间，所述第十电容C10的另一端接地，所述第四电感L4串联在所述第一级双路放 大电路的另一个输出端和所述第二变压器T2的另一个输入端之间，所第十一电容C11的一端连接在所述第四电感L4的一端和与所述第四电感L4连接的第一级双路放大电路的输出端之间，所述第十一电容C11的另一端接地，所述第十二电容C12串联在所述第二变压器T2的一个输出端和所述第二级双路放大电路的一个输入端之间，所述第十三电容C13串联在所述第二变压器T2的另一个输出端和所述第二级放大电路的另一个输入端之间。
更进一步地，所述第一级双路放大电路包括两个第一晶体管Q1，所述第二级双路放大电路包括两个第二晶体管Q2；
所述两个第一晶体管Q1的基极分别为所述第一级双路放大电路的两个输入端，所述两个第一晶体管Q1的集电极分别为所述第一级双路放大电路的两个输出端，所述两个第一晶体管Q1的发射极接地；所述两个第二晶体管Q2的基极分别为所述第二级双路放大电路的两个输入端，所述两个第二晶体管Q2的集电极分别为所述第二级双路放大电路的两个输出端，所述两个第二晶体管Q2的发射极接地。
更进一步地，所述第一晶体管Q1和所述第二晶体管Q2的基极还连接有偏置电路；
所述偏置电路包括第三晶体管Q3、第四晶体管Q4、第五晶体管Q5、第一电阻R1、第二电阻R2、第三电阻R3以及第十四电容C14；
所述第三晶体管Q3的基极和集电极、所述第四晶体管Q4的基极、所述第一电阻R1的一端以及所述第十四电容C14的一端相连接；所述第一电阻R1的另一端连接供电电压Vreg，所述第三晶体管Q3的发射极、所述第五晶体管Q5的集电极和基极相连接，所述第五晶体管Q5的发射极与第二电阻R2的一端连接，所述第二电阻R2的另一端接地，所述第十四电容C14的另一端接地，所述第四晶体管Q4的集电极连接供电电压Vbat，所述第四晶体管Q4的发射极与第三电阻R3的一端连接，所述第三电阻R3的另一端与对应的第一晶体管Q1或第二晶体管Q2的基极连接。
更进一步地，所述第一变压器T1、第二变压器T2以及第三变压器T3均为对称互绕式变压器。
有益效果：本实用新型的射频功率放大器中，包括输入匹配网络、第一级 双路放大电路、级间匹配网络、第二级双路放大电路以及输出匹配网络；其中，所述输入匹配网络包括一个第一变压器T1，所述级间匹配网络包括一个第二变压器T2，所述输出匹配网络包括一个第三变压器T3、第一电容C1、第二电容C2、第三电容C3、第四电容C4、第五电容C5以及第一电感L1；所述第一变压器T1的两个输入端分别连接射频输入信号RFin和地端，所述第一变压器T1的两个输出端分别连接所述第一级双路放大电路的两个输入端，以将单端的所述射频输入信号RFin变为一对差分信号，所述第一级双路放大电路的两个输出端分别连接所述第二变压器T2的两个输入端，所述第二变压器T2的两个输出端分别连接所述第二级双路放大电路的两个输入端，所述第二级双路放大电路的两个输出端分别连接所述第三变压器T3的两个输入端，所述第三变压器T3与所述第一电容C1、第二电容C2、第三电容C3、第四电容C4、第五电容C5以及第一电感L组成输出变压器匹配网络将射频输出信号RFout输出，通过上述方式，可以避免多个晶体管并联导致的输入输出阻抗减小而造成匹配困难问题，可以降低各级匹配网络的匹配难度，有利于提高输出功率。
附图说明
下面结合附图，通过对本实用新型的具体实施方式详细描述，将使本实用新型的技术方案及其有益效果显而易见。
图1是本实用新型实施例提供的射频功率放大器的电路图；
图2是本实用新型实施例提供的偏置电路的电路图；
图3是本实用新型的射频功率放大器的增益仿真波形图；
图4是本实用新型的射频功率放大器的增益和增益压缩的对比波形图；
图5是本实用新型的射频功率放大器的功率附加效率的仿真波形图。
具体实施方式
请参照图式，其中相同的组件符号代表相同的组件，本实用新型的原理是以实施在一适当的运算环境中来举例说明。以下的说明是基于所例示的本实用新型具体实施例，其不应被视为限制本实用新型未在此详述的其它具体实施例。
参阅图1，本实用新型实施例提供的射频功率放大器100中，包括依次串联连接的输入匹配网络11、第一级双路放大电路12、级间匹配网络13、第二级双路放大电路14以及输出匹配网络15。
其中，所述输入匹配网络11包括一个第一变压器T1，所述第一级双路放大电路12包括两个输入端和两个输出端，一个输入端和对应的一个输出端形成一路放大电路，所述级间匹配网络13包括一个第二变压器T2，所述第二级双路放大电路14包括输入端和两个输出端，一个输入端和对应的一个输出端形成一路放大电路，所述输出匹配网络15包括一个第三变压器T3、第一电容C1、第二电容C2、第三电容C3、第四电容C4、第五电容C5以及第一电感L1。
本实用新型的实施例中，第一至第三变压器均为对称互绕式变压器。此外，所述第一级双路放大电路12和第二级双路放大电路14均采用HBT晶体管实现，其中，第一级双路放大电路12包括两个第一晶体管Q1，所述第二级双路放大电路14包括两个第二晶体管Q2。所述两个第一晶体管Q1的基极分别为所述第一级双路放大电路12的两个输入端，所述两个第一晶体管Q1的集电极分别为所述第一级双路放大电路12的两个输出端，所述两个第一晶体管Q1的发射极接地；所述两个第二晶体管Q2的基极分别为所述第二级双路放大电路14的两个输入端，所述两个第二晶体管Q2的集电极分别为所述第二级双路放大电路14的两个输出端，所述两个第二晶体管Q2的发射极接地。当然，在其他实施方式中，第一级双路放大电路和第二级双路放大电路也可以采用COMS管或者其他功率管实现。为了便于说明，在以下描述中，以第一晶体管Q1和第二晶体管Q2为HBT晶体管为例进行说明。
所述第一变压器T1的两个输入端分别连接射频输入信号RFin和地端，所述第一变压器T1的两个输出端分别连接所述两个第一晶体管Q1的基极，以将单端的所述射频输入信号RFin变为一对差分信号分别输出给两个第一晶体管Q1进行放大，其中该一对差分信号大小相同相位相差180°。所述两个第一晶体管Q1的集电极分别连接所述第二变压器T2的两个输入端，所述两个第一晶体管Q1的发射极分别接地。所述第二变压器T2的两个输出端分别连接所述两个第二晶体管Q2的基极，因该第二变压器T2为双入双出结构，因此第一级双路放大电路12输出的两路差分输出信号在经过该第二变压器T2之后，继续以两路差分信号输入第二级双路放大电路14中。
所述两个第二晶体管Q2的集电极分别连接所述第三变压器T3的输入端，所述两个第二晶体管Q2的发射极分别接地。其中所述第一电容C1和第二电容 C2的一端分别与所述第三变压器T3的两个输入端连接，所述第一电容C1和第二电容C2的另一端接地，所述第三电容C3的一端和所述第四电容C4的一端均与所述第三变压器T3的一个输出端连接，所述第三电容C3的另一端接地，所述第四电容C4的另一端、所述第五电容C5的一端以及所述第一电感L1的一端相连接，所述第五电容C5的另一端接地，所述第一电感L1的另一端输出射频输出信号RFout，所述第三变压器T3的另一个输出端接地。因此，第三变压器T3为差分信号转为单端信号的变压器，经过两个第二晶体管Q2的两个相差180°的差分信号，经过该第三变压器T3将再次产生180°的相位差，此时的相位差为360°即0°，由此将两路差分信号转为一路单端信号，完成功率合成，以此获得高输出功率。
此外，通过第一电容C1、第二电容C2、第三电容C3、第四电容C4、第五电容C5、第一电感L1以及第三变压器T3共同组成输出匹配网络15，可以实现将高阻抗匹配至低阻抗，从而完成输出匹配功能。其中，第一电容C1和第二电容C2可以采用相同的电容元件实现，两者大小相同。
本实施例中，本实用新型的射频功率放大器100可适用于5G通信中的N77(3.3～4.2GHz)的功率放大器，通过在输入匹配网络11、级间匹配网络13以及输出匹配网络14采用变压器匹配的方式实现，能够显著的提高功率放大器的增益、输出功率，并解决了放大电路级间匹配较难的问题。参阅图3、图4和图5，其中图3是本实用新型的射频功率放大器的增益仿真波形图；图4是本实用新型的射频功率放大器的增益和增益压缩的对比波形图，其中曲线a表示增益，曲线b表示增益压缩；图5是本实用新型的射频功率放大器的功率附加效率的仿真波形图，通过图中的仿真波形图表明，在N77工作频段内，本实用新型的射频功率放大器增益为34～36dBm，输出功率1dB压缩点为37dBm，输出功率1dB压缩点处的功率附加效率为52.5％，输出功率回退至28.5dBm处的功率附加效率为18.9％、相邻频道泄漏比为-36.2dBc，具有较优的性能。
需要说明的是，本实用新型实施例中，第一级双路放大电路12采用两个第一晶体管Q1分别实现两路放大电路，在其他实时方式中，第一级双路放大电路12的每一路放大电路可以采用多个并联的第一晶体管Q1实现，每一路中多个并联的第一晶体管Q1的基极并联在一起，集电极并联在一起，发射极接地。 同理地，图1所示的实施例中，第二级双路放大电路14也采用两个第二晶体管Q2分别实现两路放大电路，在其他实时方式中，第二级双路放大电路14的每一路放大电路也可以采用多个并联的第二晶体管Q2实现，每一路放大电路中的多个并联的第二晶体管Q2的基极并联在一起，集电极并联在一起，发射极均接地。
本实用新型实施例中，所述输入匹配网络11还包括第六电容C6、第七电容C7、第八电容C8、第九电容C9以及第二电感L2。所述第六电容C6和第七电容C7的一端分别与所述第一变压器T1的两个输入端连接，所述第六电容C6和第七电容C7的另一端接地，所述第二电感L2串联在所述第一变压器T1的与地连接的输入端和地端之间，所述第八电容C8串联在所述第一变压器T1一个输出端和一个所述第一晶体管Q1的基极之间，所述第九电容C9串联在所述第一变压器T1的另一个输出端和另一个所述第一晶体管Q1的基极之间。因此，第六电容C6、第七电容C7、第八电容C8、第九电容C9、第二电感L2以及第二变压器T2共同组成输入匹配网络11，其中第八电容C8和第九电容C9可以采用相同的电容元件实现，两者大小相同，由此可确保两路信号为等大反相的，并且第八电容C8和第九电容C9可以调节第一级双路放大电路12的增益趋势，以及起到隔直电容的作用；而第六电容C6、第七电容C7以及第二电感L2可以调节和增加变压器的带宽，并且降低其插损。
进一步地，所述级间匹配网络13还包括第十电容C10、第十一电容C11、第十二电容C12、第十三电容C13、第三电感L3以及第四电感L4。所述第三电感L3串联在一个所述第一晶体管Q1的集电极和所述第二变压器T2的一个输入端之间，所述第十电容C10的一端和与所述第三电感L3连接的第一晶体管Q1的集电极连接，所述第十电容C10的另一端接地，所述第四电感L4串联在另一个所述第一晶体管Q1的集电极和所述第二变压器T2的另一个输入端之间，所第十一电容C11的一端和与所述第四电感L4连接的第一晶体管Q1的集电极连接，所述第十一电容C11的另一端接地，所述第十二电容C12串联在所述第二变压器T2的一个输出端和一个所述第二晶体管Q2的基极之间，所述第十三电容C13串联在所述第二变压器T2的另一个输出端和另一个所述第二晶体管Q2的基极之间。
由此，第十电容C10、第十一电容C11、第十二电容C12、第十三电容C13、第三电感L3、第四电感L4以及第二变压器T2共同组成级间匹配网络13，同理地，其中两个电容C12和C13大小相同，可确保两路信号为等大反相的，并且电容C12和C13可以调节第二级放大电路14的增益趋势，以及起到隔直电容的作用；电容C10、C11和电感L3、L4可以调节和增加变压器的带宽，并且降低其插损。此外，电容C10和电容C11可以采用相同电容元件实现，两者大小相同。
本实用新型的实施例中，每个所述第一晶体管Q1和第二晶体管Q2的基极还连接有偏置电路，如图1所示，第一晶体管Q1的基极连接有第一偏置电路161，第二晶体管Q2的基极连接有第二偏置电路162，其中第一偏置电路161和第二偏置电路162的结构可以相同也可以不相同，只要能提供合适的偏置电压即可。本实施例中，以第一偏置电路161和第二偏置电路162的结构相同为例，参阅图2，偏置电路的结构具体包括第三晶体管Q3、第四晶体管Q4、第五晶体管Q5、第一电阻R1、第二电阻R2、第三电阻R3以及第十四电容C14。
所述第三晶体管Q3的基极和集电极、所述第四晶体管Q4的基极、所述第一电阻R1的一端以及所述第十四电容C14的一端相连接；所述第一电阻R1的另一端连接供电电压Vreg，所述第三晶体管Q3的发射极、所述第五晶体管Q5的集电极和基极相连接，所述第五晶体管Q5的发射极与第二电阻R2的一端连接，所述第二电阻R2的另一端接地，所述第十四电容C14的另一端接地，所述第四晶体管Q4的集电极连接供电电压Vbat，所述第四晶体管Q4的发射极与第三电阻R3的一端连接，所述第三电阻R3的另一端与对应的第一晶体管Q1或第二晶体管Q2的基极连接。
其中，第一电阻R1和第二电阻R2为分压电阻，第三电阻R3为热效应抑制电阻，I 1、I 2为电流，第十四电容C14为滤波电容。第三晶体管Q3和第五晶体管Q5构成钳位电压，使得电流I 2为稳定电流，调节第一电阻R1和第二电阻R2的大小可调节I 2的大小。第三晶体管Q3和第四晶体管Q4组成电流镜，由于第四晶体管Q4的放大功能，第四晶体管Q4的发射极电流被镜像放大，因I 2为稳定电流，故I 1＝βI 2。当输入功率增大，功率放大器处于大功率工作状态时，第一晶体管Q1或第二晶体管Q2的直流电流增加，因晶体管自热效应和二极管 整流特性，第一晶体管Q1或第二晶体管Q2的基极电位会下降，射频线路上信号泄露进偏置电路。由于第十四电容C14的存在，信号依次经过第四晶体管Q4的发射极和基极、第十四电容C14到地。因此第四晶体管Q4的基极电位保持不变，从而功率放大器100的线性度得到有效提高。第四晶体管Q4的基极和发射极由于整流作用，该基极和发射极之间的电压降低，而由于第四晶体管Q4的基极电位保持不变，因此对第一晶体管Q1或第二晶体管Q2的基极电压降低进行有效补偿，使得第一晶体管Q1或第二晶体管Q2在高输入、输出功率状态下，保持静态工作点不变，因此增益压缩得到有效抑制。
通过本实施例的射频功率放大器，可以优化级间匹配和整体匹配的***回波损耗，提高射频功率放大器的输出功率，并且使得射频功率放大器的相邻频道泄漏比较好，在输出功率为28.5dBm处，相邻频道泄漏比小于-36.2dBc。
以上对本实用新型实施例所提供的一种射频功率放大器进行了详细介绍，本文中应用了具体个例对本实用新型的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本实用新型的方法及其核心思想；同时，对于本领域的技术人员，依据本实用新型的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本实用新型的限制。

Claims (6)

  1. 一种射频功率放大器，其特征在于，包括输入匹配网络、第一级双路放大电路、级间匹配网络、第二级双路放大电路以及输出匹配网络；
    其中，所述输入匹配网络包括一个第一变压器T1，所述级间匹配网络包括一个第二变压器T2，所述输出匹配网络包括一个第三变压器T3、第一电容C1、第二电容C2、第三电容C3、第四电容C4、第五电容C5以及第一电感L1；
    所述第一变压器T1的两个输入端分别连接射频输入信号RFin和地端，所述第一变压器T1的两个输出端分别连接所述第一级双路放大电路的两个输入端，以将单端的所述射频输入信号RFin变为一对差分信号，所述第一级双路放大电路的两个输出端分别连接所述第二变压器T2的两个输入端，所述第二变压器T2的两个输出端分别连接所述第二级双路放大电路的两个输入端，所述第二级双路放大电路的两个输出端分别连接所述第三变压器T3的两个输入端，其中所述第一电容C1和第二电容C2的一端分别与所述第三变压器T3的两个输入端连接，所述第一电容C1和第二电容C2的另一端接地，所述第三电容C3的一端和所述第四电容C4的一端均与所述第三变压器T3的一个输出端连接，所述第三电容C3的另一端接地，所述第四电容C4的另一端、所述第五电容C5的一端以及所述第一电感L1的一端相连接，所述第五电容C5的另一端接地，所述第一电感L1的另一端输出射频输出信号RFout，所述第三变压器T3的另一个输出端接地。
  2. 根据权利要求1所述的射频功率放大器，其特征在于，所述输入匹配网络还包括第六电容C6、第七电容C7、第八电容C8、第九电容C9以及第二电感L2；
    所述第六电容C6和第七电容C7的一端分别与所述第一变压器T1的两个输入端连接，所述第六电容C6和第七电容C7的另一端接地，所述第二电感L2串联在所述第一变压器T1的与地连接的输入端和地端之间，所述第八电容C8串联在所述第一变压器T1的一个输出端和所述第一级双路放大电路的一个输入端之间，所述第九电容C9串联在所述第一变压器T1的另一个输出端和所述第一级双路放大电路的另一个输入端之间。
  3. 根据权利要求1所述的射频功率放大器，其特征在于，所述级间匹配网 络还包括第十电容C10、第十一电容C11、第十二电容C12、第十三电容C13、第三电感L3以及第四电感L4；
    所述第三电感L3串联在所述第一级双路放大电路的一个输出端和所述第二变压器T2的一个输入端之间，所述第十电容C10的一端连接在所述第三电感L3的一端和与所述第三电感L3连接的第一级双路放大电路的输出端之间，所述第十电容C10的另一端接地，所述第四电感L4串联在所述第一级双路放大电路的另一个输出端和所述第二变压器T2的另一个输入端之间，所第十一电容C11的一端连接在所述第四电感L4的一端和与所述第四电感L4连接的第一级双路放大电路的输出端之间，所述第十一电容C11的另一端接地，所述第十二电容C12串联在所述第二变压器T2的一个输出端和所述第二级双路放大电路的一个输入端之间，所述第十三电容C13串联在所述第二变压器T2的另一个输出端和所述第二级放大电路的另一个输入端之间。
  4. 根据权利要求1所述的射频功率放大器，其特征在于，所述第一级双路放大电路包括两个第一晶体管Q1，所述第二级双路放大电路包括两个第二晶体管Q2；
    所述两个第一晶体管Q1的基极分别为所述第一级双路放大电路的两个输入端，所述两个第一晶体管Q1的集电极分别为所述第一级双路放大电路的两个输出端，所述两个第一晶体管Q1的发射极接地；所述两个第二晶体管Q2的基极分别为所述第二级双路放大电路的两个输入端，所述两个第二晶体管Q2的集电极分别为所述第二级双路放大电路的两个输出端，所述两个第二晶体管Q2的发射极接地。
  5. 根据权利要去4所述的射频功率放大器，其特征在于，所述第一晶体管Q1和所述第二晶体管Q2的基极还连接有偏置电路；
    所述偏置电路包括第三晶体管Q3、第四晶体管Q4、第五晶体管Q5、第一电阻R1、第二电阻R2、第三电阻R3以及第十四电容C14；
    所述第三晶体管Q3的基极和集电极、所述第四晶体管Q4的基极、所述第一电阻R1的一端以及所述第十四电容C14的一端相连接；所述第一电阻R1的另一端连接供电电压Vreg，所述第三晶体管Q3的发射极、所述第五晶体管Q5的集电极和基极相连接，所述第五晶体管Q5的发射极与第二电阻R2的一 端连接，所述第二电阻R2的另一端接地，所述第十四电容C14的另一端接地，所述第四晶体管Q4的集电极连接供电电压Vbat，所述第四晶体管Q4的发射极与第三电阻R3的一端连接，所述第三电阻R3的另一端与对应的第一晶体管Q1或第二晶体管Q2的基极连接。
  6. 根据权利要求1所述的射频功率放大器，其特征在于，所述第一变压器T1、第二变压器T2以及第三变压器T3均为对称互绕式变压器。
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