WO2023045542A1 - 应用于5g通信***的射频功率放大器及射频前端架构 - Google Patents

应用于5g通信***的射频功率放大器及射频前端架构 Download PDF

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WO2023045542A1
WO2023045542A1 PCT/CN2022/108108 CN2022108108W WO2023045542A1 WO 2023045542 A1 WO2023045542 A1 WO 2023045542A1 CN 2022108108 W CN2022108108 W CN 2022108108W WO 2023045542 A1 WO2023045542 A1 WO 2023045542A1
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transformer
transistor
input
output
capacitor
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PCT/CN2022/108108
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English (en)
French (fr)
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谢志远
赵宇霆
郭嘉帅
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深圳飞骧科技股份有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

  • the utility model relates to the technical field of power amplifiers, in particular to a radio frequency power amplifier and a radio frequency front-end architecture applied to a 5G communication system.
  • the power amplifier In the transceiver of 5G communication, the power amplifier (PA) has a great influence on the performance of the entire transceiver. Its function is to amplify the output signal, and the amplified signal is sent by the antenna. The output power of the power amplifier directly determines the strength of the signal transmitted to the space, that is, the effective coverage area of wireless communication. High output power is the basic requirement for the design of RF power amplifiers, and the 5G communication system requires RF power amplifiers to have greater output power.
  • Increasing the output power of the RF power amplifier can be done by increasing its output current swing or output voltage swing, and increasing the output current swing can be achieved by increasing the area of a single transistor or connecting multiple transistors in parallel, but this will make the transistor The input and output impedances are reduced, making matching more difficult.
  • the embodiment of the utility model provides a radio frequency power amplifier and a radio frequency front-end architecture applied to a 5G communication system, which can reduce the matching difficulty and increase the output power of the radio frequency power amplifier.
  • the embodiment of the utility model provides a radio frequency power amplifier applied to a 5G communication system, including an input transformer matching network, a first-stage dual amplifier circuit, an inter-stage LC matching network, a second Level dual amplifier circuit and output transformer matching network;
  • the input transformer matching network includes a first transformer T1
  • the interstage LC matching network includes two ⁇ -type matching units and two DC blocking capacitors C
  • the output transformer matching network includes a second transformer T2;
  • the two input terminals of the first transformer T1 are respectively connected to the radio frequency input signal RFin and the ground terminal, and the two output terminals of the first transformer T1 are respectively connected to the two input terminals of the first-stage dual amplifier circuit, so as to The single-ended radio frequency input signal RFin is changed into a pair of differential signals, and the two output terminals of the first-stage dual amplifier circuit are respectively connected to the input terminals of the two ⁇ -type matching units, and the two ⁇ -type
  • the output ends of the matching unit are respectively connected to one ends of the two DC blocking capacitors C, and the other ends of the two DC blocking capacitors C1 are respectively connected to the two input ends of the second-stage dual amplifier circuit, and the first
  • the two output terminals of the secondary dual-channel amplifier circuit are respectively connected to the two input terminals of the second transformer T2, one output terminal of the second transformer T2 is used to output the radio frequency signal RFout, and the other of the second transformer T2 One output is grounded.
  • the input transformer matching network further includes a first capacitor C1, a second capacitor C2, two third capacitors C3 and a first inductor L1;
  • One end of the first capacitor C1 and one end of the second capacitor C2 are respectively connected to the two input ends of the first transformer T1, and the other end of the first capacitor C1 is connected to the other end of the second capacitor C1. Both ends are grounded, the input terminal connected to the ground terminal in the first transformer T1 is grounded through the first inductor L1, and the two output terminals of the first transformer T1 are respectively connected to the first transformer T1 through the two third capacitors C3.
  • the two input terminals of the first-stage dual-channel amplifier circuit are connected.
  • the ⁇ -type matching unit includes a second inductor L2, a third inductor L3, and a fourth capacitor C4, one end of the second inductor L2 is connected to one end of the fourth capacitor C4, and the connection node is the The input terminal of the ⁇ -type matching unit, the other end of the second inductance L2 is grounded, the other end of the fourth capacitor C4 is connected to one end of the third inductance L3 and the connection node is the output of the ⁇ -type matching unit end, and the other end of the third inductor L3 is grounded.
  • a resistor R0 is connected in series between the DC blocking capacitor C and the input terminal of the second stage dual amplifier circuit.
  • the output transformer matching network further includes two fifth capacitors C5, one end of the two fifth capacitors is respectively connected to the two input ends of the second transformer T2, and the two fifth capacitors The other end of the ground.
  • the first-stage dual amplifier circuit includes two first transistors Q1, and the second-stage dual amplifier circuit includes two second transistors Q2;
  • the bases of the two first transistors Q1 are respectively the two input terminals of the first-stage dual amplifier circuit, and the collectors of the two first transistors Q1 are respectively the two input terminals of the first-stage dual amplifier circuit.
  • the two output terminals of the two first transistors Q1 are grounded;
  • the bases of the two second transistors Q2 are respectively the two input terminals of the second-stage dual amplifier circuit, and the two The collectors of the two second transistors Q2 are respectively the two output terminals of the second-stage dual amplifier circuit, and the emitters of the two second transistors Q2 are grounded.
  • the bases of the first transistor Q1 and the second transistor Q2 are further connected with a bias circuit
  • the bias circuit includes a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a first resistor R1, a second resistor R2, a third resistor R3 and a sixth capacitor C6;
  • the base and collector of the third transistor Q3, the base of the fourth transistor Q4, one end of the first resistor R1 and one end of the sixth capacitor C6 are connected; the first resistor R1 The other end is connected to the power supply voltage Vreg, the emitter of the third transistor Q3, the collector and the base of the fifth transistor Q5 are connected, the emitter of the fifth transistor Q5 is connected to one end of the second resistor R2, The other end of the second resistor R2 is grounded, the other end of the sixth capacitor C6 is grounded, the collector of the fourth transistor Q4 is connected to the power supply voltage Vbat, the emitter of the fourth transistor Q4 is connected to the third resistor R3 One end of the third resistor R3 is connected to the base of the corresponding first transistor Q1 or second transistor Q2.
  • an embodiment of the present utility model provides a radio frequency front-end architecture applied to a 5G communication system, including the radio frequency power amplifier described in any one of the foregoing.
  • the radio frequency power amplifier of the present utility model includes an input transformer matching network, a first-stage dual-channel amplifier circuit, an inter-stage LC matching network, a second-stage dual-channel amplifier circuit, and an output transformer matching network; wherein, the input The transformer matching network includes a first transformer T1, the interstage LC matching network includes two ⁇ -type matching units and two DC blocking capacitors C, the output transformer matching network includes a second transformer T2; the first transformer The two input terminals of T1 are respectively connected to the radio frequency input signal RFin and the ground terminal, and the two output terminals of the first transformer T1 are respectively connected to the two input terminals of the first-stage dual amplifier circuit, so that the single-ended The radio frequency input signal RFin becomes a pair of differential signals, and the two output terminals of the first-stage dual amplifying circuit are respectively connected to the input terminals of the two ⁇ -type matching units, and the output terminals of the two ⁇ -type matching units respectively connected to one end of the two DC blocking capacitors C, and the input transformer matching
  • Fig. 1 is a circuit diagram of a radio frequency power amplifier applied to a 5G communication system provided by an embodiment of the present invention
  • Fig. 2 is a circuit diagram of the bias circuit provided by the embodiment of the present invention.
  • the radio frequency power amplifier 100 of the present utility model can be applied to a power amplifier working in the N77 (3.3-4.2GHz) frequency band in 5G communication.
  • the radio frequency power amplifier 100 applied to the 5G communication system provided by the embodiment of the utility model includes an input transformer matching network 11 connected in series, a first-stage dual-channel amplifier circuit 12, an inter-stage LC matching network 13, The second stage dual amplifier circuit 14 and the output transformer matching network 15 .
  • the input transformer matching network 11 includes a first transformer T1
  • the first-stage dual amplifying circuit 12 includes two input terminals and two output terminals, and one input terminal and a corresponding output terminal form an amplifying circuit
  • the interstage LC matching network 13 includes two ⁇ -type matching units 131 and two DC blocking capacitors C
  • the second stage dual amplifier circuit 14 includes two input terminals and two output terminals, one input terminal and A corresponding output terminal forms an amplifying circuit
  • the output matching network 15 includes a second transformer T2.
  • the two input terminals of the first transformer T1 are respectively connected to the radio frequency input signal RFin and the ground terminal, and the two output terminals of the first transformer T1 are respectively connected to the two input terminals of the first-stage dual amplifying circuit 12,
  • the two output ends of the first-stage dual amplifying circuit 12 are respectively connected to the input ends of the two ⁇ -type matching units 131, and the two The output terminals of each ⁇ -type matching unit 131 are respectively connected to one end of the two DC blocking capacitors C, and the other ends of the two DC blocking capacitors C1 are respectively connected to the two inputs of the second stage dual amplifier circuit 14 terminal, the two output terminals of the second stage dual amplifier circuit 14 are respectively connected to the two input terminals of the second transformer T2, and one output terminal of the second transformer T2 is used to output the radio frequency signal RFout, the The other output end of the second transformer T2 is grounded.
  • the transformation from a single-ended signal to a differential signal is realized through the first transformer T1, and then the combination of two differential signals is realized through the second transformer T2.
  • the structure avoids the difficult matching problem caused by the reduction of input and output impedance caused by the parallel connection of multiple transistors, and the voltage output swing is improved through the power combination technology, that is, the differential structure, thereby increasing the output power of the RF power amplifier.
  • both the first-stage dual amplifying circuit 12 and the second-stage dual amplifying circuit 14 are implemented using HBT transistors, wherein the first-stage dual amplifying circuit 12 includes two first transistors Q1, and the first-stage dual amplifying circuit 14 includes two first transistors Q1.
  • the two-stage dual amplifier circuit 14 includes two second transistors Q2.
  • the bases of the two first transistors Q1 are respectively the two input terminals of the first-stage dual amplifier circuit 12, and the collectors of the two first transistors Q1 are respectively the two input terminals of the first-stage dual amplifier circuit 12.
  • the two output terminals of the circuit 12, the emitters of the two first transistors Q1 are grounded; the bases of the two second transistors Q2 are respectively the two input terminals of the second-stage dual amplifier circuit 14, The collectors of the two second transistors Q2 are respectively the two output terminals of the second-stage dual amplifier circuit 14 , and the emitters of the two second transistors Q2 are grounded.
  • the first-stage dual-channel amplifier circuit and the second-stage dual-channel amplifier circuit may also be implemented by CMOS tubes or other power tubes.
  • the first transformer T1 is used to convert the single-ended radio frequency input signal RFin into a pair of differential signals, which are respectively output to the two first transistors Q1 for amplification, wherein the pair of differential signals have the same magnitude and a phase difference of 180°.
  • the pair of differential signals is transmitted to the two second transistors Q2 after passing through the inter-stage LC matching network 13 , and then transmitted to the second transformer T2 after being amplified by the two second transistors Q2 .
  • One output terminal of the second transformer T2 outputs a radio frequency output signal RFout, and the other output terminal of the second transformer T2 is grounded.
  • the second transformer T2 is a transformer for converting a differential signal into a single-ended signal, and the two phase differences are 180 ° differential signal, through the second transformer T2 will generate a phase difference of 180 ° again, the phase difference at this time is 360 ° or 0 °, thereby converting the two differential signals into a single-ended signal to complete the power combination, This results in high output power.
  • the first-stage dual-channel amplifying circuit 12 uses two first transistors Q1 to respectively implement two-channel amplifying circuits.
  • each of the first-stage dual-channel amplifying circuits 12 One amplifying circuit can be realized by using a plurality of first transistors Q1 connected in parallel, the bases of the first transistors Q1 connected in parallel in each circuit are connected in parallel, the collectors are connected in parallel, and the emitters are grounded.
  • the second-stage dual-channel amplifier circuit 14 also uses two second transistors Q2 to realize the two-channel amplifier circuits respectively.
  • the second-stage dual-channel amplifier circuit 14 Each of the amplifying circuits can also be realized by a plurality of second transistors Q2 connected in parallel, the bases of the multiple second transistors Q2 connected in parallel in each amplifying circuit are connected in parallel, the collectors are connected in parallel, and the emitters are all grounded.
  • the input transformer matching network 11 further includes a first capacitor C1 , a second capacitor C2 , two third capacitors C3 and a first inductor L1 .
  • One end of the first capacitor C1 and one end of the second capacitor C2 are respectively connected to the two input ends of the first transformer T1, and the other end of the first capacitor C1 is connected to the other end of the second capacitor C1.
  • the input terminal connected to the ground terminal in the first transformer T1 is grounded through the first inductor L1
  • the two output terminals of the first transformer T1 are respectively connected to the two third capacitors C3 and the two The base of the first transistor Q1 is connected, that is, the third capacitor C3 is connected in series between the input terminal of the first transformer T1 and the base of the first transistor Q1.
  • the third capacitor C3 is connected in series between the input terminal of the first transformer T1 and the base of the first transistor Q1.
  • the ⁇ -type matching unit 131 includes a second inductor L2, a third inductor L3, and a fourth capacitor C4, one end of the second inductor L2 is connected to one end of the fourth capacitor C4, and the connection node is the ⁇ -type matching
  • One end of the DC blocking capacitor C is connected to the output end of the ⁇ -type matching unit 131, and the other end of the DC blocking capacitor C is connected to the base of the second transistor Q2 through a resistor R0, that is, at the DC blocking A resistor R0 is also connected in series between the capacitor C and the input terminal of the second-stage dual amplifier circuit.
  • the output transformer matching network 15 also includes two fifth capacitors C5, one end of the two fifth capacitors is respectively connected to the two input ends of the second transformer T2, and the other end of the two fifth capacitors grounded.
  • the bases of each of the first transistor Q1 and the second transistor Q2 are also connected with a bias circuit, as shown in FIG. 1 , the bases of the first transistor Q1 are connected with a first bias circuit circuit 161, the base of the second transistor Q2 is connected to a second bias circuit 162, wherein the structures of the first bias circuit 161 and the second bias circuit 162 may be the same or different, as long as a suitable bias voltage can be provided That's it.
  • the structure of the bias circuit specifically includes a third transistor Q3, a fourth transistor Q4, and a fifth transistor Q5. , a first resistor R1, a second resistor R2, a third resistor R3 and a sixth capacitor C6.
  • the base and collector of the third transistor Q3, the base of the fourth transistor Q4, one end of the first resistor R1 and one end of the sixth capacitor C6 are connected; the first resistor R1 The other end is connected to the power supply voltage Vreg, the emitter of the third transistor Q3, the collector and the base of the fifth transistor Q5 are connected, the emitter of the fifth transistor Q5 is connected to one end of the second resistor R2, The other end of the second resistor R2 is grounded, the other end of the sixth capacitor C6 is grounded, the collector of the fourth transistor Q4 is connected to the power supply voltage Vbat, the emitter of the fourth transistor Q4 is connected to the third resistor R3 One end of the third resistor R3 is connected to the base of the corresponding first transistor Q1 or second transistor Q2.
  • the first resistor R1 and the second resistor R2 are voltage dividing resistors
  • the third resistor R3 is a thermal effect suppression resistor
  • I 1 and I 2 are currents
  • the sixth capacitor C6 is a filter capacitor.
  • the third transistor Q3 and the fifth transistor Q5 form a clamping voltage, so that the current I2 is a stable current, and the magnitude of I2 can be adjusted by adjusting the magnitude of the first resistor R1 and the second resistor R2.
  • the DC current of the first transistor Q1 or the second transistor Q2 increases. Due to the self-heating effect of the transistor and the rectification characteristics of the diode, the base of the first transistor Q1 or the second transistor Q2 The potential will drop and the signal on the RF line will leak into the bias circuit. Due to the existence of the sixth capacitor C6, the signal passes through the emitter and base of the fourth transistor Q4 and the sixth capacitor C6 to ground in sequence. Therefore, the base potential of the fourth transistor Q4 remains unchanged, so that the linearity of the power amplifier 100 is effectively improved.
  • the voltage between the base and the emitter of the fourth transistor Q4 decreases, and since the base potential of the fourth transistor Q4 remains unchanged, the first transistor Q1 or the second transistor
  • the reduction of the base voltage of Q2 is effectively compensated, so that the static operating point of the first transistor Q1 or the second transistor Q2 remains unchanged under the state of high input and output power, so that the gain compression is effectively suppressed.
  • the insertion return loss of inter-stage matching and overall matching can be optimized, the output power of the RF power amplifier can be improved, and the adjacent channel leakage of the RF power amplifier is better, at an output power of 28.5dBm At , the adjacent channel leakage ratio is less than -36.2dBc.
  • An embodiment of the present invention further provides a radio frequency front-end architecture, including the radio frequency power amplifier described in any one of the above embodiments.
  • a radio frequency power amplifier and a radio frequency front-end architecture applied to a 5G communication system provided by the embodiment of the utility model have been introduced in detail above.
  • a specific example has been used to illustrate the principle and implementation of the utility model.
  • the above implementation The description of the example is only used to help understand the method of the present utility model and its core idea; at the same time, for those skilled in the art, according to the idea of the present utility model, there will be changes in the specific implementation and scope of application.
  • the contents of this specification should not be construed as limiting the present utility model.

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Abstract

本实用新型实施例公开了一种应用于5G通信***的射频功率放大器，包括输入变压器匹配网络、第一级双路放大电路、级间LC匹配网络、第二级双路放大电路以及输出变压器匹配网络；其中，所述输入变压器匹配网络包括一个第一变压器T1，所述级间LC匹配网络包括两个π型匹配单元和两个隔直电容C，所述输出变压器匹配网络包括一个第二变压器T2，所述第一变压器T1用于将单端的所述射频输入信号RFin变为一对差分信号，该从差分信号依次通过所述第一级双路放大电路和第二级双路放大电路的放大后传输至第二变压器T2，所述第二变压器T2用于将两路差分信号合成为一路输出，通过上述方式，能够降低匹配难度，提高射频功率放大器的输出功率。

Description

应用于5G通信***的射频功率放大器及射频前端架构 技术领域
本实用新型涉及功率放大器技术领域，尤其涉及一种应用于5G通信***的射频功率放大器及射频前端架构。
背景技术
在5G通信的收发机中，功率放大器(PA)对整个收发机的性能影响非常大，其作用是将输出信号进行放大，由天线将被放大的信号发出。功率放大器的输出功率直接决定了信号发射到空间的强度，即无线通信的有效覆盖面积，高输出功率是射频功率放大器设计的基本要求，而5G通信***需射频功率放大器有更大的输出功率。提高射频功率放大器的输出功率可通过提高其输出电流摆幅或者输出电压摆幅进行，而提高输出电流摆幅可通过增大单个晶体管面积或将多个晶体管并联来实现，然而这会使得晶体管的输入和输出阻抗减小，增加了匹配的难度。
实用新型内容
本实用新型实施例提供一种应用于5G通信***的射频功率放大器及射频前端架构，能够降低匹配难度，提高射频功率放大器的输出功率。
为了解决上述技术问题，第一方面，本实用新型实施例提供一种应用于5G通信***的射频功率放大器，包括输入变压器匹配网络、第一级双路放大电路、级间LC匹配网络、第二级双路放大电路以及输出变压器匹配网络；
其中，所述输入变压器匹配网络包括一个第一变压器T1，所述级间LC匹配网络包括两个π型匹配单元和两个隔直电容C，所述输出变压器匹配网络包括一个第二变压器T2；
所述第一变压器T1的两个输入端分别连接射频输入信号RFin和地端，所述第一变压器T1的两个输出端分别连接所述第一级双路放大电路的两个输入端，以将单端的所述射频输入信号RFin变为一对差分信号，所述第一级双路放大电路的两个输出端分别连接所述两个π型匹配单元的输入端，所述两个π型匹配单元的输出端分别与所述两个隔直电容C的一端连接，所述两个隔直电容 C1的另一端分别连接所述第二级双路放大电路的两个输入端，所述第二级双路放大电路的两个输出端分别连接所述第二变压器T2的两个输入端，所述第二变压器T2的一个输出端用于输出射频信号RFout，所述第二变压器T2的另一个输出端接地。
更进一步地，所述输入变压器匹配网络还包括第一电容C1、第二电容C2、两个第三电容C3以及第一电感L1；
所述第一电容C1的一端和所述第二电容C2的一端分别与所述第一变压器T1的两个输入端连接，所述第一电容C1的另一端和所述第二电容C1的另一端均接地，所述第一变压器T1中与地端连接的输入端通过第一电感L1接地，所述第一变压器T1的两个输出端分别通过所述两个第三电容C3与所述第一级双路放大电路的两个输入端连接。
更进一步地，所述π型匹配单元包括第二电感L2、第三电感L3以及第四电容C4，所述第二电感L2的一端和所述第四电容C4的一端连接且连接节点为所述π型匹配单元的输入端，所述第二电感L2的另一端接地，所述第四电容C4的另一端和所述第三电感L3的一端连接且连接节点为所述π型匹配单元的输出端，所述第三电感L3的另一端接地。
更进一步地，在所述隔直电容C和所述第二级双路放大电路的输入端之间还串联有电阻R0。
更进一步地，所述输出变压器匹配网络还包括两个第五电容C5，所述两个第五电容的一端分别与所述第二变压器T2的两个输入端连接，所述两个第五电容的另一端接地。
更进一步地，所述第一级双路放大电路包括两个第一晶体管Q1，所述第二级双路放大电路包括两个第二晶体管Q2；
所述两个第一晶体管Q1的基极分别为所述第一级双路放大电路的两个输入端，所述两个第一晶体管Q1的集电极分别为所述第一级双路放大电路的两个输出端，所述两个第一晶体管Q1的发射极接地；所述两个第二晶体管Q2的基极分别为所述第二级双路放大电路的两个输入端，所述两个第二晶体管Q2的集电极分别为所述第二级双路放大电路的两个输出端，所述两个第二晶体管Q2的发射极接地。
更进一步地，所述第一晶体管Q1和所述第二晶体管Q2的基极还连接有偏置电路；
所述偏置电路包括第三晶体管Q3、第四晶体管Q4、第五晶体管Q5、第一电阻R1、第二电阻R2、第三电阻R3以及第六电容C6；
所述第三晶体管Q3的基极和集电极、所述第四晶体管Q4的基极、所述第一电阻R1的一端以及所述第六电容C6的一端相连接；所述第一电阻R1的另一端连接供电电压Vreg，所述第三晶体管Q3的发射极、所述第五晶体管Q5的集电极和基极相连接，所述第五晶体管Q5的发射极与第二电阻R2的一端连接，所述第二电阻R2的另一端接地，所述第六电容C6的另一端接地，所述第四晶体管Q4的集电极连接供电电压Vbat，所述第四晶体管Q4的发射极与第三电阻R3的一端连接，所述第三电阻R3的另一端与对应的第一晶体管Q1或第二晶体管Q2的基极连接。
第二方面，本实用新型实施例提供一种应用于5G通信***的射频前端架构，包括上述任一项所述的射频功率放大器。
有益效果：本实用新型的射频功率放大器中，包括输入变压器匹配网络、第一级双路放大电路、级间LC匹配网络、第二级双路放大电路以及输出变压器匹配网络；其中，所述输入变压器匹配网络包括一个第一变压器T1，所述级间LC匹配网络包括两个π型匹配单元和两个隔直电容C，所述输出变压器匹配网络包括一个第二变压器T2；所述第一变压器T1的两个输入端分别连接射频输入信号RFin和地端，所述第一变压器T1的两个输出端分别连接所述第一级双路放大电路的两个输入端，以将单端的所述射频输入信号RFin变为一对差分信号，所述第一级双路放大电路的两个输出端分别连接所述两个π型匹配单元的输入端，所述两个π型匹配单元的输出端分别与所述两个隔直电容C的一端连接，所述两个隔直电容C1的另一端分别连接所述第二级双路放大电路的两个输入端，所述第二级双路放大电路的两个输出端分别连接所述第二变压器T2的两个输入端，所述第二变压器T2的一个输出端用于输出射频信号RFout，所述第二变压器T2的另一个输出端接地，通过上述方式，可以避免多个晶体管并联导致的输入输出阻抗减小而造成匹配困难问题，可以降低各级匹配网络的匹配难度，有利于提高输出功率。
附图说明
下面结合附图，通过对本实用新型的具体实施方式详细描述，将使本实用新型的技术方案及其有益效果显而易见。
图1是本实用新型实施例提供的应用于5G通信***的射频功率放大器的电路图；
图2是本实用新型实施例提供的偏置电路的电路图。
具体实施方式
请参照图式，其中相同的组件符号代表相同的组件，本实用新型的原理是以实施在一适当的运算环境中来举例说明。以下的说明是基于所例示的本实用新型具体实施例，其不应被视为限制本实用新型未在此详述的其它具体实施例。
本实用新型的射频功率放大器100可适用于5G通信中工作于N77(3.3～4.2GHz)频段的功率放大器。参阅图1，本实用新型实施例提供的应用于5G通信***的射频功率放大器100中，包括依次串联连接的输入变压器匹配网络11、第一级双路放大电路12、级间LC匹配网络13、第二级双路放大电路14以及输出变压器匹配网络15。
其中，所述输入变压器匹配网络11包括一个第一变压器T1，所述第一级双路放大电路12包括两个输入端和两个输出端，一个输入端和对应的一个输出端形成一路放大电路，所述级间LC匹配网络13包括两个π型匹配单元131和两个隔直电容C，所述第二级双路放大电路14包括两个输入端和两个输出端，一个输入端和对应的一个输出端形成一路放大电路，所述输出匹配网络15包括一个第二变压器T2。
所述第一变压器T1的两个输入端分别连接射频输入信号RFin和地端，所述第一变压器T1的两个输出端分别连接所述第一级双路放大电路12的两个输入端，以将单端的所述射频输入信号RFin变为一对差分信号，所述第一级双路放大电路12的两个输出端分别连接所述两个π型匹配单元131的输入端，所述两个π型匹配单元131的输出端分别与所述两个隔直电容C的一端连接，所述两个隔直电容C1的另一端分别连接所述第二级双路放大电路14的两个输入端，所述第二级双路放大电路14的两个输出端分别连接所述第二变压器T2的两个输入端，所述第二变压器T2的一个输出端用于输出射频信号RFout，所述 第二变压器T2的另一个输出端接地。
因此，本实施例中，通过第一变压器T1实现单端信号到差分信号的转变，再通过第二变压器T2实现两路差分信号的合成，由此，通过在输入端和输出端均采用变压器匹配结构，避免了多个晶体管并联导致的输入输出阻抗减小而导致的难匹配问题，又通过功率合成技术即差分结构提高了电压输出摆幅，进而提高了射频功率放大器的输出功率。
可选地，所述第一级双路放大电路12和第二级双路放大电路14均采用HBT晶体管实现，其中，第一级双路放大电路12包括两个第一晶体管Q1，所述第二级双路放大电路14包括两个第二晶体管Q2。所述两个第一晶体管Q1的基极分别为所述第一级双路放大电路12的两个输入端，所述两个第一晶体管Q1的集电极分别为所述第一级双路放大电路12的两个输出端，所述两个第一晶体管Q1的发射极接地；所述两个第二晶体管Q2的基极分别为所述第二级双路放大电路14的两个输入端，所述两个第二晶体管Q2的集电极分别为所述第二级双路放大电路14的两个输出端，所述两个第二晶体管Q2的发射极接地。当然，在其他实施方式中，第一级双路放大电路和第二级双路放大电路也可以采用COMS管或者其他功率管实现。
所述第一变压器T1用以将单端的所述射频输入信号RFin变为一对差分信号分别输出给两个第一晶体管Q1进行放大，其中该一对差分信号大小相同相位相差180°。该对差分信号经过级间LC匹配网络13后传输至两个第二晶体管Q2，经两个第二晶体管Q2的放大后传输至第二变压器T2。所述第二变压器T2的一个输出端输出射频输出信号RFout，所述第二变压器T2的另一个输出端接地，因此，第二变压器T2为差分信号转为单端信号的变压器，两个相差180°的差分信号，经过该第二变压器T2将再次产生180°的相位差，此时的相位差为360°即0°，由此将两路差分信号转为一路单端信号，完成功率合成，以此获得高输出功率。
需要说明的是，本实用新型实施例中，第一级双路放大电路12采用两个第一晶体管Q1分别实现两路放大电路，在其他实时方式中，第一级双路放大电路12的每一路放大电路可以采用多个并联的第一晶体管Q1实现，每一路中多个并联的第一晶体管Q1的基极并联在一起，集电极并联在一起，发射极接地。 同理地，图1所示的实施例中，第二级双路放大电路14也采用两个第二晶体管Q2分别实现两路放大电路，在其他实时方式中，第二级双路放大电路14的每一路放大电路也可以采用多个并联的第二晶体管Q2实现，每一路放大电路中的多个并联的第二晶体管Q2的基极并联在一起，集电极并联在一起，发射极均接地。
继续参阅图1，本实用新型实施例中，所述输入变压器匹配网络11还包括第一电容C1、第二电容C2、两个第三电容C3以及第一电感L1。所述第一电容C1的一端和所述第二电容C2的一端分别与所述第一变压器T1的两个输入端连接，所述第一电容C1的另一端和所述第二电容C1的另一端均接地，所述第一变压器T1中与地端连接的输入端通过第一电感L1接地，所述第一变压器T1的两个输出端分别通过所述两个第三电容C3与两个所述第一晶体管Q1的基极连接，即在第一变压器T1的输入端和第一晶体管Q1的基极之间串联有第三电容C3。通过第三电容C3，可调节第二级放大电路增益的趋势。
所述π型匹配单元131包括第二电感L2、第三电感L3以及第四电容C4，所述第二电感L2的一端和所述第四电容C4的一端连接且连接节点为所述π型匹配单元131的输入端，所述第二电感L2的另一端接地，所述第四电容C4的另一端和所述第三电感L3的一端连接且连接节点为所述π型匹配单元131的输出端，所述第三电感L3的另一端接地。所述隔直电容C的一端所述π型匹配单元131的输出端连接，所述隔直电容C的另一端通过电阻R0与所述第二晶体管Q2的基极连接，即在所述隔直电容C和所述第二级双路放大电路的输入端之间还串联有电阻R0。通过在第二晶体管Q2的基极串联有电阻R0，有利于提高第二级双路放大电路的稳定性和优化输入回波损耗S11。
所述输出变压器匹配网络15还包括两个第五电容C5，所述两个第五电容的一端分别与所述第二变压器T2的两个输入端连接，所述两个第五电容的另一端接地。
本实用新型的实施例中，每个所述第一晶体管Q1和第二晶体管Q2的基极还连接有偏置电路，如图1所示，第一晶体管Q1的基极连接有第一偏置电路161，第二晶体管Q2的基极连接有第二偏置电路162，其中第一偏置电路161和第二偏置电路162的结构可以相同也可以不相同，只要能提供合适的偏置电 压即可。本实施例中，以第一偏置电路161和第二偏置电路162的结构相同为例，参阅图2，偏置电路的结构具体包括第三晶体管Q3、第四晶体管Q4、第五晶体管Q5、第一电阻R1、第二电阻R2、第三电阻R3以及第六电容C6。
所述第三晶体管Q3的基极和集电极、所述第四晶体管Q4的基极、所述第一电阻R1的一端以及所述第六电容C6的一端相连接；所述第一电阻R1的另一端连接供电电压Vreg，所述第三晶体管Q3的发射极、所述第五晶体管Q5的集电极和基极相连接，所述第五晶体管Q5的发射极与第二电阻R2的一端连接，所述第二电阻R2的另一端接地，所述第六电容C6的另一端接地，所述第四晶体管Q4的集电极连接供电电压Vbat，所述第四晶体管Q4的发射极与第三电阻R3的一端连接，所述第三电阻R3的另一端与对应的第一晶体管Q1或第二晶体管Q2的基极连接。
其中，第一电阻R1和第二电阻R2为分压电阻，第三电阻R3为热效应抑制电阻，I 1、I 2为电流，第六电容C6为滤波电容。第三晶体管Q3和第五晶体管Q5构成钳位电压，使得电流I 2为稳定电流，调节第一电阻R1和第二电阻R2的大小可调节I 2的大小。第三晶体管Q3和第四晶体管Q4组成电流镜，由于第四晶体管Q4的放大功能，第四晶体管Q4的发射极电流被镜像放大，因I 2为稳定电流，故I 1＝βI 2。当输入功率增大，功率放大器处于大功率工作状态时，第一晶体管Q1或第二晶体管Q2的直流电流增加，因晶体管自热效应和二极管整流特性，第一晶体管Q1或第二晶体管Q2的基极电位会下降，射频线路上信号泄露进偏置电路。由于第六电容C6的存在，信号依次经过第四晶体管Q4的发射极和基极、第六电容C6到地。因此第四晶体管Q4的基极电位保持不变，从而功率放大器100的线性度得到有效提高。第四晶体管Q4的基极和发射极由于整流作用，该基极和发射极之间的电压降低，而由于第四晶体管Q4的基极电位保持不变，因此对第一晶体管Q1或第二晶体管Q2的基极电压降低进行有效补偿，使得第一晶体管Q1或第二晶体管Q2在高输入、输出功率状态下，保持静态工作点不变，因此增益压缩得到有效抑制。
通过本实施例的射频功率放大器，可以优化级间匹配和整体匹配的***回波损耗，提高射频功率放大器的输出功率，并且使得射频功率放大器的相邻频道泄漏比较好，在输出功率为28.5dBm处，相邻频道泄漏比小于-36.2dBc。
本实用新型实施例还提供一种射频前端架构，包括上述任一实施例所述的射频功率放大器。
以上对本实用新型实施例所提供的一种应用于5G通信***的射频功率放大器及射频前端架构进行了详细介绍，本文中应用了具体个例对本实用新型的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本实用新型的方法及其核心思想；同时，对于本领域的技术人员，依据本实用新型的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本实用新型的限制。

Claims (8)

  1. 一种应用于5G通信***的射频功率放大器，其特征在于，包括输入变压器匹配网络、第一级双路放大电路、级间LC匹配网络、第二级双路放大电路以及输出变压器匹配网络；
    其中，所述输入变压器匹配网络包括一个第一变压器T1，所述级间LC匹配网络包括两个π型匹配单元和两个隔直电容C，所述输出变压器匹配网络包括一个第二变压器T2；
    所述第一变压器T1的两个输入端分别连接射频输入信号RFin和地端，所述第一变压器T1的两个输出端分别连接所述第一级双路放大电路的两个输入端，以将单端的所述射频输入信号RFin变为一对差分信号，所述第一级双路放大电路的两个输出端分别连接所述两个π型匹配单元的输入端，所述两个π型匹配单元的输出端分别与所述两个隔直电容C的一端连接，所述两个隔直电容C1的另一端分别连接所述第二级双路放大电路的两个输入端，所述第二级双路放大电路的两个输出端分别连接所述第二变压器T2的两个输入端，所述第二变压器T2的一个输出端用于输出射频信号RFout，所述第二变压器T2的另一个输出端接地。
  2. 根据权利要求1所述的应用于5G通信***的射频功率放大器，其特征在于，所述输入变压器匹配网络还包括第一电容C1、第二电容C2、两个第三电容C3以及第一电感L1；
    所述第一电容C1的一端和所述第二电容C2的一端分别与所述第一变压器T1的两个输入端连接，所述第一电容C1的另一端和所述第二电容C1的另一端均接地，所述第一变压器T1中与地端连接的输入端通过第一电感L1接地，所述第一变压器T1的两个输出端分别通过所述两个第三电容C3与所述第一级双路放大电路的两个输入端连接。
  3. 根据权利要求1所述的应用于5G通信***的射频功率放大器，其特征在于，所述π型匹配单元包括第二电感L2、第三电感L3以及第四电容C4，所述第二电感L2的一端和所述第四电容C4的一端连接且连接节点为所述π型匹配单元的输入端，所述第二电感L2的另一端接地，所述第四电容C4的另一端和所述第三电感L3的一端连接且连接节点为所述π型匹配单元的输出端，所 述第三电感L3的另一端接地。
  4. 根据权利要求1所述的应用于5G通信***的射频功率放大器，其特征在于，在所述隔直电容C和所述第二级双路放大电路的输入端之间还串联有电阻R0。
  5. 根据权利要求1所述的应用于5G通信***的射频功率放大器，其特征在于，所述输出变压器匹配网络还包括两个第五电容C5，所述两个第五电容的一端分别与所述第二变压器T2的两个输入端连接，所述两个第五电容的另一端接地。
  6. 根据权利要求1所述的应用于5G通信***的射频功率放大器，其特征在于，所述第一级双路放大电路包括两个第一晶体管Q1，所述第二级双路放大电路包括两个第二晶体管Q2；
    所述两个第一晶体管Q1的基极分别为所述第一级双路放大电路的两个输入端，所述两个第一晶体管Q1的集电极分别为所述第一级双路放大电路的两个输出端，所述两个第一晶体管Q1的发射极接地；所述两个第二晶体管Q2的基极分别为所述第二级双路放大电路的两个输入端，所述两个第二晶体管Q2的集电极分别为所述第二级双路放大电路的两个输出端，所述两个第二晶体管Q2的发射极接地。
  7. 根据权利要去6所述的应用于5G通信***的射频功率放大器，其特征在于，所述第一晶体管Q1和所述第二晶体管Q2的基极还连接有偏置电路；
    所述偏置电路包括第三晶体管Q3、第四晶体管Q4、第五晶体管Q5、第一电阻R1、第二电阻R2、第三电阻R3以及第六电容C6；
    所述第三晶体管Q3的基极和集电极、所述第四晶体管Q4的基极、所述第一电阻R1的一端以及所述第六电容C6的一端相连接；所述第一电阻R1的另一端连接供电电压Vreg，所述第三晶体管Q3的发射极、所述第五晶体管Q5的集电极和基极相连接，所述第五晶体管Q5的发射极与第二电阻R2的一端连接，所述第二电阻R2的另一端接地，所述第六电容C6的另一端接地，所述第四晶体管Q4的集电极连接供电电压Vbat，所述第四晶体管Q4的发射极与第三电阻R3的一端连接，所述第三电阻R3的另一端与对应的第一晶体管Q1或第二晶体管Q2的基极连接。
  8. 一种应用于5G通信***的射频前端架构，其特征在于，包括权利要求1-7任一项所述的射频功率放大器。
PCT/CN2022/108108 2021-09-27 2022-07-27 应用于5g通信***的射频功率放大器及射频前端架构 WO2023045542A1 (zh)

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