WO2023024549A1 - GaN基HEMT器件、器件外延结构及其制备方法 - Google Patents

GaN基HEMT器件、器件外延结构及其制备方法 Download PDF

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WO2023024549A1
WO2023024549A1 PCT/CN2022/089131 CN2022089131W WO2023024549A1 WO 2023024549 A1 WO2023024549 A1 WO 2023024549A1 CN 2022089131 W CN2022089131 W CN 2022089131W WO 2023024549 A1 WO2023024549 A1 WO 2023024549A1
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layer
gan
hemt device
based hemt
epitaxial structure
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French (fr)
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马旺
陈龙
程静云
陈祖尧
王洪朝
袁理
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聚能晶源(青岛)半导体材料有限公司
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
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    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C—CHEMISTRY; METALLURGY
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    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • C30B29/403—AIII-nitrides
    • C30B29/406—Gallium nitride
    • H—ELECTRICITY
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a GaN-based HEMT device, a device epitaxial structure and a preparation method thereof.
  • Group III nitride wide bandgap semiconductors represented by gallium nitride (GaN) have large bandgap width, high electron saturation drift velocity, high critical breakdown electric field, high thermal conductivity, good stability, corrosion resistance and radiation resistance
  • GaN gallium nitride
  • the GaN heterostructure has a two-dimensional electron gas with high density and high mobility, and is known as an ideal material for the development of microwave power devices.
  • Gallium nitride (GaN)-based high electron mobility transistor (High electron mobility transistor, HEMT) is a heterojunction field effect transistor, which is considered to be the next generation semiconductor device and is widely used in military, aerospace, communication technology, Fields such as automotive electronics and switching power supplies, especially in high-power and high-frequency applications, are receiving widespread attention.
  • the GaN material has a bandgap width of 3.4eV at room temperature and is a wide bandgap semiconductor. The density of conduction band electrons and valence band holes generated by thermal excitation at room temperature is almost zero. If there are no impurities in the GaN material and the crystal lattice is complete, the GaN material is a high resistance material. High-purity GaN materials with complete lattices are the most ideal high-resistance GaN materials. Unfortunately, high-purity GaN materials with complete lattices are extremely difficult to obtain, and intrinsic GaN that is not intentionally doped is usually n-type in practice.
  • the resistivity of a semiconductor material is inversely proportional to the sum of the product of conduction band electron concentration and electron mobility and the product of valence band hole concentration and hole mobility, if you want to obtain a high-resistance GaN material, you need to reduce the GaN The electron concentration in the conduction band and the hole concentration in the valence band, and reduce the mobility of electrons and holes. Accordingly, there are generally two methods to obtain high-resistance GaN: one is to intentionally introduce structural defects, such as dislocations, into the GaN material. The structural defects can introduce electron trap levels or acceptor levels in the forbidden band of GaN, The conduction band electrons are captured by electron traps or compensated by acceptors to obtain high-resistance GaN materials.
  • a common method is to introduce a higher density of edge dislocations; the second is to intentionally dope GaN materials with impurities, such as iron (Fe) or carbon (C) atoms, which can introduce electron trap levels in the forbidden band of GaN Or the acceptor energy level, so that the conduction band electrons are trapped by electron traps or compensated by acceptors, so as to obtain high resistance GaN materials.
  • impurities such as iron (Fe) or carbon (C) atoms
  • the high dislocation density introduced by the intrinsic dislocation technology may reduce the reliability of AlGaN/GaN HEMT devices, and the intrinsic dislocations will trap charges under high voltage to cause the current collapse effect.
  • Fe-doped GaN is limited by the strong memory effect of Fe, and the doping range cannot be too large, and the doped GaN has poor insulation. If doped with high Fe, it will also cause current collapse effect.
  • Carbon (C)-doped GaN has better stability and lower memory effect, and its off-breakdown voltage is also better, so this method is chosen to obtain high-resistance GaN materials.
  • the current method commonly used in the industry is to epitaxially grow a layer of intrinsic u-GaN on the C-doped c-GaN high resistance layer.
  • GaN channel layer forming a structure of AlGaN barrier layer/u-GaN channel layer/c-GaN high resistance layer to form a two-dimensional electron gas with better performance at the interface of AlGaN barrier layer/u-GaN channel layer , which not only achieves high electrical isolation performance through c-GaN, but also uses intrinsic u-GaN as a conduction channel, avoiding a series of problems caused by C doping.
  • the purpose of the present invention is to provide a GaN-based HEMT device, a device epitaxial structure and a preparation method thereof, which are used to solve the problem of C doping in the GaN-based HEMT device epitaxial structure in the prior art.
  • the C atoms in the c-GaN high-resistance layer are easy to diffuse into the intrinsic u-GaN channel layer, which leads to problems such as reliability degradation of GaN-based HEMT devices and possible current collapse effects.
  • the present invention provides a GaN-based HEMT device epitaxial structure, the epitaxial structure sequentially includes: a C-doped c-GaN high resistance layer, a diffusion barrier layer formed on the substrate from bottom to top , intrinsic u-GaN channel layer and AlGaN barrier layer;
  • the diffusion barrier layer is a laminated structure formed of at least two layers in the group consisting of at least one Si 3 N 4 layer, at least one AlN layer and at least one GaN layer, and the laminated structure includes at least one
  • the Si 3 N 4 layer includes at least one layer of the AlN layer or the GaN layer; or the diffusion barrier layer is a superlattice structure composed of the stacked structure periodically alternately.
  • a buffer layer is formed between the substrate and the C-doped c-GaN high resistance layer.
  • the number of periods of the stacked structure in the superlattice structure is between 2 and 100.
  • the doping concentration of the C-doped c-GaN high resistance layer is between 1E+18cm ⁇ 3 and 3E+19cm ⁇ 3 .
  • the thickness of the Si 3 N 4 layer is between 0.1nm and 30nm
  • the thickness of the AlN layer is between 0.1nm and 100nm
  • the thickness of the GaN layer is between 0.1nm and 4000nm between.
  • a GaN cap layer and/or a p-GaN cap layer are formed on the AlGaN barrier layer of the epitaxial structure.
  • the present invention also provides a GaN-based HEMT device, which is prepared based on the epitaxial structure of the above-mentioned GaN-based HEMT device.
  • the present invention also provides a method for preparing the epitaxial structure of a GaN-based HEMT device, the preparation method comprising:
  • a C-doped c-GaN high-resistance layer, a diffusion barrier layer, an intrinsic u-GaN channel layer and an AlGaN barrier layer are sequentially deposited on the substrate by MOCVD process; wherein, the diffusion barrier layer is composed of at least one A stacked structure formed by at least two layers in the group consisting of a Si 3 N 4 layer, at least one AlN layer, and at least one GaN layer, and the stacked structure includes at least one Si3N4 layer, and at least A layer of the AlN layer or the GaN layer; or the diffusion barrier layer is a superlattice structure composed of the stacked layer structure alternately periodically.
  • the deposition parameters of the diffusion barrier layer are as follows: the growth temperature is between 900 ° C and 1200 ° C, the growth pressure is between 20 mbar and 500 mbar, the gas source used includes ammonia gas, and the flow rate of ammonia gas is between Between 1sccm ⁇ 100000sccm, the growth atmosphere is nitrogen or hydrogen or a mixture of the two.
  • the present invention also provides a method for preparing a GaN-based HEMT device.
  • the method for preparing a GaN-based HEMT device includes the method for preparing the epitaxial structure of a GaN-based HEMT device as described above.
  • the GaN-based HEMT device, the device epitaxial structure and its preparation method of the present invention through the C-doped c-GaN high resistance layer and the intrinsic u-GaN channel of the GaN-based HEMT device epitaxial structure
  • the diffusion barrier layer is arranged between the layers, and the Si 3 N 4 layer in the diffusion barrier layer has excellent shielding ability and can effectively shield the diffusion of impurity atoms, so it can effectively block the C-doped c-GaN C atoms in the high-resistance layer are diffused into the intrinsic u-GaN channel layer; and on the basis of utilizing the shielding function of the Si 3 N 4 layer, the AlN layer and the GaN layer are further arranged,
  • the AlN layer has high wettability
  • the GaN layer is a homogeneous material layer of the high resistance layer and the channel layer, both of which can provide the effect of growth transition for the growth of the diffusion barrier layer, so that the diffusion barrier layer While playing a shielding role
  • FIG. 1 shows a schematic structural diagram of the epitaxial structure of the GaN-based HEMT device of the present invention.
  • FIG. 2 is a schematic structural diagram of the laminated structure in the epitaxial structure of the GaN-based HEMT device in Experimental Example 1 of the present invention.
  • FIG. 3 is a schematic structural diagram of the epitaxial structure of a GaN-based HEMT device in Experimental Example 1 of the present invention.
  • FIG. 4 is a schematic structural diagram of the laminated structure in the epitaxial structure of the GaN-based HEMT device in Experimental Example 2 of the present invention.
  • FIG. 5 is a schematic structural diagram of the epitaxial structure of a GaN-based HEMT device in Experimental Example 2 of the present invention.
  • this embodiment provides an epitaxial structure of a GaN-based HEMT device, and the epitaxial structure sequentially includes: a C-doped c-GaN high-resistance layer 11, a diffusion barrier layer formed on a substrate 10 from bottom to top. 12. Intrinsic u-GaN channel layer 13 and AlGaN barrier layer 14;
  • the diffusion barrier layer 12 is formed of at least two layers in the group consisting of at least one Si3N4 layer 121, at least one AlN layer 122 and at least one GaN layer 123
  • the stacked structure 120, and the stacked structure 120 includes at least one layer of the Si 3 N 4 layer 121, and at the same time includes at least one layer of the AlN layer 122 or the GaN layer 123; as shown in Figure 3, or the
  • the diffusion barrier layer 12 is a superlattice structure 124 composed of the stacked structure 120 alternately periodically.
  • the diffusion barrier layer 12 is provided between the C-doped c-GaN high resistance layer 11 and the intrinsic u-GaN channel layer 13 of the GaN-based HEMT device epitaxial structure, and the diffusion barrier layer
  • the Si 3 N 4 layer 121 in 12 has an excellent shielding ability and can effectively shield the diffusion of impurity atoms, so it can effectively prevent the C atoms in the C-doped c-GaN high resistance layer 11 from diffusing to the In the intrinsic u-GaN channel layer 13; and on the basis of utilizing the shielding function of the Si 3 N 4 layer 121, the AlN layer 122 and the GaN layer 123 are set, and the AlN layer 122 has High wettability, the GaN layer 123 is a homogeneous material layer of a high resistance layer and a channel layer, both of which can provide a growth transition for the growth of the diffusion barrier layer 12, so that the diffusion barrier layer 12 acts While achieving the shielding effect, better crystal growth quality can be achieved, the
  • a buffer layer 15 is formed between the substrate 10 and the C-doped c-GaN high-resistance layer 11, and the buffer layer 15 is used to alleviate the relationship between the substrate 10 and the The lattice mismatch and thermal mismatch between the C-doped c-GaN high-resistance layers 11 are eliminated, and the growth quality of the epitaxial structure is improved.
  • the epitaxial growth method is preferential lateral epitaxial growth, that is, growth along the two-dimensional direction where the interface between the two is preferentially parallel to the direction of the interface. This preferential lateral epitaxial growth method can reduce the continuation of threading dislocations to a certain extent and improve the quality of crystal growth. And reduce the leakage of the buffer layer, and further improve the withstand voltage characteristics of the device.
  • the doping concentration of the C-doped c-GaN high-resistance layer 11 may be doped according to actual resistance characteristics.
  • the diffusion barrier layer 12 of this embodiment can make the doping concentration of the C-doped c-GaN high resistance layer 11 range from 1E+18cm ⁇ 3 to 3E+19cm ⁇ 3 on the basis of ensuring device performance. between 3 .
  • a GaN cap layer can also be formed on the AlGaN barrier layer 14 of the epitaxial structure to form a depletion-type GaN-based HEMT device;
  • a p-GaN cap layer is formed on the AlGaN barrier layer 14 to form an enhanced GaN-based HEMT device;
  • a GaN cap layer and a p-GaN cap layer can also be formed on the AlGaN barrier layer 14 of the epitaxial structure , forming an enhanced GaN-based HEMT device, wherein the GaN cap layer is used to protect the AlGaN barrier layer 14 .
  • the laminated structure 120 is formed of at least two layers in the group consisting of at least one Si 3 N 4 layer 121, at least one AlN layer 122 and at least one GaN layer 123, and includes at least one The Si 3 N 4 layer 121 includes at least one layer of the AlN layer 122 or the GaN layer 123. It can be understood that the stacked structure 120 is a stack of more than two layers, which must contain a layer of the Si 3 N 4 layer 121 must include a layer of the AlN layer 122 or the GaN layer 123.
  • the stacked structure 120 can be a stack of AlN layer/Si 3 N 4 layer, GaN Layer/Si 3 N 4 layer stack, AlN layer/Si 3 N 4 layer/GaN layer stack, the material layers are not repeated in this arrangement; the stack structure 120 can also be AlN layer/Si 3 N 4 layer/AlN layer stack, GaN layer/Si 3 N 4 layer/GaN layer stack, AlN layer/Si 3 N 4 layer/AlN layer/GaN layer stack, this arrangement can have Repeated material layers (the repeated material layers here refer to the same material, but the thickness of the same layer of material can be the same or different); in addition, the stacking sequence of each layer in the laminated structure 120 is not limited, for example , may be a stack of AlN layer/Si 3 N 4 layer/GaN layer, or may be a stack of Si 3 N 4 layer/AlN layer/GaN layer.
  • the barrier layer 12 is a superlattice structure 124 composed of the stacked structure 120 periodically alternately
  • the number of periods of the stacked structure 120 in the superlattice structure 124 is between 2 Between ⁇ 100.
  • the thickness of the Si 3 N 4 layer 121 in the barrier layer 12 is between 0.1 nm and 30 nm
  • the thickness of the AlN layer 122 is between 0.1 nm and 100 nm
  • the GaN layer 123 The thickness is between 0.1nm and 4000nm.
  • this experimental example provides a GaN-based HEMT device epitaxial structure
  • the epitaxial structure sequentially includes a buffer layer 15 formed on a substrate 10, a C-doped c-GaN high resistance layer 11 , a diffusion barrier layer 12 , an intrinsic u-GaN channel layer 13 and an AlGaN barrier layer 14 .
  • the substrate 10 can be selected as a Si substrate, a C-plane sapphire substrate, a SiC substrate or a GaN substrate, or other substrates suitable for preparing GaN-based HEMT device epitaxial structures.
  • the buffer layer 15 may be an AlN layer, an AlGaN layer, or a GaN layer, or may be a superlattice structure that is periodically alternately composed of stacks of AlN layers, AlGaN layers, and GaN layers.
  • the doping concentration of the C-doped c-GaN high resistance layer 11 is between 1E+18cm ⁇ 3 and 3E+19cm ⁇ 3 .
  • the diffusion barrier layer 12 is a superlattice structure 124
  • the stacked structure 120 is composed of an AlN layer 122 /Si 3 N 4 layer 121 /AlN layer 122 /GaN layer 123 .
  • the thickness of each layer in each stacked structure 120 is that the thickness of the AlN layer 122 is 1 nm, the thickness of the Si 3 N 4 layer 121 is 0.8 nm, the thickness of the AlN layer 122 is 1 nm, and the thickness of the GaN layer 123 is 5 nm.
  • the period number of the superlattice structure 124 is three.
  • the stacked structure 120 is selected as the stacked formation of AlN layer 122/Si 3 N 4 layer 121/AlN layer 122/GaN layer 123, taking into account the high wettability of the AlN layer and the same Quality, while improving the shielding ability, it can ensure the growth quality of the crystal.
  • this experimental example provides an epitaxial structure of a GaN-based HEMT device.
  • the epitaxial structure includes a buffer layer 15 formed on a substrate 10, a C-doped c-GaN high resistance layer 11 , a diffusion barrier layer 12 , an intrinsic u-GaN channel layer 13 and an AlGaN barrier layer 14 .
  • the substrate 10 can be selected as a Si substrate, a C-plane sapphire substrate, a SiC substrate or a GaN substrate, or other conventional substrates.
  • the buffer layer 15 may be an AlN layer, an AlGaN layer, or a GaN layer, or may be a superlattice structure that is periodically alternately composed of stacks of AlN layers, AlGaN layers, and GaN layers.
  • the doping concentration of the C-doped c-GaN high resistance layer 11 is between 1E+18cm ⁇ 3 and 3E+19cm ⁇ 3 .
  • the diffusion barrier layer 12 is a superlattice structure 124 , and the laminated structure 120 thereof is composed of an AlN layer 122 /Si 3 N 4 layer 121 /AlN layer 122 .
  • the thickness of each layer in each stacked structure 120 is sequentially as follows: the thickness of the AlN layer 122 is 0.6 nm, the thickness of the Si 3 N 4 layer 121 is 0.4 nm, and the thickness of the AlN layer 122 is 0.6 nm.
  • the period number of the superlattice structure 124 is ten.
  • the stacked structure 120 is selected as the stacked formation of the AlN layer 122/Si 3 N 4 layer 121/AlN layer 122, considering the high wettability of the AlN layer, while improving the shielding ability and ensuring the crystal growth quality.
  • This embodiment also provides a GaN-based HEMT device, which is prepared based on the epitaxial structure of the GaN-based HEMT device provided in this embodiment.
  • This embodiment provides a method for preparing the epitaxial structure of a GaN-based HEMT device.
  • This preparation method can be used to prepare the epitaxial structure of the GaN-based HEMT device described in the first embodiment above.
  • the preparation method of GaN-based HEMT device epitaxial structure includes:
  • a C-doped c-GaN high-resistance layer 11, a diffusion barrier layer 12, an intrinsic u-GaN channel layer 13, and an AlGaN barrier layer 14 are sequentially deposited on the substrate 10 by MOCVD; wherein, the diffusion barrier Layer 12 is a laminated structure 120 formed of at least two layers in the group consisting of at least one Si 3 N 4 layer 121 , at least one AlN layer 122 and at least one GaN layer 123 , and the laminated structure 120 includes At least one layer of the Si 3 N 4 layer 121, including at least one layer of the AlN layer 122 or the GaN layer 123; as shown in Figure 3, or the diffusion barrier layer 12 is composed of the stacked structure 120
  • the superlattice structure 124 is composed periodically and alternately.
  • the deposition parameters used in the MOCVD process are: the growth temperature is between 900° C. and 1200° C., the growth pressure is between 20 mbar and 500 mbar, and the gas source used includes ammonia gas.
  • the flow rate of the ammonia gas is between 1 sccm and 100000 sccm, and the growth atmosphere is nitrogen or hydrogen, or a mixture of the two.
  • This embodiment also provides a method for preparing a GaN-based HEMT device, which includes the method for preparing the epitaxial structure of a GaN-based HEMT device provided in this embodiment.
  • the present invention provides a GaN-based HEMT device, a device epitaxial structure and a preparation method thereof, through the C-doped c-GaN high resistance layer and the intrinsic u-
  • the diffusion barrier layer is arranged between the GaN channel layers, and the Si 3 N 4 layer in the diffusion barrier layer has excellent shielding ability, and can effectively shield the diffusion of impurity atoms, so it can effectively block the C-doped
  • the C atoms in the c-GaN high-resistance layer diffuse into the intrinsic u-GaN channel layer; and on the basis of utilizing the shielding function of the Si 3 N 4 layer, the AlN layer and the GaN layer, the AlN layer has high wettability
  • the GaN layer is a homogeneous material layer of the high resistance layer and the channel layer, both of which can provide the growth transition effect for the growth of the diffusion barrier layer, so that While playing a shielding role, the diffusion barrier layer can also achieve better crystal growth quality, achieve an optimal doping barrier

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Abstract

本发明提供一种GaN基HEMT器件、器件外延结构及其制备方法。外延结构自下向上依次包括形成于衬底上的: C掺杂c-GaN高阻层、扩散阻挡层、本征u-GaN沟道层及AlGaN势垒层; 扩散阻挡层为由至少一层Si3N4层、至少一层AlN层及至少一层GaN层构成的群组中的至少两层形成的叠层结构，且该叠层结构包括至少一层Si3N4层，同时包括至少一层AlN层或GaN层；或为由叠层结构周期***替组成的超晶格结构。Si3N4层具有极佳的遮蔽能力，能够有效地遮蔽杂质原子的扩散, 因此可以有效阻挡C掺杂c-GaN高阻层中的C原子扩散至本征u-GaN沟道层中; 再设置AlN层及GaN层，为扩散阻挡层的生长提供生长过渡的作用, 从而使扩散阻挡层在起到遮蔽作用的同时, 还可实现更好的晶体生长质量。

Description

GaN基HEMT器件、器件外延结构及其制备方法 技术领域
本发明属于半导体制造技术领域，特别是涉及一种GaN基HEMT器件、器件外延结构及其制备方法。
背景技术
以氮化镓(GaN)为代表的III族氮化物宽禁带半导体以禁带宽度大、电子饱和漂移速度高、临界击穿电场高、热导率高、稳定性好、耐腐蚀和抗辐射等优异的物理特性，继第一代半导体硅(Si)、锗(Ge)和第二代半导体砷化镓(GaAs)、磷化铟(InP)之后，成为第三代半导体的主要材料体系，特别是GaN异质结构具有高密度和高迁移率的二维电子气，被誉为是研制微波功率器件的理想材料。氮化镓(GaN)基高电子迁移率晶体管(High electron mobility transistor，HEMT)是一种异质结场效应晶体管，被认为是下一代半导体器件，被广泛应用在军事、航空航天、通信技术、汽车电子和开关电源等领域，尤其在高功率和高频应用领域正受到广泛关注。
在功率器件领域，良好的电学隔离性能可以减小截止漏电流，形成良好的沟道夹断性能和高击穿电压。因此，半绝缘的GaN材料在GaN基异质结构场效应晶体管制造中非常重要。
GaN材料室温下的禁带宽度为3.4eV，是宽禁带半导体，室温时热激发产生的导带电子和价带空穴的密度几乎为零。如果GaN材料中没有任何杂质并且晶格完整，则GaN材料是高阻材料。晶格完整的高纯GaN材料是最理想的高阻GaN材料，然而不幸的是晶格完整的高纯GaN材料极难获得，且在实际中非故意掺杂的本征GaN通常为n型。
由于半导体材料的电阻率与导带电子浓度和电子迁移率的乘积及价带空穴浓度和空穴迁移率的乘积之和成反比，因此，如果想要获得高阻GaN材料，需要减小GaN中的导带电子浓度和价带空穴浓度，并减小电子和空穴的迁移率。据此，获得高阻GaN一般有以下两种方法：一是有意在GaN材料中引入结构缺陷，如位错等，结构缺陷可在GaN的禁带中引入电子陷阱能级或受主能级，使导带电子被电子陷阱俘获或被受主补偿，从而获得高阻GaN材料。常见的方法是引入较高密度的刃位错；二是有意在GaN材料中掺入杂质，例如铁(Fe)或碳(C)原子，该杂质可在GaN的禁带中引入电子陷阱能级或受主能级，使导带电子被电子陷阱俘获或被受主补偿，从而获得高阻GaN材料。
然而，采用本征位错技术引入的高位错密度，可能会降低AlGaN/GaN HEMT器件的可靠 性，而且高压下本征位错会俘获电荷从而造成电流崩塌效应。采用Fe掺杂的GaN则受限于Fe具有很强的记忆效应，而且掺杂范围不能太大，其掺杂的GaN绝缘性也较差，如果用高Fe掺杂，则同样也会造成电流崩塌效应。碳(C)掺杂的GaN则具有比较好的稳定性和更低记忆效应，而且其关断击穿电压也更好，所以选择此种方法来获得高阻GaN材料。但是，金属有机物化学气相沉积(MOCVD)方法想要获得一定的C掺杂浓度，通常需要降低GaN的生长温度实现自掺杂，或者采用乙烯(C 2H 4)等碳源实现外置掺杂，不论采用哪种C掺杂方法，由于高浓度C杂质的引入，都会一定在程度上导致GaN材料晶体质量变差，加上C掺杂引起的缺陷都可能会导致器件可靠性的衰退和电流崩塌效应。
为了尽可能的减弱上述C掺杂所引起的器件可靠性和电流崩塌效应问题，目前业内通常使用的方法是在C掺杂的c-GaN高阻层上再外延生长一层本征的u-GaN沟道层，形成AlGaN势垒层/u-GaN沟道层/c-GaN高阻层的结构，以在AlGaN势垒层/u-GaN沟道层界面形成性能较佳的二维电子气，这样既通过c-GaN实现了较高的电学隔离性能，又利用本征u-GaN作为导通沟道，避免了C掺杂引起的一系列问题。
但是，即便采用以上所述措施减弱C掺杂所引起的器件可靠性和电流崩塌效应问题，由于C掺杂的c-GaN高阻层与本征u-GaN沟道层之间存在较大的浓度差，C掺杂的c-GaN高阻层中的C原子还是会较为容易的扩散到本征u-GaN沟道层，从而在一定程度上引发上述可靠性和电流崩塌效应的问题。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种GaN基HEMT器件、器件外延结构及其制备方法，用于解决现有技术中GaN基HEMT器件外延结构中由于C掺杂的c-GaN高阻层中的C原子易于扩散至本征u-GaN沟道层，导致GaN基HEMT器件可靠性衰退及可能产生电流崩塌效应等的问题。
为实现上述目的及其他相关目的，本发明提供一种GaN基HEMT器件外延结构，所述外延结构自下向上依次包括形成于衬底上的：C掺杂c-GaN高阻层、扩散阻挡层、本征u-GaN沟道层及AlGaN势垒层；
所述扩散阻挡层为由至少一层Si 3N 4层、至少一层AlN层及至少一层GaN层构成的群组中的至少两层形成的叠层结构，且该叠层结构包括至少一层所述Si 3N 4层，同时包括至少一层所述AlN层或所述GaN层；或所述扩散阻挡层为由所述叠层结构周期***替组成的超晶格结构。
可选地，所述衬底与所述C掺杂c-GaN高阻层之间形成有缓冲层。
可选地，所述超晶格结构中所述叠层结构的周期数介于2个～100个之间。
可选地，所述C掺杂c-GaN高阻层的掺杂浓度介于1E+18cm -3～3E+19cm -3之间。
可选地，所述Si 3N 4层的厚度介于0.1nm～30nm之间，所述AlN层的厚度介于0.1nm～100nm之间，所述GaN层的厚度介于0.1nm～4000nm之间。
可选地，所述外延结构的所述AlGaN势垒层上形成有GaN帽层和/或p-GaN帽层。
本发明还提供一种GaN基HEMT器件，该HEMT器件基于上述所述的GaN基HEMT器件外延结构制备得到。
本发明还提供一种GaN基HEMT器件外延结构的制备方法，所述制备方法包括：
提供衬底；
采用MOCVD工艺于所述衬底上依次沉积C掺杂c-GaN高阻层、扩散阻挡层、本征u-GaN沟道层及AlGaN势垒层；其中，所述扩散阻挡层为由至少一层Si 3N 4层、至少一层AlN层及至少一层GaN层构成的群组中的至少两层形成的叠层结构，且该叠层结构包括至少一层所述Si3N4层，同时包括至少一层所述AlN层或所述GaN层；或所述扩散阻挡层为由所述叠层结构周期***替组成的超晶格结构。
可选地，所述扩散阻挡层的沉积参数为：生长温度介于900℃～1200℃之间，生长压力介于20mbar～500mbar之间，采用的气源包括氨气，且氨气的流量介于1sccm～100000sccm之间，生长气氛为氮气或氢气或两者的混合气体。
本发明还提供一种GaN基HEMT器件的制备方法，所述GaN基HEMT器件的制备方法包括如上所述的GaN基HEMT器件外延结构的制备方法。
如上所述，本发明的GaN基HEMT器件、器件外延结构及其制备方法，通过在GaN基HEMT器件外延结构的所述C掺杂c-GaN高阻层与所述本征u-GaN沟道层之间设置所述扩散阻挡层，扩散阻挡层中的所述Si 3N 4层具有极佳的遮蔽能力，能够有效地遮蔽杂质原子的扩散，因此可以有效阻挡所述C掺杂c-GaN高阻层中的C原子扩散至所述本征u-GaN沟道层中；而在利用所述Si 3N 4层的遮蔽功能的基础上，再设置所述AlN层及所述GaN层，所述AlN层具有高浸润性，所述GaN层为高阻层及沟道层的同质材料层，两者均可为所述扩散阻挡层的生长提供生长过渡的作用，从而使扩散阻挡层在起到遮蔽作用的同时，还可实现更好的晶体生长质量，达到最优的掺杂阻挡效果，实现最优的器件性能。
附图说明
图1显示为本发明的GaN基HEMT器件外延结构的结构示意图。
图2显示为本发明实验例1的GaN基HEMT器件外延结构中叠层结构的结构示意图。
图3显示为本发明实验例1的GaN基HEMT器件外延结构的结构示意图。
图4显示为本发明实验例2的GaN基HEMT器件外延结构中叠层结构的结构示意图。
图5显示为本发明实验例2的GaN基HEMT器件外延结构的结构示意图。
元件标号说明
10                    衬底
11                    C掺杂的c-GaN高阻层
12                    扩散阻挡层
120                   叠层结构
121                   Si 3N 4层
122                   AlN层
123                   GaN层
124                   超晶格结构
13                    本征u-GaN沟道层
14                    AlGaN势垒层
15                    缓冲层
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1至图5。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可根据实际需要进行改变，且其组件布局型态也可能更为复杂。
实施例一
如图1所示，本实施例提供一种GaN基HEMT器件外延结构，所述外延结构自下向上依次包括形成于衬底10上的：C掺杂c-GaN高阻层11、扩散阻挡层12、本征u-GaN沟道层 13及AlGaN势垒层14；
如图1及图2所示，所述扩散阻挡层12为由至少一层Si 3N 4层121、至少一层AlN层122及至少一层GaN层123构成的群组中的至少两层形成的叠层结构120，且该叠层结构120包括至少一层所述Si 3N 4层121，同时包括至少一层所述AlN层122或所述GaN层123；如图3所示，或所述扩散阻挡层12为由所述叠层结构120周期***替组成的超晶格结构124。
本实施例中通过在GaN基HEMT器件外延结构的所述C掺杂c-GaN高阻层11与所述本征u-GaN沟道层13之间设置所述扩散阻挡层12，扩散阻挡层12中的所述Si 3N 4层121具有极佳的遮蔽能力，能够有效地遮蔽杂质原子的扩散，因此可以有效阻挡所述C掺杂c-GaN高阻层11中的C原子扩散至所述本征u-GaN沟道层13中；而在利用所述Si 3N 4层121的遮蔽功能的基础上，再设置所述AlN层122及所述GaN层123，所述AlN层122具有高浸润性，所述GaN层123为高阻层及沟道层的同质材料层，两者均可为所述扩散阻挡层12的生长提供生长过渡的作用，从而使扩散阻挡层12在起到遮蔽作用的同时，还可实现更好的晶体生长质量，达到最优的掺杂阻挡效果，实现最优的器件性能。
如图1所示，作为示例，所述衬底10与所述C掺杂c-GaN高阻层11之间形成有缓冲层15，所述缓冲层15用于缓解所述衬底10与所述C掺杂c-GaN高阻层11之间的晶格失配与热失配，提高外延结构的生长质量。由于所述Si 3N 4层121的惰性绝缘材料特性，所以可以在一定程度上降低缓冲层15的漏电，从而提高器件的耐压性能；另外，Si 3N 4在GaN层和AlN层的表面外延生长方式是优先横向外延生长，即沿着二者界面优先平行于界面方向的二维方向进行生长，此种优先横向外延生长方式可以一定程度上降低穿透位错的延续，提升晶体生长品质以及降低缓冲层漏电，进一步提高器件的耐压特性。
作为示例，所述C掺杂c-GaN高阻层11的掺杂浓度可以根据实际的电阻特性需要进行掺杂。较佳地，采用本实施例的扩散阻挡层12可在保证器件性能的基础上使所述C掺杂c-GaN高阻层11的掺杂浓度介于1E+18cm -3～3E+19cm -3之间。
作为示例，根据实际形成的GaN基HEMT器件结构，还可在所述外延结构的所述AlGaN势垒层14上形成GaN帽层，形成耗尽型GaN基HEMT器件；也可在所述外延结构的所述AlGaN势垒层14上形成p-GaN帽层，形成增强型GaN基HEMT器件；也可在所述外延结构的所述AlGaN势垒层14上形成GaN帽层及p-GaN帽层，形成增强型GaN基HEMT器件，其中，GaN帽层用于保护所述AlGaN势垒层14。
作为示例，所述叠层结构120为由至少一层Si 3N 4层121、至少一层AlN层122及至少一层GaN层123构成的群组中的至少两层形成，且包括至少一层所述Si 3N 4层121，同时包括 至少一层所述AlN层122或所述GaN层123，可理解为，该叠层结构120为两层以上的叠层，其中必须含有一层所述Si 3N 4层121，之外必须包括一层所述AlN层122或所述GaN层123，举例示之，所述叠层结构120可以为AlN层/Si 3N 4层的叠层、GaN层/Si 3N 4层的叠层、AlN层/Si 3N 4层/GaN层的叠层，此种排列方式中材料层不重复；所述叠层结构120还可以为AlN层/Si 3N 4层/AlN层的叠层、GaN层/Si 3N 4层/GaN层的叠层、AlN层/Si 3N 4层/AlN层/GaN层的叠层，此种排列方式中可以有重复的材料层(这里的重复材料层指的是材料相同，但是材料相同的层厚度可相同也可不相同)；另外，也不限制所述叠层结构120中每层的层叠顺序，举例示之，可以为AlN层/Si 3N 4层/GaN层的叠层，也可以为Si 3N 4层/AlN层/GaN层的叠层。
作为示例，当所述阻挡层12为由所述叠层结构120周期***替组成的超晶格结构124时，所述超晶格结构124中所述叠层结构120的周期数介于2个～100个之间。
作为示例，所述阻挡层12中的所述Si 3N 4层121的厚度介于0.1nm～30nm之间，所述AlN层122的厚度介于0.1nm～100nm之间，所述GaN层123的厚度介于0.1nm～4000nm之间。
下面结合具体的实验例对本实施例的GaN基HEMT器件外延结构进行说明。
实验例1
如图2及图3所示，本实验例提供一种GaN基HEMT器件外延结构，所述外延结构自下向上依次包括形成于衬底10上的缓冲层15、C掺杂c-GaN高阻层11、扩散阻挡层12、本征u-GaN沟道层13及AlGaN势垒层14。
所述衬底10可以选择为Si衬底、C面蓝宝石衬底、SiC衬底或者GaN衬底，也可以为其它适于制备GaN基HEMT器件外延结构的衬底。
所述缓冲层15可以为AlN层、AlGaN层或GaN层，也可以为以AlN层、AlGaN层及GaN层构成的叠层为周期进行周期***替组成的超晶格结构。
所述C掺杂c-GaN高阻层11的掺杂浓度介于1E+18cm -3～3E+19cm -3之间。
所述扩散阻挡层12为超晶格结构124，其中的叠层结构120为AlN层122/Si 3N 4层121/AlN层122/GaN层123构成。每个叠层结构120中每层的厚度依次为AlN层122的厚度为1nm，Si 3N 4层121的厚度为0.8nm，AlN层122的厚度为1nm，GaN层123的厚度为5nm。超晶格结构124的周期数为3。
通过该周期数目的设置，可以尽可能多的降低C掺杂的c-GaN高阻层11中的C原子扩散到本征u-GaN沟道层13的扩散效应，但是也同时兼顾晶体质量和器件的最终性能情况；另外，叠层结构120选择为AlN层122/Si 3N 4层121/AlN层122/GaN层123的叠层形成，兼顾了AlN层的高浸润性及GaN层的同质性，在提高遮蔽能力的同时保证晶体的生长质量。
实验例2
如图4及图5所示，本实验例提供一种GaN基HEMT器件外延结构，所述外延结构自下向上依次包括形成于衬底10上的缓冲层15、C掺杂c-GaN高阻层11、扩散阻挡层12、本征u-GaN沟道层13及AlGaN势垒层14。
所述衬底10可以选择为Si衬底、C面蓝宝石衬底、SiC衬底或者GaN衬底，也可以为其它常规的衬底。
所述缓冲层15可以为AlN层、AlGaN层或GaN层，也可以为以AlN层、AlGaN层及GaN层构成的叠层为周期进行周期***替组成的超晶格结构。
所述C掺杂c-GaN高阻层11的掺杂浓度介于1E+18cm -3～3E+19cm -3之间。
所述扩散阻挡层12为超晶格结构124，其中的叠层结构120为AlN层122/Si 3N 4层121/AlN层122构成。每个叠层结构120中每层的厚度依次为AlN层122的厚度为0.6nm，Si 3N 4层121的厚度为0.4nm，AlN层122的厚度为0.6nm。超晶格结构124的周期数为10。
通过该周期数目的设置，可以尽可能多的降低C掺杂的c-GaN高阻层11中的C原子扩散到本征u-GaN沟道层13的扩散效应，但是也同时兼顾晶体质量和器件的最终性能情况；另外，叠层结构120选择为AlN层122/Si 3N 4层121/AlN层122的叠层形成，考虑了AlN层的高浸润性，在提高遮蔽能力的同时保证晶体的生长质量。
本实施例还提供一种GaN基HEMT器件，该GaN基HEMT器件为基于本实施例提供的GaN基HEMT器件外延结构制备得到。
实施例二
本实施例提供一种GaN基HEMT器件外延结构的制备方法，该制备方法可以用于制备上述实施例一所述的GaN基HEMT器件外延结构，其所能达到的有益效果可请参见实施例一，以下不再赘述。
如图1所示，GaN基HEMT器件外延结构的制备方法包括：
提供衬底10；
采用MOCVD工艺于所述衬底10上依次沉积C掺杂c-GaN高阻层11、扩散阻挡层12、本征u-GaN沟道层13及AlGaN势垒层14；其中，所述扩散阻挡层12为由至少一层Si 3N 4层121、至少一层AlN层122及至少一层GaN层123构成的群组中的至少两层形成的叠层结构120，且该叠层结构120包括至少一层所述Si 3N 4层121，同时包括至少一层所述AlN层122或所述GaN层123；如图3所示，或所述扩散阻挡层12为由所述叠层结构120周期***替组成的超晶格结构124。
作为示例，沉积所述扩散阻挡层12时，MOCVD工艺采用的沉积参数为：生长温度介于900℃～1200℃之间，生长压力介于20mbar～500mbar之间，采用的气源包括氨气，且氨气的流量介于1sccm～100000sccm之间，生长气氛为氮气或氢气，或两者的混合气体。
本实施例还提供一种GaN基HEMT器件的制备方法，该制备方法包括本本实施例提供的GaN基HEMT器件外延结构的制备方法。
综上所述，本发明提供一种GaN基HEMT器件、器件外延结构及其制备方法，通过在GaN基HEMT器件外延结构的所述C掺杂c-GaN高阻层与所述本征u-GaN沟道层之间设置所述扩散阻挡层，扩散阻挡层中的所述Si 3N 4层具有极佳的遮蔽能力，能够有效地遮蔽杂质原子的扩散，因此可以有效阻挡所述C掺杂c-GaN高阻层中的C原子扩散至所述本征u-GaN沟道层中；而在利用所述Si 3N 4层的遮蔽功能的基础上，再设置所述AlN层及所述GaN层，所述AlN层具有高浸润性，所述GaN层为高阻层及沟道层的同质材料层，两者均可为所述扩散阻挡层的生长提供生长过渡的作用，从而使扩散阻挡层在起到遮蔽作用的同时，还可实现更好的晶体生长质量，达到最优的掺杂阻挡效果，实现最优的器件性能。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

  1. 一种GaN基HEMT器件外延结构，其特征在于，所述外延结构自下向上依次包括形成于衬底上的：C掺杂c-GaN高阻层、扩散阻挡层、本征u-GaN沟道层及AlGaN势垒层；
    所述扩散阻挡层为由至少一层Si 3N 4层、至少一层AlN层及至少一层GaN层构成的群组中的至少两层形成的叠层结构，且该叠层结构包括至少一层所述Si 3N 4层，同时包括至少一层所述AlN层或所述GaN层；或所述扩散阻挡层为由所述叠层结构周期***替组成的超晶格结构。
  2. 根据权利要求1所述的GaN基HEMT器件外延结构，其特征在于：所述衬底与所述C掺杂c-GaN高阻层之间形成有缓冲层。
  3. 根据权利要求1所述的GaN基HEMT器件外延结构，其特征在于：所述超晶格结构中所述叠层结构的周期数介于2个～100个之间。
  4. 根据权利要求1所述的GaN基HEMT器件外延结构，其特征在于：所述C掺杂c-GaN高阻层的掺杂浓度介于1E+18cm -3～3E+19cm -3之间。
  5. 根据权利要求1所述的GaN基HEMT器件外延结构，其特征在于：所述Si 3N 4层的厚度介于0.1nm～30nm之间，所述AlN层的厚度介于0.1nm～100nm之间，所述GaN层的厚度介于0.1nm～4000nm之间。
  6. 根据权利要求1所述的GaN基HEMT器件外延结构，其特征在于，所述外延结构的所述AlGaN势垒层上形成有GaN帽层和/或p-GaN帽层。
  7. 一种GaN基HEMT器件，其特征在于：所述HEMT器件基于权利要求1～6中任意一项所述的GaN基HEMT器件外延结构制备得到。
  8. 一种GaN基HEMT器件外延结构的制备方法，其特征在于，所述制备方法包括：
    提供衬底；
    采用MOCVD工艺于所述衬底上依次沉积C掺杂c-GaN高阻层、扩散阻挡层、本征u-GaN沟道层及AlGaN势垒层；其中，所述扩散阻挡层为由至少一层Si 3N 4层、至少一层AlN层及至少一层GaN层构成的群组中的至少两层形成的叠层结构，且该叠层结构包括至 少一层所述Si3N4层，同时包括至少一层所述AlN层或所述GaN层；或所述扩散阻挡层为由所述叠层结构周期***替组成的超晶格结构。
  9. 根据权利要求8所述的GaN基HEMT器件外延结构的制备方法，其特征在于，所述扩散阻挡层的沉积参数为：生长温度介于900℃～1200℃之间，生长压力介于20mbar～500mbar之间，采用的气源包括氨气，且氨气的流量介于1sccm～100000sccm之间，生长气氛为氮气或氢气或两者的混合气体。
  10. 一种GaN基HEMT器件的制备方法，其特征在于：所述GaN基HEMT器件的制备方法包括权利要求8或9所述的GaN基HEMT器件外延结构的制备方法。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117727773A (zh) * 2024-02-06 2024-03-19 江西兆驰半导体有限公司 GaN基HEMT外延片及其制备方法、HEMT器件

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113793868B (zh) * 2021-08-27 2023-05-12 聚能晶源(青岛)半导体材料有限公司 GaN基HEMT器件、器件外延结构及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103545348A (zh) * 2012-07-16 2014-01-29 台湾积体电路制造股份有限公司 用于硅衬底上的iii族氮化物的扩散阻挡层
US20150041825A1 (en) * 2013-08-12 2015-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, high electron mobility transistor (hemt) and method of manufacturing
CN111063726A (zh) * 2019-12-20 2020-04-24 西安电子科技大学芜湖研究院 一种Si基氮化镓器件的外延结构
CN111063736A (zh) * 2019-12-20 2020-04-24 西安电子科技大学芜湖研究院 一种高质量的hemt器件外延结构
CN113793868A (zh) * 2021-08-27 2021-12-14 聚能晶源(青岛)半导体材料有限公司 GaN基HEMT器件、器件外延结构及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4685953B2 (ja) * 2009-07-17 2011-05-18 Ｄｏｗａエレクトロニクス株式会社 横方向を電流導通方向とする電子デバイス用エピタキシャル基板およびその製造方法
JP5706102B2 (ja) * 2010-05-07 2015-04-22 ローム株式会社 窒化物半導体素子

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103545348A (zh) * 2012-07-16 2014-01-29 台湾积体电路制造股份有限公司 用于硅衬底上的iii族氮化物的扩散阻挡层
US20150041825A1 (en) * 2013-08-12 2015-02-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device, high electron mobility transistor (hemt) and method of manufacturing
CN111063726A (zh) * 2019-12-20 2020-04-24 西安电子科技大学芜湖研究院 一种Si基氮化镓器件的外延结构
CN111063736A (zh) * 2019-12-20 2020-04-24 西安电子科技大学芜湖研究院 一种高质量的hemt器件外延结构
CN113793868A (zh) * 2021-08-27 2021-12-14 聚能晶源(青岛)半导体材料有限公司 GaN基HEMT器件、器件外延结构及其制备方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117727773A (zh) * 2024-02-06 2024-03-19 江西兆驰半导体有限公司 GaN基HEMT外延片及其制备方法、HEMT器件
CN117727773B (zh) * 2024-02-06 2024-04-19 江西兆驰半导体有限公司 GaN基HEMT外延片及其制备方法、HEMT器件

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