WO2023000200A1 - 一种场效应晶体管、其制作方法及集成电路 - Google Patents

一种场效应晶体管、其制作方法及集成电路 Download PDF

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Publication number
WO2023000200A1
WO2023000200A1 PCT/CN2021/107580 CN2021107580W WO2023000200A1 WO 2023000200 A1 WO2023000200 A1 WO 2023000200A1 CN 2021107580 W CN2021107580 W CN 2021107580W WO 2023000200 A1 WO2023000200 A1 WO 2023000200A1
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Prior art keywords
doped layer
layer
field effect
effect transistor
cold source
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PCT/CN2021/107580
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English (en)
French (fr)
Inventor
董耀旗
侯朝昭
王嘉乐
吴颖
许俊豪
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华为技术有限公司
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Priority to CN202180096515.4A priority Critical patent/CN117203742A/zh
Priority to PCT/CN2021/107580 priority patent/WO2023000200A1/zh
Publication of WO2023000200A1 publication Critical patent/WO2023000200A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a field effect transistor, a manufacturing method thereof and an integrated circuit.
  • Integrated circuits generally include a field effect transistor (metal oxide semiconductor field effect transistor, MOSFET).
  • MOSFET metal oxide semiconductor field effect transistor
  • the required gate voltage increment is called the sub-threshold swing (SS), and the sub-threshold swing is related to factors such as device structure and temperature.
  • the sub-threshold swing The smaller is, the greater the working speed of the field effect transistor in the subthreshold state.
  • the subthreshold current is an exponential function related to the Boltzmann constant. Since the electrons satisfy the Boltzmann distribution characteristics, the subthreshold swing is at room temperature It cannot be less than 60mV/dec.
  • the operating voltage Vdd must be many times the subthreshold swing, where I on represents the on-state current of the field effect transistor, and I off represents the field effect transistor off-state current. If the sub-threshold swing remains unchanged, reducing the operating voltage Vdd will cause the on -state current Ion to decrease and the performance of the device to degrade. Therefore, due to the limitation of the sub-threshold swing of the field effect transistor, it is difficult to reduce the operating voltage of the integrated circuit, and furthermore, it is difficult to further reduce the power consumption of the integrated circuit.
  • the application provides a field effect transistor, its manufacturing method and an integrated circuit, which are used to reduce the sub-threshold swing of the field effect transistor, thereby reducing the operating voltage of the integrated circuit, so that the power consumption of the integrated circuit is lower.
  • the embodiment of the present application provides a field effect transistor, and the field effect transistor may include: a first cold source, a second cold source, and a A channel, a gate, and a gate dielectric layer between the channel and the gate.
  • the first cold source includes: a first doped layer, a second doped layer, and a first conductor layer located between the first doped layer and the second doped layer, and the first doped layer is in contact with the channel.
  • the second cold source includes: a third doped layer, a fourth doped layer, and a second conductor layer located between the third doped layer and the fourth doped layer, and the third doped layer is in contact with the channel.
  • the field effect transistor may be an N-type cold source transistor, the first doped layer is an N-type doped layer, and the second doped layer is a P-type doped layer.
  • the field effect transistor may be a P-type cold source transistor, the first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer.
  • the structure of the second cold source is similar to that of the first cold source, which will not be repeated here.
  • the first cold source may include a first doped layer, a first conductor layer and a second doped layer, and the first doped layer and the second doped layer belong to different doping types, for example, the first doped layer It may be an N-type doped layer, and the second doped layer may be a P-type doped layer.
  • the field effect transistor By setting doped layers with different doping types in the first cold source, an energy gap can be formed in the first cold source, and by adjusting the density of states, the energy band of the high-energy carriers filtered out makes the injected carrier The energy band of the sub is lower.
  • the traditional field effect transistor realizes switching by adjusting the thermionic emission of the channel barrier, and the energy of injected carriers is relatively high. Therefore, compared with the traditional field effect transistor, in the embodiment of the present application, the field effect transistor behaves like working in a low temperature environment. Therefore, the structure composed of the first doped layer, the first conductor layer and the second doped layer Known as a cold source, the field effect transistor may be called a cold source field effect transistor.
  • a Schottky barrier can be formed between the conductor layer and the doped layer, electrons tunnel from the side of the P-type doped layer to the conductor layer, and then Further tunneling to the side of the N-type doped layer can greatly increase the tunneling probability and increase the on-state current of the field effect transistor.
  • the above-mentioned field effect transistor is provided with a first cold source and a second cold source, and by adjusting the carrier state density of the first cold source or the second cold source, high-energy electrons can be effectively filtered, thereby reducing the
  • the sub-threshold swing of the field effect transistor can be lower than 60mV/dec, thereby reducing the operating voltage of the integrated circuit and lowering the power consumption of the integrated circuit.
  • the conductor layer in the first cold source and the second cold source the tunneling probability of electrons in the first cold source and the second cold source can be increased, thereby increasing the on-state current of the field effect transistor.
  • the above-mentioned first conductor layer may include: a metal material, a semi-metal material, or a metal silicide material.
  • the above-mentioned second conductor layer may include: metal material, semi-metal material or metal silicide material.
  • the metal material may be at least one of aluminum, gold, silver, platinum, palladium, cobalt, tungsten or ruthenium.
  • the aforementioned semimetal (Semimetal) material is a material with a very narrow gap between the guide band and the valence band.
  • the interval between the conduction band and the valence band from narrow to wide solids can be divided into metals, semi-metals, semiconductors and insulators in turn. That is to say, the interval between the conduction band and the valence band of the semi-metal material is smaller than the interval between the conduction band and the valence band of the semiconductor material, and larger than the interval between the conduction band and the valence band of the metal material.
  • the interval between the conduction band and the valence band is relatively large, so that the density of states of electrons near the Fermi level is equal to zero, which becomes the band gap, where the band gap of the insulator is larger than that of the semiconductor.
  • the Fermi level of the metal is in the conduction band, and there is a large enough electronic density of states nearby, so that the current can be well conducted.
  • semi-metallic materials since the gap between the conduction band and valence band of semi-metallic materials is very small, the density of states of electrons near the Fermi level is close to zero but not zero, so semi-metallic materials have no band gap.
  • Semi-metallic materials are in the transition position of metal to non-metal in the periodic table of elements, and their physical and chemical properties are between metal and non-metal.
  • the semi-metallic material may be at least one of arsenic, antimony, bismuth, tin or graphite.
  • the aforementioned metal silicide material may be NiSi 2 , TiSi 2 or CoSi.
  • the first conductor layer and the second conductor layer may also include other conductor materials, for example, the first conductor layer (or the second conductor layer) may include materials such as graphene, two-dimensional metal or metalloid.
  • the first cold source can be used as the source
  • the second cold source can be used as the drain
  • the first cold source can be used as the drain.
  • the cold source is used as the drain
  • the second cold source is used as the source, that is, after the source and drain of the field effect transistor in the embodiment of the application are interchanged, it still has the characteristics of a cold source transistor, which improves the integration of the field effect transistor. flexibility of use in the circuit.
  • the structure of the first cold source is similar to that of the second cold source, and can be manufactured by the same or similar process, which simplifies the complexity of the manufacturing process and reduces the cost of the manufacturing process.
  • the first cold source and the second cold source may be arranged symmetrically with respect to the channel.
  • each part of the first cold source electrode and the second cold source electrode can be manufactured using the same process, which reduces the complexity of the manufacturing process and saves the cost of the manufacturing process.
  • the flexibility of applying the field effect transistor to an integrated circuit is relatively high.
  • the first cold source and the second cold source may also be arranged asymmetrically, which is not limited here.
  • first cold source and the second cold source are arranged asymmetrically, since the structures of the first cold source and the second cold source are similar, the complexity of the manufacturing process of the field effect transistor is also low, and the cost of the manufacturing process is relatively low. Also relatively low.
  • the first cold source and the second cold source may adopt a vertically stacked symmetrical structure.
  • the first doped layer, the channel and the third doped layer are located inside the same semiconductor substrate.
  • the semiconductor substrate may be a silicon-based semiconductor material.
  • the first conductor layer is located on the surface of the semiconductor substrate, the first conductor layer is in contact with the first doped layer, and the second doped layer is located on a side of the first conductor layer away from the first doped layer.
  • the second conductor layer is located on the surface of the semiconductor substrate, the second conductor layer is in contact with the third doped layer, and the fourth doped layer is located on a side of the second conductor layer away from the third doped layer. That is to say, the first cold source and the second cold source are arranged symmetrically with respect to the channel, and both the first cold source and the second cold source adopt a vertical stacked structure.
  • the gate is located on one side of the semiconductor substrate, and the above-mentioned field effect transistor may further include: an insulating layer covering the top surface and side surfaces of the gate.
  • the insulating layer may include a first insulating layer and a second insulating layer covering the first insulating layer.
  • the first insulating layer may be made of silicon dioxide material
  • the second insulating layer may be made of silicon oxide material.
  • the second insulating layer may be made of silicon dioxide material.
  • Other materials may also be used for the first insulating layer and the second insulating layer, which are not limited here.
  • the gate by providing an insulating layer covering the top and side surfaces of the gate, it is possible to insulate the gate from the first cold source and the second cold source, preventing the gate from contacting the first cold source or the second cold source.
  • the source is shorted.
  • the first cold source electrode and the second cold source electrode may also adopt a laterally stacked symmetrical structure.
  • the first cold source, the channel and the second cold source are located inside the same semiconductor substrate, and optionally, the semiconductor substrate may be a silicon-based semiconductor material.
  • the first conductor layer is located on a side of the first doped layer away from the channel, and the second doped layer is located on a side of the first conductor layer away from the first doped layer.
  • the second conductor layer is located on a side of the third doped layer away from the channel, and the fourth doped layer is located on a side of the second conductor layer away from the third doped layer. That is to say, the first cold source and the second cold source are arranged symmetrically with respect to the channel, and both the first cold source and the second cold source adopt a lateral stacked structure.
  • a groove may be provided on the surface of the semiconductor substrate, the gate dielectric layer is located in the groove, and a part of the gate is embedded in the groove. In this way, the distance between the gate and the channel in the semiconductor substrate can be made relatively close, and it is convenient to control the on-off between the first cold source and the second cold source through the gate.
  • the field effect transistor in the embodiment of the present application may also have an asymmetric structure.
  • the first cold source, the channel and the third doped layer are located inside the same semiconductor substrate.
  • the semiconductor substrate may be a silicon-based semiconductor material.
  • the first conductor layer is located on a side of the first doped layer away from the channel, and the second doped layer is located on a side of the first conductor layer away from the first doped layer.
  • the second conductor layer is located on the surface of the semiconductor substrate, the second conductor layer is in contact with the third doped layer, and the fourth doped layer is located on a side of the second conductor layer away from the third doped layer. That is to say, the first cold source and the second cold source may also be arranged asymmetrically. Wherein, the first cold source can adopt a horizontal stacked structure, and the second cold source can adopt a vertical stacked structure.
  • the field effect transistor provided in the embodiment of the present application may also be a charge trapping field effect transistor
  • the gate dielectric layer may include: a tunneling layer located on the side of the gate close to the channel, located on A charge trapping layer between the tunneling layer and the gate, and a charge blocking layer between the charge trapping layer and the gate.
  • the aforementioned field effect transistor may also be a ferroelectric field effect transistor.
  • the gate dielectric layer includes: an interface oxide layer located on the side of the gate close to the channel, and a ferroelectric layer located between the interface oxide layer and the gate.
  • the field effect transistors in the embodiments of the present application may also be other types of field effect transistors, and the structures of several types of field effect transistors will be described below.
  • the first cold source, the channel and the second cold source form a columnar structure
  • the gate dielectric layer wraps outside the channel
  • the gate wraps outside the gate dielectric layer.
  • the field effect transistor in the embodiment of the present application may also be a vertical structure field effect transistor.
  • the structure of the vertical structure field effect transistor is relatively compact, and the second doped layer in the first cold source and the fourth doped layer in the second cold source are located at both ends, so that the first cold source and the The second cold source leads out.
  • the gate is wrapped on the outside of the channel, and the overlapping area between the gate and the channel is relatively large, which increases the width-to-length ratio of the channel and improves the performance of the field effect transistor.
  • the first cold source, the channel and the second cold source are located on the surface of the same semiconductor substrate.
  • the second doped layer is block-shaped, the first conductive layer wraps a part of the second doped layer close to the semiconductor substrate, and the first doped layer is located on the surface of the first conductive layer close to the channel.
  • the fourth doped layer is block-shaped, the second conductor layer wraps a part of the fourth doped layer close to the semiconductor substrate, and the third doped layer is located on the surface of the second conductor layer close to the channel.
  • the field effect transistor provided in the embodiment of the present application may be a fin field effect transistor.
  • the gate In the fin field effect transistor, the gate is located on the surface of the semiconductor substrate on which the channel is provided, and the gate covers the channel. In this way, the overlapping area between the gate and the channel is relatively large, and the channel is enlarged. The width-to-length ratio improves the performance of field effect transistors.
  • isolation dielectric layers 18 are provided on the outer sides of the two opposite sides of the semiconductor substrate 10 . The isolation dielectric layer 18 has the function of protecting the semiconductor substrate 10 and also plays the role of insulation.
  • the first cold source and the second cold source are located on the surface of the same semiconductor substrate.
  • the field effect transistor includes: at least two channels located on one side of the semiconductor substrate; the at least two channels in the field effect transistor are arranged in sequence in a direction perpendicular to the surface of the semiconductor substrate, and between two adjacent channels There is a gap between the semiconductor substrate and the nearest channel.
  • the gate is located on the surface of the semiconductor substrate on which the channel is provided, and the gate wraps each channel in the field effect transistor. In this way, the overlapping area between the gate and the channel is larger, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved.
  • the first doped layer is connected to one end of each of the at least two channels, and the third doped layer is connected to the other end of each of the at least two channels.
  • the first conductor layer is located on the surface of the first doped layer away from the channel, and the second doped layer is located on the surface of the first conductor layer away from the first doped layer.
  • the second conductor layer is located on the surface of the third doped layer away from the channel, and the fourth doped layer is located on the surface of the second conductor layer away from the third doped layer.
  • the field effect transistor provided in the embodiment of the present application may be a gate-all-round field effect transistor, and the second doped layer and the fourth doped layer in the gate-all-round field effect transistor are located on the outside, so that the first cold source and a second cold source lead out.
  • isolation dielectric layers 18 are provided on the outer sides of the two opposite sides of the semiconductor substrate 10 .
  • the isolation dielectric layer 18 has the function of protecting the semiconductor substrate 10 and also plays the role of insulation.
  • field effect transistors provided in the embodiments of the present application may also be of other types, which will not be listed one by one here.
  • the embodiment of the present application further provides an integrated circuit, which includes: any field effect transistor described above, and a signal line electrically connected to the field effect transistor. Since the subthreshold swing of the above-mentioned field effect transistor provided in the embodiment of the present application is low, the subthreshold swing of the field effect transistor can be less than 60mV/dec, therefore, the operating voltage of the integrated circuit in the embodiment of the present application is relatively low, Furthermore, the power consumption of the integrated circuit is low.
  • the embodiment of the present application also provides a method for manufacturing a field effect transistor, the method may include:
  • a channel, a first doped layer and a third doped layer are respectively formed by a doping process; the first doped layer is in contact with the channel, and the third doped layer is in contact with the channel; the first doped layer and the third doped layer are in contact with the channel;
  • the impurity layer belongs to the same doping type;
  • the second doped layer and the fourth doped layer are formed by a doping process; the first conductor layer is located between the first doped layer and the second doped layer, and the second conductor layer is located between the third doped layer and the fourth doped layer. between the impurity layers; the second doping layer and the fourth doping layer belong to the same doping type, and the second doping layer and the first doping layer belong to different doping types.
  • two cold sources can be formed in the field effect transistor, that is, the first cold source and the second cold source, wherein the first cold source includes: a first doped The impurity layer, the second doped layer and the first conductor layer, and the second cold source include: the third doped layer, the fourth doped layer and the second conductor layer.
  • the carrier density of states of the first cold source or the second cold source By adjusting the carrier density of states of the first cold source or the second cold source, high-energy electrons can be effectively filtered, thereby reducing the sub-threshold swing of the field effect transistor, so that the sub-threshold swing of the field effect transistor can be less than 60mV/ dec, thereby reducing the operating voltage of the integrated circuit, so that the power consumption of the integrated circuit is lower.
  • the conductor layer in the first cold source and the second cold source the tunneling probability of electrons in the first cold source and the second cold source can be increased, thereby increasing the on-state current of the field effect transistor.
  • the first cold source and the second cold source can be arranged symmetrically with respect to the channel, since the first doped layer and the third doped layer belong to the same doping type, therefore, it can be The first doping layer and the third doping layer are formed by using the same doping process, thereby saving process steps and production costs.
  • the first conductor layer and the second conductor layer can also be produced by the same process, and the second doped layer and the fourth doped layer can also be produced by the same doping process.
  • FIG. 1 is a schematic diagram of an internal structure of a terminal in an embodiment of the present application
  • Fig. 2 is the simplified structure schematic diagram of the field effect transistor that the embodiment of the present application provides;
  • FIG. 3a is a simplified structural schematic diagram of a type of field effect transistor in an embodiment of the present application.
  • Fig. 3b is a simplified structural schematic diagram of another type of field effect transistor in the embodiment of the present application.
  • 4a is a schematic diagram of an energy level structure of a field effect transistor in the related art
  • Figure 4b is a schematic diagram of the energy level structure of the field effect transistor in the embodiment of the present application.
  • Figure 5a is a schematic diagram of the relationship between the drain current and the gate voltage of a single-ended cold source transistor
  • Figure 5b is a schematic diagram of the relationship between the drain current and the gate voltage of the double-terminal cold source transistor
  • FIG. 6 is a schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • FIG. 7 is another schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • FIG. 8 is another schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • FIG. 9 is another schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • FIG. 10 is another schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a three-dimensional structure of a field effect transistor provided in an embodiment of the present application.
  • FIG. 12 is a schematic diagram of another three-dimensional structure of a field effect transistor provided in an embodiment of the present application.
  • Fig. 13 is a schematic cross-sectional view at the dotted line AA' in Fig. 12;
  • FIG. 14 is a schematic diagram of another three-dimensional structure of a field effect transistor provided in an embodiment of the present application.
  • FIG. 15 is a flow chart of a manufacturing method of a field effect transistor provided in an embodiment of the present application.
  • 10-semiconductor substrate 11-first cold source; 111-first doped layer; 112-second doped layer; 113-first conductor layer; 12-second cold source; 121-third doped 122-fourth doped layer; 123-second conductor layer; 13-channel; 14-gate; 15-gate dielectric layer; 161-first insulating layer; 162-second insulating layer; 171 - contact electrode; 172 - extraction electrode; 173 - first barrier layer; 174 - second barrier layer; 18 - isolation dielectric layer; S1 - first surface; S2 - second surface.
  • Embodiments of the present application provide a field effect transistor, a manufacturing method thereof, and an integrated circuit.
  • the field effect transistor may be a planar field effect transistor, a double gate field effect transistor, or a triple gate type.
  • Field effect transistor fin field effect transistor
  • FinFET ring gate field effect transistor
  • GAAFET gate-all-around field effect transistor
  • Vertical MOSFET Vertical MOSFET
  • Floating Gate MOSFET Charge Trapping MOSFET
  • Thin Film Transistor Thin Film Transistor
  • Ferroelectric Field Effect Transistor FeFET
  • the field effect transistor can be applied in an integrated circuit, and the integrated circuit can be an integrated circuit with various functions such as logic, storage (such as Flash, DRAM, etc.), simulation, and sensing.
  • the field effect transistors in the embodiments of the present application can also be applied to other types of integrated circuits, and no more examples will be given here.
  • FIG. 1 is a schematic diagram of the internal structure of the terminal in the embodiment of the present application. As shown in FIG. In the chip 102 mentioned above.
  • Fig. 2 is a simplified structural schematic diagram of a field effect transistor provided by the embodiment of the present application.
  • the field effect transistor may include: a first cold source 11, a second cold source 12, a The channel 13 between the second cold source 11 and the second cold source 12 , the gate 14 , and the gate dielectric layer 15 between the channel 13 and the gate 14 .
  • the first cold source 11 is used as the source of the field effect transistor
  • the second cold source 12 is used as the drain of the field effect transistor
  • the first cold source 11 is used as the drain of the field effect transistor
  • the second cold source 12 is used as the drain of the field effect transistor.
  • the cold source 12 acts as the source of the field effect transistor.
  • the source and the drain of the field effect transistor in the embodiment of the present application can be interchanged.
  • the conduction state between the source and the drain can be controlled by applying a gate voltage to the gate 14 .
  • the gate voltage is higher than the threshold voltage, the conduction between the source and the drain occurs.
  • the gate voltage is lower than the threshold voltage, the field effect transistor is in a subthreshold state, and there is a slight leakage current between the source and the drain.
  • the first cold source 11 may include: a first doped layer 111, a second doped layer 112, and a first conductor layer 113 located between the first doped layer 111 and the second doped layer 112, the first doped layer The impurity layer 111 is in contact with the channel 13 .
  • the second cold source 12 may include: a third doped layer 121, a fourth doped layer 122, and a second conductor layer 123 located between the third doped layer 121 and the fourth doped layer 122, the third doped layer The impurity layer 121 is in contact with the channel 13 .
  • the first doped layer 111 and the third doped layer 121 belong to the same doping type, and the second doped layer 112 and the fourth doped layer 122 belong to the same doping type; the first doped layer 111 and the second doped layer 112 belongs to a different doping type.
  • the structure of the second cold source 12 is similar to that of the first cold source 11, I won't repeat them here.
  • the first cold source 11 may include a first doped layer 111, a first conductor layer 113, and a second doped layer 112, and the first doped layer 111 and the second doped layer 112 belong to different doping types, for example , the first doped layer 111 may be an N-type doped layer, and the second doped layer 112 may be a P-type doped layer.
  • the traditional field effect transistor realizes switching by adjusting the thermionic emission of the channel barrier, and the energy of injected carriers is relatively high. Therefore, compared with the traditional field effect transistor, in the embodiment of the present application, the performance of the field effect transistor is like working in a low temperature environment. Therefore, the first doped layer 111, the first conductive layer 113 and the second doped layer 112
  • the composed structure is called a cold source, and the field effect transistor can be called a cold source field effect transistor.
  • Fig. 3a and Fig. 3b are the simplified structural representations of different types of field effect transistors in the embodiment of the present application.
  • the field effect transistor can be an N-type cold source transistor ( N-type cold source field effect transistor, nCSFET)
  • the first doped layer 111 can be an N-type doped layer
  • the second doped layer 112 can be a P-type doped layer
  • the third doped layer 121 can be an N-type Doped layer
  • the fourth doped layer 122 may be a P-type doped layer.
  • the field effect transistor can be a P-type cold source field effect transistor (P-type cold source field effect transistor, pCSFET), and the first doped layer 111 can be a P-type Doped layers, the second doped layer 112 may be an N-type doped layer, the third doped layer 121 may be a P-type doped layer, and the fourth doped layer 122 may be an N-type doped layer.
  • P-type cold source field effect transistor P-type cold source field effect transistor
  • pCSFET P-type cold source field effect transistor
  • the semiconductor layer may include materials such as silicon, germanium, silicon germanium, silicon carbide, III-V compound semiconductors, oxide semiconductors, or carbon nanotubes.
  • the semiconductor layer may also include other semiconductor materials. Do limited.
  • the field effect transistor is provided with a first cold source and a second cold source, and by adjusting the carrier density of states of the first cold source or the second cold source, high-energy electrons can be effectively filtered , so as to reduce the sub-threshold swing of the field effect transistor, so that the sub-threshold swing of the field effect transistor can be less than 60mV/dec, thereby reducing the operating voltage of the integrated circuit and lowering the power consumption of the integrated circuit.
  • the conductor layer in the first cold source and the second cold source the tunneling probability of electrons in the first cold source and the second cold source can be increased, thereby increasing the on-state current of the field effect transistor.
  • the principle that the field effect transistor in the embodiment of the present application can reduce the sub-threshold swing will be described in detail below with reference to the accompanying drawings.
  • the field effect transistor in the embodiment of the present application as an example shown in FIG. 112 may be a P-type doped layer
  • the third doped layer 121 in the second cold source 12 may be an N-type doped layer
  • the fourth doped layer 122 may be a P-type doped layer.
  • the principle that the field effect transistor of the type shown in FIG. 3b can reduce the sub-threshold swing is similar and will not be repeated here.
  • FIG. 4 a is a schematic diagram of an energy level structure of a field effect transistor in the related art
  • FIG. 4 b is a schematic diagram of an energy level structure of a field effect transistor in an embodiment of the present application.
  • the energy bands of the P-type doped layer and the N-type doped layer include a conduction band Ec, a forbidden band and a valence band Ev, wherein the conduction band Ec is above the forbidden band, and the valence band Ev is at Below the forbidden band.
  • the energy band of injected carriers that is, the region indicated by arrow W1 in Figure 4a
  • the energy band of injected carriers is above the conduction band Ec, that is, the energy of injected carriers is higher .
  • the energy band of the P-type doped layer moves up relative to the energy band of the N-type doped layer, while the energy band of the N-type doped layer Relative to the energy band of the P-type doped layer, it moves down until the Fermi level.
  • the energy band of the P-type doped layer is equal to the energy band of the N-type doped layer, the energy band stops moving relatively.
  • the PN junction formed between the impurity layer and the N-type doped layer reaches an equilibrium state. In the balanced PN junction, there is an overlapping region between the valence band Ev of the P-type doped layer and the conduction band Ec of the N-type doped layer.
  • the region indicated by arrow W2 is the energy band of filtered high-energy carriers
  • the region indicated by arrow W3 is the energy band of injected carriers. Since the overlapping area where electron tunneling can occur only accounts for a small part of the area, while the forbidden band where electrons cannot tunnel accounts for most of the area, the PN junction can effectively suppress the high-energy carriers excited by thermal energy and reduce the thermal excitation. Leakage, thereby reducing the sub-threshold swing, for example, the sub-threshold swing can be lower than 60mV/dec. At this time, the field effect transistor behaves like working in a low temperature environment, so it can be called a cold source field effect transistor.
  • the on-state current of the field effect transistor cannot meet the requirements.
  • a Schottky barrier can be formed between the conductor layer and the doped layer, and electrons flow from the P-type doped layer One side tunnels to the conductor layer, and then further tunnels to the side of the N-type doped layer, which can greatly increase the tunneling probability and increase the on-state current of the field effect transistor.
  • the source is electrically connected to the contact electrode, and carriers are injected into the source from the contact electrode. Since the hot carriers on the potential barrier satisfy the Fermi distribution, the subthreshold swing is between It cannot be less than 60mV/dec at room temperature.
  • the first cold source or the second cold source suppresses the thermal tail by introducing an energy gap.
  • the first cold source or the second cold source is controlled by the density of states to form "cold" carriers injected into the source.
  • the distribution of "cold" carriers does not extend into the thermalized Fermi band tail in the off state, because the hot band tail has been cut off by the upper band gap, so the off-state current is greatly reduced.
  • the sub-threshold swing of the field effect transistor in the embodiment of the present application may not be limited to 60 mV/dec.
  • the above-mentioned first conductor layer may include: a metal material, a semi-metal material, or a metal silicide material.
  • the above-mentioned second conductor layer may include: metal material, semi-metal material or metal silicide material.
  • the above metal material can be at least one of aluminum (Al), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), cobalt (Co), tungsten (W) or ruthenium (Ru) kind.
  • the aforementioned semimetal (Semimetal) material is a material with a very narrow gap between the guide band and the valence band.
  • the interval between the conduction band and the valence band from narrow to wide solids can be divided into metals, semi-metals, semiconductors and insulators in turn. That is to say, the interval between the conduction band and the valence band of the semi-metal material is smaller than the interval between the conduction band and the valence band of the semiconductor material, and larger than the interval between the conduction band and the valence band of the metal material.
  • the interval between the conduction band and the valence band is relatively large, so that the density of states of electrons near the Fermi level is equal to zero, which becomes the band gap, where the band gap of the insulator is larger than that of the semiconductor.
  • the Fermi level of the metal is in the conduction band, and there is a large enough electronic density of states nearby, so that the current can be well conducted.
  • Semi-metallic materials since the gap between the conduction band and valence band of semi-metallic materials is very small, the density of states of electrons near the Fermi level is close to zero but not zero, so semi-metallic materials have no band gap.
  • Semi-metallic materials are in the transition position of metal to non-metal in the periodic table of elements, and their physical and chemical properties are between metal and non-metal.
  • the above semi-metallic material may be at least one of arsenic, antimony, bismuth, tin or graphite.
  • the aforementioned metal silicide may be made of NiSi 2 , TiSi 2 or CoSi.
  • the first conductor layer and the second conductor layer may also include other conductor materials, for example, the first conductor layer (or the second conductor layer) may include materials such as graphene, two-dimensional metals or metalloids.
  • the first cold source can be used as the source
  • the second cold source can be used as the drain
  • the first cold source can be used as the drain.
  • the cold source is used as the drain
  • the second cold source is used as the source, that is, after the source and drain of the field effect transistor in the embodiment of the application are interchanged, it still has the characteristics of a cold source transistor, which improves the integration of the field effect transistor. flexibility of use in the circuit.
  • the structure of the first cold source is similar to that of the second cold source, and can be manufactured by the same or similar process, which simplifies the complexity of the manufacturing process and reduces the cost of the manufacturing process.
  • Fig. 5a is a schematic diagram of the curve relationship between the drain current and the gate voltage of the single-ended cold source transistor
  • Fig. 5b is a schematic diagram of the curve relationship between the drain current and the gate voltage of the double-terminal cold source transistor.
  • the steeper the curve the smaller the subthreshold swing.
  • a single-ended cold source transistor means that only one of the source and drain is set as a cold source.
  • the curve L1 is the drain when the source is set as a cold source.
  • the curve L2 is the relationship curve between the drain current and the gate voltage when the drain is set as a cold source.
  • the double-terminal cold source transistor refers to that the field effect transistor includes two cold sources, a first cold source and a second cold source. Using the first cold source as the source and the second cold source as the drain, or using the first cold source as the drain and the second cold source as the source, the drain current and the gate current in these two cases
  • the relationship curves of the pole voltages can all be the curve L3 in FIG. 5b.
  • the double-ended cold-source transistor After the source and drain of the double-ended cold-source transistor are interchanged, the double-ended cold-source transistor The ability to control the density of states is not affected, and the subthreshold swing of the double-terminal cold source transistor is less than 60mV/dec. Therefore, compared with the single-ended cold-source transistor, the double-ended cold-source transistor can realize the excellent characteristic that the source and the drain are used interchangeably. In addition, the double-terminal cold source transistor can reduce the process complexity, which is beneficial to the process integration of integrated circuits.
  • the first cold source and the second cold source may be arranged symmetrically with respect to the channel.
  • each part of the first cold source electrode and the second cold source electrode can be manufactured using the same process, which reduces the complexity of the manufacturing process and saves the cost of the manufacturing process.
  • the flexibility of applying the field effect transistor to an integrated circuit is relatively high.
  • the first cold source and the second cold source may also be arranged asymmetrically, which is not limited here.
  • first cold source and the second cold source are arranged asymmetrically, since the structures of the first cold source and the second cold source are similar, the complexity of the manufacturing process of the field effect transistor is also low, and the cost of the manufacturing process is relatively low. Also relatively low.
  • the first cold source and the second cold source may adopt a vertically stacked symmetrical structure, as shown in FIG. 6 , which is a schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • the first doped The layer 111, the channel 13 and the third doped layer 121 are located inside the same semiconductor substrate 10.
  • the semiconductor substrate 10 may be a silicon-based semiconductor material, and the semiconductor substrate 10 may have: opposite first surfaces S1 and the second surface S2 , for example, the first surface S1 may be the upper surface of the semiconductor substrate 10 , and the second surface S2 may be the lower surface of the semiconductor substrate 10 .
  • the first conductive layer 113 is located on the surface of the semiconductor substrate 10, the first conductive layer 113 is in contact with the first doped layer 111, and the second doped layer 112 is located on the side of the first conductive layer 113 away from the first doped layer 111 .
  • the second conductor layer 123 is located on the surface of the semiconductor substrate 10, for example, the first conductor layer 113 and the second conductor layer 123 may be located on the first surface S1 of the semiconductor substrate 10, the second conductor layer 123 and the third doped
  • the fourth doped layer 122 is located on the side of the second conductive layer 123 away from the third doped layer 121 . That is to say, the first cold source 11 and the second cold source 12 can be arranged symmetrically with respect to the channel 13 , and both the first cold source 11 and the second cold source 12 adopt a vertical stacked structure.
  • a doping process may be used to form the first doped layer 111 , the third doped layer 121 and the channel 13 on the surface of the semiconductor substrate 10 . Since the first doped layer 111 and the third doped layer 121 belong to the same doping type, the first doped layer 111 and the third doped layer 121 can be produced by the same doping process, thereby saving process steps and production costs . Moreover, the first conductive layer 113 and the second conductive layer 123 can also be fabricated by the same process, and the second doped layer 112 and the fourth doped layer 122 can also be fabricated by the same process.
  • the above-mentioned field effect transistor may also include: a contact electrode 171 and an extraction electrode 172, and the contact electrode 171 and the second doped layer 112 (or the fourth doped layer 122)
  • the lead electrode 172 is electrically connected to the contact electrode 171 .
  • the contact electrodes 171 and the lead-out electrodes 172 can be made of metal materials, for example, metal tungsten can be used.
  • a barrier layer can be set on the side of the contact electrode 171, for example, a first barrier layer 173 can be set on the side of the contact electrode 171, and the first barrier layer 173 A second barrier layer 174 is provided on the side of the .
  • the barrier layer is generally made of conductive material, so the barrier layer has better conductivity and will not affect the electrical connection between the contact electrode 171 and the second doped layer 112 (or the fourth doped layer 122).
  • the barrier layer can be made of materials such as titanium or titanium nitride.
  • the gate 14 is located on one side of the semiconductor substrate 10, and the above field effect transistor may further include: an insulating layer covering the top surface and side surfaces of the gate 14, insulating The layer may insulate the gate 14 from the first cold source 11 and the insulating layer may insulate the gate 14 from the second cold source 12 .
  • the insulating layer may include a first insulating layer 161, and a second insulating layer 162 covering the first insulating layer 161, the first insulating layer 161 may be made of a silicon dioxide material, and the second insulating layer 162 may be made of a silicon oxide material.
  • first insulating layer 161 and the second insulating layer 162 can also be used for the first insulating layer 161 and the second insulating layer 162 , which are not limited here.
  • the gate 14 by setting an insulating layer covering the top and side surfaces of the gate 14, the gate 14 can be insulated from the first cold source 11 and the second cold source 12, preventing the gate 14 from contacting the first cold source. pole 11 or the second cold source pole 12 is short-circuited.
  • first cold source and the second cold source may also adopt a laterally stacked symmetrical structure, as shown in FIG.
  • the pole 11, the channel 13 and the second cold source 12 are located inside the same semiconductor substrate 10.
  • the semiconductor substrate 10 can be a silicon-based semiconductor material, and the semiconductor substrate 10 can have: opposite first surfaces S1 and the second surface S2 , for example, the first surface S1 may be the upper surface of the semiconductor substrate 10 , and the second surface S2 may be the lower surface of the semiconductor substrate 10 .
  • the first cold source 11 , the channel 13 and the second cold source 12 may be located on a side of the semiconductor substrate 10 close to the first surface S1 .
  • the first conductive layer 113 is located on a side of the first doped layer 111 away from the channel 13
  • the second doped layer 112 is located on a side of the first conductive layer 113 away from the first doped layer 111
  • the second conductive layer 123 is located on a side of the third doped layer 121 away from the channel 13
  • the fourth doped layer 122 is located on a side of the second conductive layer 123 away from the third doped layer 121 . That is to say, the first cold source 11 and the second cold source 12 are arranged symmetrically with respect to the channel 13 , and both the first cold source 11 and the second cold source 12 adopt a lateral stacked structure.
  • the first doped layer 111 and the third doped layer 121 can be formed on the surface of the semiconductor substrate 10 by using the same doping process, and the second doped layer 121 can be formed on the surface of the semiconductor substrate 10 by using the same doping process.
  • the impurity layer 112 and the fourth doped layer 122 therefore, the manufacturing process of the field effect transistor is simple, the process steps are less, and the manufacturing cost is lower.
  • a groove U is provided on the surface of the above-mentioned semiconductor substrate 10 , the gate dielectric layer 15 is located in the groove U, and a part of the gate 14 is embedded in the groove U. In this way, the distance between the gate 14 and the channel 13 in the semiconductor substrate 10 can be made relatively close, which is convenient for controlling the on-off between the first cold source 11 and the second cold source 12 through the gate 14 .
  • the field effect transistor in the embodiment of the present application may also have an asymmetric structure, as shown in Figure 8, which is another schematic cross-sectional view of the field effect transistor provided in the embodiment of the present application, the first cold source 11.
  • the channel 13 and the third doped layer 121 are located inside the same semiconductor substrate 10 .
  • the semiconductor substrate 10 may be a silicon-based semiconductor material, and the semiconductor substrate 10 may have: opposite first surfaces S1 and second surfaces S2, for example, the first surface S1 may be the upper surface of the semiconductor substrate 10 , the second surface S2 may be the lower surface of the semiconductor substrate 10 .
  • the first conductive layer 113 is located on a side of the first doped layer 111 away from the channel 13
  • the second doped layer 112 is located on a side of the first conductive layer 113 away from the first doped layer 111
  • the second conductor layer 121 is located on the surface of the semiconductor substrate 10, for example, the first cold source 11, the channel 13 and the third doped layer 121 may be located on the side of the semiconductor substrate 10 close to the first surface S1, and the second The conductor layer 123 may be located on the first surface S1 of the semiconductor substrate 10, the second conductor layer 123 is in contact with the third doped layer 121, and the fourth doped layer 122 is located on the side of the second conductor layer 123 away from the third doped layer 121. side. That is to say, the first cold source 11 and the second cold source 12 may also be arranged asymmetrically. Wherein, the first cold source 11 may adopt a horizontal stacked structure, and the second cold source 12 may adopt a vertical stacked structure.
  • the first doped layer 111 and the third doped layer 122 can be formed on the surface of the semiconductor substrate 10 by using the same doping process, so that the process steps can be reduced and the manufacturing cost is low.
  • the first cold source 11 and the second cold source 12 are arranged asymmetrically, the structures of the first cold source 11 and the second cold source 12 are similar, and the manufacturing process is also comparative. Easy and cheap to make.
  • the field effect transistor provided in the embodiment of the present application may also be a charge trapping field effect transistor, as shown in FIG. 9 , which is another schematic cross-sectional view of the field effect transistor provided in the embodiment of the present application.
  • the dielectric layer may include: a tunneling layer 151 located on the side of the gate 14 close to the channel 13, a charge trapping layer 152 located between the tunneling layer 151 and the gate 14, and a charge trapping layer 152 located between the charge trapping layer 152 and the gate 14.
  • the charge blocking layer 153 may be a charge trapping field effect transistor, as shown in FIG. 9 , which is another schematic cross-sectional view of the field effect transistor provided in the embodiment of the present application.
  • the dielectric layer may include: a tunneling layer 151 located on the side of the gate 14 close to the channel 13, a charge trapping layer 152 located between the tunneling layer 151 and the gate 14, and a charge trapping layer 152 located between the charge trapping layer 152 and the gate 14.
  • the aforementioned field effect transistor may also be a ferroelectric field effect transistor, as shown in FIG. 10 , which is another schematic cross-sectional view of the field effect transistor provided in the embodiment of the present application.
  • the aforementioned gate dielectric layer may include : the interface oxide layer 154 located on the side of the gate 14 close to the channel 13 , and the ferroelectric layer 155 located between the interface oxide layer 154 and the gate 14 .
  • the field effect transistors in the embodiments of the present application may also be other types of field effect transistors.
  • the structures of several types of field effect transistors will be described below with reference to the accompanying drawings.
  • Fig. 11 is a schematic diagram of the three-dimensional structure of the field effect transistor provided by the embodiment of the present application.
  • the first cold source 11, the channel and the second cold source 12 form a columnar structure, wherein the channel is located The position between the cold source 11 and the second cold source 12 .
  • the gate dielectric layer 15 wraps outside the channel, and the gate 14 wraps outside the gate dielectric layer 14 . That is to say, the field effect transistor in the embodiment of the present application may also be a vertical structure field effect transistor.
  • the structure of the vertical structure field effect transistor is relatively compact, and the second doped layer 112 in the first cold source 11 and the fourth doped layer 122 in the second cold source 12 are respectively located at both ends, so that the first The cold source 11 and the second cold source 12 are drawn out.
  • the gate 14 is wrapped around the outside of the channel, and the overlapping area between the gate 14 and the channel is larger, which increases the width-to-length ratio of the channel and improves the performance of the field effect transistor.
  • Figure 12 is a schematic diagram of another three-dimensional structure of the field effect transistor provided by the embodiment of the present application
  • Figure 13 is a schematic cross-sectional diagram at the dotted line AA' in Figure 12, as shown in Figure 12 and Figure 13, the first cold source 11, the trench The track 13 and the second cold source 12 are located on the same semiconductor substrate 10.
  • the semiconductor substrate 10 may be a silicon-based semiconductor material.
  • the semiconductor substrate 10 may include: a first surface S1 and a second surface S2 oppositely arranged, for example, the first surface S1 may be the upper surface of the semiconductor substrate 10, and the second surface S2 may be the lower surface of the semiconductor substrate 10 .
  • the first cold source 11 , the channel 13 and the second cold source 12 may be located on the first surface S1 of the semiconductor substrate 10 .
  • isolation dielectric layers 18 are provided on the outer sides of the two opposite sides of the semiconductor substrate 10 .
  • the isolation dielectric layer 18 has the function of protecting the semiconductor substrate 10 and also plays the role of insulation.
  • the second doped layer 112 is block-shaped, the first conductive layer 113 wraps a part of the second doped layer 112 close to the semiconductor substrate 10, and the first doped layer 111 is located on the surface of the first conductive layer 113 near the channel 13 .
  • the fourth doped layer 122 is block-shaped, the second conductive layer 123 wraps a part of the fourth doped layer 122 close to the semiconductor substrate 10, and the third doped layer 121 is located on the surface of the second conductive layer 123 close to the channel 13 . That is to say, the field effect transistor provided in the embodiment of the present application may be a fin field effect transistor.
  • the gate 14 is located on the surface of the semiconductor substrate 10 provided with the channel 13, for example, the gate 14 may be located on the first surface S1 of the semiconductor substrate 10, and the gate 14 covers channel 13 , in this way, the overlapping area between the gate 14 and the channel 13 is larger, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved.
  • FIG. 12 in order to clearly illustrate the internal structure of the field effect transistor, the position of the gate 14 is indicated by a dotted line.
  • the top of the second doped layer 112 is not covered by the first conductive layer. 113 wrapping, therefore, it is convenient to electrically connect the second doped layer 112 with the contact electrode, that is, it is convenient to lead out the first cold source electrode 11 .
  • the top of the fourth doped layer 122 is not covered by the second conductor layer 123 , so it is convenient to electrically connect the fourth doped layer 122 to the contact electrode, that is, to lead out the second cold source 12 .
  • FIG. 14 is a schematic diagram of another three-dimensional structure of the field effect transistor provided by the embodiment of the present application.
  • the first cold source 11 and the second cold source 12 are located on the surface of the same semiconductor substrate 10, for example, The first cold source 11 and the second cold source 12 may be located on the first surface S1 of the semiconductor substrate 10 .
  • the semiconductor substrate 10 may be a silicon-based semiconductor material.
  • the semiconductor substrate 10 may include: a first surface S1 and a second surface S2 oppositely arranged, for example, the first surface S1 may be the upper surface of the semiconductor substrate 10, and the second surface S2 may be the lower surface of the semiconductor substrate 10 .
  • isolation dielectric layers 18 are provided on the outer sides of the two opposite sides of the semiconductor substrate 10 .
  • the isolation dielectric layer 18 has the function of protecting the semiconductor substrate 10 and also plays the role of insulation.
  • the field effect transistor may include: at least two channels 13 located on one side of the semiconductor substrate 10 , for example, the channels 13 may be located on the side of the first surface S1 of the semiconductor substrate 10 . At least two channels 13 in the field effect transistor are arranged in sequence in a direction perpendicular to the surface of the semiconductor substrate 10, and there is a gap between two adjacent channels 13, and the distance between the semiconductor substrate 10 and the nearest channel 13 is There are gaps between them.
  • the field effect transistor includes three channels 13 as an example for illustration, and the number of channels 13 in the field effect transistor is not limited.
  • the gate 14 is located on the surface of the semiconductor substrate 10 provided with the channel 13 side, for example, the gate 14 can be located on the first surface S1 side of the semiconductor substrate 10, and the gate 14 wraps each trench in the field effect transistor Road 13. In this way, the overlapping area between the gate 14 and the channel 13 is larger, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved.
  • the position of the gate 14 is indicated by a dotted line.
  • the first doped layer 111 is connected to one end of each channel 13
  • the third doped layer 121 is connected to the other end of each channel 13
  • the first conductive layer 113 is located on the surface of the first doped layer 111 away from the channel 13
  • the second doped layer 112 is located on the surface of the first conductive layer 113 away from the first doped layer 111
  • the second conductive layer 123 is located on the surface of the third doped layer 121 away from the channel 13
  • the fourth doped layer 122 is located on the surface of the second conductive layer 123 away from the third doped layer 121 .
  • the field effect transistor provided in the embodiment of the present application may be a gate-all-round field effect transistor, and the second doped layer 112 and the fourth doped layer 122 in the gate-all-around field effect transistor are located on the outside, so that the first cold The source 11 and the second cold source 12 are drawn out.
  • field effect transistors provided in the embodiments of the present application may also be of other types, which will not be listed one by one here.
  • an embodiment of the present application further provides an integrated circuit, which may include: any field effect transistor described above, and a signal line electrically connected to the field effect transistor. Since the subthreshold swing of the above-mentioned field effect transistor provided in the embodiment of the present application is low, the subthreshold swing of the field effect transistor can be less than 60mV/dec, therefore, the operating voltage of the integrated circuit in the embodiment of the present application is relatively low, Furthermore, the power consumption of the integrated circuit is low.
  • FIG. 15 is a flow chart of the method for manufacturing a field effect transistor provided in the embodiment of the application. As shown in FIG. 15 , the manufacturing method may include :
  • two cold sources can be formed in the field effect transistor, that is, the first cold source and the second cold source, wherein the first cold source includes: a first doped The impurity layer, the second doped layer and the first conductor layer, and the second cold source include: the third doped layer, the fourth doped layer and the second conductor layer.
  • the carrier density of states of the first cold source or the second cold source By adjusting the carrier density of states of the first cold source or the second cold source, high-energy electrons can be effectively filtered, thereby reducing the sub-threshold swing of the field effect transistor, so that the sub-threshold swing of the field effect transistor can be less than 60mV/ dec, thereby reducing the operating voltage of the integrated circuit, so that the power consumption of the integrated circuit is lower.
  • the conductor layer in the first cold source and the second cold source the tunneling probability of electrons in the first cold source and the second cold source can be increased, thereby increasing the on-state current of the field effect transistor.
  • S201, S202, and S203 are only to identify each step, and do not limit the order of each step. In actual implementation, the order of each step can be adjusted according to the specific structure of the field effect transistor. .
  • the first cold source and the second cold source can be arranged symmetrically with respect to the channel.
  • the same doping process can be used to form the first doped layer 111 and the third doped layer 121, thereby saving process steps and manufacturing costs.
  • the first conductive layer 113 and the second conductive layer 123 can also be fabricated by the same process, and the second doped layer 112 and the fourth doped layer 122 can also be fabricated by the same primary doping process.

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Abstract

本申请提供一种场效应晶体管、其制作方法及集成电路，该场效应晶体管可以包括：第一冷源极、第二冷源极、沟道、栅极，以及栅极介质层。第一冷源极包括：第一掺杂层、第二掺杂层，以及第一导体层，第一掺杂层与沟道接触。第二冷源极包括：第三掺杂层、第四掺杂层，以及第二导体层，第三掺杂层与沟道接触。第一掺杂层与第三掺杂层属于同一掺杂类型，第二掺杂层与第四掺杂层属于同一掺杂类型，第一掺杂层与第二掺杂层属于不同的掺杂类型。通过在场效应晶体管中设置第一冷源极和第二冷源极，通过调整第一冷源极或第二冷源极的载流子态密度，可以降低场效应晶体管的亚阈值摆幅，进而降低集成电路的工作电压，使集成电路的功耗较低。

Description

一种场效应晶体管、其制作方法及集成电路 技术领域
本申请涉及半导体技术领域，特别涉及一种场效应晶体管、其制作方法及集成电路。
背景技术
随着电子技术的不断发展，集成电路的发展趋势已由追求性能和集成度，转变为以降低功耗为主，而降低功耗的最有效的方法为降低工作电压Vdd。集成电路一般包括场效应晶体管(metal oxide semiconductor field effect transistor，MOSFET)，场效应晶体管的栅极电压低于阈值电压时，场效应晶体管处于截止区(或称亚阈值状态)，此时，源极与漏极之间具有微量漏电流，该微量漏电流称为亚阈值电流。使漏极电流变化一个数量级时，所需要的栅极电压的增量称为亚阈值摆幅(sub-threshold swing，SS)，亚阈值摆幅与器件结构和温度等因素有关，亚阈值摆幅越小，则场效应晶体管在亚阈值状态的工作速率越大。
传统的场效应晶体管通过调节沟道势垒的热电子发射实现开关，亚阈值电流是与玻尔兹曼常数有关的指数函数，由于电子满足玻尔兹曼分布特征，使得亚阈值摆幅在室温下无法小于60mV/dec。为了使场效应晶体管保持较大的开关比I on/I off，工作电压Vdd必须是亚阈值摆幅的很多倍，其中，I on表示场效应晶体管的开态电流，I off表示场效应晶体管的关态电流。如果亚阈值摆幅不变，降低工作电压Vdd，会造成开态电流I on变小和器件的性能退化。因此，由于受到场效应晶体管的亚阈值摆幅的限制，难以降低集成电路的工作电压，进而集成电路的功耗难以继续降低。
发明内容
本申请提供了一种场效应晶体管、其制作方法及集成电路，用于降低场效应晶体管的亚阈值摆幅，进而降低集成电路的工作电压，使集成电路的功耗较低。
第一方面，本申请实施例提供了一种场效应晶体管，该场效应晶体管可以包括：第一冷源极、第二冷源极、位于第一冷源极与第二冷源极之间的沟道、栅极，以及位于沟道与栅极之间的栅极介质层。第一冷源极包括：第一掺杂层、第二掺杂层，以及位于第一掺杂层与第二掺杂层之间的第一导体层，第一掺杂层与沟道接触。第二冷源极包括：第三掺杂层、第四掺杂层，以及位于第三掺杂层与第四掺杂层之间的第二导体层，第三掺杂层与沟道接触。第一掺杂层与第三掺杂层属于同一掺杂类型，第二掺杂层与第四掺杂层属于同一掺杂类型；第一掺杂层与第二掺杂层属于不同的掺杂类型。在本申请的一种实施方式中，该场效应晶体管可以为N型冷源晶体管，第一掺杂层为N型掺杂层，第二掺杂层为P型掺杂层。在本申请的另一实施方式中，该场效应晶体管可以为P型冷源晶体管，第一掺杂层为P型掺杂层，第二掺杂层为N型掺杂层。
在本申请实施例中，通过设置第一冷源极和第二冷源极，以第一冷源极为例，第二冷源极与第一冷源极的结构类似，此处不再赘述。第一冷源极可以包括第一掺杂层、第一导体层及第二掺杂层，且第一掺杂层与第二掺杂层属于不同的掺杂类型，例如，第一掺杂层可以为N型掺杂层，第二掺杂层可以为P型掺杂层。通过在第一冷源极中设置掺杂类型不同的掺杂层，可以在第一冷源极内形成能量间隙，通过调控态密度，滤除的高能载流子的 能带，使注入载流子的能带较低。而传统的场效应晶体管通过调节沟道势垒的热电子发射实现开关，注入载流子的能量较高。因此，相比于传统的场效应晶体管，本申请实施例中，场效应晶体管的表现像工作在低温环境下，因此，第一掺杂层、第一导体层及第二掺杂层组成的结构称为冷源极，该场效应晶体管可以称为冷源场效应晶体管。
通过在第一冷源极和第二冷源极中设置导体层，导体层和掺杂层之间可以形成肖特基势垒，电子从P型掺杂层一侧遂穿到导体层，再进一步遂穿到N型掺杂层一侧，这样可以大大提高遂穿几率，提升场效应晶体管的开态电流。
上述场效应晶体管中设有第一冷源极和第二冷源极，通过调整第一冷源极或第二冷源极的载流子态密度，可以有效过滤高能电子，从而降低场效应晶体管的亚阈值摆幅，使场效应晶体管的亚阈值摆幅能够小于60mV/dec，进而降低集成电路的工作电压，使集成电路的功耗较低。并且，通过在第一冷源极和第二冷源极中设置导体层，可以提升第一冷源极和第二冷源极中电子的隧穿几率，进而提高场效应晶体管的开态电流。
在具体实施时，本申请实施例提供的上述场效应晶体管中，上述第一导体层可以包括：金属材料、半金属材料、或金属硅化物材料。上述第二导体层可以包括：金属材料、半金属材料或金属硅化物材料。其中，金属材料可以为铝、金、银、铂、钯、钴、钨或钌中的至少一种。上述半金属(Semimetal)材料是指导带和价带之间相隔很窄的材料。根据能带理论，根据导带和价带之间的间隔从窄到宽，固体可以依次分为金属、半金属、半导体和绝缘体。也就是说，半金属材料的导带与价带之间的间隔，小于半导体材料的导带与价带之间的间隔，且大于金属材料的导带与价带之间的间隔。对于半导体和绝缘体，导带和价带之间的间隔相对较大，使得费米能级附近电子的态密度等于零，成为带隙，其中绝缘体的带隙比半导体的大。金属的费米能级则在导带当中，附近有足够大的电子态密度，使得电流可以良好地传导。而对于半金属材料，由于半金属材料的导带和价带之间的间隔十分小，使得费米能级附近电子的态密度接近于零但不为零，因此半金属材料没有带隙。半金属材料在元素周期表中处于金属向非金属过渡的位置，物理性质和化学性质介于金属和非金属之间。例如，半金属材料可以为砷、锑、铋、锡或石墨中的至少一种。上述金属硅化物材料可以为NiSi 2、TiSi 2或CoSi。当然，上述第一导体层和第二导体层也可以包括其他导体材料，例如，第一导体层(或第二导体层)可以包括石墨烯、二维金属或类金属等材料。
本申请实施例中，通过在场效应晶体管中设置第一冷源极和第二冷源极，可以将第一冷源极作为源极，第二冷源极作为漏极，或者，可以将第一冷源作为漏极，第二冷源极作为源极，即本申请实施例中的场效应晶体管的源极和漏极互换后，仍具有冷源晶体管的特点，提升了场效应晶体管在集成电路中使用的灵活性。并且，第一冷源极与第二冷源极的结构类似，可以采用相同或相似的工艺制作，简化了制作工艺的复杂度，降低了制作工艺的成本。
可选地，本申请实施例提供的上述场效应晶体管中，第一冷源极与第二冷源极相对于沟道可以对称设置。在制作过程中，可以采用相同的工艺制作第一冷源极和第二冷源极中的各部分，降低制作工艺的复杂度，节省制作工艺的成本。并且，将该场效应晶体管应用于集成电路中的灵活性较高。当然，第一冷源极与第二冷源极也可以设置为非对称，此处不做限定。第一冷源极与第二冷源极为非对称设置时，由于第一冷源极与第二冷源极的结构相似，该场效应晶体管的制作工艺的复杂度也较低，制作工艺的成本也比较低。
举例来说，第一冷源极与第二冷源极可以采用竖向层叠的对称结构。具体地，第一掺杂层、沟道及第三掺杂层位于同一半导体衬底的内部，可选地，半导体衬底可以为硅基半导体材料。第一导体层位于半导体衬底的表面上，第一导体层与第一掺杂层接触，第二掺杂层位于第一导体层远离第一掺杂层的一侧。第二导体层位于半导体衬底的表面上，第二导体层与第三掺杂层接触，第四掺杂层位于第二导体层远离第三掺杂层的一侧。也就是说，第一冷源极与第二冷源极相对于沟道对称设置，且第一冷源极和第二冷源极均采用竖向叠层结构。
在本申请的一种实现方式中，栅极位于半导体衬底的一侧，上述场效应晶体管还可以包括：覆盖栅极的顶面和侧面的绝缘层。例如，该绝缘层可以包括第一绝缘层，以及覆盖第一绝缘层的第二绝缘层，第一绝缘层可以采用二氧化硅材料制作，第二绝缘层可以采用氧化硅材料制作，当然，第一绝缘层和第二绝缘层也可以采用其他材料，此处不做限定。本申请实施例中，通过设置覆盖栅极的顶面和侧面的绝缘层，可以绝缘栅极与第一冷源极和第二冷源极，防止栅极与第一冷源极或第二冷源极发生短接。
在本申请的一种实现方式中，第一冷源极与第二冷源极也可以采用横向层叠的对称结构。具体地，第一冷源极、沟道及第二冷源极位于同一半导体衬底的内部，可选地，半导体衬底可以为硅基半导体材料。第一导体层位于第一掺杂层远离沟道的一侧，第二掺杂层位于第一导体层远离第一掺杂层的一侧。第二导体层位于第三掺杂层远离沟道的一侧，第四掺杂层位于第二导体层远离第三掺杂层的一侧。也就是说，第一冷源极与第二冷源极相对于沟道对称设置，且第一冷源极和第二冷源极均采用横向叠层结构。
在实际应用中，半导体衬底的表面可以设置凹槽，栅极介质层位于凹槽内，栅极的一部分嵌入到凹槽内。这样，可以使栅极与半导体衬底中的沟道的距离较近，便于通过栅极控制第一冷源极与第二冷源极之间的通断。
在本申请的一种实现方式中，本申请实施例中的场效应晶体管也可以为非对称结构。第一冷源极、沟道及第三掺杂层位于同一半导体衬底的内部。可选地，半导体衬底可以为硅基半导体材料。第一导体层位于第一掺杂层远离沟道的一侧，第二掺杂层位于第一导体层远离第一掺杂层的一侧。第二导体层位于半导体衬底的表面上，第二导体层与第三掺杂层接触，第四掺杂层位于第二导体层远离第三掺杂层的一侧。也就是说，第一冷源极与第二冷源极也可以为非对称设置。其中，第一冷源极可以采用横向叠层结构，第二冷源极可以采用竖向叠层结构。
在本申请的一种实现方式中，本申请实施例提供的场效应晶体管也可以为电荷俘获型场效应晶体管，栅极介质层可以包括：位于栅极靠近沟道一侧的隧穿层，位于隧穿层与栅极之间的电荷俘获层，以及位于电荷俘获层与栅极之间的电荷阻挡层。
在本申请的一种实现方式中，上述场效应晶体管也可以为铁电场效应晶体管。栅极介质层包括：位于栅极靠近沟道一侧的界面氧化层，以及位于界面氧化层与栅极之间的铁电层。
除上述几种结构外，本申请实施例中的场效应晶体管也可以为其他类型的场效应晶体管，以下对几种类型的场效应晶体管的结构进行说明。
在本申请的一种实现方式中，第一冷源极、沟道及第二冷源极构成柱状结构，栅极介质层包裹于沟道的外侧，栅极包裹于栅极介质层的外侧。也就是说，本申请实施例中的场效应晶体管也可以为垂直结构场效应晶体管。该垂直结构场效应晶体管的结构较紧凑，且 第一冷源极中的第二掺杂层与第二冷源极中的第四掺杂层分别位于两端，便于将第一冷源极和第二冷源极引出。此外，栅极包裹于沟道的外侧，栅极与沟道之间的重叠面积较大，增大沟道的宽长比，提升场效应晶体管的性能。
在本申请的一种实现方式中，第一冷源极、沟道及第二冷源极位于同一半导体衬底的表面上。第二掺杂层为块状，第一导体层包裹靠近半导体衬底的部分第二掺杂层，第一掺杂层位于第一导体层靠近沟道一侧的表面。第四掺杂层为块状，第二导体层包裹靠近半导体衬底的部分第四掺杂层，第三掺杂层位于第二导体层靠近沟道一侧的表面。也就是说，本申请实施例提供的场效应晶体管可以为鳍式场效应晶体管。该鳍式场效应晶体管中，栅极位于半导体衬底设有沟道一侧的表面上，且栅极覆盖沟道，这样，栅极与沟道之间的重叠面积较大，增大沟道的宽长比，提升场效应晶体管的性能。另外，在半导体衬底10的两侧相对的侧面的外侧分别设有隔离介质层18。隔离介质层18具有保护半导体衬底10的作用，并且，起到绝缘的作用。
在本申请的一种实现方式中，第一冷源极及第二冷源极位于同一半导体衬底的表面上。场效应晶体管包括：位于半导体衬底一侧的至少两个沟道；场效应晶体管中的至少两个沟道在垂直于半导体衬底的表面的方向上依次排列，且相邻两个沟道之间具有间隙，半导体衬底与最近的沟道之间具有间隙。可选地，栅极位于半导体衬底设有沟道一侧的表面，且栅极包裹场效应晶体管中的每一个沟道。这样，栅极与沟道之间的重叠面积较大，增大沟道的宽长比，提升场效应晶体管的性能。
第一掺杂层与至少两个沟道中的每一个沟道的一端连接，第三掺杂层与至少两个沟道中的每一个沟道的另一端连接。第一导体层位于第一掺杂层远离沟道一侧的表面，第二掺杂层位于第一导体层远离第一掺杂层一侧的表面。第二导体层位于第三掺杂层远离沟道一侧的表面，第四掺杂层位于所第二导体层远离第三掺杂层一侧的表面。也就是说，本申请实施例提供的场效应晶体管可以为环栅场效应晶体管，该环栅场效应晶体管中的第二掺杂层与第四掺杂层位于外侧，便于将第一冷源极和第二冷源极引出。另外，在半导体衬底10的两侧相对的侧面的外侧分别设有隔离介质层18。隔离介质层18具有保护半导体衬底10的作用，并且，起到绝缘的作用。
当然，本申请实施例提供的场效应晶体管也可以为其他类型，此处不再一一举例。
第二方面，本申请实施例还提供了一种集成电路，该集成电路包括：上述任一场效应晶体管，以及与场效应晶体管电连接的信号线。由于本申请实施例提供的上述场效应晶体管的亚阈值摆幅较低，该场效应晶体管的亚阈值摆幅能够小于60mV/dec，因而，本申请实施例中的集成电路的工作电压较低，进而，该集成电路的功耗较低。
第三方面，本申请实施例还提供了一种场效应晶体管的制作方法，该制作方法可以包括：
采用掺杂工艺分别形成沟道、第一掺杂层和第三掺杂层；第一掺杂层与沟道接触，第三掺杂层与沟道接触；第一掺杂层与第三掺杂层属于同一掺杂类型；
形成第一导体层和第二导体层；
采用掺杂工艺形成第二掺杂层和第四掺杂层；第一导体层位于第一掺杂层与第二掺杂层之间，第二导体层位于第三掺杂层与第四掺杂层之间；第二掺杂层与第四掺杂层属于同一掺杂类型，第二掺杂层与第一掺杂层属于不同的掺杂类型。
在本申请实施例中，通过采用上述制作方法，可以在场效应晶体管中形成两个冷源极， 即第一冷源极和第二冷源极，其中，第一冷源极包括：第一掺杂层、第二掺杂层及第一导体层，第二冷源极包括：第三掺杂层、第四掺杂层及第二导体层。通过调整第一冷源极或第二冷源极的载流子态密度，可以有效过滤高能电子，从而降低场效应晶体管的亚阈值摆幅，使场效应晶体管的亚阈值摆幅能够小于60mV/dec，进而降低集成电路的工作电压，使集成电路的功耗较低。并且，通过在第一冷源极和第二冷源极中设置导体层，可以提升第一冷源极和第二冷源极中电子的隧穿几率，进而提高场效应晶体管的开态电流。
可选地，本申请实施例中，第一冷源极与第二冷源极相对于沟道可以对称设置，由于第一掺杂层与第三掺杂层属于同一掺杂类型，因而，可以采用同一次掺杂工艺，形成第一掺杂层和第三掺杂层，从而节省工艺步骤，节约制作成本。同理，第一导体层和第二导体层也可以采用同一工艺制作，第二掺杂层和第四掺杂层也可以采用同一次掺杂工艺制作。
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图1为本申请实施例中终端的内部结构示意图；
图2为本申请实施例提供的场效应晶体管的简化结构示意图；
图3a为本申请实施例中一种类型的场效应晶体管的简化结构示意图；
图3b为本申请实施例中另一种类型的场效应晶体管的简化结构示意图；
图4a为相关技术中的场效应晶体管的能级结构示意图；
图4b为本申请实施例中的场效应晶体管的能级结构示意；
图5a为单端冷源晶体管的漏极电流与栅极电压的曲线关系示意图；
图5b为双端冷源晶体管的漏极电流与栅极电压的曲线关系示意图；
图6为本申请实施例提供的场效应晶体管的截面示意图；
图7为本申请实施例提供的场效应晶体管的另一截面示意图；
图8为本申请实施例提供的场效应晶体管的另一截面示意图；
图9为本申请实施例提供的场效应晶体管的另一截面示意图；
图10为本申请实施例提供的场效应晶体管的另一截面示意图；
图11为本申请实施例提供的场效应晶体管的立体结构示意图；
图12为本申请实施例提供的场效应晶体管的另一立体结构示意图；
图13为图12中虚线AA′处的截面示意图；
图14为本申请实施例提供的场效应晶体管的另一立体结构示意图；
图15为本申请实施例提供的场效应晶体管的制作方法流程图。
附图标记：
10-半导体衬底；11-第一冷源极；111-第一掺杂层；112-第二掺杂层；113-第一导体层；12-第二冷源极；121-第三掺杂层；122-第四掺杂层；123-第二导体层；13-沟道；14-栅极；15-栅极介质层；161-第一绝缘层；162-第二绝缘层；171-接触电极；172-引出电极；173-第一阻挡层；174-第二阻挡层；18-隔离介质层；S1-第一表面；S2-第二表面。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。应注意的是，在本说明书中，相似的标号和字母在下面的附图中表示类似项， 因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
本申请实施例提供了一种场效应晶体管、其制作方法及集成电路，该场效应晶体管可以为平面型场效应晶体管、双栅型(double gate)场效应晶体管、三闸极式(triple gate)场效应晶体管、鳍式场效应晶体管(fin field-effect transistor，FinFET)、环栅场效应晶体管(gate-all-around field effect transistor，GAAFET)、垂直结构金属氧化物半导体场效应晶体管(Vertical MOSFET)、浮栅型金属氧化物半导体场效应晶体管(Floating Gate MOSFET)、电荷俘获型金属氧化物半导体场效应晶体管(Charge Trapping MOSFET)、薄膜晶体管(Thin Film Transistor)、铁电场效应晶体管(FeFET)等各种类型的场效应晶体管，此处不对场效应晶体管的类型进行限定。该场效应晶体管可以应用于集成电路中，该集成电路可以为逻辑、存储(例如Flash、DRAM等)、模拟、传感等各种功能的集成电路。当然，本申请实施例中的场效应晶体管也可以应用于其他类型的集成电路中，此处不再一一举例。
本申请实施例提供的场效应晶体管也可以应用于终端中，由于本申请中的场效应晶体管的亚阈值摆幅较低，该场效应晶体管的亚阈值摆幅能够小于60mV/dec，因而，将该场效应晶体管应用于终端中，可以降低终端的功耗。可选地，图1为本申请实施例中终端的内部结构示意图，如图1所示，该终端可以包括印刷电路板101(printed circuit board，PCB)及芯片102,，上述场效应晶体管可以设置在上述芯片102中。
图2为本申请实施例提供的场效应晶体管的简化结构示意图，如图2所示，该场效应晶体管可以包括：第一冷源极11、第二冷源极12、位于第一冷源极11与第二冷源极12之间的沟道13、栅极14，以及位于沟道13与栅极14之间的栅极介质层15。可选地，第一冷源极11作为场效应晶体管的源极，第二冷源极12作为场效应晶体管的漏极；或者，第一冷源极11作为场效应晶体管的漏极，第二冷源极12作为场效应晶体管的源极。也就是说，本申请实施例中场效应晶体管的源极与漏极可以互换。在实际应用中，可以通过向栅极14施加栅极电压，来控制源极与漏极之间的导通状态。当栅极电压高于阈值电压时，源极与漏极之间导通。当栅极电压低于阈值电压时，场效应晶体管处于亚阈值状态，源极与漏极之间具有微量漏电流。
第一冷源极11可以包括：第一掺杂层111、第二掺杂层112，以及位于第一掺杂层111与第二掺杂层112之间的第一导体层113，第一掺杂层111与沟道13接触。第二冷源极12可以包括：第三掺杂层121、第四掺杂层122，以及位于第三掺杂层121与第四掺杂层122之间的第二导体层123，第三掺杂层121与沟道13接触。第一掺杂层111与第三掺杂层121属于同一掺杂类型，第二掺杂层112与第四掺杂层122属于同一掺杂类型；第一掺杂层111与第二掺杂层112属于不同的掺杂类型。
在本申请实施例中，通过设置第一冷源极11和第二冷源极12，以第一冷源极11为例，第二冷源极12与第一冷源极11的结构类似，此处不再赘述。第一冷源极11可以包括第一掺杂层111、第一导体层113及第二掺杂层112，且第一掺杂层111与第二掺杂层112属于不同的掺杂类型，例如，第一掺杂层111可以为N型掺杂层，第二掺杂层112可以为P型掺杂层。通过在第一冷源极11中设置掺杂类型不同的掺杂层，可以在第一冷源极内形成能量间隙，通过调控态密度，滤除的高能载流子的能带，使注入载流子的能带较低。而传统的场效应晶体管通过调节沟道势垒的热电子发射实现开关，注入载流子的能量较高。因此，相比于传统的场效应晶体管，本申请实施例中，场效应晶体管的表现像工作在低温环境下， 因此，第一掺杂层111、第一导体层113及第二掺杂层112组成的结构称为冷源极，该场效应晶体管可以称为冷源场效应晶体管。
图3a和图3b为本申请实施例中不同类型的场效应晶体管的简化结构示意图，如图3a所示，在本申请的一种实施方式中，该场效应晶体管可以为N型冷源晶体管(N-type cold source field effect transistor，nCSFET)，第一掺杂层111可以为N型掺杂层，第二掺杂层112可以为P型掺杂层，第三掺杂层121可以为N型掺杂层，第四掺杂层122可以为P型掺杂层。如图3b所示，在本申请的另一实施方式中，该场效应晶体管可以为P型冷源晶体管(P-type cold source field effect transistor，pCSFET)，第一掺杂层111可以为P型掺杂层，第二掺杂层112可以为N型掺杂层，第三掺杂层121可以为P型掺杂层，第四掺杂层122可以为N型掺杂层。
在制作本申请中的场效应晶体管的过程中，可以在半导体层中掺入P型离子，得到P型掺杂层，在半导体层中掺入N型离子，得到N型掺杂层。具体地，该半导体层可以包括：硅、锗、硅锗、碳化硅、III-V化合物半导体、氧化物半导体或碳纳米管等材料，当然，该半导体层也可以包括其他半导体材料，此处不做限定。
本申请实施例中，该场效应晶体管中设有第一冷源极和第二冷源极，通过调整第一冷源极或第二冷源极的载流子态密度，可以有效过滤高能电子，从而降低场效应晶体管的亚阈值摆幅，使场效应晶体管的亚阈值摆幅能够小于60mV/dec，进而降低集成电路的工作电压，使集成电路的功耗较低。并且，通过在第一冷源极和第二冷源极中设置导体层，可以提升第一冷源极和第二冷源极中电子的隧穿几率，进而提高场效应晶体管的开态电流。
以下结合附图，对本申请实施例中的场效应晶体管能够降低亚阈值摆幅的原理进行详细说明。并且，以本申请实施例中的场效应晶体管为图3a所示的类型为例，即第一冷源极11中的第一掺杂层111可以为N型掺杂层，第二掺杂层112可以为P型掺杂层，第二冷源极12中的第三掺杂层121可以为N型掺杂层，第四掺杂层122可以为P型掺杂层。图3b所示类型的场效应晶体管能够降低亚阈值摆幅的原理类似，不再一一赘述。
图4a为相关技术中的场效应晶体管的能级结构示意图，图4b为本申请实施例中的场效应晶体管的能级结构示意。如图4a和图4b所示，P型掺杂层和N型掺杂层的能带包括导带Ec、禁带和价带Ev，其中，导带Ec在禁带的上方，价带Ev在禁带的下方。如图4a所示，相关技术中的场效应晶体管中，注入载流子的能带(即图4a中箭头W1所示的区域)在导带Ec的上方，即注入载流子的能量较高。
如图4b所示，在第一冷源极或第二冷源极中，P型掺杂层的能带相对于N型掺杂层的能带上移，而N型掺杂层的能带相对于P型掺杂层的能带下移，直至费米能级处，P型掺杂层的能带与N型掺杂层的能带相等时，能带才停止相对移动，P型掺杂层与N型掺杂层之间形成的PN结达到平衡状态。达到平衡状态的PN结中，P型掺杂层的价带Ev和N型掺杂层的导带Ec存在重叠区域，在该重叠区域中，电子可以从P型掺杂层遂穿到N型掺杂层，而禁带所在的区域，电子无法遂穿。因而，在图4b中，箭头W2所示的区域为滤除的高能载流子的能带，箭头W3所示的区域为注入载流子的能带。由于可以产生电子遂穿的重叠区域仅占比较小的一部分区域，而电子无法遂穿的禁带占了大部分区域，PN结可以有效抑制受热能激发的高能载流子，降低由热激发造成的漏电，从而降低亚阈值摆幅，例如亚阈值摆幅可以低于60mV/dec。此时，场效应晶体管的表现像工作在低温环境下，因此，可以称为冷源场效应晶体管。
然而，由于PN结中电子遂穿的几率小，场效应晶体管的开态电流无法满足要求。通过在第一冷源极和第二冷源极中设置导体层，即在PN结中设置导体层，导体层和掺杂层之间可以形成肖特基势垒，电子从P型掺杂层一侧遂穿到导体层，再进一步遂穿到N型掺杂层一侧，这样可以大大提高遂穿几率，提升场效应晶体管的开态电流。
相关技术中的场效应晶体管中，源极与接触电极电连接，载流子从接触电极处注入到源极中，由于在势垒上的热载流子满足费米分布，亚阈值摆幅在室温下不能小60mV/dec。本申请实施例提供的场效应晶体管中，第一冷源极或第二冷源极通过引入能量间隙，来抑制热尾。第一冷源极或第二冷源极通过态密度调控，形成“冷”载流子注入到源极。“冷”载流子的分布在关断状态下不延伸到热化费米带尾中，因为热带尾已经被上面的能带间隙切断，所以关态电流被大大减小。而对于该场效应晶体管的开态电流，热载流子在导通状态下可以直接从源极输运到漏极。因此，本申请实施例中的场效应晶体管的亚阈值摆幅可以不限于60mV/dec。
在具体实施时，本申请实施例提供的上述场效应晶体管中，上述第一导体层可以包括：金属材料、半金属材料、或金属硅化物材料。上述第二导体层可以包括：金属材料、半金属材料或金属硅化物材料。其中，上述金属材料可以为铝(Al)、金(Au)、银(Ag)、铂(Pt)、钯(Pd)、钴(Co)、钨(W)或钌(Ru)中的至少一种。上述半金属(Semimetal)材料是指导带和价带之间相隔很窄的材料。根据能带理论，根据导带和价带之间的间隔从窄到宽，固体可以依次分为金属、半金属、半导体和绝缘体。也就是说，半金属材料的导带与价带之间的间隔，小于半导体材料的导带与价带之间的间隔，且大于金属材料的导带与价带之间的间隔。对于半导体和绝缘体，导带和价带之间的间隔相对较大，使得费米能级附近电子的态密度等于零，成为带隙，其中绝缘体的带隙比半导体的大。金属的费米能级则在导带当中，附近有足够大的电子态密度，使得电流可以良好地传导。而对于半金属材料，由于半金属材料的导带和价带之间的间隔十分小，使得费米能级附近电子的态密度接近于零但不为零，因此半金属材料没有带隙。半金属材料在元素周期表中处于金属向非金属过渡的位置，物理性质和化学性质介于金属和非金属之间。例如，上述半金属材料可以为砷、锑、铋、锡或石墨中的至少一种。上述金属硅化物可以材料为NiSi 2、TiSi 2或CoSi。当然，上述第一导体层和第二导体层也可以包括其他导体材料，例如，第一导体层(或第二导体层)可以包括石墨烯、二维金属或类金属等材料。
本申请实施例中，通过在场效应晶体管中设置第一冷源极和第二冷源极，可以将第一冷源极作为源极，第二冷源极作为漏极，或者，可以将第一冷源作为漏极，第二冷源极作为源极，即本申请实施例中的场效应晶体管的源极和漏极互换后，仍具有冷源晶体管的特点，提升了场效应晶体管在集成电路中使用的灵活性。并且，第一冷源极与第二冷源极的结构类似，可以采用相同或相似的工艺制作，简化了制作工艺的复杂度，降低了制作工艺的成本。
图5a为单端冷源晶体管的漏极电流与栅极电压的曲线关系示意图，图5b为双端冷源晶体管的漏极电流与栅极电压的曲线关系示意图。漏极电流与栅极电压的关系曲线中，曲线越陡表示亚阈值摆幅越小。如图5a所示，单端冷源晶体管指的是，只将源极和漏极中的其中之一设置为冷源极，图5a中，曲线L1为将源极设置为冷源极时漏极电流与栅极电压的关系曲线，曲线L2为将漏极设置为冷源极时漏极电流与栅极电压的关系曲线。图5b中，双端冷源晶体管指的是，该场效应晶体管包括第一冷源极和第二冷源极两个冷源极。将第 一冷源极作为源极，第二冷源极作为漏极，或者，将第一冷源极作为漏极，第二冷源极作为源极，这两种情况的漏极电流与栅极电压的关系曲线可以均为图5b中的曲线L3。
从图5a可看出，仅将漏极设置为冷源极时，该场效应晶体管不具有冷源的效果，此时亚阈值摆幅大于60mV/dec。只有将源极设置为冷源极时，该场效应晶体管才具有冷源的效果，此时亚阈值摆幅小于60mV/dec。单端冷源晶体管的源极与漏极互换后，会失去态密度调控的能力，从图5b可看出，双端冷源晶体管的源极与漏极互换后，双端冷源晶体管的态密度调控的能力不受影响，双端冷源晶体管的亚阈值摆幅小于60mV/dec。因此，相较于单端冷源晶体管，双端冷源晶体管可以实现源极与漏极互换使用的优良特性。此外，双端冷源晶体管可以降低工艺复杂度，有利于集成电路的工艺集成。
可选地，本申请实施例提供的上述场效应晶体管中，第一冷源极与第二冷源极相对于沟道可以对称设置。在制作过程中，可以采用相同的工艺制作第一冷源极和第二冷源极中的各部分，降低制作工艺的复杂度，节省制作工艺的成本。并且，将该场效应晶体管应用于集成电路中的灵活性较高。当然，第一冷源极与第二冷源极也可以设置为非对称，此处不做限定。第一冷源极与第二冷源极为非对称设置时，由于第一冷源极与第二冷源极的结构相似，该场效应晶体管的制作工艺的复杂度也较低，制作工艺的成本也比较低。
举例来说，第一冷源极与第二冷源极可以采用竖向层叠的对称结构，如图6所示，图6为本申请实施例提供的场效应晶体管的截面示意图，第一掺杂层111、沟道13及第三掺杂层121位于同一半导体衬底10的内部，可选地，半导体衬底10可以为硅基半导体材料，该半导体衬底10可以具有：相对的第一表面S1和第二表面S2，例如，第一表面S1可以为半导体衬底10的上表面，第二表面S2可以为半导体衬底10的下表面。第一导体层113位于半导体衬底10的表面上，第一导体层113与第一掺杂层111接触，第二掺杂层112位于第一导体层113远离第一掺杂层111的一侧。第二导体层123位于半导体衬底10的表面上，例如，第一导体层113与第二导体层123可以位于半导体衬底10的第一表面S1上，第二导体层123与第三掺杂层121接触，第四掺杂层122位于第二导体层123远离第三掺杂层121的一侧。也就是说，第一冷源极11与第二冷源极12相对于沟道13可以对称设置，且第一冷源极11和第二冷源极12均采用竖向叠层结构。
在制作过程中，可以采用掺杂工艺在半导体衬底10的表面形成第一掺杂层111、第三掺杂层121以及沟道13。由于第一掺杂层111与第三掺杂层121属于同一掺杂类型，可以采用同一次掺杂工艺制作第一掺杂层111和第三掺杂层121，从而节省工艺步骤，节约制作成本。并且，第一导体层113和第二导体层123也可以采用同一工艺制作，第二掺杂层112和第四掺杂层122也可以采用同一工艺制作。
为了将第一冷源极和第二冷源极引出，上述场效应晶体管还可以包括：接触电极171和引出电极172，接触电极171与第二掺杂层112(或第四掺杂层122)电连接，引出电极172与接触电极171电连接。接触电极171和引出电极172可以采用金属材料制作，例如，可以采用金属钨。为了阻挡接触电极171中的金属扩散，防止金属进入到周围介质中，可以在接触电极171的侧面设置阻挡层，例如可以在接触电极171的侧面设置第一阻挡层173，在第一阻挡层173的侧面设置第二阻挡层174。阻挡层一般采用导电材料制作，因而阻挡层的导电性能较好，不会影响接触电极171与第二掺杂层112(或第四掺杂层122)之间的电性连接，举例来说，阻挡层可以采用钛或氮化钛等材料制作。
继续参照图6，本申请实施例提供的场效应晶体管中，栅极14位于半导体衬底10的 一侧，上述场效应晶体管还可以包括：覆盖栅极14的顶面和侧面的绝缘层，绝缘层可以绝缘栅极14与第一冷源极11，且绝缘层可以绝缘栅极14与第二冷源极12。例如，该绝缘层可以包括第一绝缘层161，以及覆盖第一绝缘层161的第二绝缘层162，第一绝缘层161可以采用二氧化硅材料制作，第二绝缘层162可以采用氧化硅材料制作，当然，第一绝缘层161和第二绝缘层162也可以采用其他材料，此处不做限定。本申请实施例中，通过设置覆盖栅极14的顶面和侧面的绝缘层，可以绝缘栅极14与第一冷源极11和第二冷源极12，防止栅极14与第一冷源极11或第二冷源极12发生短接。
此外，第一冷源极与第二冷源极也可以采用横向层叠的对称结构，如图7所示，图7为本申请实施例提供的场效应晶体管的另一截面示意图，第一冷源极11、沟道13及第二冷源极12位于同一半导体衬底10的内部，可选地，半导体衬底10可以为硅基半导体材料，该半导体衬底10可以具有：相对的第一表面S1和第二表面S2，例如，第一表面S1可以为半导体衬底10的上表面，第二表面S2可以为半导体衬底10的下表面。第一冷源极11、沟道13及第二冷源极12可以位于半导体衬底10中靠近第一表面S1的一侧。第一导体层113位于第一掺杂层111远离沟道13的一侧，第二掺杂层112位于第一导体层113远离第一掺杂层111的一侧。第二导体层123位于第三掺杂层121远离沟道13的一侧，第四掺杂层122位于第二导体层123远离第三掺杂层121的一侧。也就是说，第一冷源极11与第二冷源极12相对于沟道13对称设置，且第一冷源极11和第二冷源极12均采用横向叠层结构。
在制作过程中，可以采用同一掺杂工艺在半导体衬底10的表面形成第一掺杂层111和第三掺杂层121，并采用同一掺杂工艺在半导体衬底10的表面形成第二掺杂层112和第四掺杂层122，因而，该场效应晶体管的制作工艺简单，工艺步骤较少，制作成本较低。
继续参照图7，上述半导体衬底10的表面设有凹槽U，栅极介质层15位于凹槽U内，栅极14的一部分嵌入到凹槽U内。这样，可以使栅极14与半导体衬底10中的沟道13的距离较近，便于通过栅极14控制第一冷源极11与第二冷源极12之间的通断。
在具体实施时，本申请实施例中的场效应晶体管也可以为非对称结构，如图8所示，图8为本申请实施例提供的场效应晶体管的另一截面示意图，第一冷源极11、沟道13及第三掺杂层121位于同一半导体衬底10的内部。可选地，半导体衬底10可以为硅基半导体材料，该半导体衬底10可以具有：相对的第一表面S1和第二表面S2，例如，第一表面S1可以为半导体衬底10的上表面，第二表面S2可以为半导体衬底10的下表面。第一导体层113位于第一掺杂层111远离沟道13的一侧，第二掺杂层112位于第一导体层113远离第一掺杂层111的一侧。第二导体层121位于半导体衬底10的表面上，例如，第一冷源极11、沟道13及第三掺杂层121可以位于半导体衬底10靠近第一表面S1的一侧，第二导体层123可以位于半导体衬底10的第一表面S1上，第二导体层123与第三掺杂层121接触，第四掺杂层122位于第二导体层123远离第三掺杂层121的一侧。也就是说，第一冷源极11与第二冷源极12也可以为非对称设置。其中，第一冷源极11可以采用横向叠层结构，第二冷源极12可以采用竖向叠层结构。
在制作过程中，可以采用同一掺杂工艺在半导体衬底10的表面形成第一掺杂层111和第三掺杂层122，从而可以减少工艺步骤，制作成本较低。虽然，图8所示的结构中，第一冷源极11与第二冷源极12为非对称设置，但第一冷源极11与第二冷源极12的结构类似，制作工艺也比较容易，制作成本较低。
可选地，本申请实施例提供的场效应晶体管也可以为电荷俘获型场效应晶体管，如图9所示，图9为本申请实施例提供的场效应晶体管的另一截面示意图，上述栅极介质层可以包括：位于栅极14靠近沟道13一侧的隧穿层151，位于隧穿层151与栅极14之间的电荷俘获层152，以及位于电荷俘获层152与栅极14之间的电荷阻挡层153。
在本申请实施例中，上述场效应晶体管也可以为铁电场效应晶体管，如图10所示，图10为本申请实施例提供的场效应晶体管的另一截面示意图，上述栅极介质层可以包括：位于栅极14靠近沟道13一侧的界面氧化层154，以及位于界面氧化层154与栅极14之间的铁电层155。
除上述图6至图10所示的结构外，本申请实施例中的场效应晶体管也可以为其他类型的场效应晶体管，以下结合附图，对几种类型的场效应晶体管的结构进行说明。
图11为本申请实施例提供的场效应晶体管的立体结构示意图，如图11所示，第一冷源极11、沟道及第二冷源极12构成柱状结构，其中，沟道位于第一冷源极11与第二冷源极12之间的位置。栅极介质层15包裹于沟道的外侧，栅极14包裹于栅极介质层14的外侧。也就是说，本申请实施例中的场效应晶体管也可以为垂直结构场效应晶体管。该垂直结构场效应晶体管的结构较紧凑，且第一冷源极11中的第二掺杂层112与第二冷源极12中的第四掺杂层122分别位于两端，便于将第一冷源极11和第二冷源极12引出。此外，栅极14包裹于沟道的外侧，栅极14与沟道之间的重叠面积较大，增大沟道的宽长比，提升场效应晶体管的性能。
图12为本申请实施例提供的场效应晶体管的另一立体结构示意图，图13为图12中虚线AA′处的截面示意图，如图12和图13所示，第一冷源极11、沟道13及第二冷源极12位于同一半导体衬底10的表面上，可选地，半导体衬底10可以为硅基半导体材料。该半导体衬底10可以包括：相对设置的第一表面S1和第二表面S2，例如，第一表面S1可以为半导体衬底10的上表面，第二表面S2可以为半导体衬底10的下表面。第一冷源极11、沟道13及第二冷源极12可以位于半导体衬底10的第一表面S1上。另外，在半导体衬底10的两侧相对的侧面的外侧分别设有隔离介质层18。隔离介质层18具有保护半导体衬底10的作用，并且，起到绝缘的作用。
第二掺杂层112为块状，第一导体层113包裹靠近半导体衬底10的部分第二掺杂层112，第一掺杂层111位于第一导体层113靠近沟道13一侧的表面。第四掺杂层122为块状，第二导体层123包裹靠近半导体衬底10的部分第四掺杂层122，第三掺杂层121位于第二导体层123靠近沟道13一侧的表面。也就是说，本申请实施例提供的场效应晶体管可以为鳍式场效应晶体管。该鳍式场效应晶体管中，栅极14位于半导体衬底10设有沟道13一侧的表面上，例如，栅极14可以位于半导体衬底10的第一表面S1上，且栅极14覆盖沟道13，这样，栅极14与沟道13之间的重叠面积较大，增大沟道的宽长比，提升场效应晶体管的性能。图12中为了清楚的示意场效应晶体管的内部结构，以虚线表示栅极14的位置。
此外，由于第二掺杂层112为块状，且第一导体层113包裹靠近半导体衬底10的部分第二掺杂层112，这样，第二掺杂层112的顶部未被第一导体层113包裹，因而，便于将第二掺杂层112与接触电极电连接，即便于将第一冷源极11引出。同理，第四掺杂层122的顶部未被第二导体层123包裹，因而，便于将第四掺杂层122与接触电极电连接，即便于将第二冷源极12引出。
图14为本申请实施例提供的场效应晶体管的另一立体结构示意图，如图14所示，第一冷源极11及第二冷源极12位于同一半导体衬底10的表面上，例如，第一冷源极11及第二冷源极12可以位于半导体衬底10的第一表面S1上。可选地，半导体衬底10可以为硅基半导体材料。该半导体衬底10可以包括：相对设置的第一表面S1和第二表面S2，例如，第一表面S1可以为半导体衬底10的上表面，第二表面S2可以为半导体衬底10的下表面。另外，在半导体衬底10的两侧相对的侧面的外侧分别设有隔离介质层18。隔离介质层18具有保护半导体衬底10的作用，并且，起到绝缘的作用。
场效应晶体管可以包括：位于半导体衬底10一侧的至少两个沟道13，例如，这些沟道13可以位于半导体衬底10的第一表面S1的一侧。场效应晶体管中的至少两个沟道13在垂直于半导体衬底10的表面的方向上依次排列，且相邻两个沟道13之间具有间隙，半导体衬底10与最近的沟道13之间具有间隙，图13中以场效应晶体管包括三个沟道13为例进行示意，不对场效应晶体管中沟道13的数量进行限定。栅极14位于半导体衬底10设有沟道13一侧的表面，例如，栅极14可以位于半导体衬底10的第一表面S1一侧，且栅极14包裹场效应晶体管中的每一个沟道13。这样，栅极14与沟道13之间的重叠面积较大，增大沟道的宽长比，提升场效应晶体管的性能。图14中为了清楚的示意场效应晶体管的内部结构，以虚线表示栅极14的位置。
第一掺杂层111与每一个沟道13的一端连接，第三掺杂层121与每一个沟道13的另一端连接。第一导体层113位于第一掺杂层111远离沟道13一侧的表面，第二掺杂层112位于第一导体层113远离第一掺杂层111一侧的表面。第二导体层123位于第三掺杂层121远离沟道13一侧的表面，第四掺杂层122位于所第二导体层123远离第三掺杂层121一侧的表面。也就是说，本申请实施例提供的场效应晶体管可以为环栅场效应晶体管，该环栅场效应晶体管中的第二掺杂层112与第四掺杂层122位于外侧，便于将第一冷源极11和第二冷源极12引出。
当然，本申请实施例提供的场效应晶体管也可以为其他类型，此处不再一一举例。
基于同一技术构思，本申请实施例还提供了一种集成电路，该集成电路可以包括：上述任一场效应晶体管，以及与场效应晶体管电连接的信号线。由于本申请实施例提供的上述场效应晶体管的亚阈值摆幅较低，该场效应晶体管的亚阈值摆幅能够小于60mV/dec，因而，本申请实施例中的集成电路的工作电压较低，进而，该集成电路的功耗较低。
基于同一技术构思，本申请实施例还提供了一种场效应晶体管的制作方法，图15为本申请实施例提供的场效应晶体管的制作方法流程图，如图15所示，该制作方法可以包括：
S201、采用掺杂工艺分别形成沟道、第一掺杂层和第三掺杂层；第一掺杂层与沟道接触，第三掺杂层与沟道接触；第一掺杂层与第三掺杂层属于同一掺杂类型；
S202、形成第一导体层和第二导体层；
S203、采用掺杂工艺形成第二掺杂层和第四掺杂层；第一导体层位于第一掺杂层与第二掺杂层之间，第二导体层位于第三掺杂层与第四掺杂层之间；第二掺杂层与第四掺杂层属于同一掺杂类型，第二掺杂层与第一掺杂层属于不同的掺杂类型。
在本申请实施例中，通过采用上述制作方法，可以在场效应晶体管中形成两个冷源极，即第一冷源极和第二冷源极，其中，第一冷源极包括：第一掺杂层、第二掺杂层及第一导体层，第二冷源极包括：第三掺杂层、第四掺杂层及第二导体层。通过调整第一冷源极或 第二冷源极的载流子态密度，可以有效过滤高能电子，从而降低场效应晶体管的亚阈值摆幅，使场效应晶体管的亚阈值摆幅能够小于60mV/dec，进而降低集成电路的工作电压，使集成电路的功耗较低。并且，通过在第一冷源极和第二冷源极中设置导体层，可以提升第一冷源极和第二冷源极中电子的隧穿几率，进而提高场效应晶体管的开态电流。
应该说明的是，在图15中，S201、S202和S203只是对各步骤进行标识，并不限定各步骤的顺序，在具体实施时，可以根据场效应晶体管的具体结构，来调整各步骤的顺序。
可选地，本申请实施例中，第一冷源极与第二冷源极相对于沟道可以对称设置，参照图6和图7所示的结构，由于第一掺杂层111与第三掺杂层121属于同一掺杂类型，因而，可以采用同一次掺杂工艺，形成第一掺杂层111和第三掺杂层121，从而节省工艺步骤，节约制作成本。同理，第一导体层113和第二导体层123也可以采用同一工艺制作，第二掺杂层112和第四掺杂层122也可以采用同一次掺杂工艺制作。
尽管已描述了本申请的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本申请范围的所有变更和修改。
显然，本领域的技术人员可以对本申请实施例进行各种改动和变型而不脱离本申请实施例的范围。这样，倘若本申请实施例的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (23)

  1. 一种场效应晶体管，其特征在于，包括：第一冷源极、第二冷源极、位于所述第一冷源极与所述第二冷源极之间的沟道、栅极，以及位于所述沟道与所述栅极之间的栅极介质层；
    所述第一冷源极包括：第一掺杂层、第二掺杂层，以及位于所述第一掺杂层与所述第二掺杂层之间的第一导体层，所述第一掺杂层与所述沟道接触；
    所述第二冷源极包括：第三掺杂层、第四掺杂层，以及位于所述第三掺杂层与所述第四掺杂层之间的第二导体层，所述第三掺杂层与所述沟道接触；
    所述第一掺杂层与所述第三掺杂层属于同一掺杂类型，所述第二掺杂层与所述第四掺杂层属于同一掺杂类型；所述第一掺杂层与所述第二掺杂层属于不同的掺杂类型。
  2. 如权利要求1所述的场效应晶体管，其特征在于，所述第一冷源极与所述第二冷源极相对于所述沟道对称设置。
  3. 如权利要求2所述的场效应晶体管，其特征在于，所述第一掺杂层、所述沟道及所述第三掺杂层位于同一半导体衬底的内部；
    所述第一导体层位于所述半导体衬底的表面上，所述第一导体层与所述第一掺杂层接触，所述第二掺杂层位于所述第一导体层远离所述第一掺杂层的一侧；
    所述第二导体层位于所述半导体衬底的表面上，所述第二导体层与所述第三掺杂层接触，第四掺杂层位于所述第二导体层远离所述第三掺杂层的一侧。
  4. 如权利要求2所述的场效应晶体管，其特征在于，所述第一冷源极、所述沟道及所述第二冷源极位于同一半导体衬底的内部；
    所述第一导体层位于所述第一掺杂层远离所述沟道的一侧，所述第二掺杂层位于所述第一导体层远离所述第一掺杂层的一侧；
    所述第二导体层位于所述第三掺杂层远离所述沟道的一侧，所述第四掺杂层位于所述第二导体层远离所述第三掺杂层的一侧。
  5. 如权利要求1所述的场效应晶体管，其特征在于，所述第一冷源极、所述沟道及所述第三掺杂层位于同一半导体衬底的内部；
    所述第一导体层位于所述第一掺杂层远离所述沟道的一侧，所述第二掺杂层位于所述第一导体层远离所述第一掺杂层的一侧；
    所述第二导体层位于所述半导体衬底的表面上，所述第二导体层与所述第三掺杂层接触，第四掺杂层位于所述第二导体层远离所述第三掺杂层的一侧。
  6. 如权利要求1～5任一项所述的场效应晶体管，其特征在于，所述栅极介质层包括：位于所述栅极靠近所述沟道一侧的隧穿层，位于所述隧穿层与所述栅极之间的电荷俘获层，以及位于所述电荷俘获层与所述栅极之间的电荷阻挡层。
  7. 如权利要求1～5任一项所述的场效应晶体管，其特征在于，所述栅极介质层包括：位于所述栅极靠近所述沟道一侧的界面氧化层，以及位于所述界面氧化层与所述栅极之间的铁电层。
  8. 如权利要求3～7任一项所述的场效应晶体管，其特征在于，所述栅极位于所述半导体衬底的一侧；
    所述场效应晶体管还包括：覆盖所述栅极的顶面和侧面的绝缘层，所述绝缘层绝缘所 述栅极与所述第一冷源极，且所述绝缘层绝缘所述栅极与所述第二冷源极。
  9. 如权利要求3～8任一项所述的场效应晶体管，其特征在于，所述半导体衬底的表面设有凹槽；
    所述栅极介质层位于所述凹槽内，所述栅极的一部分嵌入到所述凹槽内。
  10. 如权利要求2所述的场效应晶体管，其特征在于，所述第一冷源极、所述沟道及所述第二冷源极构成柱状结构；
    所述栅极介质层包裹于所述沟道的外侧，所述栅极包裹于所述栅极介质层的外侧。
  11. 如权利要求2所述的场效应晶体管，其特征在于，所述第一冷源极、所述沟道及所述第二冷源极位于同一半导体衬底的表面上；
    所述第二掺杂层为块状，所述第一导体层包裹靠近所述半导体衬底的部分所述第二掺杂层；所述第一掺杂层位于所述第一导体层靠近所述沟道一侧的表面；
    所述第四掺杂层为块状，所述第二导体层包裹靠近所述半导体衬底的部分所述第四掺杂层；所述第三掺杂层位于所述第二导体层靠近所述沟道一侧的表面。
  12. 如权利要求11所述的场效应晶体管，其特征在于，所述栅极位于所述半导体衬底设有所述沟道一侧的表面上，且所述栅极覆盖所述沟道。
  13. 如权利要求2所述的场效应晶体管，其特征在于，所述第一冷源极及所述第二冷源极位于同一半导体衬底的表面上；
    所述场效应晶体管包括：位于所述半导体衬底一侧的至少两个沟道；所述至少两个沟道在垂直于所述半导体衬底的表面的方向上依次排列，且相邻两个所述沟道之间具有间隙，所述半导体衬底与最近的所述沟道之间具有间隙；
    所述第一掺杂层与所述至少两个沟道中的每一个所述沟道的一端连接，所述第三掺杂层与所述至少两个沟道中的每一个所述沟道的另一端连接；
    所述第一导体层位于所述第一掺杂层远离所述沟道一侧的表面，所述第二掺杂层位于所述第一导体层远离所述第一掺杂层一侧的表面；
    所述第二导体层位于所述第三掺杂层远离所述沟道一侧的表面，所述第四掺杂层位于所第二导体层远离所述第三掺杂层一侧的表面。
  14. 如权利要求13所述的场效应晶体管，其特征在于，所述栅极位于所述半导体衬底设有所述沟道一侧的表面，且所述栅极包裹所述至少两个沟道中的每一个所述沟道。
  15. 如权利要求1～14任一项所述的场效应晶体管，其特征在于，所述第一掺杂层为N型掺杂层，所述第二掺杂层为P型掺杂层。
  16. 如权利要求1～14任一项所述的场效应晶体管，其特征在于，所述第一掺杂层为P型掺杂层，所述第二掺杂层为N型掺杂层。
  17. 如权利要求1～16任一项所述的场效应晶体管，其特征在于，所述第一导体层包括：金属材料、半金属材料、或金属硅化物材料；
    所述第二导体层包括：金属材料、半金属材料或金属硅化物材料。
  18. 如权利要求17所述的场效应晶体管，其特征在于，所述金属材料包括：铝、金、银、铂、钯、钴、钨或钌中的至少一种。
  19. 如权利要求17所述的场效应晶体管，其特征在于，所述半金属材料包括：砷、锑、铋、锡或石墨中的至少一种。
  20. 如权利要求17所述的场效应晶体管，其特征在于，所述金属硅化物材料包括：NiSi 2、 TiSi 2或CoSi。
  21. 一种集成电路，其特征在于，包括：如权利要求1～20任一项所述的场效应晶体管，以及与所述场效应晶体管电连接的信号线。
  22. 一种场效应晶体管的制作方法，其特征在于，包括：
    采用掺杂工艺分别形成沟道、第一掺杂层和第三掺杂层；所述第一掺杂层与所述沟道接触，所述第三掺杂层与所述沟道接触；所述第一掺杂层与所述第三掺杂层属于同一掺杂类型；
    形成第一导体层和第二导体层；
    采用掺杂工艺形成第二掺杂层和第四掺杂层；所述第一导体层位于所述第一掺杂层与所述第二掺杂层之间，所述第二导体层位于所述第三掺杂层与所述第四掺杂层之间；所述第二掺杂层与所述第四掺杂层属于同一掺杂类型，所述第二掺杂层与所述第一掺杂层属于不同的掺杂类型。
  23. 如权利要求22所述的制作方法，其特征在于，所述采用掺杂工艺分别形成沟道、第一掺杂层和第三掺杂层，包括：
    采用同一次掺杂工艺，形成所述第一掺杂层和所述第三掺杂层；
    所述采用掺杂工艺形成第二掺杂层和第四掺杂层，包括：
    采用同一次掺杂工艺，形成所述第二掺杂层和所述第四掺杂层。
PCT/CN2021/107580 2021-07-21 2021-07-21 一种场效应晶体管、其制作方法及集成电路 WO2023000200A1 (zh)

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