WO2023000200A1 - Transistor à effet de champ, son procédé de fabrication et circuit intégré - Google Patents

Transistor à effet de champ, son procédé de fabrication et circuit intégré Download PDF

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Publication number
WO2023000200A1
WO2023000200A1 PCT/CN2021/107580 CN2021107580W WO2023000200A1 WO 2023000200 A1 WO2023000200 A1 WO 2023000200A1 CN 2021107580 W CN2021107580 W CN 2021107580W WO 2023000200 A1 WO2023000200 A1 WO 2023000200A1
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Prior art keywords
doped layer
layer
field effect
effect transistor
cold source
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PCT/CN2021/107580
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English (en)
Chinese (zh)
Inventor
董耀旗
侯朝昭
王嘉乐
吴颖
许俊豪
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华为技术有限公司
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Priority to CN202180096515.4A priority Critical patent/CN117203742A/zh
Priority to PCT/CN2021/107580 priority patent/WO2023000200A1/fr
Publication of WO2023000200A1 publication Critical patent/WO2023000200A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a field effect transistor, a manufacturing method thereof and an integrated circuit.
  • Integrated circuits generally include a field effect transistor (metal oxide semiconductor field effect transistor, MOSFET).
  • MOSFET metal oxide semiconductor field effect transistor
  • the required gate voltage increment is called the sub-threshold swing (SS), and the sub-threshold swing is related to factors such as device structure and temperature.
  • the sub-threshold swing The smaller is, the greater the working speed of the field effect transistor in the subthreshold state.
  • the subthreshold current is an exponential function related to the Boltzmann constant. Since the electrons satisfy the Boltzmann distribution characteristics, the subthreshold swing is at room temperature It cannot be less than 60mV/dec.
  • the operating voltage Vdd must be many times the subthreshold swing, where I on represents the on-state current of the field effect transistor, and I off represents the field effect transistor off-state current. If the sub-threshold swing remains unchanged, reducing the operating voltage Vdd will cause the on -state current Ion to decrease and the performance of the device to degrade. Therefore, due to the limitation of the sub-threshold swing of the field effect transistor, it is difficult to reduce the operating voltage of the integrated circuit, and furthermore, it is difficult to further reduce the power consumption of the integrated circuit.
  • the application provides a field effect transistor, its manufacturing method and an integrated circuit, which are used to reduce the sub-threshold swing of the field effect transistor, thereby reducing the operating voltage of the integrated circuit, so that the power consumption of the integrated circuit is lower.
  • the embodiment of the present application provides a field effect transistor, and the field effect transistor may include: a first cold source, a second cold source, and a A channel, a gate, and a gate dielectric layer between the channel and the gate.
  • the first cold source includes: a first doped layer, a second doped layer, and a first conductor layer located between the first doped layer and the second doped layer, and the first doped layer is in contact with the channel.
  • the second cold source includes: a third doped layer, a fourth doped layer, and a second conductor layer located between the third doped layer and the fourth doped layer, and the third doped layer is in contact with the channel.
  • the field effect transistor may be an N-type cold source transistor, the first doped layer is an N-type doped layer, and the second doped layer is a P-type doped layer.
  • the field effect transistor may be a P-type cold source transistor, the first doped layer is a P-type doped layer, and the second doped layer is an N-type doped layer.
  • the structure of the second cold source is similar to that of the first cold source, which will not be repeated here.
  • the first cold source may include a first doped layer, a first conductor layer and a second doped layer, and the first doped layer and the second doped layer belong to different doping types, for example, the first doped layer It may be an N-type doped layer, and the second doped layer may be a P-type doped layer.
  • the field effect transistor By setting doped layers with different doping types in the first cold source, an energy gap can be formed in the first cold source, and by adjusting the density of states, the energy band of the high-energy carriers filtered out makes the injected carrier The energy band of the sub is lower.
  • the traditional field effect transistor realizes switching by adjusting the thermionic emission of the channel barrier, and the energy of injected carriers is relatively high. Therefore, compared with the traditional field effect transistor, in the embodiment of the present application, the field effect transistor behaves like working in a low temperature environment. Therefore, the structure composed of the first doped layer, the first conductor layer and the second doped layer Known as a cold source, the field effect transistor may be called a cold source field effect transistor.
  • a Schottky barrier can be formed between the conductor layer and the doped layer, electrons tunnel from the side of the P-type doped layer to the conductor layer, and then Further tunneling to the side of the N-type doped layer can greatly increase the tunneling probability and increase the on-state current of the field effect transistor.
  • the above-mentioned field effect transistor is provided with a first cold source and a second cold source, and by adjusting the carrier state density of the first cold source or the second cold source, high-energy electrons can be effectively filtered, thereby reducing the
  • the sub-threshold swing of the field effect transistor can be lower than 60mV/dec, thereby reducing the operating voltage of the integrated circuit and lowering the power consumption of the integrated circuit.
  • the conductor layer in the first cold source and the second cold source the tunneling probability of electrons in the first cold source and the second cold source can be increased, thereby increasing the on-state current of the field effect transistor.
  • the above-mentioned first conductor layer may include: a metal material, a semi-metal material, or a metal silicide material.
  • the above-mentioned second conductor layer may include: metal material, semi-metal material or metal silicide material.
  • the metal material may be at least one of aluminum, gold, silver, platinum, palladium, cobalt, tungsten or ruthenium.
  • the aforementioned semimetal (Semimetal) material is a material with a very narrow gap between the guide band and the valence band.
  • the interval between the conduction band and the valence band from narrow to wide solids can be divided into metals, semi-metals, semiconductors and insulators in turn. That is to say, the interval between the conduction band and the valence band of the semi-metal material is smaller than the interval between the conduction band and the valence band of the semiconductor material, and larger than the interval between the conduction band and the valence band of the metal material.
  • the interval between the conduction band and the valence band is relatively large, so that the density of states of electrons near the Fermi level is equal to zero, which becomes the band gap, where the band gap of the insulator is larger than that of the semiconductor.
  • the Fermi level of the metal is in the conduction band, and there is a large enough electronic density of states nearby, so that the current can be well conducted.
  • semi-metallic materials since the gap between the conduction band and valence band of semi-metallic materials is very small, the density of states of electrons near the Fermi level is close to zero but not zero, so semi-metallic materials have no band gap.
  • Semi-metallic materials are in the transition position of metal to non-metal in the periodic table of elements, and their physical and chemical properties are between metal and non-metal.
  • the semi-metallic material may be at least one of arsenic, antimony, bismuth, tin or graphite.
  • the aforementioned metal silicide material may be NiSi 2 , TiSi 2 or CoSi.
  • the first conductor layer and the second conductor layer may also include other conductor materials, for example, the first conductor layer (or the second conductor layer) may include materials such as graphene, two-dimensional metal or metalloid.
  • the first cold source can be used as the source
  • the second cold source can be used as the drain
  • the first cold source can be used as the drain.
  • the cold source is used as the drain
  • the second cold source is used as the source, that is, after the source and drain of the field effect transistor in the embodiment of the application are interchanged, it still has the characteristics of a cold source transistor, which improves the integration of the field effect transistor. flexibility of use in the circuit.
  • the structure of the first cold source is similar to that of the second cold source, and can be manufactured by the same or similar process, which simplifies the complexity of the manufacturing process and reduces the cost of the manufacturing process.
  • the first cold source and the second cold source may be arranged symmetrically with respect to the channel.
  • each part of the first cold source electrode and the second cold source electrode can be manufactured using the same process, which reduces the complexity of the manufacturing process and saves the cost of the manufacturing process.
  • the flexibility of applying the field effect transistor to an integrated circuit is relatively high.
  • the first cold source and the second cold source may also be arranged asymmetrically, which is not limited here.
  • first cold source and the second cold source are arranged asymmetrically, since the structures of the first cold source and the second cold source are similar, the complexity of the manufacturing process of the field effect transistor is also low, and the cost of the manufacturing process is relatively low. Also relatively low.
  • the first cold source and the second cold source may adopt a vertically stacked symmetrical structure.
  • the first doped layer, the channel and the third doped layer are located inside the same semiconductor substrate.
  • the semiconductor substrate may be a silicon-based semiconductor material.
  • the first conductor layer is located on the surface of the semiconductor substrate, the first conductor layer is in contact with the first doped layer, and the second doped layer is located on a side of the first conductor layer away from the first doped layer.
  • the second conductor layer is located on the surface of the semiconductor substrate, the second conductor layer is in contact with the third doped layer, and the fourth doped layer is located on a side of the second conductor layer away from the third doped layer. That is to say, the first cold source and the second cold source are arranged symmetrically with respect to the channel, and both the first cold source and the second cold source adopt a vertical stacked structure.
  • the gate is located on one side of the semiconductor substrate, and the above-mentioned field effect transistor may further include: an insulating layer covering the top surface and side surfaces of the gate.
  • the insulating layer may include a first insulating layer and a second insulating layer covering the first insulating layer.
  • the first insulating layer may be made of silicon dioxide material
  • the second insulating layer may be made of silicon oxide material.
  • the second insulating layer may be made of silicon dioxide material.
  • Other materials may also be used for the first insulating layer and the second insulating layer, which are not limited here.
  • the gate by providing an insulating layer covering the top and side surfaces of the gate, it is possible to insulate the gate from the first cold source and the second cold source, preventing the gate from contacting the first cold source or the second cold source.
  • the source is shorted.
  • the first cold source electrode and the second cold source electrode may also adopt a laterally stacked symmetrical structure.
  • the first cold source, the channel and the second cold source are located inside the same semiconductor substrate, and optionally, the semiconductor substrate may be a silicon-based semiconductor material.
  • the first conductor layer is located on a side of the first doped layer away from the channel, and the second doped layer is located on a side of the first conductor layer away from the first doped layer.
  • the second conductor layer is located on a side of the third doped layer away from the channel, and the fourth doped layer is located on a side of the second conductor layer away from the third doped layer. That is to say, the first cold source and the second cold source are arranged symmetrically with respect to the channel, and both the first cold source and the second cold source adopt a lateral stacked structure.
  • a groove may be provided on the surface of the semiconductor substrate, the gate dielectric layer is located in the groove, and a part of the gate is embedded in the groove. In this way, the distance between the gate and the channel in the semiconductor substrate can be made relatively close, and it is convenient to control the on-off between the first cold source and the second cold source through the gate.
  • the field effect transistor in the embodiment of the present application may also have an asymmetric structure.
  • the first cold source, the channel and the third doped layer are located inside the same semiconductor substrate.
  • the semiconductor substrate may be a silicon-based semiconductor material.
  • the first conductor layer is located on a side of the first doped layer away from the channel, and the second doped layer is located on a side of the first conductor layer away from the first doped layer.
  • the second conductor layer is located on the surface of the semiconductor substrate, the second conductor layer is in contact with the third doped layer, and the fourth doped layer is located on a side of the second conductor layer away from the third doped layer. That is to say, the first cold source and the second cold source may also be arranged asymmetrically. Wherein, the first cold source can adopt a horizontal stacked structure, and the second cold source can adopt a vertical stacked structure.
  • the field effect transistor provided in the embodiment of the present application may also be a charge trapping field effect transistor
  • the gate dielectric layer may include: a tunneling layer located on the side of the gate close to the channel, located on A charge trapping layer between the tunneling layer and the gate, and a charge blocking layer between the charge trapping layer and the gate.
  • the aforementioned field effect transistor may also be a ferroelectric field effect transistor.
  • the gate dielectric layer includes: an interface oxide layer located on the side of the gate close to the channel, and a ferroelectric layer located between the interface oxide layer and the gate.
  • the field effect transistors in the embodiments of the present application may also be other types of field effect transistors, and the structures of several types of field effect transistors will be described below.
  • the first cold source, the channel and the second cold source form a columnar structure
  • the gate dielectric layer wraps outside the channel
  • the gate wraps outside the gate dielectric layer.
  • the field effect transistor in the embodiment of the present application may also be a vertical structure field effect transistor.
  • the structure of the vertical structure field effect transistor is relatively compact, and the second doped layer in the first cold source and the fourth doped layer in the second cold source are located at both ends, so that the first cold source and the The second cold source leads out.
  • the gate is wrapped on the outside of the channel, and the overlapping area between the gate and the channel is relatively large, which increases the width-to-length ratio of the channel and improves the performance of the field effect transistor.
  • the first cold source, the channel and the second cold source are located on the surface of the same semiconductor substrate.
  • the second doped layer is block-shaped, the first conductive layer wraps a part of the second doped layer close to the semiconductor substrate, and the first doped layer is located on the surface of the first conductive layer close to the channel.
  • the fourth doped layer is block-shaped, the second conductor layer wraps a part of the fourth doped layer close to the semiconductor substrate, and the third doped layer is located on the surface of the second conductor layer close to the channel.
  • the field effect transistor provided in the embodiment of the present application may be a fin field effect transistor.
  • the gate In the fin field effect transistor, the gate is located on the surface of the semiconductor substrate on which the channel is provided, and the gate covers the channel. In this way, the overlapping area between the gate and the channel is relatively large, and the channel is enlarged. The width-to-length ratio improves the performance of field effect transistors.
  • isolation dielectric layers 18 are provided on the outer sides of the two opposite sides of the semiconductor substrate 10 . The isolation dielectric layer 18 has the function of protecting the semiconductor substrate 10 and also plays the role of insulation.
  • the first cold source and the second cold source are located on the surface of the same semiconductor substrate.
  • the field effect transistor includes: at least two channels located on one side of the semiconductor substrate; the at least two channels in the field effect transistor are arranged in sequence in a direction perpendicular to the surface of the semiconductor substrate, and between two adjacent channels There is a gap between the semiconductor substrate and the nearest channel.
  • the gate is located on the surface of the semiconductor substrate on which the channel is provided, and the gate wraps each channel in the field effect transistor. In this way, the overlapping area between the gate and the channel is larger, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved.
  • the first doped layer is connected to one end of each of the at least two channels, and the third doped layer is connected to the other end of each of the at least two channels.
  • the first conductor layer is located on the surface of the first doped layer away from the channel, and the second doped layer is located on the surface of the first conductor layer away from the first doped layer.
  • the second conductor layer is located on the surface of the third doped layer away from the channel, and the fourth doped layer is located on the surface of the second conductor layer away from the third doped layer.
  • the field effect transistor provided in the embodiment of the present application may be a gate-all-round field effect transistor, and the second doped layer and the fourth doped layer in the gate-all-round field effect transistor are located on the outside, so that the first cold source and a second cold source lead out.
  • isolation dielectric layers 18 are provided on the outer sides of the two opposite sides of the semiconductor substrate 10 .
  • the isolation dielectric layer 18 has the function of protecting the semiconductor substrate 10 and also plays the role of insulation.
  • field effect transistors provided in the embodiments of the present application may also be of other types, which will not be listed one by one here.
  • the embodiment of the present application further provides an integrated circuit, which includes: any field effect transistor described above, and a signal line electrically connected to the field effect transistor. Since the subthreshold swing of the above-mentioned field effect transistor provided in the embodiment of the present application is low, the subthreshold swing of the field effect transistor can be less than 60mV/dec, therefore, the operating voltage of the integrated circuit in the embodiment of the present application is relatively low, Furthermore, the power consumption of the integrated circuit is low.
  • the embodiment of the present application also provides a method for manufacturing a field effect transistor, the method may include:
  • a channel, a first doped layer and a third doped layer are respectively formed by a doping process; the first doped layer is in contact with the channel, and the third doped layer is in contact with the channel; the first doped layer and the third doped layer are in contact with the channel;
  • the impurity layer belongs to the same doping type;
  • the second doped layer and the fourth doped layer are formed by a doping process; the first conductor layer is located between the first doped layer and the second doped layer, and the second conductor layer is located between the third doped layer and the fourth doped layer. between the impurity layers; the second doping layer and the fourth doping layer belong to the same doping type, and the second doping layer and the first doping layer belong to different doping types.
  • two cold sources can be formed in the field effect transistor, that is, the first cold source and the second cold source, wherein the first cold source includes: a first doped The impurity layer, the second doped layer and the first conductor layer, and the second cold source include: the third doped layer, the fourth doped layer and the second conductor layer.
  • the carrier density of states of the first cold source or the second cold source By adjusting the carrier density of states of the first cold source or the second cold source, high-energy electrons can be effectively filtered, thereby reducing the sub-threshold swing of the field effect transistor, so that the sub-threshold swing of the field effect transistor can be less than 60mV/ dec, thereby reducing the operating voltage of the integrated circuit, so that the power consumption of the integrated circuit is lower.
  • the conductor layer in the first cold source and the second cold source the tunneling probability of electrons in the first cold source and the second cold source can be increased, thereby increasing the on-state current of the field effect transistor.
  • the first cold source and the second cold source can be arranged symmetrically with respect to the channel, since the first doped layer and the third doped layer belong to the same doping type, therefore, it can be The first doping layer and the third doping layer are formed by using the same doping process, thereby saving process steps and production costs.
  • the first conductor layer and the second conductor layer can also be produced by the same process, and the second doped layer and the fourth doped layer can also be produced by the same doping process.
  • FIG. 1 is a schematic diagram of an internal structure of a terminal in an embodiment of the present application
  • Fig. 2 is the simplified structure schematic diagram of the field effect transistor that the embodiment of the present application provides;
  • FIG. 3a is a simplified structural schematic diagram of a type of field effect transistor in an embodiment of the present application.
  • Fig. 3b is a simplified structural schematic diagram of another type of field effect transistor in the embodiment of the present application.
  • 4a is a schematic diagram of an energy level structure of a field effect transistor in the related art
  • Figure 4b is a schematic diagram of the energy level structure of the field effect transistor in the embodiment of the present application.
  • Figure 5a is a schematic diagram of the relationship between the drain current and the gate voltage of a single-ended cold source transistor
  • Figure 5b is a schematic diagram of the relationship between the drain current and the gate voltage of the double-terminal cold source transistor
  • FIG. 6 is a schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • FIG. 7 is another schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • FIG. 8 is another schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • FIG. 9 is another schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • FIG. 10 is another schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • FIG. 11 is a schematic diagram of a three-dimensional structure of a field effect transistor provided in an embodiment of the present application.
  • FIG. 12 is a schematic diagram of another three-dimensional structure of a field effect transistor provided in an embodiment of the present application.
  • Fig. 13 is a schematic cross-sectional view at the dotted line AA' in Fig. 12;
  • FIG. 14 is a schematic diagram of another three-dimensional structure of a field effect transistor provided in an embodiment of the present application.
  • FIG. 15 is a flow chart of a manufacturing method of a field effect transistor provided in an embodiment of the present application.
  • 10-semiconductor substrate 11-first cold source; 111-first doped layer; 112-second doped layer; 113-first conductor layer; 12-second cold source; 121-third doped 122-fourth doped layer; 123-second conductor layer; 13-channel; 14-gate; 15-gate dielectric layer; 161-first insulating layer; 162-second insulating layer; 171 - contact electrode; 172 - extraction electrode; 173 - first barrier layer; 174 - second barrier layer; 18 - isolation dielectric layer; S1 - first surface; S2 - second surface.
  • Embodiments of the present application provide a field effect transistor, a manufacturing method thereof, and an integrated circuit.
  • the field effect transistor may be a planar field effect transistor, a double gate field effect transistor, or a triple gate type.
  • Field effect transistor fin field effect transistor
  • FinFET ring gate field effect transistor
  • GAAFET gate-all-around field effect transistor
  • Vertical MOSFET Vertical MOSFET
  • Floating Gate MOSFET Charge Trapping MOSFET
  • Thin Film Transistor Thin Film Transistor
  • Ferroelectric Field Effect Transistor FeFET
  • the field effect transistor can be applied in an integrated circuit, and the integrated circuit can be an integrated circuit with various functions such as logic, storage (such as Flash, DRAM, etc.), simulation, and sensing.
  • the field effect transistors in the embodiments of the present application can also be applied to other types of integrated circuits, and no more examples will be given here.
  • FIG. 1 is a schematic diagram of the internal structure of the terminal in the embodiment of the present application. As shown in FIG. In the chip 102 mentioned above.
  • Fig. 2 is a simplified structural schematic diagram of a field effect transistor provided by the embodiment of the present application.
  • the field effect transistor may include: a first cold source 11, a second cold source 12, a The channel 13 between the second cold source 11 and the second cold source 12 , the gate 14 , and the gate dielectric layer 15 between the channel 13 and the gate 14 .
  • the first cold source 11 is used as the source of the field effect transistor
  • the second cold source 12 is used as the drain of the field effect transistor
  • the first cold source 11 is used as the drain of the field effect transistor
  • the second cold source 12 is used as the drain of the field effect transistor.
  • the cold source 12 acts as the source of the field effect transistor.
  • the source and the drain of the field effect transistor in the embodiment of the present application can be interchanged.
  • the conduction state between the source and the drain can be controlled by applying a gate voltage to the gate 14 .
  • the gate voltage is higher than the threshold voltage, the conduction between the source and the drain occurs.
  • the gate voltage is lower than the threshold voltage, the field effect transistor is in a subthreshold state, and there is a slight leakage current between the source and the drain.
  • the first cold source 11 may include: a first doped layer 111, a second doped layer 112, and a first conductor layer 113 located between the first doped layer 111 and the second doped layer 112, the first doped layer The impurity layer 111 is in contact with the channel 13 .
  • the second cold source 12 may include: a third doped layer 121, a fourth doped layer 122, and a second conductor layer 123 located between the third doped layer 121 and the fourth doped layer 122, the third doped layer The impurity layer 121 is in contact with the channel 13 .
  • the first doped layer 111 and the third doped layer 121 belong to the same doping type, and the second doped layer 112 and the fourth doped layer 122 belong to the same doping type; the first doped layer 111 and the second doped layer 112 belongs to a different doping type.
  • the structure of the second cold source 12 is similar to that of the first cold source 11, I won't repeat them here.
  • the first cold source 11 may include a first doped layer 111, a first conductor layer 113, and a second doped layer 112, and the first doped layer 111 and the second doped layer 112 belong to different doping types, for example , the first doped layer 111 may be an N-type doped layer, and the second doped layer 112 may be a P-type doped layer.
  • the traditional field effect transistor realizes switching by adjusting the thermionic emission of the channel barrier, and the energy of injected carriers is relatively high. Therefore, compared with the traditional field effect transistor, in the embodiment of the present application, the performance of the field effect transistor is like working in a low temperature environment. Therefore, the first doped layer 111, the first conductive layer 113 and the second doped layer 112
  • the composed structure is called a cold source, and the field effect transistor can be called a cold source field effect transistor.
  • Fig. 3a and Fig. 3b are the simplified structural representations of different types of field effect transistors in the embodiment of the present application.
  • the field effect transistor can be an N-type cold source transistor ( N-type cold source field effect transistor, nCSFET)
  • the first doped layer 111 can be an N-type doped layer
  • the second doped layer 112 can be a P-type doped layer
  • the third doped layer 121 can be an N-type Doped layer
  • the fourth doped layer 122 may be a P-type doped layer.
  • the field effect transistor can be a P-type cold source field effect transistor (P-type cold source field effect transistor, pCSFET), and the first doped layer 111 can be a P-type Doped layers, the second doped layer 112 may be an N-type doped layer, the third doped layer 121 may be a P-type doped layer, and the fourth doped layer 122 may be an N-type doped layer.
  • P-type cold source field effect transistor P-type cold source field effect transistor
  • pCSFET P-type cold source field effect transistor
  • the semiconductor layer may include materials such as silicon, germanium, silicon germanium, silicon carbide, III-V compound semiconductors, oxide semiconductors, or carbon nanotubes.
  • the semiconductor layer may also include other semiconductor materials. Do limited.
  • the field effect transistor is provided with a first cold source and a second cold source, and by adjusting the carrier density of states of the first cold source or the second cold source, high-energy electrons can be effectively filtered , so as to reduce the sub-threshold swing of the field effect transistor, so that the sub-threshold swing of the field effect transistor can be less than 60mV/dec, thereby reducing the operating voltage of the integrated circuit and lowering the power consumption of the integrated circuit.
  • the conductor layer in the first cold source and the second cold source the tunneling probability of electrons in the first cold source and the second cold source can be increased, thereby increasing the on-state current of the field effect transistor.
  • the principle that the field effect transistor in the embodiment of the present application can reduce the sub-threshold swing will be described in detail below with reference to the accompanying drawings.
  • the field effect transistor in the embodiment of the present application as an example shown in FIG. 112 may be a P-type doped layer
  • the third doped layer 121 in the second cold source 12 may be an N-type doped layer
  • the fourth doped layer 122 may be a P-type doped layer.
  • the principle that the field effect transistor of the type shown in FIG. 3b can reduce the sub-threshold swing is similar and will not be repeated here.
  • FIG. 4 a is a schematic diagram of an energy level structure of a field effect transistor in the related art
  • FIG. 4 b is a schematic diagram of an energy level structure of a field effect transistor in an embodiment of the present application.
  • the energy bands of the P-type doped layer and the N-type doped layer include a conduction band Ec, a forbidden band and a valence band Ev, wherein the conduction band Ec is above the forbidden band, and the valence band Ev is at Below the forbidden band.
  • the energy band of injected carriers that is, the region indicated by arrow W1 in Figure 4a
  • the energy band of injected carriers is above the conduction band Ec, that is, the energy of injected carriers is higher .
  • the energy band of the P-type doped layer moves up relative to the energy band of the N-type doped layer, while the energy band of the N-type doped layer Relative to the energy band of the P-type doped layer, it moves down until the Fermi level.
  • the energy band of the P-type doped layer is equal to the energy band of the N-type doped layer, the energy band stops moving relatively.
  • the PN junction formed between the impurity layer and the N-type doped layer reaches an equilibrium state. In the balanced PN junction, there is an overlapping region between the valence band Ev of the P-type doped layer and the conduction band Ec of the N-type doped layer.
  • the region indicated by arrow W2 is the energy band of filtered high-energy carriers
  • the region indicated by arrow W3 is the energy band of injected carriers. Since the overlapping area where electron tunneling can occur only accounts for a small part of the area, while the forbidden band where electrons cannot tunnel accounts for most of the area, the PN junction can effectively suppress the high-energy carriers excited by thermal energy and reduce the thermal excitation. Leakage, thereby reducing the sub-threshold swing, for example, the sub-threshold swing can be lower than 60mV/dec. At this time, the field effect transistor behaves like working in a low temperature environment, so it can be called a cold source field effect transistor.
  • the on-state current of the field effect transistor cannot meet the requirements.
  • a Schottky barrier can be formed between the conductor layer and the doped layer, and electrons flow from the P-type doped layer One side tunnels to the conductor layer, and then further tunnels to the side of the N-type doped layer, which can greatly increase the tunneling probability and increase the on-state current of the field effect transistor.
  • the source is electrically connected to the contact electrode, and carriers are injected into the source from the contact electrode. Since the hot carriers on the potential barrier satisfy the Fermi distribution, the subthreshold swing is between It cannot be less than 60mV/dec at room temperature.
  • the first cold source or the second cold source suppresses the thermal tail by introducing an energy gap.
  • the first cold source or the second cold source is controlled by the density of states to form "cold" carriers injected into the source.
  • the distribution of "cold" carriers does not extend into the thermalized Fermi band tail in the off state, because the hot band tail has been cut off by the upper band gap, so the off-state current is greatly reduced.
  • the sub-threshold swing of the field effect transistor in the embodiment of the present application may not be limited to 60 mV/dec.
  • the above-mentioned first conductor layer may include: a metal material, a semi-metal material, or a metal silicide material.
  • the above-mentioned second conductor layer may include: metal material, semi-metal material or metal silicide material.
  • the above metal material can be at least one of aluminum (Al), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), cobalt (Co), tungsten (W) or ruthenium (Ru) kind.
  • the aforementioned semimetal (Semimetal) material is a material with a very narrow gap between the guide band and the valence band.
  • the interval between the conduction band and the valence band from narrow to wide solids can be divided into metals, semi-metals, semiconductors and insulators in turn. That is to say, the interval between the conduction band and the valence band of the semi-metal material is smaller than the interval between the conduction band and the valence band of the semiconductor material, and larger than the interval between the conduction band and the valence band of the metal material.
  • the interval between the conduction band and the valence band is relatively large, so that the density of states of electrons near the Fermi level is equal to zero, which becomes the band gap, where the band gap of the insulator is larger than that of the semiconductor.
  • the Fermi level of the metal is in the conduction band, and there is a large enough electronic density of states nearby, so that the current can be well conducted.
  • Semi-metallic materials since the gap between the conduction band and valence band of semi-metallic materials is very small, the density of states of electrons near the Fermi level is close to zero but not zero, so semi-metallic materials have no band gap.
  • Semi-metallic materials are in the transition position of metal to non-metal in the periodic table of elements, and their physical and chemical properties are between metal and non-metal.
  • the above semi-metallic material may be at least one of arsenic, antimony, bismuth, tin or graphite.
  • the aforementioned metal silicide may be made of NiSi 2 , TiSi 2 or CoSi.
  • the first conductor layer and the second conductor layer may also include other conductor materials, for example, the first conductor layer (or the second conductor layer) may include materials such as graphene, two-dimensional metals or metalloids.
  • the first cold source can be used as the source
  • the second cold source can be used as the drain
  • the first cold source can be used as the drain.
  • the cold source is used as the drain
  • the second cold source is used as the source, that is, after the source and drain of the field effect transistor in the embodiment of the application are interchanged, it still has the characteristics of a cold source transistor, which improves the integration of the field effect transistor. flexibility of use in the circuit.
  • the structure of the first cold source is similar to that of the second cold source, and can be manufactured by the same or similar process, which simplifies the complexity of the manufacturing process and reduces the cost of the manufacturing process.
  • Fig. 5a is a schematic diagram of the curve relationship between the drain current and the gate voltage of the single-ended cold source transistor
  • Fig. 5b is a schematic diagram of the curve relationship between the drain current and the gate voltage of the double-terminal cold source transistor.
  • the steeper the curve the smaller the subthreshold swing.
  • a single-ended cold source transistor means that only one of the source and drain is set as a cold source.
  • the curve L1 is the drain when the source is set as a cold source.
  • the curve L2 is the relationship curve between the drain current and the gate voltage when the drain is set as a cold source.
  • the double-terminal cold source transistor refers to that the field effect transistor includes two cold sources, a first cold source and a second cold source. Using the first cold source as the source and the second cold source as the drain, or using the first cold source as the drain and the second cold source as the source, the drain current and the gate current in these two cases
  • the relationship curves of the pole voltages can all be the curve L3 in FIG. 5b.
  • the double-ended cold-source transistor After the source and drain of the double-ended cold-source transistor are interchanged, the double-ended cold-source transistor The ability to control the density of states is not affected, and the subthreshold swing of the double-terminal cold source transistor is less than 60mV/dec. Therefore, compared with the single-ended cold-source transistor, the double-ended cold-source transistor can realize the excellent characteristic that the source and the drain are used interchangeably. In addition, the double-terminal cold source transistor can reduce the process complexity, which is beneficial to the process integration of integrated circuits.
  • the first cold source and the second cold source may be arranged symmetrically with respect to the channel.
  • each part of the first cold source electrode and the second cold source electrode can be manufactured using the same process, which reduces the complexity of the manufacturing process and saves the cost of the manufacturing process.
  • the flexibility of applying the field effect transistor to an integrated circuit is relatively high.
  • the first cold source and the second cold source may also be arranged asymmetrically, which is not limited here.
  • first cold source and the second cold source are arranged asymmetrically, since the structures of the first cold source and the second cold source are similar, the complexity of the manufacturing process of the field effect transistor is also low, and the cost of the manufacturing process is relatively low. Also relatively low.
  • the first cold source and the second cold source may adopt a vertically stacked symmetrical structure, as shown in FIG. 6 , which is a schematic cross-sectional view of a field effect transistor provided in an embodiment of the present application.
  • the first doped The layer 111, the channel 13 and the third doped layer 121 are located inside the same semiconductor substrate 10.
  • the semiconductor substrate 10 may be a silicon-based semiconductor material, and the semiconductor substrate 10 may have: opposite first surfaces S1 and the second surface S2 , for example, the first surface S1 may be the upper surface of the semiconductor substrate 10 , and the second surface S2 may be the lower surface of the semiconductor substrate 10 .
  • the first conductive layer 113 is located on the surface of the semiconductor substrate 10, the first conductive layer 113 is in contact with the first doped layer 111, and the second doped layer 112 is located on the side of the first conductive layer 113 away from the first doped layer 111 .
  • the second conductor layer 123 is located on the surface of the semiconductor substrate 10, for example, the first conductor layer 113 and the second conductor layer 123 may be located on the first surface S1 of the semiconductor substrate 10, the second conductor layer 123 and the third doped
  • the fourth doped layer 122 is located on the side of the second conductive layer 123 away from the third doped layer 121 . That is to say, the first cold source 11 and the second cold source 12 can be arranged symmetrically with respect to the channel 13 , and both the first cold source 11 and the second cold source 12 adopt a vertical stacked structure.
  • a doping process may be used to form the first doped layer 111 , the third doped layer 121 and the channel 13 on the surface of the semiconductor substrate 10 . Since the first doped layer 111 and the third doped layer 121 belong to the same doping type, the first doped layer 111 and the third doped layer 121 can be produced by the same doping process, thereby saving process steps and production costs . Moreover, the first conductive layer 113 and the second conductive layer 123 can also be fabricated by the same process, and the second doped layer 112 and the fourth doped layer 122 can also be fabricated by the same process.
  • the above-mentioned field effect transistor may also include: a contact electrode 171 and an extraction electrode 172, and the contact electrode 171 and the second doped layer 112 (or the fourth doped layer 122)
  • the lead electrode 172 is electrically connected to the contact electrode 171 .
  • the contact electrodes 171 and the lead-out electrodes 172 can be made of metal materials, for example, metal tungsten can be used.
  • a barrier layer can be set on the side of the contact electrode 171, for example, a first barrier layer 173 can be set on the side of the contact electrode 171, and the first barrier layer 173 A second barrier layer 174 is provided on the side of the .
  • the barrier layer is generally made of conductive material, so the barrier layer has better conductivity and will not affect the electrical connection between the contact electrode 171 and the second doped layer 112 (or the fourth doped layer 122).
  • the barrier layer can be made of materials such as titanium or titanium nitride.
  • the gate 14 is located on one side of the semiconductor substrate 10, and the above field effect transistor may further include: an insulating layer covering the top surface and side surfaces of the gate 14, insulating The layer may insulate the gate 14 from the first cold source 11 and the insulating layer may insulate the gate 14 from the second cold source 12 .
  • the insulating layer may include a first insulating layer 161, and a second insulating layer 162 covering the first insulating layer 161, the first insulating layer 161 may be made of a silicon dioxide material, and the second insulating layer 162 may be made of a silicon oxide material.
  • first insulating layer 161 and the second insulating layer 162 can also be used for the first insulating layer 161 and the second insulating layer 162 , which are not limited here.
  • the gate 14 by setting an insulating layer covering the top and side surfaces of the gate 14, the gate 14 can be insulated from the first cold source 11 and the second cold source 12, preventing the gate 14 from contacting the first cold source. pole 11 or the second cold source pole 12 is short-circuited.
  • first cold source and the second cold source may also adopt a laterally stacked symmetrical structure, as shown in FIG.
  • the pole 11, the channel 13 and the second cold source 12 are located inside the same semiconductor substrate 10.
  • the semiconductor substrate 10 can be a silicon-based semiconductor material, and the semiconductor substrate 10 can have: opposite first surfaces S1 and the second surface S2 , for example, the first surface S1 may be the upper surface of the semiconductor substrate 10 , and the second surface S2 may be the lower surface of the semiconductor substrate 10 .
  • the first cold source 11 , the channel 13 and the second cold source 12 may be located on a side of the semiconductor substrate 10 close to the first surface S1 .
  • the first conductive layer 113 is located on a side of the first doped layer 111 away from the channel 13
  • the second doped layer 112 is located on a side of the first conductive layer 113 away from the first doped layer 111
  • the second conductive layer 123 is located on a side of the third doped layer 121 away from the channel 13
  • the fourth doped layer 122 is located on a side of the second conductive layer 123 away from the third doped layer 121 . That is to say, the first cold source 11 and the second cold source 12 are arranged symmetrically with respect to the channel 13 , and both the first cold source 11 and the second cold source 12 adopt a lateral stacked structure.
  • the first doped layer 111 and the third doped layer 121 can be formed on the surface of the semiconductor substrate 10 by using the same doping process, and the second doped layer 121 can be formed on the surface of the semiconductor substrate 10 by using the same doping process.
  • the impurity layer 112 and the fourth doped layer 122 therefore, the manufacturing process of the field effect transistor is simple, the process steps are less, and the manufacturing cost is lower.
  • a groove U is provided on the surface of the above-mentioned semiconductor substrate 10 , the gate dielectric layer 15 is located in the groove U, and a part of the gate 14 is embedded in the groove U. In this way, the distance between the gate 14 and the channel 13 in the semiconductor substrate 10 can be made relatively close, which is convenient for controlling the on-off between the first cold source 11 and the second cold source 12 through the gate 14 .
  • the field effect transistor in the embodiment of the present application may also have an asymmetric structure, as shown in Figure 8, which is another schematic cross-sectional view of the field effect transistor provided in the embodiment of the present application, the first cold source 11.
  • the channel 13 and the third doped layer 121 are located inside the same semiconductor substrate 10 .
  • the semiconductor substrate 10 may be a silicon-based semiconductor material, and the semiconductor substrate 10 may have: opposite first surfaces S1 and second surfaces S2, for example, the first surface S1 may be the upper surface of the semiconductor substrate 10 , the second surface S2 may be the lower surface of the semiconductor substrate 10 .
  • the first conductive layer 113 is located on a side of the first doped layer 111 away from the channel 13
  • the second doped layer 112 is located on a side of the first conductive layer 113 away from the first doped layer 111
  • the second conductor layer 121 is located on the surface of the semiconductor substrate 10, for example, the first cold source 11, the channel 13 and the third doped layer 121 may be located on the side of the semiconductor substrate 10 close to the first surface S1, and the second The conductor layer 123 may be located on the first surface S1 of the semiconductor substrate 10, the second conductor layer 123 is in contact with the third doped layer 121, and the fourth doped layer 122 is located on the side of the second conductor layer 123 away from the third doped layer 121. side. That is to say, the first cold source 11 and the second cold source 12 may also be arranged asymmetrically. Wherein, the first cold source 11 may adopt a horizontal stacked structure, and the second cold source 12 may adopt a vertical stacked structure.
  • the first doped layer 111 and the third doped layer 122 can be formed on the surface of the semiconductor substrate 10 by using the same doping process, so that the process steps can be reduced and the manufacturing cost is low.
  • the first cold source 11 and the second cold source 12 are arranged asymmetrically, the structures of the first cold source 11 and the second cold source 12 are similar, and the manufacturing process is also comparative. Easy and cheap to make.
  • the field effect transistor provided in the embodiment of the present application may also be a charge trapping field effect transistor, as shown in FIG. 9 , which is another schematic cross-sectional view of the field effect transistor provided in the embodiment of the present application.
  • the dielectric layer may include: a tunneling layer 151 located on the side of the gate 14 close to the channel 13, a charge trapping layer 152 located between the tunneling layer 151 and the gate 14, and a charge trapping layer 152 located between the charge trapping layer 152 and the gate 14.
  • the charge blocking layer 153 may be a charge trapping field effect transistor, as shown in FIG. 9 , which is another schematic cross-sectional view of the field effect transistor provided in the embodiment of the present application.
  • the dielectric layer may include: a tunneling layer 151 located on the side of the gate 14 close to the channel 13, a charge trapping layer 152 located between the tunneling layer 151 and the gate 14, and a charge trapping layer 152 located between the charge trapping layer 152 and the gate 14.
  • the aforementioned field effect transistor may also be a ferroelectric field effect transistor, as shown in FIG. 10 , which is another schematic cross-sectional view of the field effect transistor provided in the embodiment of the present application.
  • the aforementioned gate dielectric layer may include : the interface oxide layer 154 located on the side of the gate 14 close to the channel 13 , and the ferroelectric layer 155 located between the interface oxide layer 154 and the gate 14 .
  • the field effect transistors in the embodiments of the present application may also be other types of field effect transistors.
  • the structures of several types of field effect transistors will be described below with reference to the accompanying drawings.
  • Fig. 11 is a schematic diagram of the three-dimensional structure of the field effect transistor provided by the embodiment of the present application.
  • the first cold source 11, the channel and the second cold source 12 form a columnar structure, wherein the channel is located The position between the cold source 11 and the second cold source 12 .
  • the gate dielectric layer 15 wraps outside the channel, and the gate 14 wraps outside the gate dielectric layer 14 . That is to say, the field effect transistor in the embodiment of the present application may also be a vertical structure field effect transistor.
  • the structure of the vertical structure field effect transistor is relatively compact, and the second doped layer 112 in the first cold source 11 and the fourth doped layer 122 in the second cold source 12 are respectively located at both ends, so that the first The cold source 11 and the second cold source 12 are drawn out.
  • the gate 14 is wrapped around the outside of the channel, and the overlapping area between the gate 14 and the channel is larger, which increases the width-to-length ratio of the channel and improves the performance of the field effect transistor.
  • Figure 12 is a schematic diagram of another three-dimensional structure of the field effect transistor provided by the embodiment of the present application
  • Figure 13 is a schematic cross-sectional diagram at the dotted line AA' in Figure 12, as shown in Figure 12 and Figure 13, the first cold source 11, the trench The track 13 and the second cold source 12 are located on the same semiconductor substrate 10.
  • the semiconductor substrate 10 may be a silicon-based semiconductor material.
  • the semiconductor substrate 10 may include: a first surface S1 and a second surface S2 oppositely arranged, for example, the first surface S1 may be the upper surface of the semiconductor substrate 10, and the second surface S2 may be the lower surface of the semiconductor substrate 10 .
  • the first cold source 11 , the channel 13 and the second cold source 12 may be located on the first surface S1 of the semiconductor substrate 10 .
  • isolation dielectric layers 18 are provided on the outer sides of the two opposite sides of the semiconductor substrate 10 .
  • the isolation dielectric layer 18 has the function of protecting the semiconductor substrate 10 and also plays the role of insulation.
  • the second doped layer 112 is block-shaped, the first conductive layer 113 wraps a part of the second doped layer 112 close to the semiconductor substrate 10, and the first doped layer 111 is located on the surface of the first conductive layer 113 near the channel 13 .
  • the fourth doped layer 122 is block-shaped, the second conductive layer 123 wraps a part of the fourth doped layer 122 close to the semiconductor substrate 10, and the third doped layer 121 is located on the surface of the second conductive layer 123 close to the channel 13 . That is to say, the field effect transistor provided in the embodiment of the present application may be a fin field effect transistor.
  • the gate 14 is located on the surface of the semiconductor substrate 10 provided with the channel 13, for example, the gate 14 may be located on the first surface S1 of the semiconductor substrate 10, and the gate 14 covers channel 13 , in this way, the overlapping area between the gate 14 and the channel 13 is larger, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved.
  • FIG. 12 in order to clearly illustrate the internal structure of the field effect transistor, the position of the gate 14 is indicated by a dotted line.
  • the top of the second doped layer 112 is not covered by the first conductive layer. 113 wrapping, therefore, it is convenient to electrically connect the second doped layer 112 with the contact electrode, that is, it is convenient to lead out the first cold source electrode 11 .
  • the top of the fourth doped layer 122 is not covered by the second conductor layer 123 , so it is convenient to electrically connect the fourth doped layer 122 to the contact electrode, that is, to lead out the second cold source 12 .
  • FIG. 14 is a schematic diagram of another three-dimensional structure of the field effect transistor provided by the embodiment of the present application.
  • the first cold source 11 and the second cold source 12 are located on the surface of the same semiconductor substrate 10, for example, The first cold source 11 and the second cold source 12 may be located on the first surface S1 of the semiconductor substrate 10 .
  • the semiconductor substrate 10 may be a silicon-based semiconductor material.
  • the semiconductor substrate 10 may include: a first surface S1 and a second surface S2 oppositely arranged, for example, the first surface S1 may be the upper surface of the semiconductor substrate 10, and the second surface S2 may be the lower surface of the semiconductor substrate 10 .
  • isolation dielectric layers 18 are provided on the outer sides of the two opposite sides of the semiconductor substrate 10 .
  • the isolation dielectric layer 18 has the function of protecting the semiconductor substrate 10 and also plays the role of insulation.
  • the field effect transistor may include: at least two channels 13 located on one side of the semiconductor substrate 10 , for example, the channels 13 may be located on the side of the first surface S1 of the semiconductor substrate 10 . At least two channels 13 in the field effect transistor are arranged in sequence in a direction perpendicular to the surface of the semiconductor substrate 10, and there is a gap between two adjacent channels 13, and the distance between the semiconductor substrate 10 and the nearest channel 13 is There are gaps between them.
  • the field effect transistor includes three channels 13 as an example for illustration, and the number of channels 13 in the field effect transistor is not limited.
  • the gate 14 is located on the surface of the semiconductor substrate 10 provided with the channel 13 side, for example, the gate 14 can be located on the first surface S1 side of the semiconductor substrate 10, and the gate 14 wraps each trench in the field effect transistor Road 13. In this way, the overlapping area between the gate 14 and the channel 13 is larger, the width-to-length ratio of the channel is increased, and the performance of the field effect transistor is improved.
  • the position of the gate 14 is indicated by a dotted line.
  • the first doped layer 111 is connected to one end of each channel 13
  • the third doped layer 121 is connected to the other end of each channel 13
  • the first conductive layer 113 is located on the surface of the first doped layer 111 away from the channel 13
  • the second doped layer 112 is located on the surface of the first conductive layer 113 away from the first doped layer 111
  • the second conductive layer 123 is located on the surface of the third doped layer 121 away from the channel 13
  • the fourth doped layer 122 is located on the surface of the second conductive layer 123 away from the third doped layer 121 .
  • the field effect transistor provided in the embodiment of the present application may be a gate-all-round field effect transistor, and the second doped layer 112 and the fourth doped layer 122 in the gate-all-around field effect transistor are located on the outside, so that the first cold The source 11 and the second cold source 12 are drawn out.
  • field effect transistors provided in the embodiments of the present application may also be of other types, which will not be listed one by one here.
  • an embodiment of the present application further provides an integrated circuit, which may include: any field effect transistor described above, and a signal line electrically connected to the field effect transistor. Since the subthreshold swing of the above-mentioned field effect transistor provided in the embodiment of the present application is low, the subthreshold swing of the field effect transistor can be less than 60mV/dec, therefore, the operating voltage of the integrated circuit in the embodiment of the present application is relatively low, Furthermore, the power consumption of the integrated circuit is low.
  • FIG. 15 is a flow chart of the method for manufacturing a field effect transistor provided in the embodiment of the application. As shown in FIG. 15 , the manufacturing method may include :
  • two cold sources can be formed in the field effect transistor, that is, the first cold source and the second cold source, wherein the first cold source includes: a first doped The impurity layer, the second doped layer and the first conductor layer, and the second cold source include: the third doped layer, the fourth doped layer and the second conductor layer.
  • the carrier density of states of the first cold source or the second cold source By adjusting the carrier density of states of the first cold source or the second cold source, high-energy electrons can be effectively filtered, thereby reducing the sub-threshold swing of the field effect transistor, so that the sub-threshold swing of the field effect transistor can be less than 60mV/ dec, thereby reducing the operating voltage of the integrated circuit, so that the power consumption of the integrated circuit is lower.
  • the conductor layer in the first cold source and the second cold source the tunneling probability of electrons in the first cold source and the second cold source can be increased, thereby increasing the on-state current of the field effect transistor.
  • S201, S202, and S203 are only to identify each step, and do not limit the order of each step. In actual implementation, the order of each step can be adjusted according to the specific structure of the field effect transistor. .
  • the first cold source and the second cold source can be arranged symmetrically with respect to the channel.
  • the same doping process can be used to form the first doped layer 111 and the third doped layer 121, thereby saving process steps and manufacturing costs.
  • the first conductive layer 113 and the second conductive layer 123 can also be fabricated by the same process, and the second doped layer 112 and the fourth doped layer 122 can also be fabricated by the same primary doping process.

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Abstract

La présente demande concerne un transistor à effet de champ, son procédé de fabrication et un circuit intégré. Le transistor à effet de champ peut comprendre une première source froide, une seconde source froide, un canal, une grille et une couche diélectrique de grille. La première source froide comprend une première couche dopée, une deuxième couche dopée et une première couche conductrice, la première couche dopée étant en contact avec le canal. La seconde source froide comprend une troisième couche dopée, une quatrième couche dopée et une seconde couche conductrice, la troisième couche dopée étant en contact avec le canal. La première couche dopée et la troisième couche dopée appartiennent à un même type de dopage, la deuxième couche dopée et la quatrième couche dopée appartiennent à un même type de dopage, et la première couche dopée et la deuxième couche dopée appartiennent à des types de dopage différents. En disposant la première source froide et la seconde source froide dans le transistor à effet de champ, et en ajustant la densité d'état de support de la première source froide ou de la seconde source froide, le basculement de sous-seuil du transistor à effet de champ peut être réduit, ce qui permet de réduire la tension de travail du circuit intégré, et de réduire la consommation d'énergie du circuit intégré.
PCT/CN2021/107580 2021-07-21 2021-07-21 Transistor à effet de champ, son procédé de fabrication et circuit intégré WO2023000200A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116581147A (zh) * 2023-06-06 2023-08-11 长鑫存储技术有限公司 半导体结构及其制备方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211987A (zh) * 2006-12-29 2008-07-02 海力士半导体有限公司 具有电荷俘获层的非易失性存储器件及其制造方法
US7442614B1 (en) * 2008-03-21 2008-10-28 International Business Machines Corporation Silicon on insulator devices having body-tied-to-source and methods of making
CN104201205A (zh) * 2014-08-27 2014-12-10 北京大学 一种芯-壳场效应晶体管及其制备方法
CN106057899A (zh) * 2015-04-14 2016-10-26 三星电子株式会社 多层鳍式场效应晶体管装置
CN112201692A (zh) * 2020-09-30 2021-01-08 上海华力集成电路制造有限公司 全包围栅极鳍式场效应晶体管及其制造方法
CN112424917A (zh) * 2018-06-06 2021-02-26 港大科桥有限公司 具有冷源极的金属氧化物半导体场效应晶体管
CN113054023A (zh) * 2020-03-31 2021-06-29 台湾积体电路制造股份有限公司 铁电场效应晶体管和形成半导体结构的方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101211987A (zh) * 2006-12-29 2008-07-02 海力士半导体有限公司 具有电荷俘获层的非易失性存储器件及其制造方法
US7442614B1 (en) * 2008-03-21 2008-10-28 International Business Machines Corporation Silicon on insulator devices having body-tied-to-source and methods of making
CN104201205A (zh) * 2014-08-27 2014-12-10 北京大学 一种芯-壳场效应晶体管及其制备方法
CN106057899A (zh) * 2015-04-14 2016-10-26 三星电子株式会社 多层鳍式场效应晶体管装置
CN112424917A (zh) * 2018-06-06 2021-02-26 港大科桥有限公司 具有冷源极的金属氧化物半导体场效应晶体管
CN113054023A (zh) * 2020-03-31 2021-06-29 台湾积体电路制造股份有限公司 铁电场效应晶体管和形成半导体结构的方法
CN112201692A (zh) * 2020-09-30 2021-01-08 上海华力集成电路制造有限公司 全包围栅极鳍式场效应晶体管及其制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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