WO2022252172A1 - 像素阵列及相关图像传感器、指纹检测芯片及电子装置 - Google Patents

像素阵列及相关图像传感器、指纹检测芯片及电子装置 Download PDF

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WO2022252172A1
WO2022252172A1 PCT/CN2021/098080 CN2021098080W WO2022252172A1 WO 2022252172 A1 WO2022252172 A1 WO 2022252172A1 CN 2021098080 W CN2021098080 W CN 2021098080W WO 2022252172 A1 WO2022252172 A1 WO 2022252172A1
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Prior art keywords
transistor
operational amplifier
pixel array
coupled
photodiodes
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PCT/CN2021/098080
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English (en)
French (fr)
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梁颖思
杨富强
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迪克创新科技有限公司
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Priority to PCT/CN2021/098080 priority Critical patent/WO2022252172A1/zh
Priority to CN202180001655.9A priority patent/CN113508577B/zh
Publication of WO2022252172A1 publication Critical patent/WO2022252172A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current

Definitions

  • the present application relates to a circuit, in particular to a pixel array and a related image sensor, a fingerprint detection chip and an electronic device.
  • CMOS complementary Metal Oxide Semiconductor
  • image sensors implemented using a thin-film semiconductor structure have many shortcomings that need to be overcome.
  • a photodiode realized by using a thin film semiconductor structure has relatively large dark current, that is, relatively large noise.
  • changing the design of the pixel unit in order to reduce the dark current often sacrifices the fill factor.
  • One of the objectives of the present application is to disclose a pixel array and related image sensor, fingerprint detection chip and electronic device to solve the above problems.
  • An embodiment of the present application discloses a pixel array, including: an operational amplifier having a positive terminal, a negative terminal and an output terminal; N photodiodes, including the 1st to Nth photodiodes, wherein N is greater than 1, the N photodiodes are located in the same row of the pixel array, and each photodiode is selectively coupled between a preset voltage and the negative terminal of the operational amplifier in a forward or reverse manner, wherein when each of the photodiodes When the photodiode is coupled between the preset voltage and the negative terminal of the operational amplifier in a forward manner, the anode of each photodiode is coupled to the preset voltage, and each photodiode The cathode of the photodiode is coupled to the negative terminal of the operational amplifier, and when the photodiodes are coupled between the preset voltage and the negative terminal of the operational amplifier in an inverse manner, each of the photodiodes The anode of the photodiode is coupled to the
  • An embodiment of the present application discloses an image sensor, including the above-mentioned pixel array.
  • An embodiment of the present application discloses a fingerprint detection chip, including the image sensor.
  • An embodiment of the present application discloses an electronic device, including the fingerprint detection chip.
  • the pixel array, image sensor, related fingerprint detection chip and electronic device of the present application can improve the fill factor of the pixel array, especially the fill factor of the pixel array realized by the thin film semiconductor structure.
  • FIG. 1 is a schematic diagram of a first embodiment of a pixel unit in a pixel array of an image sensor of the present application.
  • FIG. 2 is a schematic diagram of a second embodiment of a pixel unit in a pixel array of an image sensor of the present application.
  • FIG. 3 is a schematic diagram of an embodiment of a pixel array of an image sensor of the present application.
  • FIG. 4 is a schematic diagram of an embodiment of an image sensor of the present application.
  • FIG. 5 is a schematic diagram of a third embodiment of a pixel unit in a pixel array of an image sensor of the present application.
  • first and second features are in direct contact with each other; and may also include additional components are formed between the first and second features, such that the first and second features may not be in direct contact.
  • this disclosure may reuse reference symbols and/or labels in various embodiments. Such repetition is for the sake of brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.
  • image sensors implemented using thin-film semiconductor structures are compared to photodiodes implemented using complementary metal-oxide-semiconductor structures, photodiodes implemented using thin-film semiconductor structures, when their anode and cathode are biased, It is easy to generate a larger dark current.
  • the image sensor proposed in this application can solve this problem, the details of which will be described later.
  • the entire pixel unit 100 in FIG. 1 can be implemented with a thin film semiconductor structure, including a photodiode 102 , an operational amplifier 104 , a capacitor unit 106 , a transistor 108 , a source follower transistor 110 and a row selection transistor 112 .
  • the anode and cathode of the photodiode 102 of the pixel unit 100 are coupled to the positive terminal and the negative terminal of the operational amplifier 104, and the operational amplifier 104 is set as negative feedback, so the photoelectric The voltage difference between the anode and cathode of diode 102 is limited to zero by operational amplifier 104 . In this way, the dark current of the photodiode 102 can be reduced, and the signal-to-noise ratio of the pixel unit 100 can be improved.
  • the transistor 108 When the pixel unit 100 is operating in the sampling phase, the transistor 108 is turned off by the control signal S1, and the operational amplifier 104 integrates the capacitor unit 106, so that the photocurrent generated by the photodiode 102 forms a voltage difference at both ends of the capacitor unit 106, and passes through the source The output of the following transistor 110 and the row selection transistor 112 is the sensing result VPO.
  • the transistor 108 When the pixel unit 100 is operating in the reset phase, the transistor 108 is turned on by the control signal S1, and the voltage difference formed across the capacitor unit 106 is reset to zero.
  • the anode of the photodiode 102 is coupled to the preset voltage V1.
  • the operational amplifier 104 has a positive terminal, a negative terminal and an output terminal, the positive terminal is coupled to the anode of the photodiode 102 ; the negative terminal is coupled to the cathode of the photodiode 102 .
  • the capacitor unit 106 and the first transistor 108 are arranged in parallel, and both are coupled between the output terminal and the negative terminal of the operational amplifier 104 .
  • the gate of the source follower transistor 110 is coupled to the output terminal of the operational amplifier 110 .
  • the row selection transistor 112 is connected in series with the source follower transistor 110 and selectively outputs the sensing result VPO according to the row selection signal.
  • the present application further proposes the pixel unit 200 shown in FIG. 2 to improve the fill factor of the overall pixel array.
  • the pixel unit 200 has the biggest difference that the pixel unit 200 includes N photodiodes, that is, photodiodes 202_1 to 202_N, and the N photodiodes share the operational amplifier 104, the capacitor unit 106, the transistor 108 .
  • FIG. 3 is a schematic diagram of a pixel array 300 .
  • the N pixels of the pixel unit 200 may be N pixels P1 to PN located in the same row and different columns in the pixel array 300.
  • the N pixels of the pixel unit 200 are located in the same row of the pixel array 300 and Consecutive N columns.
  • each photodiode in the N photodiodes uses the operational amplifier 104, the capacitor unit 106, the transistor 108, the source follower transistor 110 and the row selection transistor 112 for only 1 /N, the overall light-sensing performance of the pixel array 300 is bound to be reduced to 1/N, which greatly reduces the signal-to-noise ratio. It is not an ideal result to reduce the photosensitive performance to 1/N in order to increase the fill factor.
  • the solution proposed in this application is to perform N configurations of N photodiodes 202_1 to 202_N in N time periods based on the concept of encoding, and obtain N mixed sensing results VPO.
  • the mixed sensing result VPO includes the mixed information of some or all of the photodiodes 202_1 to 202_N; on the contrary, FIG. 1
  • the sensing results VPO of the pixel units 100 only include single pixel information.
  • the N mixed sensing results VPO can be reversely decoded according to the encoding method, and the respective sensing information of the N photodiodes 202_1 to 202_N can be obtained.
  • the computing unit 402 can be used to
  • the N non-mixed sensing results VPO′ are calculated according to the N mixed sensing results VPO, corresponding to the photodiodes 202_1 to 202_N one-to-one.
  • the entire pixel unit 200 may be implemented with a thin film semiconductor structure, while the operation unit 402 is a CMOS structure.
  • the encoding method should not just switch each photodiode between on and off.
  • This application utilizes the characteristic that the voltage difference between the anode and the cathode of each photodiode in the photodiodes 202_1 to 202_N is limited to 0 by the operational amplifier 104, so that each photodiode can be selectively coupled in a forward or reverse manner between the preset voltage V1 and the negative terminal of the operational amplifier 104 . In this way, regardless of the forward or reverse configuration, the photodiode will still contribute the sensing result to the mixed sensing result VPO, but for the forward and reverse configurations, the contribution of the two configurations to the mixed sensing result VPO on the contrary.
  • each photodiode when each photodiode is coupled between the preset voltage V1 and the negative terminal of the operational amplifier 104 in a forward manner, the anode of each photodiode is coupled to the preset voltage V1, and the anode of each photodiode The cathode is coupled to the negative terminal of the operational amplifier 104; conversely, when each photodiode is coupled between the preset voltage V1 and the negative terminal of the operational amplifier 104 in an inverse manner, the anode of each photodiode is coupled to the negative terminal of the operational amplifier 104. Connected to the negative terminal of the operational amplifier 104, the cathode of each photodiode is coupled to a predetermined voltage V1.
  • each photodiode when each photodiode is coupled between the preset voltage V1 and the negative terminal of the operational amplifier 104 in a forward direction, the anode of each photodiode is coupled to the preset voltage through the second switch V1, and the cathode of each photodiode are coupled to the negative terminal of the operational amplifier 104 through a third switch; when each photodiode is coupled between the preset voltage V1 and the negative terminal of the operational amplifier 104 in a reverse manner , the anode of each photodiode is coupled to the negative terminal of the operational amplifier 104 through the first switch, and the cathode of each photodiode is coupled to the preset voltage V1 through the fourth switch.
  • the photodiode 202_1 when the photodiode 202_1 is forwardly coupled between the predetermined voltage V1 and the negative terminal of the operational amplifier 104, the first switch 21_1 and the fourth switch 24_1 are turned off, and the second switch 22_1 and the third switch 23_1 are turned on; when the photodiode 202_1 is reversely coupled between the preset voltage V1 and the negative terminal of the operational amplifier 104, the first switch 21_1 and the fourth switch 24_1 are turned on, and the second The second switch 22_1 and the third switch 23_1 are turned off.
  • the original sensing time period T of each pixel can be cut into N time periods on average, wherein in the Xth time period, the Nth photodiode 202_1 to photodiode 202_N
  • the coupling mode of the Y photodiodes 202_Y is A XY , wherein X and Y are integers from 1 to N, and A XY being 1 means that the coupling mode of the Yth photodiode in the X time period is forward, A XY being -1 means that the coupling mode of the Yth photodiode in the X time period is reversed, and A XY being 0 means that the Yth photodiode is not coupled to the preset in the X time period voltage and the negative terminal of the operational amplifier.
  • a XY being 1 or -1 means that the Yth photodiode is turned on in the X time period and the sensing result will contribute to the mixed sensing result VPO
  • a XY being 0 means that the Yth photodiode is turned on in the X time period. The Yth photodiode is turned off and the sensing result will not contribute to the mixed sensing result VPO.
  • the pixel array 300 For the first time period to the Nth time period, the pixel array 300 correspondingly undergoes N reset phases and N sampling phases, so as to avoid mutual interference of N mixed sensing results in N time periods, that is, the pixel unit 200
  • the capacitor unit 106 will be reset between corresponding output of N hybrid sensing results.
  • the matrix formed by A XY can be expressed as If the photodiode 202_1 to the photodiode 202_N of the pixel unit 200 are forwardly coupled between the preset voltage V1 and the negative terminal of the operational amplifier 104 during the entire sensing period T, then the photodiode 202_1 to the photodiode 202_N can correspondingly contribute the amount of PD 1 to PD N to the mixed sensing result VPO.
  • the photodiode 202_1 to the photodiode 202_N of the pixel unit 200 are coupled between the preset voltage V1 and the negative terminal of the operational amplifier 104 in an inverse manner during the entire sensing period T, then the photodiode 202_1 to the photodiode 202_N
  • the amounts of -PD 1 to -PD N can be correspondingly contributed to the mixed sensing result VPO.
  • the corresponding first mixed sensing results VPO 1 to Nth mixed sensing results VPO N from the first time period to the Nth time period can be expressed as:
  • the corresponding inverse matrix can be expressed as:
  • the matrix All the elements A XY in are non-zero, that is to say, adopt forward or reverse configuration when encoding, and do not turn off the photodiode, otherwise the light-sensing performance will be reduced. In other words, make all elements A XY 1 or -1, avoid 0.
  • the variation of gain can be increased, for example, all elements A XY can be set to 1, -1, 2 or -2, so as to increase the flexibility of operation.
  • it should be considered that all elements A XY ' in the corresponding inverse matrix should also avoid being 0 during encoding.
  • N the complexity of the computing unit 402 may increase.
  • the design of the present application can improve the fill factor without reducing the signal-to-noise ratio, especially for pixel units implemented with thin-film semiconductor structures.
  • the capacitor unit 106 can be reduced to 1/2, or if the size of the capacitor unit 106 is not changed, the dynamic range can be doubled.
  • the present application can also reduce certain aspects of noise, such as time-based noise (especially low-frequency noise) and space-based noise.
  • the present application also proposes the pixel unit 500 in FIG. 5 to further improve the leakage current problem of the transistor 108 .
  • the pixel unit 500 has a leakage suppression unit 202 , which can further reduce the overall leakage of the path where the transistor 108 and the transistor 204 are located in the sampling phase.
  • the leakage suppression unit 202 includes a transistor 204 and a transistor 206 .
  • the transistor 204 is connected in series with the transistor 108 , and the series connected transistor 108 and transistor 204 are connected in parallel to the capacitor unit 106 and coupled between the output terminal and the negative terminal of the operational amplifier 104 .
  • the transistor 206 is turned off by the control signal S3 , and the series-connected transistor 108 and transistor 204 are turned on by the control signals S1 and S2 to reset the voltage difference formed across the capacitor unit 106 in the sampling phase.
  • the serially connected transistor 108 and transistor 204 are both off, and the transistor 206 of the leakage suppression unit 202 is turned on, so that one terminal of the transistor 204 can be coupled to the positive terminal of the operational amplifier 104 through the transistor 206 .
  • the other terminal of the transistor 204 is coupled to the negative terminal of the operational amplifier 104 , so the voltage difference between the two terminals of the transistor 204 is clamped at 0 during the sampling phase, which can reduce the leakage current passing through the two terminals of the transistor 204 . Since the transistor 204 is connected in series with the transistor 108 and the transistor 204 is used as a gatekeeper for the leakage current, the actual leakage current caused by the transistor 108 can be greatly reduced under the condition that the occurrence rate of the leakage current of the transistor 108 remains unchanged.
  • the polarity of all transistors is not particularly limited, that is, each transistor is not limited to be P-type or N-type, nor is the bulk connection method of each transistor emphasized.
  • the present application also provides a fingerprint detection chip, including the image sensor, and the image sensor may include a pixel array 300, and may include pixel units 100/200/400/500.
  • the use of the fingerprint detection chip in the embodiment of the present application can increase the fill factor or increase the dynamic range, and reduce the noise of some aspects, and further improve the performance of fingerprint detection.
  • the present application also provides an electronic device, which includes the fingerprint detection chip.
  • the fingerprint detection chip can be arranged under the display screen of the electronic device to realize fingerprint detection under the screen.
  • the fingerprint detection chip can be arranged inside the display screen, that is, the fingerprint detection chip is integrated inside the display screen to realize fingerprint detection in the screen.

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Abstract

本申请公开了一种像素阵列及相关图像传感器、指纹检测芯片及电子装置。像素阵列包括：运算放大器；N个光电二极管位于所述像素阵列的同一行，各光电二极管选择性地以顺向或逆向的方式耦接于预设电压及所述运算放大器的所述负端之间；电容单元，耦接于所述运算放大器的所述输出端与所述负端之间；第一晶体管，耦接于所述运算放大器的所述输出端与所述负端之间；其中所述N个光电二极管共享所述运算放大器、所述电容单元、所述第一晶体管。

Description

像素阵列及相关图像传感器、指纹检测芯片及电子装置 技术领域
本申请涉及一种电路，尤其涉及一种像素阵列及相关图像传感器、指纹检测芯片及电子装置。
背景技术
使用薄膜半导体结构实现的图像传感器，其成本远远低于使用互补金属氧化物(Complementary Metal Oxide Semiconductor,CMOS)半导体结构实现的图像传感器，但使用薄膜半导体结构实现的图像传感器有许多缺点需要克服，例如使用薄膜半导体结构实现的光电二极管的暗电流较大，也就是有较大的噪声。然而，为了降低暗电流而改变像素单元的设计，往往牺牲了填充系数。
因此，如何改善像素阵列的填充系数，特别是以薄膜半导体结构实现的像素阵列的填充系数，已成为本领域亟需解决的问题之一。
发明内容
本申请的目的之一在于公开一种像素阵列及相关图像传感器、指纹检测芯片及电子装置，来解决上述问题。
本申请的一实施例公开了一种像素阵列，包括：运算放大器，具有正端、负端与输出端；N个光电二极管，包含第1至第N个光电二极管，其中N大于1，所述N个光电二极管位于所述像素阵列的同一行，各光电二极管选择性地以顺向或逆向的方式耦接于预设电压及所述运算放大器的所述负端之间，其中当所述各光电二极管以顺向的方式耦接于所述预设电压及所述运算放大器的所述负端之间时，所 述各光电二极管的阳极耦接至所述预设电压，所述各光电二极管的阴极耦接至所述运算放大器的所述负端，当所述各光电二极管以逆向的方式耦接于所述预设电压及所述运算放大器的所述负端之间时，所述各光电二极管的阳极耦接至所述运算放大器的所述负端，所述各光电二极管的阴极耦接至所述预设电压；电容单元，耦接于所述运算放大器的所述输出端与所述负端之间，其中在采样阶段，所述多个光电二极管产生的光电流使所述电容单元两端形成电压差，在重置阶段所述电容单元两端的电压差被重置为零；第一晶体管，耦接于所述运算放大器的所述输出端与所述负端之间，其中在所述采样阶段，所述第一晶体管断开，在所述重置阶段，所述第一晶体管导通其中所述N个光电二极管共享所述运算放大器、所述电容单元及所述第一晶体管。
本申请的一实施例公开了一种图像传感器，包括所述的像素阵列。
本申请的一实施例公开了一种指纹检测芯片，包括所述的图像传感器。
本申请的一实施例公开了一种电子装置，包括所述的指纹检测芯片。
本申请的像素阵列、图像传感器及相关指纹检测芯片及电子装置，可以提升像素阵列的填充系数，特别是以薄膜半导体结构实现的像素阵列的填充系数。
附图说明
图1为本申请的图像传感器的像素阵列中的像素单元的第一实施例的示意图。
图2为本申请的图像传感器的像素阵列中的像素单元的第二实施例的示意图。
图3为本申请的图像传感器的像素阵列的实施例的示意图。
图4为本申请的图像传感器的实施例的示意图。
图5为本申请的图像传感器的像素阵列中的像素单元的第三实施例的示意图。
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见，这些叙述仅为例示，其本意并非用于限制本揭示内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
使用薄膜半导体结构实现的图像传感器造成的问题之一在于，相较于使用互补金属氧化物半导体结构实现的光电二极管，使用薄膜半导体结构实现的光电二极管在其阳极和阴极有偏压的情况下，容易产生更大的暗电流。本申请提出的图像传感器可以解决此问题，其细节说明于后。
在图1中的像素单元100的整体可以是以薄膜半导体结构实现，包含光电二极管102、运算放大器104、电容单元106、晶体管108、源跟随晶体管110以及行选择晶体管112。为了降低光电二极管102的暗电流，像素单元100的光电二极管102的阳极与阴极耦接至运算放大器104的所述正端与所述负端，又运算放大器104被设置为负回授，因此光电二极管102的阳极与阴极之间的电压差被运算放大器104限制在0。这样一来便可降低光电二极管102的暗电流，提高像素单元100的信噪比。
当像素单元100操作在采样阶段时，晶体管108通过控制信号S1断开，运算放大器104对电容单元106进行积分，使光电二极管102产生的光电流在电容单元106两端形成电压差，并通过源跟随晶体管110及行选择晶体管112输出为感测结果VPO。当像素单元100操作在重置阶段时，晶体管108通过控制信号S1导通，电容单元106两端形成电压差会被重置为0。
具体来说，像素单元100中，光电二极管102的阳极耦接至预设电压V1。运算放大器104具有正端、负端与输出端，所述正端耦接至光电二极管102的阳极；所述负端耦接至光电二极管102的阴极。电容单元106与第一晶体管108并联设置，且皆耦接于运算放大器104的所述输出端与所述负端之间。源跟随晶体管110的栅极耦接至运算放大器110的所述输出端。行选择晶体管112串接于源跟随晶体管110，并依据行选择信号来选择性地输出感测结果VPO。
虽然像素单元100的光电二极管102的暗电流降低了，但加入了运算放大器104需要占用额外的面积，使像素单元100的填充系数下降。因此，本申请又提出图2的像素单元200来改善整体像素阵列的 填充系数。像素单元200相较于像素单元100，最大的差异在于像素单元200中，包含了N个光电二极管，即光电二极管202_1至光电二极管202_N，且N个光电二极管共享运算放大器104、电容单元106、晶体管108、源跟随晶体管110及行选择晶体管112。也就是说，实际上像素单元200包含了N个像素，其中N为大于1的整数。图3为像素阵列300的示意图。像素单元200的N个像素可以是在像素阵列300中位于同一行且不同列的N个像素P1至PN，在本实施例中，像素单元200的N个像素是位于像素阵列300的同一行且连续N列。
因为同时有N个光电二极管共享运算放大器104、电容单元106、晶体管108、源跟随晶体管110及行选择晶体管112，因此若没有特殊的设计，N个光电二极管中各光电二极管不能同时开启，否则会互相干扰，但这样一来，N个光电二极管中各光电二极管使用运算放大器104、电容单元106、晶体管108、源跟随晶体管110及行选择晶体管112的时间只有原本(例如图1的情况)的1/N，像素阵列300整体的感光效能势必会降低至1/N，大大地降低信噪比。为了提高填充系数而让感光效能降低至1/N，并不是理想的结果。
因此为了不降低感光效能，需要解决N个光电二极管中各光电二极管同时开启时的互相干扰的问题。本申请提出的解决方式，是以编码的概念对N个光电二极管202_1至光电二极管202_N在N个时间段进行N种配置，并得到N个混合感测结果VPO。应注意的是，在图2的像素单元200中，依据配置的方式，混合感测结果VPO包含有光电二极管202_1至光电二极管202_N中的部分或全部的光电二极管的混合信息；相反的，图1的像素单元100的感测结果VPO都只包含单一像素信息。N个混合感测结果VPO可以依据编码的方式逆向解码回来，得到N个光电二极管202_1至光电二极管202_N各自的感测信息，如图4中的图像传感器400的实施例中，运算单元402可用来依据N个混合感测结果VPO计算N个非混合感测结果VPO'一对一地对应光电二极管202_1至光电二极管202_N。在本实施例中，像素单元200的整体可以是以薄膜半导体结构实现，而运算单 元402为互补金属氧化物半导体结构。
要能增加上述使用编码及解码的实施上的可行性，又要不降低感光效能，编码的方式就不能只是让各光电二极管切换于导通或关闭之间。本申请利用光电二极管202_1至光电二极管202_N中各光电二极管的阳极与阴极之间的电压差被运算放大器104限制在0的特性，使各光电二极管可以选择性地以顺向或逆向的方式耦接于预设电压V1及运算放大器104的所述负端之间。这样一来，光电二极管不论顺向或逆向配置，都依然会贡献感测结果至混合感测结果VPO，只是对于顺向和逆向配置来说，两种配置方式对混合感测结果VPO造成的贡献相反。
具体来说，当各光电二极管以顺向的方式耦接于预设电压V1及运算放大器104的所述负端之间时，各光电二极管的阳极耦接至预设电压V1，各光电二极管的阴极耦接至运算放大器104的所述负端；相反地，当各光电二极管以逆向的方式耦接于预设电压V1及运算放大器104的所述负端之间时，各光电二极管的阳极耦接至运算放大器104的所述负端，各光电二极管的阴极耦接至预设电压V1。在本实施例中，当各光电二极管以顺向的方式耦接于预设电压V1及运算放大器104的所述负端之间时，各光电二极管的阳极通过第二开关耦接至预设电压V1，以及各光电二极管的阴极通过第三开关耦接至运算放大器104的所述负端；当各光电二极管以逆向的方式耦接于预设电压V1及运算放大器104的所述负端之间时，各光电二极管的阳极通过第一开关耦接至运算放大器104的所述负端，以及各光电二极管的阴极通过第四开关耦接至预设电压V1。
举例来说，当光电二极管202_1以顺向的方式耦接于预设电压V1及运算放大器104的所述负端之间时，第一开关21_1和第四开关24_1断开，且第二开关22_1和第三开关23_1导通；当光电二极管202_1以逆向的方式耦接于预设电压V1及运算放大器104的所述负端之间时，第一开关21_1和第四开关24_1导通，且第二开关22_1和第三开关23_1断开。当光电二极管202_2以顺向的方式耦接于预 设电压V1及运算放大器104的所述负端之间时，第一开关21_2和第四开关24_2断开，且第二开关22_2和第三开关23_2导通；当光电二极管202_2以逆向的方式耦接于预设电压V1及运算放大器104的所述负端之间时，第一开关21_2和第四开关24_2导通，且第二开关22_2和第三开关23_2断开。对于光电二极管202_3至202_N则依此类推。应注意的是，图2中为了简洁仅绘示了光电二极管202_1及其对应的第一开关21_2、第二开关22_2、第三开关23_2及第四开关24_2。
具体来说，可以将原本(例如图1的情况)的每个像素的感测时间段T平均切为N个时间段，其中在第X时间段，N个光电二极管202_1至光电二极管202_N中第Y个光电二极管202_Y的耦接方式为A XY，其中X及Y皆为1至N的整数，A XY为1代表在第X时间段所述第Y个光电二极管的耦接方式为顺向，A XY为-1代表在第X时间段所述第Y个光电二极管的耦接方式为逆向，A XY为0代表在第X时间段所述第Y个光电二极管不耦接于所述预设电压及所述运算放大器的所述负端之间。也就是说，A XY为1或-1代表在第X时间段所述第Y个光电二极管导通且感测结果会贡献至混合感测结果VPO，A XY为0代表在第X时间段所述第Y个光电二极管关闭且感测结果不会贡献至混合感测结果VPO。
针对第一时间段至第N时间段，像素阵列300对应地经历N次重置阶段与N次采样阶段，以避免N个时间段的N个混合感测结果互相干扰，也就是像素单元200在对应地输出N个混合感测结果之间都会重置电容单元106。
A XY所构成的矩阵可表示为
Figure PCTCN2021098080-appb-000001
若像素单元200的光电二极管202_1至光电二极管202_N在整个感测时间段T为顺向的方式耦接于预设电压V1及运算放大器104的所述负端之间，则光电二极管202_1至光电二极管202_N能对应地贡献PD 1至PD N的量至 混合感测结果VPO。若像素单元200的光电二极管202_1至光电二极管202_N在整个感测时间段T为逆向的方式耦接于预设电压V1及运算放大器104的所述负端之间，则光电二极管202_1至光电二极管202_N能对应地贡献-PD 1至-PD N的量至混合感测结果VPO。
于是可以将第一时间段至第N时间段的对应第一混合感测结果VPO 1至第N混合感测结果VPO N表示为：
Figure PCTCN2021098080-appb-000002
其中在矩阵
Figure PCTCN2021098080-appb-000003
为满秩(full rank)的情况下，可以得到对应的逆矩阵。
所述对应的逆矩阵可以表示为：
Figure PCTCN2021098080-appb-000004
且
Figure PCTCN2021098080-appb-000005
如此一来，
Figure PCTCN2021098080-appb-000006
因此，为了要让运算单元402能够依据第一混合感测结果VPO 1至第N混合感测结果VPO N来还原出PD 1至PD N，矩阵
Figure PCTCN2021098080-appb-000007
需为满秩。除此之外，为了尽量利用到所有的感测信息，矩阵
Figure PCTCN2021098080-appb-000008
中所有元素A XY皆不为零，也就是说，在编码时采取顺向或逆向配置，而不要关闭光电二极管，否则会降低感光效能。换句话说，使所有元素A XY为1或-1，避免为0。在有些实施例中，可以增加增益的变化，例如使所有元素A XY为1、-1、2或-2，以增加运用的弹性。又，为了尽量利用到所有的感测信息，在编码时要考虑使对应的逆矩阵中所有元素A XY'也避免为0。
由于N＝2时，无法在限制A XY为1或-1的情况下得到满秩矩阵。又当N＝3时，虽然可以在限制A XY为1或-1的情况下得到满秩矩阵，但对应的逆矩阵中有部分元素为0。因此最小能满足上述所有条件的方案为N＝4。N＝4时，矩阵
Figure PCTCN2021098080-appb-000009
逆矩阵
Figure PCTCN2021098080-appb-000010
虽然本申请并没有限制N的大小，只要符合条件即可，但应注意的是，若N过大可能会造成运算单元402的复杂度提高。
本申请的设计可以在不降低信噪比的情况下，提升填充系数，特别是针对以薄膜半导体结构实现的像素单元。且由于将感测时间段T平均切为N个时间段，以上述N＝4的矩阵配置来看，平均的混合感测结果VPO是原本(例如图1的实施例)的1/2，因此电容单元106可减小为1/2，或是不改变电容单元106的大小，则动态范围可以提高一倍。本申请还可以降低某些态样的噪声，例如基于时间的噪声(特别是低频噪声)和基于空间的噪声。
本申请还提出图5的像素单元500来进一步改善晶体管108的漏电流问题。像素单元500相较于像素单元200增加了漏电抑制单元202，可进一步在所述采样阶段降低晶体管108和晶体管204所在的路径的整体漏电。漏电抑制单元202包含晶体管204和晶体管206。晶体管204串接晶体管108，串接的晶体管108和晶体管204并联于电容单元106，且耦接于运算放大器104的所述输出端与所述负端之间。
在所述重置阶段，晶体管206通过控制信号S3断开，串接的晶体管108和晶体管204通过控制信号S1和S2导通以重置电容单元106两端在所述采样阶段形成的电压差。在所述采样阶段，串接的晶体管108和晶体管204皆不导通，漏电抑制单元202的晶体管206导通，使晶体管204的一端可通过晶体管206耦接至运算放大器104的所述正端。晶体管204的另一端则耦接至运算放大器104的所述负端，因此晶体管204的两端的电压差在所述采样阶段被箝制在0，可降低通过晶体管204两端的漏电流。由于晶体管204串接晶体管108，利用晶体管204做漏电流的把关，在晶体管108漏电流发生率不变的情况下，可以大幅降低晶体管108实际造成的漏电流。也就是使晶体管108和晶体管204的路径上的整体漏电流大幅降低，降低光电二极管102的光电流受到晶体管108的漏电流的干扰程度，因此像素单元500的信噪比会优于像素单元200。像素单元200和像素单元500中，并没有特别限制所有晶体管的极性，即没有限制各晶体管为P型或N型，也没有强调各晶体管的体的连接方式。
本申请还提供了一种指纹检测芯片，包括所述图像传感器，所述图像传感器可包含像素阵列300，可包含像素单元100/200/400/500。采用本申请实施例中的指纹检测芯片，能够提升填充系数或提高动态范围，并且降低某些态样的噪声，进一步能够提升指纹检测的性能。本申请还提供了一种电子装置，其包括所述指纹检测芯片，可选的，所述指纹检测芯片可以设置在所述电子装置的显示屏的下方，以实现屏下指纹检测，在某些实施例中，所述指纹检测芯片可以设置于所述显示屏的内部，即将所述指纹检测芯片集成于所述显示屏的内部，以 实现屏内指纹检测。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本揭示内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本揭示内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本揭示内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本揭示内容之精神与范围。

Claims (18)

  1. 一种像素阵列，其特征在于，包括：
    运算放大器，具有正端、负端与输出端；
    N个光电二极管，包含第1至第N个光电二极管，其中N大于1，所述N个光电二极管位于所述像素阵列的同一行，各光电二极管选择性地以顺向或逆向的方式耦接于预设电压及所述运算放大器的所述负端之间，其中当所述各光电二极管以顺向的方式耦接于所述预设电压及所述运算放大器的所述负端之间时，所述各光电二极管的阳极耦接至所述预设电压，所述各光电二极管的阴极耦接至所述运算放大器的所述负端，当所述各光电二极管以逆向的方式耦接于所述预设电压及所述运算放大器的所述负端之间时，所述各光电二极管的阳极耦接至所述运算放大器的所述负端，所述各光电二极管的阴极耦接至所述预设电压；
    电容单元，耦接于所述运算放大器的所述输出端与所述负端之间，其中在采样阶段，所述多个光电二极管产生的光电流使所述电容单元两端形成电压差，在重置阶段所述电容单元两端的电压差被重置为零；以及
    第一晶体管，耦接于所述运算放大器的所述输出端与所述负端之间，其中在所述采样阶段，所述第一晶体管断开，在所述重置阶段，所述第一晶体管导通；
    其中所述N个光电二极管共享所述运算放大器、所述电容单元及所述第一晶体管。
  2. 如权利要求1所述的像素阵列，其特征在于，在第X时间段，所述第Y个光电二极管的耦接方式为A XY，其中X及Y皆为1至N的整数，A XY为1代表在第X时间段所述第Y个光电二极管的耦接方式为顺向，A XY为-1代表在第X时间段所述第Y个光电二极管的耦接方式为逆向，A XY为0代表在第X时间段所述第Y个光电二极管不耦接于所述预设电压及所述运算放大器的所述负端之 间，且A XY所构成的矩阵
    Figure PCTCN2021098080-appb-100001
    为满秩。
  3. 如权利要求2所述的像素阵列，其特征在于，在所述第一时间段至所述第N时间段，所述像素阵列对应地经历N次所述重置阶段与N次所述采样阶段，并对应地输出N个所述混合感测结果。
  4. 如权利要求2所述的像素阵列，其特征在于，A XY皆不为零，其中X及Y皆为1至N的整数。
  5. 如权利要求2所述的像素阵列，其特征在于，所述矩阵的逆矩阵的元素皆不为零。
  6. 如权利要求2所述的像素阵列，其特征在于，N为4。
  7. 如权利要求1所述的像素阵列，其特征在于，所述N个光电二极管中：
    各光电二极管的阳极通过第一开关选择性地耦接至所述运算放大器的所述负端，以及各光电二极管的阴极通过第四开关选择性地耦接至所述预设电压；或
    各光电二极管的阳极通过第二开关选择性地耦接至所述预设电压，以及各光电二极管的阴极通过第三开关选择性地耦接至所述运算放大器的所述负端。
  8. 如权利要求1所述的像素阵列，其特征在于，所述运算放大器的所述正端耦接至所述预设电压。
  9. 如权利要求1所述的像素阵列，其特征在于，所述N个光电二极管位于所述像素阵列的同一行的连续N列。
  10. 如权利要求1所述的像素阵列，其特征在于，所述像素阵列还包括：
    源跟随晶体管，耦接至所述运算放大器的所述输出端，用来在所述采样阶段依据所述运算放大器的所述输出端的输出产生混 合感测结果；以及
    行选择晶体管，耦接于所述源跟随晶体管，用来输出所述混合感测结果；
    其中所述N个光电二极管还共享所述源跟随晶体管及所述行选择晶体管。
  11. 如权利要求1所述的像素阵列，其特征在于，所述像素阵列还包括：
    漏电抑制单元，包含：
    第二晶体管，串接所述第一晶体管，且串接的所述第一晶体管和所述第二晶体管耦接于所述运算放大器的所述输出端与所述负端之间，其中在重置阶段，串接的所述第一晶体管和所述第二晶体管导通以重置所述电容单元两端在所述采样阶段形成的电压差；在所述采样阶段，串接的所述第一晶体管和所述第二晶体管不导通，所述第二晶体管的一端耦接至所述运算放大器的所述负端，所述第二晶体管的另一端耦接至所述运算放大器的所述正端，使所述第二晶体管的跨压为零。
  12. 如权利要求11所述的像素阵列，其特征在于，所述漏电抑制单元还包括第三晶体管，所述第三晶体管在所述采样阶段导通，且所述第二晶体管的所述另一端在所述采样阶段通过所述第三晶体管耦接至所述运算放大器的所述正端。
  13. 如权利要求12所述的像素阵列，其特征在于，所述第三晶体管在所述重置阶段不导通，且所述第二晶体管的所述另一端在所述重置阶段和所述运算放大器的所述正端断开。
  14. 如权利要求1至13中任一项所述的像素阵列，其特征在于，所述像素阵列为薄膜半导体结构。
  15. 一种图像传感器，其特征在于，包括：
    如权利要求1至14中任一项所述的像素阵列；以及
    运算单元，用来依据N个所述混合感测结果计算所述N个光电二 极管的非混合感测结果。
  16. 如权利要求15所述的图像传感器，其特征在于，所述运算单元为互补金属氧化物半导体结构。
  17. 一种指纹检测芯片，其特征在于，包括：
    如权利要求16所述的图像传感器。
  18. 一种电子装置，其特征在于，包括：
    如权利要求17所述的指纹检测芯片。
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