WO2022242081A1 - 显示面板及制备方法、显示装置 - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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- H—ELECTRICITY
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- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Definitions
- the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method, and a display device.
- a display panel in a first aspect, includes: a base substrate, an active pattern layer, and a first conductive layer.
- the active pattern layer is disposed on the base substrate, and the active pattern layer includes: at least one first conductive connection line.
- the first conductive layer is disposed on the side of the active pattern layer away from the base substrate, and the first conductive layer includes: at least one connection line extending along a first direction; and arranged along the first direction and A plurality of initialization signal lines extending along a second direction, one end of each initialization signal line is coupled to a connection line, wherein the first direction crosses the second direction.
- One first conductive connection line is coupled to at least two initialization signal lines, wherein the at least two initialization signal lines are coupled to the same connection line.
- the display panel has through holes.
- the plurality of initialization signal lines include a plurality of first initialization signal lines, and the other end of each first initialization signal line extends to the through hole.
- One first conductorized connection line is coupled to at least two first initialization signal lines, wherein the at least two first initialization signal lines are coupled to the same connection line.
- the first conductive layer includes: two connecting wires disposed opposite to each other.
- the plurality of initialization signal lines further include a plurality of second initialization signal lines arranged along the first direction and extending along the second direction, wherein each of the two ends of the second initialization signal line is connected to a connection line coupling.
- Each first conductive connection line is also coupled to at least one second initialization signal line.
- the display panel further includes at least one first connection pattern disposed on a side of the first conductive layer away from the base substrate.
- One first conductive connection line is coupled to one initialization signal line through a first connection pattern.
- the display panel further includes a second conductive layer disposed between the base substrate and the active pattern layer; the second conductive layer includes At least one conductive line extending in the direction. One conductive line and one initialization signal line are coupled through at least two coupling points.
- the third direction is parallel to the second direction.
- the active pattern layer further includes a plurality of active layers.
- the second conductive layer also includes a plurality of light-shielding patterns. Wherein, the orthographic projection of an active layer on the base substrate is located within the orthographic projection of a light-shielding pattern on the base substrate.
- the display panel further includes: a third connection pattern disposed on a side of the first conductive layer away from the base substrate, the third connection pattern is configured to connect each first Initialize the signal line coupling.
- a display device in a second aspect, includes the display panel described in any one of the above embodiments.
- a method for manufacturing a display panel including: forming an active pattern layer on a base substrate, and the active pattern layer includes: at least one first conductive connection line; A first conductive layer is formed on a side away from the base substrate, and the first conductive layer includes: at least one connection line extending along a first direction, and multiple wires arranged along the first direction and extending along a second direction.
- One initialization signal line, one end of each initialization signal line is coupled to one connection line; wherein, the first direction crosses the second direction; one first conductive connection line is connected to at least two initialization signal lines coupling, wherein the at least two initialization signal lines are coupled to the same connection line.
- FIG. 2A is a structural diagram of a display panel provided by some embodiments of the present disclosure.
- Figure 3C is a sectional view taken along the line A-A' in Figure 3B;
- FIG. 4A is an equivalent circuit diagram of a pixel driving circuit in the related art
- FIG. 4B is a top view of another display panel provided by some embodiments of the present disclosure.
- FIG. 5A is a structural diagram of a pattern layer of the display panel in FIG. 4B;
- FIG. 5C is a structural diagram of three pattern layers of the display panel in FIG. 4B;
- FIG. 5D is a structural diagram of four pattern layers of the display panel in FIG. 4B;
- FIG. 6 is a top view of another display panel provided by some embodiments of the present disclosure.
- Fig. 7 is a top view of another display panel provided by some embodiments of the present disclosure.
- Fig. 8 is a sectional view taken along the line B-B' in the display panel shown in Fig. 7;
- FIG. 9 is a structural diagram of another display panel provided by some embodiments of the present disclosure.
- Fig. 10 is a top view of another display panel provided by some embodiments of the present disclosure.
- Fig. 11 is a top view of another display panel provided by some embodiments of the present disclosure.
- FIG. 12 is a flow chart of a method for manufacturing a display panel provided by some embodiments of the present disclosure.
- Fig. 13 is a process flow chart of another method of manufacturing a display panel provided by some embodiments of the present disclosure.
- FIG. 14 is a process flow diagram of another method for manufacturing a display panel provided by some embodiments of the present disclosure.
- the expressions “coupled” and “connected” and their derivatives may be used.
- the term “connected” may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other.
- the term “coupled” may be used when describing some embodiments to indicate that two or more elements are in direct physical or electrical contact.
- the terms “coupled” or “communicatively coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
- the embodiments disclosed herein are not necessarily limited by the context herein.
- At least one of A, B and C has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, A and B A combination of A and C, a combination of B and C, and a combination of A, B and C.
- a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
- Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
- the thickness of layers and regions are exaggerated for clarity. Accordingly, variations in shape from the drawings as a result, for example, of manufacturing techniques and/or tolerances are contemplated.
- example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have curved features.
- the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
- “Setting multiple patterns on the same layer” means that multiple patterns belong to the same pattern layer, that is, multiple patterns are formed through the same patterning process, wherein the patterning process refers to a process that can simultaneously form multiple patterns on a carrier surface.
- multiple patterns are organic materials, and the patterning process can be evaporation or printing.
- the patterning process may include: first forming a thin film using a film forming process, and then patterning the thin film to form a pattern layer containing multiple patterns; wherein, the patterning process may include: Coating photoresist, exposure, development, etching and other processes.
- the multiple patterns may be at least partially connected, or may be spaced apart from each other.
- multiple patterns may have different thicknesses (heights, so to speak).
- multiple layers shown in the drawings in this embodiment may all be pattern layers, for example, an active pattern layer, a first conductive layer, a second conductive layer, and the like.
- Some display panels such as OLED display panels, include a pixel driving circuit and an initialization signal line, and the initialization signal line is configured to transmit an initialization signal to the pixel driving circuit, wherein, referring to FIG. One side aa of the panel extends to the opposite side bb.
- the initialization signal line transmits the initialization signal to the pixel driving circuit coupled to it, due to the voltage drop on the initialization signal line, the transmitted signal gradually attenuates during the transmission process, resulting in the final transmission to the pixel driving circuit. The signal in the circuit is inaccurate, resulting in uneven brightness of the display screen.
- the edges of the physical holes in the display screen are shown by circles, and the initialization signal lines a, b, and c are the above-mentioned initialization signal lines that generate interrupts in AA; in addition, the display screen also includes several lines in AA. Continuous initialization signal lines, such as initialization signal lines d and e in FIG. 1B .
- the initialization signal lines a, b, and c are disconnected at the position of the physical hole, and one end of the disconnected initialization signal line extending to the physical hole cannot be connected to the connection line CL on the opposite sides of the display screen, the above-mentioned in AA
- the voltage drop on the initialization signal line that generates the interrupt is larger than the voltage drop on the continuous initialization signal line in AA.
- the large voltage drop on the initialization signal line causes the initialization signal transmitted by the initialization signal line to attenuate. After the attenuated initialization signal is written into the corresponding pixel driving circuit, the charging rate of the pixel driving circuit is reduced.
- the charging rate of each pixel driving circuit gradually decreases, and then it will appear as a horizontal bar with gradual brightness on a macroscopic level, that is, horizontal display unevenness.
- a display device refers to a product with an image display function. Exemplarily, it can be: a monitor, a TV, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a personal digital assistant (Personal Digital Assistant, PDA), Digital cameras, portable camcorders, viewfinders, monitors, navigators, vehicles, large-area walls, home appliances, information query equipment (such as business query equipment for e-government, banks, hospitals, electric power and other departments, monitors, etc.
- PDA Personal Digital Assistant
- the display device usually includes a display panel.
- the display panel may be an OLED (Organic Light Emitting Diode, organic light emitting diode) display panel, a QLED (Quantum Dot Light Emitting Diodes, quantum dot light emitting diode) display panel, a micro LED (including: miniLED or microLED) display panels, etc.
- the display device may further include other components, for example, a power system for supplying power to the display panel, a circuit board connected to the display panel, and the like.
- FIG. 2A shows a top view of a display panel provided by some embodiments of the present disclosure.
- the display panel 10 has a display area AA and a peripheral area SS located on at least one side of the display area AA. It is shown in FIG. 2A that the peripheral area SS is arranged around the display area AA, but it is not limited thereto. One side of display area AA.
- the display panel 10 further includes a plurality of sub-pixels P disposed in the display area AA. Exemplarily, the plurality of sub-pixels P may be arranged in an array as shown in FIG. 2A to form a plurality of sub-pixel rows and a plurality of sub-pixel columns. Of course, the number and arrangement of the sub-pixels P are not limited to those shown in the figure, and can be designed according to requirements.
- FIG. 2B shows a display panel provided by some embodiments of the present disclosure.
- the display panel 10 may include a driving backplane 100 and a plurality of light emitting devices 200.
- the driving backplane 100 includes a base substrate 101 and a plurality of pixel driving circuits D disposed on the base substrate 101, each pixel driving circuit D is coupled with a light emitting device 200 to form a sub-pixel P, and the pixel driving circuit D is configured to drive the light emitting device 200 coupled thereto to emit light.
- a plurality of pixel driving circuits D may be arranged in order on the base substrate 101 , for example, a plurality of pixel driving circuits D are distributed in an array on the base substrate 210 .
- the light emitting device 200 is the main structure for the sub-pixel P to realize light emission, and each light emitting device 200 may be a structure in which multiple layers of thin films are stacked.
- the light emitting device 200 includes a cathode 230 and an anode 210 , and a light emitting functional layer 220 located between the cathode 230 and the anode 210 .
- the light-emitting functional layer 220 can include, for example, a light-emitting layer 224, a hole transport layer 222 (Hole Transporting Layer) between the light-emitting layer 224 and the anode 210, an electron transport layer 226 (Election Layer) between the light-emitting layer 224 and the cathode 230.
- a hole injection layer 221 (Hole Injection Layer) can also be set between the hole transport layer 222 and the anode 210, and an electron injection layer can be set between the electron transport layer 226 and the cathode 230.
- Layer 227 (Election Injection Layer).
- an electron blocking layer 223 (Electron Blocking Layer) can also be provided between the hole transport layer 222 and the light emitting layer 224, and a hole blocking layer 225 (Hole Blocking Layer) can also be provided between the electron transport layer 226 and the light emitting layer 224 .
- FIG. 3A is a top view of the driving backplane 100 of the display panel provided by some embodiments of the present disclosure.
- Drive backplane 100 may include multiple layers, each layer in drive backplane 100 is shown in a different fill pattern in FIG. 3A .
- the driving backplane 100 includes an active pattern layer 110 and a first conductive layer 120 .
- the active pattern layer 110 is disposed on the base substrate 101
- the first conductive layer 120 is disposed on a side of the active pattern layer 110 away from the base substrate 120 .
- an insulating layer (called a first insulating layer) may be first formed on the side of the active pattern layer 110 away from the base substrate, and then, An insulating layer forms the first conductive layer 120 on a side away from the active pattern layer 110 , so that the active pattern layer 110 and the first conductive layer 120 can be separated by the first insulating layer.
- the active pattern layer 110 of the driving backplane 100 includes: at least one first conductive connection line 111 .
- Conductorization refers to a process in which the conductivity of an object with poor conductivity is enhanced after a certain treatment. Among them, poor conductivity is a relative concept. For example, the conductivity of insulators is poor compared to semiconductors or conductors, and the conductivity of semiconductors is poor compared to conductors.
- the conductorization may be a doping process, for example, the first conductorization connection line 111 in the driving backplane 100 may be obtained by doping a semiconductor connection line, wherein the material forming the semiconductor connection line may be polysilicon.
- the number of first conductive connection lines 111 in the active pattern layer 110 may be one or more.
- the active pattern layer 110 includes a plurality of first conductive connection lines 111, and may also include other conductive patterns Or a semiconductor pattern, wherein the semiconductor pattern can be used to form a gate of a transistor, and the conductorized pattern can be used to form a source or a drain of a transistor.
- Embodiments of the present disclosure do not limit the shape of the first conductive connection line 111 , which can be designed according to needs.
- the first conductive connection line 111 may be straight, wavy, or zigzag.
- the first conductive connecting line 111 may include a plurality of periodic repeating line segments, and the extension direction of the connecting line of each repeated line segment at the same position can be used as the extending direction of the first conductive connecting line 111 .
- the extension directions of the multiple first conductive connecting lines 111 may be approximately parallel, for example, the angle between the extending directions of any two first conductive connecting lines 111 is not more than 5°.
- the extending direction of these first conductorized connecting lines 111 can be designed according to requirements.
- the first conductive layer 120 of the drive backplane 100 includes: at least one connection line 121 extending along the first direction Y, and a plurality of initialization signal lines arranged along the first direction Y and extending along the second direction X Vint, one end of each initialization signal line Vint is coupled to a connection line 121 ; wherein, the first direction Y crosses the second direction X.
- the first direction Y is a horizontal direction
- the second direction X is a vertical direction
- the angle between the first direction Y and the second direction X is a right angle
- the embodiments of the present disclosure do not limit the specific directions of the first direction Y and the second direction X, for example, the angle formed by the intersection of the first direction Y and the second direction X may be an acute angle or an obtuse angle.
- the initialization signal line is configured in the display panel to transmit an initialization signal, and the initialization signal may come from an IC of the display device.
- each connection line 121 may be located in the peripheral area SS of the display panel 10, and at least one connection line 121 is coupled to a signal providing circuit (eg, IC) of the display device.
- a signal providing circuit eg, IC
- the display panel includes only one connection line, such as 121a or 121b in FIG.
- connection line 121a can receive the initialization signal provided by the IC; of course, only the connection line 121b can receive the initialization signal provided by the IC, or the connection lines 121a and 121b can respectively receive the initialization signal from the IC.
- the first conductive layer 120 includes only one connection line 121, all initialization signal lines Vint in the display panel are coupled to this connection line; in the case that the first conductive layer 120 includes a plurality of connection lines 121, The initialization signal line Vint may be coupled to at least one connection line 121 of the plurality of connection lines 121 .
- one initialization signal line Vint is only coupled to one connection line 121, for example, the display panel includes two connection lines 121a and 121b, and one initialization signal line Vint may only be coupled to connection line 121a, or only to be connected to line 121b, then the display panel may include a plurality of initialization signal lines coupled only to the connection line 121a and a plurality of initialization signal lines coupled only to the connection line 121b; It is coupled to two connection lines 121 at the same time.
- one end of an initialization signal line Vint is coupled to the connection line 121a, and the other end is coupled to the connection line 121b.
- the initialization signal line coupled to only one connection line is called a first initialization signal line
- the initialization signal line whose two ends are respectively coupled to a connection line is called a second initialization signal line.
- One connection line 121 can transmit the initialization signal to the sub-pixels P (the sub-pixels P are shown in FIG. 2A ) coupled with the initialization signal lines Vint in the display panel 10 through the initialization signal lines Vint coupled thereto.
- one initialization signal line Vint may be coupled to multiple sub-pixels P, for example, the multiple sub-pixels P coupled to one initialization signal line Vint may be sub-pixels in the same row.
- Each sub-pixel P is coupled to the initialization signal line Vint through one or more nodes in the pixel driving circuit D, so as to initialize the voltage of the one or more nodes in the pixel driving circuit.
- One first conductive connection line is coupled to at least two initialization signal lines Vint, wherein at least two initialization signal lines Vint are coupled to the same connection line 121 .
- one first conductive connection line 111 is coupled to two initialization signal lines Vint, for example, the first conductive connection line 111 in FIG. 3A is coupled to initialization signal lines Vint(a) and Vint(b) simultaneously. catch.
- the initialization signal line Vint(a) and the initialization signal line Vint(a) are coupled together through the first conductive connection line 111, the initialization signal line Vint(a) and the initialization signal line Vint(b) are connected in parallel to form
- the equivalent resistance of is smaller than the resistance of any one of the initialization signal line Vint(a) and the initialization signal line Vint(b), so that the voltage drop on each initialization signal line (Vint(a), Vint(b)) is relatively When it is not connected in parallel, the signal loss on the first initialization signal line (Vint(a), Vint(b)) can also be reduced accordingly.
- the difference in the initialization signals received by the sub-pixels P coupled to the initialization signal line decreases, for example, the pixel driving circuits coupled to the initialization signal line
- the received initialization signals (initial voltages) are almost equal, then, the voltage of the corresponding node in each pixel driving circuit reaches the preset voltage value after initialization, or only has a small deviation from the preset voltage value, so , the charging rate of each pixel driving circuit is almost the same, so that the brightness difference of each sub-pixel light emission is reduced.
- At least one first conductive connection line 111 is arranged on the active pattern layer 110, and one first conductive connection line 111 is coupled with at least two initialization signal lines Vint, so that all The at least two initialization signal lines Vint are connected in parallel, and the equivalent resistance after the parallel connection of the initialization signal lines Vint is smaller than the resistance of each initialization signal line Vint, so that the voltage drop on each initialization signal line Vint can be reduced reduce.
- the attenuation of the initialization signal transmitted through the initialization signal line Vint will also be reduced, so that the initialization signal written to each sub-pixel is more accurate, thereby improving the display unevenness of the display panel. Improve the display quality of the display device.
- FIG. 3B is a top view of another driving backplane 100 of a display panel provided by some embodiments of the present disclosure.
- the driving backplane 100 includes a through hole H.
- the through hole H is a hole penetrating through opposite sides of the driving backplane 100 in the thickness direction, and the size and position of the hole can be designed as required.
- the number of through holes in the driving backplane 100 may be multiple, and when the driving backplane 100 includes a plurality of through holes H, the position and arrangement of each through hole may be designed according to actual conditions.
- the embodiments of the present disclosure are described by taking the driving backplane including a through hole H as an example.
- the first conductive layer 120 of the drive backplane 100 includes: at least one connection line 121 extending along the first direction Y, and a plurality of first initialization wires 121 arranged along the first direction Y and extending along the second direction X.
- Signal lines 122 wherein the first initialization signal line 122 is a kind of initialization signal line Vint, one end of each first initialization signal line 122 is coupled to a connection line 121, and the other end extends to the through hole H, wherein the first One direction Y intersects the second direction X.
- the first conductive layer 120 includes a plurality of connecting wires 121 extending along the first direction Y.
- the connection lines 121 a and 121 b are respectively disposed in the peripheral area SS on opposite sides of the display panel 10 .
- the first conductive layer 120 further includes a plurality of first initialization signal lines 122 arranged along the first direction Y and extending along the second direction X.
- the first initialization signal line 122 may be a broken line caused by the through hole H, so the number of broken lines depends on the size of the through hole H. Referring to FIG.
- each row of sub-pixels in the display panel is connected to the initialization signal lines extending in the X direction, the distance between the initialization signal lines extending in the X direction is not the same as the size of a sub-pixel in the Y direction (or the extension in the X direction).
- the width of a row of sub-pixels) is roughly the same.
- first initialization signal lines 122 a , 122 b , 122 c and 122 d included in the first conductive layer 120 are connected to the same connection line 121a, and are arranged at intervals along the first direction Y.
- the first initialization signal lines 122c and 122c are connected to the same connection line 121b and arranged at intervals along the first direction Y.
- the distance between two adjacent first initialization signal lines 122 may be equal or different.
- each first initialization signal line 122 is coupled to a connection line 121, and the other end extends to the through hole H.
- a connection line 121 For example, referring to FIG. 3B, one end of the first initialization signal line 122a (or 122b) can be connected to the left One connection line 121a is coupled, and the other end extends to the through hole H.
- One end of the first initialization signal line 122c (or 122d ) may be coupled to a connecting line 121b located on the right side, and the other end extends to the through hole H. As shown in FIG.
- One first conductive connection line 111 is coupled to at least two first initialization signal lines 122 , wherein the at least two first initialization signal lines 122 are coupled to the same connection line 121 .
- the equivalent resistance formed by the two first initialization signal lines 122 coupled by a first conductive connection line 111 is smaller than the resistance of any one of the two first initialization signal lines 122, so that the two first initialization signal lines 122 The voltage drops on the initialization signal lines 122 are all reduced, which is beneficial to ensure the accuracy of the respective transmitted signals.
- the charging rate of the pixel driving circuit of the sub-pixel closest to the connection line is the highest, and the pixel drive circuit of the closest to the through hole H The charging rate of the pixel driving circuit of the sub-pixel is the lowest.
- the brightness of the sub-pixel closest to the connection line is the brightest
- the brightness of the sub-pixel closest to the through hole is the darkest
- the brightness of the middle sub-pixel is in between. between.
- the brightness of each sub-pixel is closer to the brightest sub-pixel, so that the brightness difference between the brightest sub-pixel and the darkest sub-pixel is reduced, and the display device For example, the brightness gradient from one side of the display device to the physical aperture becomes less noticeable.
- the active pattern layer 110 includes a plurality of first conductive connection lines 111 , and each first conductive connection line 111 is coupled to at least two initialization signal lines Vint.
- Embodiments of the present disclosure do not limit the arrangement of the first conductive connection lines 111 , which can be designed according to needs. For example, referring to FIG. 3A and FIG. 3B , the multiple first conductive connection lines 111 can be arranged in parallel.
- the first initialization signal lines 122a, 122b are coupled through a plurality of first conductive connection lines 111 located between the connection line 121a and the through hole H , wherein, the first initialization signal line 122a and the first initialization signal line 122b between every two adjacent first conductorized connection lines 111 can be regarded as a parallel relationship, for example, every two adjacent first conductorized connection lines 111
- the resistors formed by the parallel connection between a part of the first initialization signal line 122 a and a part of the first initialization signal line 122 b between the connection lines 111 are R1 , R2 , and R3 shown in dashed boxes in FIG.
- R1, R2, and R3 are in parallel relationship with each other.
- the first initialization signal line 122a and the first initialization signal line 122b between the connection line 121a and the through hole H are connected in parallel multiple times, and their equivalent resistance is further reduced compared with only one parallel connection, so that each first initialization signal line
- the voltage drop on the signal lines 122a, 122b is lower than when only one first conductorized connection line 111 is used to couple, then, the initialization signal written to the pixel driving circuit through the first initialization signal line 122a, 122b also becomes be more accurate.
- the first conductive layer 120 includes two connecting wires 121a and 121b oppositely arranged; the first conductive layer 120 further includes: multiple wires arranged along the first direction Y and extending along the second direction X Two second initialization signal lines 123 , wherein the second initialization signal line 123 is a kind of initialization signal line Vint, and two ends of each second initialization signal line 123 are respectively coupled to one connection line 121 .
- the voltage drop on the second initialization signal line 123 is extremely small or almost zero.
- a plurality of second initialization signal lines 123 may be arranged on both sides of the first initialization signal line 122 at certain intervals, for example, the second initialization signal lines 123 in FIG. 3B are located on the upper and lower sides of the through hole,
- each second initialization signal line 123 is arranged equidistantly, and at the same time, the distance between one second initialization signal line 123 and one first initialization signal line 122 is also equal.
- Each first conductive connection line 111 is also coupled to at least one second initialization signal line 123 .
- each first conductorized connection line 111 is coupled to at least two first initialization signal lines 122 and is also coupled to one second initialization signal line 123 . Since the voltage drop on the second initialization signal line is extremely small or almost zero, when at least two first initialization signal lines 122 are coupled to one second initialization signal line 123, the at least two first initialization signal lines 122 It is connected in parallel with a second initialization signal line 123. After parallel connection, the voltage drop on each first initialization signal line 122 is smaller than the voltage drop on the second initialization signal line 123, so that the voltage drop on the first initialization signal line 122 can be reduced. Greatly reduced.
- each first conductorized connection line 111 may also be coupled to a plurality of second initialization signal lines 123 while being coupled to at least two first initialization signal lines 122, and the coupled second initialization signal lines The more the number 123 is, the more the number of second initialization signal lines 123 connected in parallel to each first initialization signal line 122 is, and the smaller the voltage drop on each first initialization signal line 122 after parallel connection is.
- each first conductive connection line 111 is coupled to each second initialization signal line 123 in the drive backplane, in this case, the voltage drop on each second initialization signal line 123 can be minimized
- a first conductorized connection line 111 is only coupled to several second initialization signal lines 123 in the drive backplane, that is, the second initialization signal line to which the at least one first conductorized connection line 111 is coupled The number of 123 is less than the total number of the second initialization signal lines 123 in the driving backplane.
- the active pattern layer 110 further includes: at least one second conductive connection line 112 , and each second conductive connection line 112 is coupled to at least two second initialization signal lines 123 .
- each second conductive connection line 112 is coupled to at least two second initialization signal lines 123 .
- the at least two second initialization signal lines 123 can be connected in parallel.
- the at least two second initialization signal lines 123 can be connected in parallel multiple times, thereby further reducing the voltage drop on each second initialization signal line 123.
- the principle is It is the same as when at least two first initialization signal lines 122 are connected in parallel, so details are not repeated here.
- Some embodiments of the present disclosure provide a driving backplane 100, and the driving backplane 100 is provided with a plurality of pixel driving circuits.
- the pixel driving circuit is composed of thin film transistors (Thin Film Transistor, TFT for short), capacitors (Capacitance, C for short) and other electronic devices.
- the pixel driving circuit may include two thin film transistors (a switching transistor and a driving transistor) and a capacitor to form a 2T1C structure; of course, the pixel driving circuit may also include more than two thin film transistors (a plurality of switching transistors and a driving transistor) transistor) and at least one capacitor, for example, the pixel driving circuit may include one capacitor and seven transistors to form a 7T1C structure.
- the structure of the pixel driving circuit will be described below by taking a pixel driving circuit with a 7T1C structure as an example.
- FIG. 4A shows an equivalent circuit diagram of a pixel driving circuit with a 7T1C structure.
- the pixel driving circuit includes: a capacitor Cst, a plurality of switch transistors (T1, T2, T4, T5, T6, T7) and a driving transistor T3.
- Vint, Re, G, EM, Vdata, VDD respectively represent the signal lines coupled to the corresponding transistors, for example, Vint represents the initialization signal line, Re represents the first reset signal line, and Re' represents the second Reset signal line, G stands for scan control signal line, EM stands for light emission control signal line, Vdata stands for data signal line, VDD stands for power signal line, and the signal transmitted by Re' is the same as the signal transmitted by G.
- the control electrodes (gates) of a part of switching transistors are coupled to the reset signal line Re for receiving the first reset signal; the control electrodes (gates) of a part of switching transistors (such as T7) pole) is coupled to the reset signal line Re' for receiving the second reset signal.
- the control electrodes of another part of switch transistors (for example, T2 and T4 ) are coupled to the scan control signal line G for receiving the scan control signal.
- the second reset signal is the same as the scan control signal.
- the control electrodes of another part of the switch transistors (for example, T5, T6) are coupled to the light emission control signal line EM for receiving the light emission control signal.
- the transistors T1 and T7 are turned on in response to the reset signal, and the initialization signal (transmitted through the initialization signal line Vint) is transmitted to the control electrode (g) of the driving transistor T3 and the anode of the light-emitting device L through the transistors T1 and T7 respectively, so as to achieve the control of light emission.
- the anode of the device L and the control electrode of the driving transistor T3 are reset.
- the transistors T2 and T4 are turned on, the control electrode g of the drive transistor T3 is coupled to the drain (d), and the drive transistor T3 is in a diode conduction state.
- the data signal (transmitted through the data signal line Vdata) is written into the source (s) of the driving transistor T3 through the transistors T2 and T4, and compensates the threshold voltage of the driving transistor T3.
- the transistor T5 and the transistor T6 are turned on, and the driving current is transmitted to the light emitting device L through the above current path, so as to drive the light emitting device L to emit light.
- one pole (such as the anode) of the light emitting device L receives the driving current from the pixel circuit, and the other pole (such as the cathode) of the light emitting device L is coupled to a fixed voltage terminal; for example, the fixed voltage terminal is configured to transmit DC voltage, such as DC low voltage.
- FIG. 5C also shows the specific structure of the first conductive layer of the driving backplane, where the first conductive layer can form the initialization signal line Vint, for example, the first conductive layer can form the connection line described in the embodiment of the present disclosure, First initialize the signal lines and so on.
- the first conductive layer can also form the second plate Cst2 of the capacitor Cst.
- FIG. 5D also shows the specific structure of the third conductive layer of the driving backplane, where the third conductive layer can form the source and drain of the transistor.
- the third conductive layer can also form a power signal line VDD and a data signal line Vdata.
- the first connection pattern 141 can be completed through a patterning process using a mask plate for making other patterns in the third conductive layer 140, compared to punching holes on the first insulating layer 103 after forming the first insulating layer 103 , and then form the first initialization signal line 122 in the first conductive layer 120, so that the first conductive connection line 111 in the active pattern layer 110 and the first initialization signal line 122 in the first conductive layer 120 pass through the first
- the via coupling in the insulating layer 103 can save a mask plate, thereby increasing the manufacturing cost of the driving backplane.
- the coupling point where a first connection pattern 141 is coupled to a second initialization signal line 123 is located at the intersection of a first conductive connection line 111 and a second initialization signal line 123 coupled through the first connection pattern 141 position, its beneficial effect is the same as that of the above-mentioned first initialization signal line 122, and will not be repeated here.
- the first conductive connection line 111 extends along the first direction Y and is straight.
- the straight first conductorized connection line 111 has a simple shape and is easy to manufacture, which is beneficial to improve the yield rate in the production process of the driving backplane.
- the driving backplane further includes a second conductive layer disposed between the base substrate and the active pattern layer.
- the second conductive layer includes: at least one conductive line extending along the third direction, one conductive line and one initialization signal line are coupled through at least two coupling points.
- one conductive line 131 is coupled to one second initialization signal line 123 through at least two coupling points.
- first initialization signal line 122 For its coupling method, refer to the above-mentioned first initialization signal line 122 , which will not be repeated here.
- the third direction is parallel to the second direction X.
- the conductive lines 131 in the driving backplane 100 may be parallel to the first initialization signal lines 122 or the second initialization signal lines 123 .
- the second connection pattern 142 may be located on the same layer as the first connection pattern 141 , for example, the second connection pattern 142 is located on the third conductive layer 140 .
- the buffer layer 105 may be formed on the side of the second conductive layer 130 away from the base substrate 101 , and then the buffer layer 105 is away from the base substrate 101
- the active pattern layer 110, the first conductive layer 120 and the like are formed on one side.
- a third via hole V3 can also be formed, wherein the third via hole V3 penetrates the second insulating layer 104, the first insulating layer 103 and the buffer.
- a conductive line 131 is coupled to a second initialization signal line 123 through a second connection pattern 142 , and the coupling method thereof is referred to the first initialization signal line 122 , which will not be repeated here.
- the second conductive layer 130 includes a plurality of conductive lines 131 , wherein each first initialization signal line 122 and each second initialization signal line 123 is coupled to one conductive line 131 .
- a first conductive signal line 111, a second initialization signal line 123, and a conductive line 131 are coupled through a second connection pattern 142, and the coupling method is similar to that of the above-mentioned first initialization signal line 122, and no longer repeat.
- the active pattern layer 110 further includes a plurality of active layers.
- the plurality of active layers may be a part of the active layers in the active pattern layer 110 , or may be all the active layers in the active pattern layer 110 .
- the active pattern layer 110 includes a plurality of active patterns 112, each active pattern 112 includes a plurality of active layers, for example, in the pixel driving circuit of 7T1C, each active The pattern 112 may include 7 active layers, wherein one of the 7 active layers is the active layer DA of the driving transistor.
- a plurality of active layers in the active pattern layer 110 may include active layers DA of all driving transistors in the active pattern layer 110 .
- the second conductive layer 130 further includes: a plurality of light-shielding patterns 132, wherein the orthographic projection of one active layer (for example, each active layer in a plurality of active layers) on the base substrate 101 is located in one light-shielding pattern 132 Within the orthographic projection on the substrate substrate.
- the orthographic projection of the active layer DA of each driving transistor in the active pattern layer 110 on the base substrate 101 is respectively located within the orthographic projection of a light-shielding pattern 132 on the base substrate.
- the display device usually includes an infrared imaging component, and the infrared imaging component is usually located on one side of the display panel in the thickness direction of the display device, for example, the infrared imaging component is located on the display panel close to the substrate side of the substrate.
- the infrared imaging component When the infrared imaging component is working, the infrared rays emitted by it irradiate the display panel, causing the transistor in the driving backplane of the display panel to have a transistor characteristic shift phenomenon, which in turn leads to defective bright spots of the display panel.
- the light-shielding pattern 132 on the second conductive layer 130 of the driving backplane can play the role of shielding infrared rays, which can prevent infrared rays from continuously irradiating the active layer DA of the driving transistor, and avoid the characteristic shift phenomenon of the driving transistor to a certain extent , thereby improving the display quality of the display panel.
- the driving backplane 100 further includes a power signal line VDD disposed on a side of the first conductive layer 120 away from the base substrate 101 , and the plurality of light-shielding patterns 132 are coupled to the power signal line VDD.
- the power signal line VDD may be located on the same layer as the first connection pattern 141 , for example, the power signal line VDD is located on the third conductive layer 140 .
- the plurality of light-shielding patterns 132 may be coupled to the power signal line VDD by punching holes.
- the light-shielding patterns 132 in the same row in the driving backplane 100 can be connected first, and the connection line between two adjacent light-shielding patterns 132 can be coupled to the power signal line VDD through the fourth via hole V4 .
- the fourth via hole V4 can be formed before forming the third conductive layer 140, and the fourth via hole V4 can penetrate the second insulating layer 104, the first insulating layer 103 and the buffer layer 105 to two adjacent light-shielding patterns. 132 on the connecting line.
- the light-shielding pattern 132 is connected to a stable signal, for example, the light-shielding pattern 132 is connected to the signal provided by the power signal line VDD, which can avoid the substrate bias effect, thereby preventing the substrate bias effect from affecting the driving transistor and causing display issues.
- forming the active pattern layer on the base substrate in the above step A includes: forming at least one semiconductor connection line on the base substrate, and conducting at least one semiconductor connection line to obtain at least one first An active pattern layer for conductive connection lines.
- step S1 may include: S101-S103, wherein,
- a plurality of semiconductor patterns 112s are arranged in an array, and each semiconductor pattern 112s is located in a sub-pixel, and the semiconductor patterns in the same column are connected end to end to form a column of semiconductor patterns 112s, and each semiconductor connection line can 111s is located between two adjacent rows of semiconductor patterns 112s.
- S102 in FIG. 13 is the shape after the photoresist PR partially covers the semiconductor pattern. After doping the semiconductor pattern 112s and the plurality of semiconductor connection lines 111s covered by the photoresist, it can be obtained including at least one first conductor. The active pattern layer of the connection line 111.
- the part corresponding to the channel of the transistor is covered with a photoresist, and the uncovered part is conductorized, wherein the part covered by the photoresist forms the active layer of the transistor, and the photoresist The part not covered by the resist forms the source-drain metal layer of the transistor.
- the active layer of the transistor is first formed on the semiconductor pattern layer, and then the source-drain metal layer of the transistor is formed by doping the part of the semiconductor pattern layer except the active layer of the transistor.
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Abstract
一种显示面板,所述显示面板包括:衬底基板、有源图案层和第一导电层。其中,有源图案层设置于衬底基板上,有源图案层包括:至少一条第一导体化连接线。第一导电层设置在所述有源图案层远离所述衬底基板的一侧,第一导电层包括:沿第一方向延伸的至少一条连接线,和沿第一方向排列且沿第二方向延伸的多条初始化信号线,每条初始化信号线的一端与一条连接线耦接;其中,第一方向与第二方向交叉。一条第一导体化连接线与至少两条初始化信号线耦接,其中,所述至少两条初始化信号线与同一条连接线耦接。
Description
本申请要求于2021年05月21日提交的、申请号为202110557443.0的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本公开涉及显示技术领域,尤其涉及一种显示面板及制备方法、显示装置。
显示面板按照不同的显示原理,可划分成多种类型。例如,有机电致发光二极管(Organic Light-Emitting Diode,简称为OLED)显示面板可以包括多个包含有机发光材料的OLED器件,其中,有机发光材料能够在电信号的驱动下发光。通过调节驱动每个OLED器件电信号的大小,可以改变该OLED器件的发光亮度,从而使得OLED显示面板能够显示图像。
发明内容
第一方面,提供一种显示面板,所述显示面板包括:衬底基板、有源图案层和第一导电层。其中,有源图案层设置于所述衬底基板上,所述有源图案层包括:至少一条第一导体化连接线。第一导电层设置在所述有源图案层远离所述衬底基板的一侧,所述第一导电层包括:沿第一方向延伸的至少一条连接线;和沿所述第一方向排列且沿第二方向延伸的多条初始化信号线,每条初始化信号线的一端与一条连接线耦接,其中,所述第一方向与所述第二方向交叉。一条第一导体化连接线与至少两条初始化信号线耦接,其中,所述至少两条初始化信号线与同一条所述连接线耦接。
在一些实施例中,所述显示面板具有通孔。所述多条初始化信号线包括多条第一初始化信号线,每条第一初始化信号线的另一端延伸至所述通孔。一条所述第一导体化连接线与至少两条第一初始化信号线耦接,其中,所述至少两条第一初始化信号线与同一条所述连接线耦接。
在一些实施例中,所述第一导电层包括:相对设置的两条连接线。所述多条初始化信号线还包括沿所述第一方向排列且沿所述第二方向延伸的多条第二初始化信号线,其中,每条第二初始化信号线的两端各与一条连接线耦接。每条第一导体化连接线还与至少一条第二初始化信号线耦接。
在一些实施例中,所述有源图案层还包括至少一条第二导体化连接线,每条第二导体化连接线与至少两条第二初始化信号线耦接。
在一些实施例中,所述显示面板还包括设置在所述第一导电层远离所述 衬底基板的一侧的至少一个第一连接图案。一条所述第一导体化连接线与一条初始化信号线通过一个第一连接图案耦接。
在一些实施例中,所述一个第一连接图案与所述一条初始化信号线耦接的耦接点位于通过所述第一连接图案耦接的所述一条第一导体化连接线和所述一条初始化信号线的交叉位置处。
在一些实施例中,所述第一导体化连接线沿所述第一方向延伸,且为直条形。
在一些实施例中,所述显示面板还包括第二导电层,所述第二导电层设置在所述衬底基板与所述有源图案层之间;所述第二导电层包括沿第三方向延伸的至少一条导电线。一条导电线与一条初始化信号线通过至少两个耦接点耦接。
在一些实施例中,所述第三方向和所述第二方向平行。
在一些实施例中,所述显示面板还包括设置在所述第一导电层远离所述衬底基板的一侧的至少一个第二连接图案;其中,所述一条导电线与所述一条初始化信号线通过一个第二连接图案耦接。
在一些实施例中,一条第一导体化信号线、一条初始化信号线和一条导电线通过一个第二连接图案耦接。
在一些实施例中,所述有源图案层还包括多个有源层。所述第二导电层还包括多个遮光图案。其中,一个有源层在所述衬底基板上的正投影位于一个遮光图案在所述衬底基板上的正投影以内。
在一些实施例中,所述显示面板还包括设置在所述第一导电层远离所述衬底基板的一侧的电源信号线;所述多个遮光图案与所述电源信号线耦接。
在一些实施例中,所述显示面板还包括:设置在所述第一导电层远离所述衬底基板的一侧的第三连接图案,所述第三连接图案被配置为将每条第一初始化信号线耦接。
第二方面,提供一种显示装置,所述显示装置包括上述任一实施例所述的显示面板。
第三方面,提供一种显示面板的制备方法,包括:在衬底基板上形成有源图案层,所述有源图案层包括:至少一条第一导体化连接线;在所述有源图案层远离所述衬底基板的一侧形成第一导电层,所述第一导电层包括:沿第一方向延伸的至少一条连接线,和沿所述第一方向排列且沿第二方向延伸的多条初始化信号线,每条初始化信号线的一端与一条连接线耦接;其中,所述第一方向与所述第二方向交叉;一条所述第一导体化连接线与至少两条 初始化信号线耦接,其中,所述至少两条初始化信号线与同一条连接线耦接。
在一些实施例中,所述在衬底基板上形成有源图案层包括:在所述衬底基板上形成至少一条半导体连接线,并且将所述至少一条半导体连接线导体化,得到包括至少一条第一导体化连接线的有源图案层。
为了更清楚地说明本公开中的技术方案,下面将对本公开一些实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本公开的一些实施例的附图,对于本领域普通技术人员来讲,还可以根据这些附图获得其他的附图。此外,以下描述中的附图可以视作示意图,并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1A为相关技术中的一种显示面板的结构图;
图1B为相关技术中的另一种显示面板的结构图;
图2A为本公开的一些实施例提供的一种显示面板的结构图;
图2B为图2A中的显示面板的剖面图;
图3A为本公开的一些实施例提供的一种显示面板的俯视图;
图3B为本公开的一些实施例提供的另一种显示面板的俯视图;
图3C为沿图3B中的A-A’线截取的剖面图;
图4A为相关技术中的像素驱动电路的等效电路图;
图4B为本公开的一些实施例提供的又一种显示面板的俯视图;
图5A为图4B中的显示面板的一个图案层的结构图;
图5B为图4B中的显示面板的两个图案层的结构图;
图5C为图4B中的显示面板的三个图案层的结构图;
图5D为图4B中的显示面板的四个图案层的结构图;
图6为本公开的一些实施例提供的又一种显示面板的俯视图;
图7为本公开的一些实施例提供的又一种显示面板的俯视图;
图8为沿图7所示的显示面板中的B-B’线截取的剖面图;
图9为本公开的一些实施例提供的又一种显示面板的结构图;
图10为本公开的一些实施例提供的又一种显示面板的俯视图;
图11为本公开的一些实施例提供的又一种显示面板的俯视图;
图12为本公开的一些实施例提供的一种显示面板的制备方法的流程图;
图13为本公开的一些实施例提供的另一种显示面板的制备方法的 工艺流程图;
图14为本公开的一些实施例提供的又一种显示面板的制备方法的工艺流程图。
下面将结合附图,对本公开一些实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本公开一部分实施例,而不是全部的实施例。基于本公开所提供的实施例,本领域普通技术人员所获得的所有其他实施例,都属于本公开保护的范围。
除非上下文另有要求,否则,在整个说明书和权利要求书中,术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思,即为“包含,但不限于”。在说明书的描述中,术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外,所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中,除非另有说明,“多个”的含义是两个或两个以上。
在描述一些实施例时,可能使用了“耦接”和“连接”及其衍伸的表达。例如,描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如,描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而,术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触,但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义,均包括以下A、B和C的组合:仅A,仅B,仅C,A和B的组合,A和C的组合,B和C的组合,及A、B和C的组合。
“A和/或B”,包括以下三种组合:仅A,仅B,及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言,其不排除适用于或被配置为执行额外任务或步骤的设备。
另外,“基于”的使用意味着开放和包容性,因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样,“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值,其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即,测量***的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中,为了清楚,放大了层和区域的厚度。因此,可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此,示例性实施方式不应解释为局限于本文示出的区域的形状,而是包括因例如制造而引起的形状偏差。例如,示为矩形的蚀刻区域通常将具有弯曲的特征。因此,附图中所示的区域本质上是示意性的,且它们的形状并非旨在示出设备的区域的实际形状,并且并非旨在限制示例性实施方式的范围。
多个图案“同层设置”指的是多个图案属于同一图案层,即多个图案通过同一构图工艺形成,其中,构图工艺是指能够在一承载面上同时形成多个图案的工艺。例如,多个图案是有机材料,该构图工艺可以是蒸镀或打印等。又如,多个图案是金属材料,此时构图工艺可以包括:先采用成膜工艺形成一薄膜,然后将该薄膜图案化形成包含多个图案的图案层;其中,图案化的过程可以包括:涂覆光刻胶、曝光、显影、刻蚀等工艺。需要说明的是,多个图案可以有至少部分连接,或者相互间隔。此外,多个图案可能具有不同厚度(可以说是高度)。例如,本实施例中附图中示出的多个层均可以是图案层,例如,有源图案层、第一导电层、第二导电层等。
一些显示面板,例如OLED显示面板中包括像素驱动电路和初始化信号线,初始化信号线被配置为向像素驱动电路传输初始化信号,其中,参见图1A,初始化信号线Vint可由IC引出,并且可以从显示面板的一侧aa延伸至与其相对的另一侧bb。在相关技术中,初始化信号线在向与其耦接的像素驱动电路传输初始化信号的过程中,由于初始化信号线上的压降,被传输的信号在传输过程中逐渐衰减,致使最终传输到像素驱动电路中的信号不准确,从而产生显示画面的亮度不均问题。
此外,对于具有摄像或者感应功能的显示装置,还需要在显示面板的特 定位置处打孔(即开物理孔),以保证光线能够透过显示面板进入摄像头或者感应器件中,物理孔将部分初始化信号线打断,被打断的初始化信号线的压降进一步增大,使得位于物理孔两侧的子像素的正常发光受到影响,在显示面板中产生横向显示不均问题。
参见图1B,显示屏中的物理孔的边沿用圆圈示出,初始化信号线a、b、c即为上述在AA内产生中断的初始化信号线;此外,显示屏中还包括若干条在AA内连续的初始化信号线,例如图1B中的初始化信号线d、e。由于初始化信号线a、b、c在物理孔的位置处断开,而断开的初始化信号线延伸至物理孔的一端无法连接至位于显示屏相对两侧的连接线CL,使得上述在AA内产生中断的初始化信号线上的压降相比于在AA内连续的初始化信号线上的压降大。而初始化信号线上大的压降使得该条初始化信号线传输的初始化信号产生衰减,衰减后的初始化信号写入对应的像素驱动电路后使得该像素驱动电路的充电率降低,例如,从显示屏的一侧到物理孔的边沿,各个像素驱动电路的充电率逐渐降低,那么在宏观上会表现为一条渐变亮度的横条,即横向显示不均。
为了解决上述问题,本公开的实施例提供了一种显示装置。显示装置是指具有图像显示功能的产品,示例性地,可以是:显示器,电视,广告牌,数码相框,具有显示功能的激光打印机,电话,手机,个人数字助理(Personal Digital Assistant,PDA),数码相机,便携式摄录机,取景器,监视器,导航仪,车辆,大面积墙壁、家电、信息查询设备(如电子政务、银行、医院、电力等部门的业务查询设备,监视器等。
显示装置通常包括显示面板,示例性地,显示面板可以是OLED(Organic Light Emitting Diode,有机发光二极管)显示面板、QLED(Quantum Dot Light Emitting Diodes,量子点发光二极管)显示面板、微LED(包括:miniLED或microLED)显示面板等。此外,显示装置还可以包括其他部件,例如,对显示面板进行供电的电源***、与显示面板相连接的电路板等。
图2A示出了本公开的一些实施例提供的显示面板的俯视图。该显示面板10具有显示区AA和位于显示区AA至少一侧的周边区SS,图2A中示出了周边区SS围绕显示区AA设置,但不限于此,例如,周边区SS可以仅设置在显示区AA的一侧。显示面板10还包括设置在显示区AA中的多个子像素P,示例性地,所述多个子像素P可以如图2A所示呈阵列排布,形成多个子像素排和多个子像素列。当然,子像素P的个数和排布方式并不限于图中所示,其可以根据需要进行设计。
图2B示出了本公开的一些实施例提供的显示面板。显示面板10可以包括驱动背板100和多个发光器件200,示例性地,驱动背板100包括衬底基板101和设置在衬底基板101上的多个像素驱动电路D,每个像素驱动电路D与一个发光器件200耦接,构成一个子像素P,像素驱动电路D被配置为驱动与其相耦接的发光器件200发光。其中,多个像素驱动电路D可以在衬底基板101上有序排列,例如,多个像素驱动电路D在衬底基板210上呈阵列分布。
发光器件200是子像素P实现发光的主体结构,每个发光器件200可以为多层薄膜叠加的结构。示例性地,发光器件200包括阴极230和阳极210,以及位于阴极230和阳极210之间的发光功能层220。其中,发光功能层220例如可以包括发光层224、位于发光层224和阳极210之间的空穴传输层222(Hole Transporting Layer)、位于发光层224和阴极230之间的电子传输层226(Election Transporting Layer)。当然,根据需要,在一些实施例中,还可以在空穴传输层222和阳极210之间设置空穴注入层221(Hole Injection Layer),可以在电子传输层226和阴极230之间设置电子注入层227(Election Injection Layer)。此外,在空穴传输222与发光层224之间还可以设置电子阻挡层223(Electron Blocking Layer),在电子传输层226与发光层224之间还可以设置空穴阻挡层225(Hole Blocking Layer)。
图3A为本公开的一些实施例提供的显示面板的驱动背板100的俯视图。驱动背板100可以包括多个层,驱动背板100中的每个层在图3A中以不同的填充图案示出。
示例性地,驱动背板100包括有源图案层110和第一导电层120。其中,有源图案层110设置于衬底基板101上,第一导电层120设置在有源图案层110远离衬底基板120的一侧。例如,在衬底基板101上形成有源图案层110之后,可以在有源图案层110远离衬底基板的一侧首先形成一层绝缘层(称为第一绝缘层),之后,再在第一绝缘层远离有源图案层110的一侧形成第一导电层120,这样,有源图案层110与第一导电层120之间可以通过第一绝缘层隔开。
参见图3A,驱动背板100的有源图案层110包括:至少一条第一导体化连接线111。导体化是指原本导电性较差的物体经过一定的处理后,其导电性得以增强的工艺。其中,导电性较差是一个相对概念,例如,绝缘体的导电性相对于半导体或导体来说是较差的,半导体的导电性相对于导体来说是 较差的。示例性地,导体化可以是掺杂工艺,例如,驱动背板100中的第一导体化连接线111可以通过对半导体连接线进行掺杂得到,其中,形成半导体连接线的材料可以是多晶硅。
有源图案层110中的第一导体化连接线111的数量可以是一条或者多条,示例性地,有源图案层110包括多条第一导体化连接线111,还可以包括其他导体化图案或半导体图案,其中,半导体图案可以用来形成晶体管的栅极,导体化图案可以用来形成晶体管的源极或漏极。
本公开的实施例对第一导体化连接线111的形状不做限制,可以根据需要进行设计。例如,第一导体化连接线111可以是直条形、波浪型或者折线形等。当第一导体化连接线111为波浪型或折线形,可以包括多个周期性的重复线段,各个重复线段在相同位置的连线的延伸方向可以作为该第一导体化连接线111的延伸方向。当第一导体化连接线111是多条时,多条第一导体化连接线111的延伸方向可以大致平行,例如,任意两条第一导体化连接线111的延伸方向之间的夹角不超过5°。这些第一导体化连接线111的延伸方向可以根据需要进行设计。
继续参见图3A,驱动背板100的第一导电层120包括:沿第一方向Y延伸的至少一条连接线121,和沿第一方向Y排列且沿第二方向X延伸的多条初始化信号线Vint,每条初始化信号线Vint的一端与一条连接线121耦接;其中,第一方向Y与第二方向X交叉。
示例性地,第一方向Y为水平方向,第二方向X为竖直方向,当第一方向Y与第二方向X交叉时,第一方向Y与第二方向X之间的夹角为直角。当然,本公开的实施例对第一方向Y和第二方向X的具体方向不做限制,例如,第一方向Y与第二方向X交叉所成的夹角可以是锐角、钝角。
初始化信号线在显示面板中被配置为传输初始化信号,初始化信号可以来自于显示装置的IC。示例性地,各连接线121可以位于显示面板10的周边区SS,并且,至少一条连接线121与显示装置的信号提供电路(例如,IC)耦接。当显示装置10显示画面时,至少一条连接线121可以从IC接收初始化信号,并将所接收的初始化信号传输给显示面板10的子像素P。示例性地,显示面板中仅包括一条连接线,例如图3A中的121a或121b,该条连接线接收IC提供的初始化信号;又示例性地,显示面板中包括:两条连接线121a和121b。其中,连接线121a可以接收IC提供的初始化信号;当然,还可以仅由连接线121b接收IC提供的初始化信号,或者,由连接线121a、121b分别从IC接收初始化信号。
在第一导电层120仅包括一条连接线121的情况下,显示面板中的所有初始化信号线Vint均与该条连接线耦接;在第一导电层120包括多条连接线121的情况下,初始化信号线Vint可以与所述多条连接线121中的至少一条连接线121耦接。示例性地,一条初始化信号线Vint仅与一条连接线121耦接,例如,显示面板中包括两条连接线121a和121b,一条初始化信号线Vint可以仅与连接线121a耦接,或者仅与连接线121b耦接,那么,显示面板中可以包括多条仅与连接线121a耦接的初始化信号线和多条仅与连接线121b耦接的初始化信号线;又示例性地,一条初始化信号线Vint同时与两条连接线121耦接,例如,参见图3A,一条初始化信号线Vint的一端与连接线121a耦接,另一端与连接线121b耦接。为了便于描述,在下文中,将仅与一条连接线耦接的初始化信号线称为第一初始化信号线,将两端分别与一条连接线耦接的初始化信号线称为第二初始化信号线。
一条连接线121可以通过与其相耦接的初始化信号线Vint将初始化信号传输给显示面板10中与这些初始化信号线Vint耦接的子像素P(子像素P在图2A中示出)。示例性地,一条初始化信号线Vint可以与多个子像素P耦接,例如,与一条初始化信号线Vint耦接的多个子像素P可以是同一排的子像素。每个子像素P通过像素驱动电路D中的一个或多个节点与初始化信号线Vint耦接,以将像素驱动电路中的所述一个或多个节点的电压初始化。
一条第一导体化连接线与至少两条初始化信号线Vint耦接,其中,至少两条初始化信号线Vint与同一条连接线121耦接。
示例性地,一条第一导体化连接线111与两条初始化信号线Vint耦接,例如,图3A中的第一导体化连接线111同时与初始化信号线Vint(a)、Vint(b)耦接。当初始化信号线Vint(a)和初始化信号线Vint(a)通过第一导体化连接线111耦接在一起时,初始化信号线Vint(a)与初始化信号线Vint(b)并联,并联后形成的等效电阻小于初始化信号线Vint(a)和初始化信号线Vint(b)中的任一者的电阻,使得每条初始化信号线(Vint(a)、Vint(b))上的压降相对于未并联时降低,从而可以使第一初始化信号线(Vint(a)、Vint(b))上的信号损失也随之降低。
当初始化信号线上的压降降低时,与该条初始化信号线耦接的各个子像素P所接收的初始化信号的差异减小,例如,与该条初始化信号线耦接的各个像素驱动电路所接收到的初始化信号(初始电压)几乎相等,那么,每个像素驱动电路中对应节点的电压经过初始化之后均达到预设的电压值,或者 仅与预设的电压值存在较小的偏差,这样,每个像素驱动电路的充电率几乎相同,从而使各子像素发光的亮度差异减小。
在本公开的实施例中,通过在有源图案层110上设置至少一条第一导体化连接线111,并且一条第一导体化连接线111通过与至少两条初始化信号线Vint耦接,使得所述至少两条初始化信号线Vint被并联起来,初始化信号线Vint并联之后的等效电阻相比于每条初始化信号线Vint各自的电阻更小,从而可以将每条初始化信号线Vint上的压降降低。当初始化信号线Vint上的压降降低后,通过初始化信号线Vint传输的初始化信号的衰减也会降低,使得写入到各个子像素的初始化信号更加准确,进而改善显示面板的显示不均问题,提升显示装置的显示画质。
图3B为本公开的一些实施例提供的另一种显示面板的驱动背板100的俯视图。其中,驱动背板100包括通孔H。通孔H为贯穿驱动背板100的厚度方向上的相对两侧的孔,孔的大小和位置可以根据需要进行设计。驱动背板100中的通孔数量可以是多个,并且,当驱动背板100中包括多个通孔H时,每个通孔的位置和排列方式可以根据实际情况进行设计。本公开的实施例均以驱动背板中包括一个通孔H为例进行说明。
继续参见图3B,驱动背板100的第一导电层120包括:沿第一方向Y延伸的至少一条连接线121,和沿第一方向Y排列且沿第二方向X延伸的多条第一初始化信号线122,其中,第一初始化信号线122是初始化信号线Vint的一种,每条第一初始化信号线122的一端与一条连接线121耦接,另一端延伸至通孔H,其中,第一方向Y与第二方向X交叉。
示例性地,第一导电层120包括多条沿第一方向Y延伸的连接线121,例如,参见图3B,第一导电层120包括连接线121a和连接线121b,连接线121a、121b可以分别设置在驱动背板100的相对两侧,例如,连接线121a和连接线121b分别设置在位于显示面板10相对两侧的周边区SS中。参见图3B,第一导电层120还包括沿第一方向Y排列且沿第二方向X延伸的多条第一初始化信号线122。第一初始化信号线122可以是因通孔H而产生的断线,因此断线的多少取决于通孔H的尺寸。其中,由于显示面板中每行子像素都要连接X方向延伸的初始化信号线,因此X方向延伸的初始化信号线之间的距离与一子像素在Y方向上的尺寸(或者说是X方向延伸的一排子像素的宽度)大致相同。例如,当因通孔H而去除的子像素行数为多行(记为N,N≥2;例如,N=9,或者N=15),那么连接到一条连接线121的第一初始化信号线122的数量也为多条(记为M,M≥2;例如,M=N,或者,M=N+1,或者 M=N-1)。图3B中仅示意性地示出第一导电层120包括的第一初始化信号线122a、122b、122c和122d。其中,第一初始化信号线122a和122b连接同一条连接线121a,且沿第一方向Y间隔排列。第一初始化信号线122c和122c连接同一条连接线121b,且沿第一方向Y间隔排列。此外,相邻两条第一初始化信号线122之间的距离可以相等或不等。
每条第一初始化信号线122的一端与一条连接线121耦接,另一端延伸至通孔H,例如,参见图3B,第一初始化信号线122a(或122b)的一端可以与位于左侧的一条连接线121a耦接,另一端延伸至通孔H。第一初始化信号线122c(或122d)的一端可以与位于右侧的一条连接线121b耦接,另一端延伸至通孔H。
一条第一导体化连接线111与至少两条第一初始化信号线122耦接,其中,所述至少两条第一初始化信号线122与同一条连接线121线耦接。通过一条第一导体化连接线111耦接后的两条第一初始化信号线122形成的等效电阻小于所述两条第一初始化信号线122中任意条的电阻,使得,所述两条第一初始化信号线122上的压降均降低,进而有利于保证各自所传输的信号的准确性。
通过一条第一初始化信号线122耦接的子像素P中,由于第一初始化信号线上存在压降,使得最靠近连接线的子像素的像素驱动电路的充电率最高,最靠近通孔H的子像素的像素驱动电路的充电率最低,在发光阶段,最靠近连接线的子像素的亮度最亮,最靠近通孔的子像素的亮度最暗,中间的子像素的亮度介于二者之间。当第一初始化信号线上的压降降低后,每个子像素的亮度均向最亮的子像素靠近,使得最亮的子像素与最暗的子像素之间的亮度差异减小,对显示装置来说,从显示装置的一侧到物理孔之间的亮度渐变就会变得更加不明显。
在一些实施例中,有源图案层110包括多条第一导体化连接线111,并且每条第一导体化连接线111均与至少两条初始化信号线Vint耦接。本公开的实施例对多条第一导体化连接线111的排列方式不做限制,可以根据需要进行设计,例如,参见图3A和图3B,多条第一导体化连接线111可以平行设置。
示例性地,参见图3B,以第一初始化信号线为例进行说明,第一初始化信号线122a、122b通过多条位于连接线121a和通孔H之间的第一导体化连接线111耦接,其中,每相邻两条第一导体化连接线111之间的第一初始化信号线122a和第一初始化信号线122b均可以被视为并联关系,例如,每相 邻两条第一导体化连接线111之间通过第一初始化信号线122a的一部分和第一初始化信号线122b的一部分并联形成的电阻分别为图3B中虚线框示出的R1、R2、R3。其中,R1、R2、R3之间又互为并联关系。这样,连接线121a与通孔H之间的第一初始化信号线122a和第一初始化信号线122b经过多次并联,其等效电阻相比于仅并联一次进一步减小,使得每条第一初始化信号线122a、122b上的压降相比于仅通过一条第一导体化连接线111耦接时更低,那么,通过第一初始化信号线122a、122b写入到像素驱动电路的初始化信号也变得更加准确。
在一些实施例中,参见图3B,第一导电层120包括相对设置的两条连接线121a、121b;第一导电层120还包括:沿第一方向Y排列且沿第二方向X延伸的多条第二初始化信号线123,其中,第二初始化信号线123是初始化信号线Vint的一种,每条第二初始化信号线123的两端各与一条连接线121耦接。当第二初始化信号线123的两端均耦接至连接线121时,第二初始化信号线123上产生的压降极小或几乎为零。
示例性地,多条第二初始化信号线123可以以一定间隔设置在第一初始化信号线122的两侧,例如,图3B中的第二初始化信号线123位于通孔的上、下两侧,并且每条第二初始化信号线123等距离设置,同时,一条第二初始化信号线123与一条第一初始化信号线122之间的距离也相等。
每条第一导体化连接线111还与至少一条第二初始化信号线123耦接。示例性地,每条第一导体化连接线111在耦接至少两条第一初始化信号线122的同时还与一条第二初始化信号线123耦接。由于第二初始化信号线上的压降极小或几乎为零,当至少两条第一初始化信号线122与一条第二初始化信号线123耦接时,所述至少两条第一初始化信号线122与一条第二初始化信号线123并联,并联后每条第一初始化信号线122上的压降均小于第二初始化信号线123上的压降,从而可以使第一初始化信号线122上的压降大大降低。
又示例性地,每条第一导体化连接线111在耦接至少两条第一初始化信号线122的同时还可以与多条第二初始化信号线123耦接,耦接的第二初始化信号线123的数量越多,每条第一初始化信号线122并联的第二初始化信号线123的数量越多,并联后每条第一初始化信号线122上产生的压降越小。例如,每条第一导体化连接线111将驱动背板中的每条第二初始化信号线123均耦接,在这种情况下,每条第二初始化信号线123上的压降可以达到最小;又如,一条第一导体化连接线111仅将驱动背板中的几条第二初始化信号线 123耦接,即所述至少一条第一导体化连接线111耦接的第二初始化信号线123的数量小于驱动背板中第二初始化信号线123的总数。
在一些实施例中,参见图3B,有源图案层110还包括:至少一条第二导体化连接线112,每条第二导体化连接线112与至少两条第二初始化信号线123耦接。当至少两条第二初始化信号线123通过一条第二导体化连接线112耦接时,所述至少两条第二初始化信号线123可以被并联起来,当至少两条第二初始化信号线123通过多条第二导体化连接线112耦接时,所述至少两条第二初始化信号线123可以被并联多次,进而将每条第二初始化信号线123上的压降也进一步降低,其原理与至少两条第一初始化信号线122并联时相同,不再赘述。
本公开的一些实施例提供了一种驱动背板100,驱动背板100设置了多个像素驱动电路。
本公开的实施例对像素驱动电路的具体结构不作限定,可以根据实际情况进行设计。示例性地,像素驱动电路由薄膜晶体管(Thin Film Transistor,简称TFT)、电容器(Capacitance,简称C)等电子器件组成。例如,像素驱动电路可以包括两个薄膜晶体管(一个开关晶体管和一个驱动晶体管)和一个电容器,构成2T1C结构;当然,像素驱动电路还可以包括两个以上的薄膜晶体管(多个开关晶体管和一个驱动晶体管)和至少一个电容器,例如像素驱动电路可以包括一个电容器和七个晶体管,构成7T1C结构。
下面以7T1C结构的像素驱动电路为例对像素驱动电路的结构进行说明,参见图4A,该图示出了一个7T1C结构的像素驱动电路的等效电路图。其中,该像素驱动电路包括:电容器Cst、多个开关晶体管(T1、T2、T4、T5、T6、T7)和一个驱动晶体管T3。图中的字母标注(Vint、Re、G、EM、Vdata、VDD)分别代表与对应晶体管耦接的信号线,例如,Vint代表初始化信号线、Re代表第一复位信号线,Re’代表第二复位信号线,G代表扫描控制信号线、EM代表发光控制信号线、Vdata代表数据信号线、VDD代表电源信号线,其中,Re’传输的信号与G传输的信号相同。
例如,如图4A所示,一部分开关晶体管(例如T1)的控制极(栅极)与复位信号线Re耦接,用于接收第一复位信号;一部分开关晶体管(例如T7)的控制极(栅极)与复位信号线Re’耦接,用于接收第二复位信号。另一部分开关晶体管(例如,T2、T4)的控制极与扫描控制信号线G耦接,用于接收扫描控制信号。其中,第二复位信号与扫描控制信号相同。又一部 分开关晶体管(例如,T5、T6)的控制极与发光控制信号线EM耦接,用于接收发光控制信号。例如,晶体管T1和T7响应于复位信号导通,初始化信号(通过初始化信号线Vint传输)通过晶体管T1和T7分别传输至驱动晶体管T3的控制极(g)以及发光器件L的阳极,达到对发光器件L的阳极以及驱动晶体管T3的控制极进行复位的目的。在扫描控制信号(通过扫描控制信号G传输)的控制下,晶体管T2、T4导通,驱动晶体管T3的控制极g与漏极(d)耦接,该驱动晶体管T3成二极管导通状态。此时,数据信号(通过数据信号线Vdata传输)通过该晶体管T2和T4写入至驱动晶体管T3的源极(s),并对驱动晶体管T3的阈值电压进行补偿。在发光控制信号(通过发光控制信号EM传输)的控制下,晶体管T5和晶体管T6导通,驱动电流通过上述电流通路传输至发光器件L,以驱动发光器件L进行发光。示例性地,发光器件L的一极(例如阳极)接收来自像素电路的驱动电流,发光器件L的另一极(例如阴极)与固定电压端耦接;例如,该固定电压端被配置为传输直流电压,例如直流低电压。
图4B示出了上述7T1C结构的像素驱动电路在驱动背板上的结构图。其中,驱动背板由多个图案层叠加而成。示例性地,驱动背板包括衬底基板,以及在衬底基板上依次形成的有源图案层、第四导电层、第一导电层以及第三导电层。图5A至图5D依次示出了各个图案层的具体结构。
其中,图5A示出了驱动背板中的有源图案层的具体结构,其中,有源图案层包括开关晶体管(T1、T2、T4、T5、T6、T7)和个驱动晶体管T3的有源层T1a~T7a,如图5A中的虚线框所示(仅以一个像素驱动电路为例)。
图5B还示出了驱动背板的第四导电层的具体结构,其中,第四导电层可以形成开关晶体管(T1、T2、T4、T5、T6、T7)和个驱动晶体管T3的栅极T1g~T7g。此外,第四导电层还可以形成对应的第一复位信号线Re、第二复位信号线Re’扫描控制信号线G、发光控制信号线EM以及电容器Cst的第一极板Cst1。
图5C还示出了驱动背板的第一导电层的具体结构,其中,第一导电层可以形成初始化信号线Vint,例如,第一导电层可以形成本公开的实施例所述的连接线、第一初始化信号线等。此外,第一导电层还可以形成电容器Cst的第二极板Cst2。
图5D还示出了驱动背板的第三导电层的具体结构,其中,第三导电层可以形成晶体管的源漏极。此外,第三导电层还可以形成电源信号线VDD和数据信号线Vdata。
在一些实施例中,参见图3B,驱动背板100还包括设置在第一导电层120远离衬底基板101的一侧的至少一个第一连接图案141。一条第一导体化连接线111与一条初始化信号线Vint通过一个第一连接图案141耦接。
示例性地,一条第一导体化连接线111与一条第一初始化信号线122通过一个第一连接图案141耦接。
示例性地,第一连接图案141可以设置在第三导电层140,其中,第三导电层140可以设置在第一导电层120远离衬底基板101的一侧。第一导电层120与第三导电层140之间还可以通过第二绝缘层104隔开。参见图3B、图3C和图4B,当一条第一导体化连接线111与一条第一初始化信号线122通过一个第一连接图案141耦接时,可以在形成第二绝缘层104之后,首先形成第一过孔V1和第二过孔V2,其中,第一过孔V1穿透第二绝缘层104和第一绝缘层103,通到第一导体化连接线111上,第二过孔V2穿透第二绝缘层104,通到第一初始化信号线122上。之后,在形成第一连接图案141时,可以使第一连接图案141同时覆盖第一过孔V1和第二过孔V2,以将第一导体化连接线111与第一初始化信号线122耦接。
其中,第一连接图案141可以使用制作第三导电层140中的其他图案的掩膜板通过一次构图工艺完成,相比于在形成第一绝缘层103之后,在第一绝缘层103上打孔,再形成第一导电层120中的第一初始化信号线122,使得有源图案层110中的第一导体化连接线111与第一导电层120中的第一初始化信号线122通过位于第一绝缘层103中的过孔耦接,可以节省一块掩膜板,进而提高驱动背板的制作成本。
类似地,一条第一导体化连接线111与一条第二初始化信号线123可以通过一个第一连接图案141耦接,其耦接方式和有益效果同第一初始化信号线122,不再赘述。
在一些实施例中,一个第一连接图案与一条初始化信号线耦接的耦接点位于通过该第一连接图案耦接的一条第一导体化连接线和所述一条初始化信号线的交叉位置处。
示例性地,参见图4B,一个第一连接图案141与一条第一初始化信号线122耦接的耦接点位于通过该第一连接图案141耦接的一条第一导体化连接线111和一条第一初始化信号线122的交叉位置处。
第一连接图案141与一条第一初始化信号线122耦接的耦接点需要位于该条第一初始化信号线122上,使得第二过孔V2可以通到该条第一初始化信号线122上,例如,上述第一连接图案141与一条第一初始化信号线122耦 接的耦接点可以为第二过孔V2。当上述耦接点位于除了该条第一初始化信号线122与第一导体化连接线111的交叉点之外的位置时,第一连接图案141可以做成“L”形;当上述耦接点位于该条第一初始化信号线122与第一导体化连接线111的交叉点时,第一连接图案141可以做成“1”字形,显然地,当第一连接图案141做成“1”字形时,相比于“L”形在第三导电层140中所占的面积更小,有利于子像素的小型化设计。
类似地,一个第一连接图案141与一条第二初始化信号线123耦接的耦接点位于通过第一连接图案141耦接的一条第一导体化连接线111和一条第二初始化信号线123的交叉位置处,其有益效果同上述第一初始化信号线122,不再赘述。
在一些实施例中,第一导体化连接线111沿第一方向Y延伸,且为直条形。直条形的第一导体化连接线111形状简单,便于制作,有利于在驱动背板生产过程中提高良率。
在一些实施例中,驱动背板还包括第二导电层,第二导电层设置在衬底基板与有源图案层之间。第二导电层包括:沿第三方向延伸的至少一条导电线,一条导电线与一条初始化信号线通过至少两个耦接点耦接。
示例性地,参见图6,驱动背板100还包括第二导电层130,第二导电层130设置在衬底基板101与有源图案层110之间。第二导电层130包括:沿第三方向延伸的至少一条导电线131,一条导电线131与一条第一初始化信号线122通过至少两个耦接点耦接。其中,上述至少两个耦接点中,至少一个耦接点位于该条导电线131上,并且,至少一个耦接点位于该条第一初始化信号线122上。
类似地,一条导电线131与一条第二初始化信号线123通过至少两个耦接点耦接。其耦接方式可以参照上述第一初始化信号线122,不再赘述。
第三方向可以与第一方向Y或第二方向X交叉;第三方向还可以与第一方向Y或第二方向X中的一者平行。
在一些实施例中,第三方向和第二方向X平行,在这种情况下,驱动背板100中的导电线131可以与第一初始化信号线122或第二初始化信号线123平行。
在一些实施例中,驱动背板还包括设置在第一导电层远离衬底基板的一侧的至少一个第二连接图案,其中,一条导电线与一条初始化信号线通过一个第二连接图案耦接。例如,参见图6,驱动背板100还包括设置在第一导电层120远离衬底基板101的一侧的至少一个第二连接图案142,其中,一条导 电线131与一条第一初始化信号线122通过一个第二连接图案142耦接。
示例性地,第二连接图案142可以与第一连接图案141位于同一层,例如,第二连接图案142位于第三导电层140。
示例性地,参见图7和图8,在形成第二导电层130之后,可以在第二导电层130远离衬底基板101的一侧形成缓冲层105,之后在缓冲层105远离衬底基板101的一侧形成有源图案层110、第一导电层120等。在形成第二绝缘层104之后,形成第二过孔V2’的同时,还可以形成第三过孔V3,其中,第三过孔V3穿透第二绝缘层104、第一绝缘层103以及缓冲层105,通到导电线131上,之后,在形成第三导电层140时,可以形成第二连接图案142,其中,第二连接图案142可以同时覆盖第二过孔V2’和第三过孔V3以将一条导电线131与一条第一初始化信号线122耦接。在这种情况下,耦接一条导电线131与一条第一初始化信号线122的耦接点可以例如是第二过孔V2’和第三过孔V3。
类似地,一条导电线131与一条第二初始化信号线123通过一个第二连接图案142耦接,其耦接方式参照第一初始化信号线122,不再赘述。
在一些实施例中,第二导电层130包括多条导电线131,其中,每条第一初始化信号线122和每条第二初始化信号线123均与一条导电线131耦接。
在一些实施例中,一条第一导体化信号线、一条初始化信号线和一条导电线通过一个第二连接图案耦接。示例性地,参见图7,一条第一导体化信号线111、一条第一初始化信号线122和一条导电线131通过一个第二连接图案142耦接,例如,参见图8,连接图案142可以同时将第一通孔V1、第二通孔V2以及第三通孔V3覆盖。
类似地,一条第一导体化信号线111、一条第二初始化信号线123和一条导电线131通过一个第二连接图案142耦接,其耦接方式与上述第一初始化信号线122类似,不再赘述。
在一些实施例中,有源图案层110还包括多个有源层。其中,所述多个有源层可以是有源图案层110中的一部分有源层,也可以是有源图案层110中的全部有源层。
示例性地,参见图9,有源图案层110中包括多个有源图案112,每个有源图案112中包括多个有源层,例如,在7T1C的像素驱动电路中,每个有源图案112可以包括7个有源层,其中,所述7个有源层中有一个是驱动晶体管的有源层DA。例如,有源图案层110中的多个有源层可以包括有源图案层110中所有驱动晶体管的有源层DA。
第二导电层130还包括:多个遮光图案132,其中,一个有源层(例如,多个有源层中的每个有源层)在衬底基板101上的正投影位于一个遮光图案132在衬底基板上的正投影以内。
示例性地,有源图案层110中每个驱动晶体管的有源层DA在衬底基板101上的正投影分别位于一个遮光图案132在衬底基板上的正投影以内。
对于具有红外成像功能的显示装置来说,该显示装置通常包括红外线成像组件,红外线成像组件在显示装置中通常位于显示面板厚度方向上的一侧,例如,红外线成像组件位于显示面板的靠近衬底基板的一侧。当红外线成像组件工作时,其发出的红外线照射显示面板,使得显示面板的驱动背板中的晶体管产生晶体管特性偏移现象,进而导致显示面板产生亮点不良。驱动背板的第二导电层130上的遮光图案132可以起到遮挡红外线的作用,其可以防止红外线不断地对驱动晶体管的有源层DA进行照射,在一定程度上避免驱动晶体管特性偏移现象的出现,从而改善显示面板的显示画质。
在一些实施例中,驱动背板100还包括设置在第一导电层120远离衬底基板101的一侧的电源信号线VDD,多个遮光图案132与电源信号线VDD耦接。
示例性地,电源信号线VDD可以与第一连接图案141位于同一层,例如,电源信号线VDD位于第三导电层140。多个遮光图案132与电源信号线VDD可以通过打过孔的方式耦接。例如,参见图10,驱动背板100中位于同一排的遮光图案132可以首位相连,并且相邻两个遮光图案132之间的连接线可以通过第四过孔V4与电源信号线VDD耦接。其中,第四过孔V4可以在形成第三导电层140之前形成,并且第四过孔V4可以穿透第二绝缘层104、第一绝缘层103以及缓冲层105通到相邻两个遮光图案132之间的连接线上。
在遮光图案132接入稳定的信号的情况下,例如,遮光图案132接入电源信号线VDD提供的信号,可以避免衬底偏置效应,进而防止衬底偏置效应对应驱动晶体管产生影响而导致的显示问题。
在一些实施例中,参见图11,驱动背板100还包括设置在第一导电层120远离衬底基板101的一侧的第三连接图案143,被配置为将每条第一初始化信号线122耦接。
示例性地,第三连接图案143可以与第一连接图案141位于同一层,例如,第三连接图案143位于第三导电层140。
例如,驱动背板100中包括多条第一初始化信号线122a~122d,每条第一初始化信号线上均包括一个第五过孔V5,其中,第五过孔V5可以在形成第 三导电层140之前形成,并且,第五过孔V5穿透第二绝缘层104通到第一初始化信号线上。第三连接图案143将每条第一初始化信号线上的第五过孔V5覆盖,使得每条第一初始化信号线均与第三连接图案143耦接。当第三连接图案143将驱动背板100中的多条第一初始化信号线耦接起来时,可以进一步降低每条第一初始化信号线上的压降。
本公开的实施例还提供一种显示面板的制备方法。参见图12,所述制备方法主要包括步骤S1和步骤S2,其中,
步骤S1:在衬底基板上形成有源图案层,其中,有源图案层包括:至少一条第一导体化连接线;
步骤S2:在有源图案层远离衬底基板的一侧形成第一导电层,其中,第一导电层包括:沿第一方向延伸的至少一条连接线,和沿第一方向排列且沿第二方向延伸的多条初始化信号线,每条初始化信号线的一端与一条连接线耦接,其中,第一方向与第二方向交叉。一条第一导体化连接线与至少两条初始化信号线耦接,其中,所述至少两条初始化信号线与同一条连接线耦接。
在一些实施例中,上述步骤A中的在衬底基板上形成有源图案层包括:在衬底基板上形成至少一条半导体连接线,并且将至少一条半导体连接线导体化,得到包括至少一条第一导体化连接线的有源图案层。示例性地,步骤S1可以包括:S101~S103,其中,
S101:在衬底基板上形成多个半导体图案112s和至少一条半导体连接线111s。
S102:使用光刻胶将每个半导体图案中的有源层遮盖。
S103:对遮盖后的半导体图案和多条半导体连接线111s掺杂,形成包括至少一条第一导体化信号线111的有源图案层。
例如,参见图13,多个半导体图案112s呈阵列排布,每个半导体图案112s位于一个子像素中,并且,位于同一列的半导体图案首尾相连,构成一列半导体图案112s,每条半导体连接线可以111s位于相邻两列半导体图案112s之间。
图13中S102为光刻胶PR将半导体图案部分遮盖后的形状,在对由光刻胶遮盖后的半导体图案112s和多条半导体连接线111s掺杂后,可以得到包括至少一条第一导体化连接线111的有源图案层。
此外,完成步骤S101~S103形成有源图案层之后,还可以继续步骤S2和S3。步骤S2为形成第一导电层,其中,第一导电层包括第一初始化信号线122和/或第二初始化信号线123,步骤S3为形成第三导电层,其中,第三导电层 包括第二连接图案142。此外,在形成第一导电层之前,还可以通过步骤S104形成第四导电层。
本公开的实施例在形成半导体图案层后,通过使用光刻胶将对应晶体管沟道的部分遮盖,将未遮盖的部分导体化,其中,光刻胶遮盖的部分形成晶体管的有源层,光刻胶未遮盖的部分形成晶体管的源漏金属层。相比于相关技术中,在半导体图案层上首先形成晶体管的有源层,再对半导体图案层中除去晶体管的有源层的部分掺杂形成晶体管的源漏金属层,本公开的实施例提供的制备方法可以避免在晶体管的有源层上掺杂导致的晶格破坏,因为在晶体管的有源层上掺杂需要的能量大,掺杂后需要退火修复,损坏晶格。
图14示出了另一种显示面板的工艺图,除了包括图12和图13所示的步骤S1~S3外,还包括步骤S100,其中,步骤S100为在衬底基板上形成第二导电层,其中,第二导电层包括导电线131。在一些实施例中,第二导电层还可以包括遮光图案132。
以上所述,仅为本公开的具体实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以所述权利要求的保护范围为准。
Claims (18)
- 一种显示面板,包括:衬底基板;有源图案层,设置于所述衬底基板上,所述有源图案层包括:至少一条第一导体化连接线;第一导电层,设置在所述有源图案层远离所述衬底基板的一侧,所述第一导电层包括:沿第一方向延伸的至少一条连接线,和沿所述第一方向排列且沿第二方向延伸的多条初始化信号线,每条初始化信号线的一端与一条连接线耦接;其中,所述第一方向与所述第二方向交叉;一条第一导体化连接线与至少两条初始化信号线耦接,其中,所述至少两条初始化信号线与同一条所述连接线耦接。
- 根据权利要求1所述的显示面板,其中,所述有源图案层包括:多条所述第一导体化连接线;其中,所述每条第一导体化连接线均与至少两条初始化信号线耦接。
- 根据权利要求1或2所述的显示面板,其中,所述显示面板具有通孔;所述多条初始化信号线包括多条第一初始化信号线,每条第一初始化信号线的另一端延伸至所述通孔;一条所述第一导体化连接线与至少两条第一初始化信号线耦接,其中,所述至少两条第一初始化信号线与同一条所述连接线耦接。
- 根据权利要求3所述的显示面板,其中,所述第一导电层包括:相对设置的两条连接线;所述多条初始化信号线还包括:沿所述第一方向排列且沿所述第二方向延伸的多条第二初始化信号线,其中,每条第二初始化信号线的两端各与一条连接线耦接;每条第一导体化连接线还与至少一条第二初始化信号线耦接。
- 根据权利要求4所述的显示面板,其中,所述有源图案层还包括:至少一条第二导体化连接线,每条第二导体化连接线与至少两条第二初始化信号线耦接。
- 根据权利要求1至5中的任一项所述的显示面板,还包括:设置在所述第一导电层远离所述衬底基板的一侧的至少一个第一连接图案;一条所述第一导体化连接线与一条初始化信号线通过一个第一连接图案耦接。
- 根据权利要求6所述的显示面板,其中,所述一个第一连接图案与所述一条初始化信号线耦接的耦接点位于通过所述第一连接图案耦接的所述一条第一导体化连接线和所述一条初始化信号线的交叉位置处。
- 根据权利要求1至7中的任一项所述的显示面板,其中,所述第一导体化连接线沿所述第一方向延伸,且为直条形。
- 根据权利要求1至8中的任一项所述的显示面板,还包括:第二导电层,设置在所述衬底基板与所述有源图案层之间;所述第二导电层包括:沿第三方向延伸的至少一条导电线,一条导电线与一条初始化信号线通过至少两个耦接点耦接。
- 根据权利要求9所述的显示面板,其中,所述第三方向和所述第二方向平行。
- 根据权利要求9或10所述的显示面板,还包括:设置在所述第一导电层远离所述衬底基板的一侧的至少一个第二连接图案;其中,所述一条导电线与所述一条初始化信号线通过一个第二连接图案耦接。
- 根据权利要求11所述的显示面板,其中,一条第一导体化信号线、一条初始化信号线和一条导电线通过一个第二连接图案耦接。
- 根据权利要求9至12中的任一项所述的显示面板,其中,所述有源图案层还包括:多个有源层;所述第二导电层还包括:多个遮光图案,其中,一个有源层在所述衬底 基板上的正投影位于一个遮光图案在所述衬底基板上的正投影以内。
- 根据权利要求13所述的显示面板,还包括:设置在所述第一导电层远离所述衬底基板的一侧的电源信号线;所述多个遮光图案与所述电源信号线耦接。
- 根据权利要求2至14中的任一项所述的显示面板,还包括:设置在所述第一导电层远离所述衬底基板的一侧的第三连接图案,所述第三连接图案被配置为将每条第一初始化信号线耦接。
- 一种显示装置,包括权利要求1至15中的任一项所述的显示面板。
- 一种显示面板的制备方法,包括:在衬底基板上形成有源图案层,所述有源图案层包括:至少一条第一导体化连接线;在所述有源图案层远离所述衬底基板的一侧形成第一导电层,所述第一导电层包括:沿第一方向延伸的至少一条连接线,和沿所述第一方向排列且沿第二方向延伸的多条初始化信号线,每条初始化信号线的一端与一条连接线耦接;其中,所述第一方向与所述第二方向交叉;一条所述第一导体化连接线与至少两条初始化信号线耦接,其中,所述至少两条初始化信号线与同一条连接线耦接。
- 根据权利要求17所述的制备方法,其中,所述在衬底基板上形成有源图案层包括:在所述衬底基板上形成至少一条半导体连接线,并且将所述至少一条半导体连接线导体化,得到包括至少一条第一导体化连接线的有源图案层。
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- 2021-11-23 WO PCT/CN2021/132565 patent/WO2022242081A1/zh active Application Filing
- 2021-11-23 US US17/920,156 patent/US20240224640A1/en active Pending
Patent Citations (4)
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US20180217393A1 (en) * | 2017-02-01 | 2018-08-02 | Oculus Vr, Llc | Spherical display using flexible substrates |
CN110599963A (zh) * | 2019-09-25 | 2019-12-20 | 京东方科技集团股份有限公司 | 像素驱动电路、阵列基板、显示装置及像素驱动方法 |
CN111584610A (zh) * | 2020-06-10 | 2020-08-25 | 京东方科技集团股份有限公司 | 一种显示面板及显示装置 |
CN113299712A (zh) * | 2021-05-21 | 2021-08-24 | 京东方科技集团股份有限公司 | 显示面板及其制备方法、显示装置 |
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