WO2022229830A1 - Procédé de réalisation d'une structure d'interconnexion à plots entre microcircuits - Google Patents
Procédé de réalisation d'une structure d'interconnexion à plots entre microcircuits Download PDFInfo
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- WO2022229830A1 WO2022229830A1 PCT/IB2022/053844 IB2022053844W WO2022229830A1 WO 2022229830 A1 WO2022229830 A1 WO 2022229830A1 IB 2022053844 W IB2022053844 W IB 2022053844W WO 2022229830 A1 WO2022229830 A1 WO 2022229830A1
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- Prior art keywords
- layer
- pads
- metal
- dielectric material
- circuit
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 45
- 229910052751 metal Inorganic materials 0.000 claims abstract description 29
- 239000002184 metal Substances 0.000 claims abstract description 29
- 239000003989 dielectric material Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 16
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000005516 engineering process Methods 0.000 claims abstract description 8
- 238000011049 filling Methods 0.000 claims abstract description 3
- 238000003825 pressing Methods 0.000 claims abstract description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 13
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- 229910045601 alloy Inorganic materials 0.000 claims description 9
- 239000000956 alloy Substances 0.000 claims description 9
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 6
- 239000003870 refractory metal Substances 0.000 claims description 5
- 239000000919 ceramic Substances 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000377 silicon dioxide Substances 0.000 claims description 2
- 238000001465 metallisation Methods 0.000 abstract 1
- 238000009396 hybridization Methods 0.000 description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 11
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000013459 approach Methods 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 229910052737 gold Inorganic materials 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 239000011810 insulating material Substances 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000008188 pellet Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 2
- 239000011324 bead Substances 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011133 lead Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000004626 scanning electron microscopy Methods 0.000 description 2
- 229910052720 vanadium Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000002998 adhesive polymer Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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Definitions
- the present invention generally relates to a method for producing miniaturized interconnection networks based on protruding conductive micro-bumps ("micro-bumps” in English terminology) in particular in chip circuit assembly technologies. turned over (“flip-chip” in Anglo-Saxon terminology).
- connection network between two circuits when they are assembled one above the other. These connections can be very dense, and this technique is widely used today in electronic products such as display screens, integrated circuits with a very large number of inputs-outputs, and especially CCD hybrid matrix image sensors. /C-MOS.
- metal studs are made either on one of the two circuits, or on both, for example by one of the following techniques:
- an adhesive of the ACA type for Anisotropic Conductive Adhesive in Anglo-Saxon terminology
- ACA type for Anisotropic Conductive Adhesive in Anglo-Saxon terminology
- the density and size of the conductive beads are chosen according to the pitch and the geometry of the interconnections so that at least one conductive ball is present in line with each pad; when the two circuits are assembled under high temperature, the pressure exerted on them deforms the balls and the studs and the polymerization of the adhesive is carried out at the same time to fix the two circuits together;
- the present invention aims to provide an industrially viable solution, easily integrated into a C-MOS circuit manufacturing process, to achieve on the one hand interconnections by salient pads with very high densities, and on the other hand, during same steps, connection pads for connecting wires when integrating the circuits in a box provided with connection elements.
- a method for manufacturing an electronic circuit in C-MOS technology is proposed for this purpose, the method comprising:
- Steps (a) to (d) being repeated to form metal connections at different depth levels, connected by interconnection vias in the thickness of the circuit, the method being characterized in that it further comprises an iteration of step (a) to simultaneously form:
- the conductive elements constitute interconnection pads with homologous conductive pads of the other circuit.
- steps (b) to (d) to form a set of individualized conductive elements surmounted by columns of said interconnecting metal contained in a layer of dielectric material
- said interconnect metal is a refractory metal or an alloy based on refractory metal.
- said interconnect metal is tungsten or a tungsten-based alloy.
- the dielectric material is silicon dioxide.
- the metal deposit constituting said metal connections comprises a main layer of aluminum or cupro-aluminum and at least one secondary layer of ceramic such as titanium nitride, covering the main layer.
- the method comprises a step of eliminating the secondary layer at the level of the bonding pads.
- step (a) the step of eliminating the secondary layer at the level of the bonding pads is implemented before the iteration of step (a).
- step (a) the step of eliminating the secondary layer at the level of the bonding pads is implemented after the iteration of step (a).
- the method comprises a step of eliminating the dielectric material and the material of the secondary layer at the level of the bonding pads to form cavities where the main layer is exposed.
- the method includes a step of depositing a layer of additional dielectric material covering the columns before the step of removing the dielectric material and the secondary layer.
- Fig. 1 illustrates different steps implemented in a method for producing a conventional C-MOS circuit
- FIG. 2 illustrates iterations of certain steps of a C-MOS process to produce interconnection pads with another circuit
- FIG. 2 illustrates a variant of the steps of FIG. 2,
- FIG. 3 is a microscopic photograph of an experimental interconnect pad structure obtained with the method of FIG. 2,
- FIG. 4 illustrates iterations of certain steps of a C-MOS process to produce interconnection columns with another circuit
- - Fig. 4' illustrates a variant of the steps of FIG. 4
- - Fig. 5 is a microscopic photograph of an experimental interconnect column structure obtained with the method of FIG. 4.
- C-MOS circuit manufacturing processes use aluminum as the bonding layer base metal within a level and a refractory metal or alloy such as tungsten as the metal for interconnection between the different levels.
- step (A) consists in producing on a substrate of dielectric insulating material 100, typically S1O2, a layer 200 intended to form conductive tracks P at the same level of depth, this layer comprising three sandwich sub-layers namely, from bottom to top, a first layer 221 of ceramic material such as titanium nitride TiN forming an adhesion and diffusion barrier layer, a central layer 210 of aluminum-copper alloy with a high aluminum content ( it will be called in the following “aluminum layer” by convention), and second layer 222, upper, of ceramic material, here again for example TiN.
- a first layer 221 of ceramic material such as titanium nitride TiN forming an adhesion and diffusion barrier layer
- a central layer 210 of aluminum-copper alloy with a high aluminum content it will be called in the following “aluminum layer” by convention
- second layer 222 upper, of ceramic material, here again for example TiN.
- the following steps include a photolithography step to define the patterns of the interconnection tracks P to be produced, followed by a step of selective etching of the areas left free by the photolithography.
- Step (B) consists in covering the assembly with another layer of dielectric insulating material 110, here again in S1O2, which extends layer 100 upwards over a given thickness.
- This layer 110 undergoes a finish by chemical-mechanical polishing (CMP) in order to obtain a flat surface at the atomic scale.
- CMP chemical-mechanical polishing
- the next step (C) consists in producing in the layer of dielectric material 110, in positions which will determine the electrical connections between layers in the thickness of the substrate, holes 112 to a depth reaching the conductive tracks P under adjacent, by a conventional process of lithography and etching.
- step (D) a layer of tungsten 300 is deposited so as to fill the holes at 310, overflowing in a continuous layer 320 above the free surface of the substrate 100.
- step (E) the excess tungsten that constitutes this continuous layer 320 is typically eliminated by mechanical-chemical polishing, to leave only the parts 310 occupying the holes 112 and forming interconnection vias between spaced conductive layers in the thickness of the substrate (“W-Plug” in Anglo-Saxon terminology).
- step (G) also includes the deposition of a layer of passivation 400 to complete the circuit.
- This layer 400 is typically composed of a layer of dielectric insulating material in S1O2 surmounted by a layer of silicon nitride SiN in order in particular to provide protection against humidity.
- a lithography step and an etching step make it possible to produce cavities 410 by local removal of the layers 400 and 120 of dielectric material and of the ceramic layer 222, cavities in which the metal or alloy of the underlying layer 210 is exposed to form bonding pads PB for the connection of bonding wires, typically in gold, with pins or other circuit connection elements with the external environment (“wire bonding” in Anglo-Saxon terminology).
- One aspect of the present invention consists in relying on this conventional process to produce salient connection pads with another circuit in order to carry out a hybridization, namely the connection with a very fine pitch, for example between a C-MOS circuit obtained by a process as explained above and a circuit for example analog, more particularly a circuit of pixels accumulating electrical charges of photonic origin forming an image sensor, this being in no way limiting.
- vias V were made at chosen positions and a subsequent and final layer 200F of TiN/Al/TiN similar to layer 200 was applied as described previously, the three thicknesses of this layer being designated by 221F, 210F and 222F.
- step (B) the layer 222F of TiN is eliminated by selective etching to form areas 230 where the metal 210 is exposed and to form pads PB for bonding wires, generally arranged peripherally.
- step (C) the combination of a photolithography and etching step makes it possible to selectively remove the 200F layer to leave on the free surface of the substrate a set of projecting pads PL for interconnection with another circuit, as well as than the PB studs for connecting wires.
- a circuit is produced equipped on its free face with a portion of pads PB for connecting wires, devoid of the upper layer of TiN 222F to allow the soldering of the son, and on the other hand salient interconnection pads PL for the hybridization of the circuit with another circuit.
- the flatness of the hybridization pads PL is here excellent due to the nature of the steps implemented, and in particular due to the fact that the surface 110 on which the final metallic layer 200F has been deposited has been the subject of mechanical-chemical polishing and that the deposition of the layers 221F, 210F and 222 of the sandwich can be carried out with excellent precision in thickness.
- the ceramic layer 222F such as TiN which covers each of the pads PL is reputed to have excellent chemical stability. Thus, even in the case where these PL pads are exposed before carrying out the hybridization, their free surface is not subject to oxidation.
- step (B') photolithography and etching made it possible to delimit the bonding pad PB and the hybridization pads PL
- step (C') the upper layer 222F of TiN was partially eliminated at the bonding pad PB to allow a bonding wire to be welded.
- Fig. 2 will generally be preferred because in this case the lithography and etching steps to remove the 222F layer from the bond pads are performed on a flat surface, with easier and more efficient spin-coating, both said and that in the approach of Fig. 2’ we must work with an irregular surface, more prone to manufacturing defects.
- Fig. 3 is a scanning electron microscopy (SEM) view of a hybrid circuit with the pads produced according to the method of FIG. 2.
- steps derived from those used in C-MOS technology are again used to produce hybridization pads having very good flatness and at the same time an excellent ability to compensate for flatness defects in the other circuit.
- step (A) at the level of the last conductive layer, a set of conductive pads P′” was produced, with two pads intended to be connected to hybridization pads and one pad intended to form a pad PB for bond wire welding.
- CO columns were also produced by the same process as that implemented to produce the vias V, above the two hybridization pads, by deposition of tungsten to fill the cavities 112 formed in the last layer 140 of dielectric material (part 310 of the deposited metal) and overflow above the dielectric material (part 320 of the deposited metal), this latter part having been eliminated by mechanical-chemical polishing.
- the flatness of the free faces of the CO column vias is thus excellent.
- the pellet intended to form a bonding pad PB is itself, at this stage, completely embedded in the dielectric insulating material 140.
- step (B) a cavity 141 is hollowed out by lithography and etching above the bonding pad PB so as to remove in this zone the entire thickness of the dielectric material 140 as well as the upper layer 222F of TiN thereby exposing layer 210F to which a bonding wire can be soldered.
- step (C) part of the thickness of the dielectric insulator 140 is removed, by dry etching or chemical etching, chosen to preserve the tungsten parts 310, so as to make the columns CO protruding above above the remaining dielectric material and thus form narrow, protruding tungsten pads for interconnection with the other circuit.
- This removal of the dielectric material 140 can be done up to an intermediate level between the upper face and the lower face of the pads conductors P'”.
- the etching conditions are also chosen to preserve the material of the layers 221F and 222F (TiN typically) and 210 (aluminum or aluminum copper alloy typically). It is possible, for example, to choose etching with hydrofluoric acid vapor or etching of the BOE (“Buffered Oxide Etch”) type.
- the conductive pads can be left entirely embedded in the dielectric material.
- the fact that the base of the CO columns is retained in the dielectric material can contribute to their mechanical robustness when assembling the two circuits.
- the CO columns thus form hybridization pads of great hardness and low cross-section, with at the same time excellent flatness of their vertices, to thus achieve a quality contact with the other circuit during the contacting phase.
- the process described allows the tops of the columns to deviate at most by a distance of the order of 50 to 2000 nm from an “ideal” common plane.
- the small cross-section of the columns CO and their high hardness makes it possible to some extent to overcome flatness defects at the level of the contacts of the other circuit.
- the two circuits are brought closer to each other with a view to assembling them, by exerting a certain pressure force between them, the columns CO come into contact with the contact pads of the other circuit, generally made with a more ductile metal.
- This variant is illustrated in Fig. 4'. It consists in step (A') of producing a layer of dielectric material 150 above the free layer obtained after the mechanical-chemical polishing which followed the deposition of tungsten.
- the cavity 141 is then hollowed out in the layers 150 then 140, also removing the layer 222F (step (B′)) to form the cavity, to obtain the same configuration of bonding pad PB as in the case of FIG. 4.
- Fig. 5 represents, by way of illustration, a P’” pellet surmounted by two CO columns in scanning electron microscopy.
- the present invention makes it possible to produce high density hybridization plots
- two or more CO columns can be provided in line with each pair of conductive pads of the other circuit. This in particular makes it possible to further limit the cross-section of each column and to facilitate the deformation of the pads of the other circuit when it is made necessary by columns projecting beyond the ideal plane.
- the permanent attachment of the circuits to each other can be achieved for example by applying an adhesive polymer interposed between the two circuits, or simply by molecular bonding thanks to the Van der Vais forces generated by a surface contact between the circuits.
- the method may comprise an additional step consisting in making trenches by etching between the contact pads PL (Figs. 2 and 2') or the columns CO (Figs. 4 and 4'), in particular so as to facilitate the escape of excess adhesive, without it does not obstruct the proper assembly and proper contacting of the two circuits.
- an annealing step can be provided to reinforce the covalent bonds between the two surfaces and therefore the strength of the assembly.
- the minimum dimension of the conductive pads and therefore of the PL hybridization pads in the embodiments of Figs. 2 and 2′ is of the order of 0.28 ⁇ m, while the dimension of the interlevel contact vias and therefore of the columns CO In the embodiments of Figs. 4 and 4' is generally 0.24 ⁇ m to 0.28 ⁇ m.
- the conductive pads of the other circuit are made of gold.
- the Young's modulus of gold being 78 Gpa, then for a column with a cross section of 0.3 ⁇ m x 0.3 ⁇ m, the insertion force necessary for each stud so as to compensate for the inequalities of height between the tops of the columns can be estimated at 0.07 mN (millinewton).
- the total force required is only of the order of 70 N.
- the conductive pads of the other circuit can be made of aluminum or copper.
- the conductive pads of the other circuit can be made of aluminum or copper.
- its Young's modulus being 69 Gpa, the effect obtained in terms of force reduction is even better than that obtained for gold.
- the invention applies in particular to the assembly and connection of all circuits requiring high-density electrical connections, in particular hybrid circuits combining an analog circuit (for example, but not limited to, an analog circuit of sensors accumulating charges of photonic origin) with a reading and processing circuit in C-MOS technology.
- an analog circuit for example, but not limited to, an analog circuit of sensors accumulating charges of photonic origin
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Abstract
Description
Claims
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160021743A1 (en) * | 2014-07-17 | 2016-01-21 | Siliconware Precision Industries Co., Ltd. | Coreless packaging substrate and fabrication method thereof |
WO2016064510A1 (fr) * | 2014-10-22 | 2016-04-28 | Sandisk Technologies Inc. | Boîtier de semi-conducteur avec des interconnexions électriques doubles de deuxième niveau |
US20210035878A1 (en) * | 2019-07-31 | 2021-02-04 | Samsung Electronics Co., Ltd. | Semiconductor package |
US20210111125A1 (en) * | 2019-10-09 | 2021-04-15 | Industrial Technology Research Institute | Multi-chip package and manufacture method thereof |
US20210118786A1 (en) * | 2019-10-16 | 2021-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conductive structure, semiconductor package and methods of forming the same |
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2022
- 2022-04-26 WO PCT/IB2022/053844 patent/WO2022229830A1/fr active Application Filing
- 2022-04-26 CN CN202280031111.1A patent/CN117461125A/zh active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20160021743A1 (en) * | 2014-07-17 | 2016-01-21 | Siliconware Precision Industries Co., Ltd. | Coreless packaging substrate and fabrication method thereof |
WO2016064510A1 (fr) * | 2014-10-22 | 2016-04-28 | Sandisk Technologies Inc. | Boîtier de semi-conducteur avec des interconnexions électriques doubles de deuxième niveau |
US20210035878A1 (en) * | 2019-07-31 | 2021-02-04 | Samsung Electronics Co., Ltd. | Semiconductor package |
US20210111125A1 (en) * | 2019-10-09 | 2021-04-15 | Industrial Technology Research Institute | Multi-chip package and manufacture method thereof |
US20210118786A1 (en) * | 2019-10-16 | 2021-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conductive structure, semiconductor package and methods of forming the same |
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