WO2022227339A1 - 晶圆研磨方法及晶圆失效分析方法 - Google Patents
晶圆研磨方法及晶圆失效分析方法 Download PDFInfo
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- WO2022227339A1 WO2022227339A1 PCT/CN2021/112272 CN2021112272W WO2022227339A1 WO 2022227339 A1 WO2022227339 A1 WO 2022227339A1 CN 2021112272 W CN2021112272 W CN 2021112272W WO 2022227339 A1 WO2022227339 A1 WO 2022227339A1
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- wafer
- dicing
- layer
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- 238000000227 grinding Methods 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000004458 analytical method Methods 0.000 title claims description 18
- 239000010410 layer Substances 0.000 claims abstract description 88
- 239000011241 protective layer Substances 0.000 claims abstract description 56
- 239000003292 glue Substances 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 14
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000002245 particle Substances 0.000 claims description 4
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 125000004122 cyclic group Chemical group 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 description 89
- 230000008569 process Effects 0.000 description 14
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 230000002093 peripheral effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 239000007788 liquid Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000013543 active substance Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000008521 reorganization Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
Definitions
- the present application relates to the technical field of semiconductor manufacturing, and in particular, to a wafer grinding method and a wafer failure analysis method.
- the failure analysis is usually to grind the wafer by chemical mechanical polishing. After the positioning point or the fault point (ie the test address) is exposed, the nano probe is used to test and analyze the positioning point or the fault point.
- the test address for failure analysis is usually located at the peripheral gate (PG) layer in the edge region of the wafer, and multiple metal interconnect layers are usually formed on the peripheral gate layer.
- the wafer is ground to expose the peripheral gate layer.
- the connection layer cannot be completely clear, and the residual metal layer is easily conductively connected with other metals with uncertain factors, causing gate body leakage (Gate-Body Leakage), which ultimately affects the accuracy and reliability of the test results.
- Gate-Body Leakage gate body leakage
- a wafer grinding method and a wafer failure analysis method provided by some embodiments of the present application are used to solve the problem of poor wafer grinding quality, so as to improve the accuracy and reliability of subsequent failure analysis.
- the present application provides a wafer grinding method, comprising the following steps:
- an initial wafer comprising a plurality of bare chips, and having test addresses in the bare chips located at the edges of the initial wafer;
- test address is exposed, if not, the exposed next layer is used as the current layer of the next cycle step.
- the present application also provides a wafer failure analysis method, comprising the following steps:
- test address is tested for failure using nanoprobes.
- the initial wafer to be ground is split and reorganized, and the position of the bare chip with the test address is adjusted to the middle of the reorganized wafer, thereby avoiding the need for The problem of grinding slope is prone to occur due to the edge position of the die with the test address.
- the protective layer is covered above the test address, after the other areas are ground, the protective layer is removed, and the area above the test address is separately ground in a small range, so that the test address can be It can be exposed completely and flatly, and there is no problem of bridging the metal interconnection layer above the test address, reducing or even avoiding the leakage problem of the gate body.
- 2A-2H are main schematic diagrams in the process of grinding wafers in the specific embodiment of the present application.
- FIG. 1 is a flowchart of the wafer grinding method in the specific embodiment of the present application
- FIGS. 2A-2H are the main steps in the process of grinding the wafer in the specific embodiment of the present application.
- step S11 an initial wafer 20 including a plurality of bare chips is provided, and the bare chips located at the edge of the initial wafer 20 have test addresses 21 , as shown in FIG. 2A .
- the initial wafer 20 has a plurality of the bare chips arranged in an array.
- the initial wafer 20 includes 16 bare chips arranged in a two-dimensional array (ie, the first die 200 to sixteenth die 215 ), wherein the sixteenth die 215 located at the edge of the initial wafer 20 has a test address 21 for failure analysis.
- Each of the bare chips has a plurality of active areas (AA) arranged in an array, and each of the active areas has a plurality of stacked in a direction perpendicular to the initial wafer 20 .
- AA active areas
- test address 21 is usually set inside the bare chip to prevent the test address 21 from being affected by the external environment.
- the test address 21 may be the peripheral gate layer or the gate contact layer.
- the multiple mentioned in this specific embodiment refers to two or more.
- Step S12 splitting and reassembling a plurality of the bare chips to form a reconstituted wafer 30 , so that the bare chip with the test address 21 is located in the middle of the reconstituted wafer 30 , as shown in FIG. 2B .
- the initial wafer 20 has a plurality of scribe lines 22 for dividing the adjacent bare chips; the specific steps of forming the reconstituted wafer 30 include:
- a plurality of the dicing blocks are spliced to form a reconstituted wafer 30 , so that the bare chip with the test address 21 is located in the middle of the reconstituted wafer 30 .
- the polishing speed of the wafer edge position is faster, so that a slope is easily formed on the wafer edge.
- the initial wafer 20 is cut along the dicing road, the initial wafer 20 is divided into a plurality of cutting blocks, and then the reconstituted wafer 30 is formed by arranging and recombining, so that the reconstituted wafer 30 has the The position of the bare chip of the test address 21 is located in the middle of the reconstituted wafer 30 , so as to avoid the problem that the test address 21 is located at the edge of the wafer and a grinding slope is easily generated during the grinding process.
- the initial wafer 20 is cut along the dicing lane 22 by cutting the initial wafer 20 along only one dicing lane 22 to form two dicing blocks; or, it can also be cut along a plurality of strips Lane 22 cuts the initial wafer 20 to form a plurality of dicing blocks.
- the specific steps of forming the plurality of cutting blocks include:
- the initial wafer 20 is diced along a dicing road located in the middle of the initial wafer 20 to form a first dicing block 231 and a second dicing block 232 , and the edge of the first dicing block 231 includes a dicing block having the test address 21 . the bare chip.
- the present embodiment cuts the initial wafer 20 along the middle of the initial wafer 20, and divides the initial wafer 20 into equal parts into the first cutting block 231 and the second cutting block 231. Cutting block 232 . Then, the edge of the first cutting block 231 with the test address 21 is spliced with the edge of the second cutting block 232 to form the reconstituted wafer 30 , as shown in FIG. 2B .
- the specific steps of splicing the first cutting block 231 and the second cutting block 232 include:
- the first cutting block 231 and the second cutting block 232 are pasted on the surface of the substrate 24 , and the first cutting block 231 and the second cutting block 232 are bonded.
- the specific steps of adhering the first cutting block 231 and the second cutting block 232 to the surface of the substrate 24 and adhering the first cutting block 231 and the second cutting block 232 include: :
- the base 24 is used to support and carry the first cutting block 231 and the second cutting block 232.
- the first curing glue is applied to the area of the surface of the substrate 24 for carrying the first cutting block 231 and the second cutting block 232
- the first cutting block 231 and the second cutting block 232 are cut
- the blocks 232 are aligned on the surface of the substrate 24
- the edge of the first cutting block 231 with the test address 21 is aligned and connected to the edge of the second cutting block 232 .
- the substrate 24 is baked to cure the first curing glue.
- the baking time is determined according to the type of the first curing glue and the applied dose of the first curing glue, for example, it can be 20 minutes. After baking, the substrate is allowed to cool naturally, eg, left to cool for 5 minutes.
- the second dicing block 232 is connected with the edge of the first dicing block 231 having the test address 21. On the one hand, it can prevent the first dicing block 231 from grinding during the grinding process. The problem of chipping caused by pressure; on the other hand, the second cutting block 232 can also improve the flatness during the grinding process of the area above the test address 21, and subsequently form a protective layer above the test address 21 At 26 , the protective layer 26 is supported to ensure that the protective layer 26 can effectively cover the area above the test address 21 .
- the top surface of the second cutting block 232 after bonding is lower than the top surface of the first cutting block 231 or the top surface of the second cutting block 232 after bonding is lower than the top surface of the second cutting block 232 after bonding.
- the top surface of a cutting block 231 is flush.
- the protection layer 26 formed later can be improved. flatness, thereby further improving the final wafer grinding effect.
- step S13 a protective layer 26 is formed on the exposed current layer 25 of the reconstituted wafer 30 , and the protective layer 26 is located at least above the test address 21 , as shown in FIG. 2C .
- the specific steps of forming the protective layer 26 on the exposed current layer 25 of the reconstituted wafer 30 include:
- the second cured adhesive is baked to form a protective layer 26 .
- the existence of the second cutting block 232 can effectively prevent the second curing glue from being adsorbed from the surface of the first cutting block 231 to the surface of the substrate 24 during the baking process, ensuring effective
- the protective layer 26 is formed on the surface of the first cutting block 231.
- the first curing glue and the second curing glue are of the same type.
- the first curing glue and the second curing glue are mixed glues composed of epoxy resin and curing agent.
- the protective layer 26 covers the bare chip with the test address 21 , the gap between the first dicing block 231 and the second dicing block 232 , and the second dicing block 232 .
- the first cutting block 231 and the second curing glue are of the same type, and both are made by mixing epoxy resin and curing agent in a weight ratio of 9:1.
- Step S14 grinding the current layer 25 in the reconstituted wafer 30 that is not covered by the protective layer 26 to expose the next layer 27 adjacent to the current layer 26 , as shown in FIG. 2D .
- step S15 the protective layer 26 and the current layer 25 remaining under the protective layer 26 are removed, and the next layer 27 located under the protective layer 26 is exposed, as shown in FIG. 2F .
- Step S16 it is judged whether the test address 21 is exposed, if not, the exposed next layer 27 is used as the current layer in the next cycle step. If it is determined that the test address has been completely exposed, step S17 is performed, that is, the looping step is ended.
- the specific steps of grinding the current layer 25 not covered by the protective layer 26 in the reconstituted wafer 30 include:
- the first cutting block 231 is not covered by the protective layer 26 from the edge of the first cutting block 231 away from the second cutting block 232 . chemical mechanical polishing of the area.
- the grinding liquid can be selected according to the specific material of the current layer 25 .
- the current layer 25 is the third metal interconnection layer, and a mixed liquid of silicon dioxide with a particle size of 0.5 ⁇ m and a pH of 9 and an active agent can be used as the grinding liquid.
- the specific steps of removing the protective layer 26 and the current layer 25 remaining under the protective layer 26 include:
- the preset range is greater than or equal to the length of one bare chip and less than or equal to the sum of the lengths of three bare chips.
- the protection function of the address 21 is to test whether the lateral distance between the edge 271 of the exposed next layer 27 facing the second cutting block 232 and the address 21 enters the preset range, and if so, stop After the current CMP process, the protective layer 26 and the current layer 25 remaining under the protective layer 26 are removed.
- the size of each bare chip on the reconstituted wafer 30 is the same. For example, when the lateral distance between the exposed edge of the next layer 27 and the test address 21 is equal to the sum of the lengths of 2 bare chips, the current CMP process is stopped.
- the length of the bare chip refers to the length of the bare chip along the direction of the first dicing block 231 to the second dicing block 232 .
- the lateral distance between the edge of the next layer 27 and the test address 21 refers to the difference between the projection of the edge 271 of the exposed first layer 27 facing the second cutting block 232 on the substrate 24 .
- the distance between the projections of the test address 21 on the substrate 24 is not limited to the length of the bare chip along the direction of the first dicing block 231 to the second dicing block 232 .
- the specific steps of removing the protective layer 26 and the current layer 25 remaining under the protective layer 26 include:
- the protective layer 26 is removed by grinding with sandpaper
- the remaining current layer 25 is removed using a grinder.
- the sandpaper is diamond sandpaper with a particle size of 0.5 ⁇ m or 1 ⁇ m.
- the grinding speed of the grinding machine is below 150 rpm.
- diamond sandpaper with a particle size of 0.5 ⁇ m or 1 ⁇ m may be used to gently grind off all the protective layers 26 to expose the current layer 25 under the protective layers 26 . Then, the grinder lightly polishes the exposed current layer 25 at a grinding speed of less than 150 rpm until the next layer 27 located below the position of the protective layer 26 is exposed.
- FIG. 2G is a schematic diagram of the test address 21 exposed after grinding.
- the gate contact layer 29 above the peripheral gate layer 28 can be completely exposed, thereby ensuring the smooth progress of subsequent wafer failure analysis.
- 2H is a schematic diagram of the leakage current of the gate body after grinding.
- the abscissa in FIG. 2H represents the magnitude of the gate applied voltage (V), and the ordinate represents the magnitude of the gate body leakage current (A).
- V gate applied voltage
- A the leakage current of the gate body
- the leakage current of the gate body can be reduced from ⁇ A level to pA level, which greatly improves the leakage current problem of the gate body.
- the present application also provides a wafer failure analysis method.
- the wafer grinding method shown in FIG. 1 and FIGS. 2A-2H can be used to grind the wafer for failure analysis.
- the wafer failure analysis method includes the following steps:
- test address is tested for failure using nanoprobes.
- the position of the bare chip with the test address is adjusted to the middle of the reconstituted wafer, thereby avoiding the The die with the test address is at the edge and is prone to the problem of grinding slope.
- the protective layer is covered above the test address, after the other areas are ground, the protective layer is removed, and the area above the test address is separately ground in a small range, so that the test address can be It can be exposed completely and flatly, and there is no problem of bridging the metal interconnection layer above the test address, reducing or even avoiding the leakage problem of the gate body.
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Abstract
晶圆研磨方法包括如下步骤:提供边缘具有测试地址(21)的初始晶圆(20);形成测试地址(21)位于中部的重组晶圆(30);进行如下循环步骤:于重组晶圆(30)的当前层(25)上形成至少位于测试地址(21)上方的保护层(26);研磨未被覆盖的当前层(25);去除保护层(26)和残留的当前层(25);判断测试地址(21)是否暴露,若否,则进行下一次循环步骤。本申请能够减少栅极本体的漏电问题。
Description
相关申请引用说明
本申请要求于2021年4月28日递交的中国专利申请号202110465899.4、申请名为“晶圆研磨方法及晶圆失效分析方法”的优先权,其全部内容以引用的形式附录于此。
本申请涉及半导体制造技术领域,尤其涉及一种晶圆研磨方法及晶圆失效分析方法。
失效分析通常是采用化学机械研磨的方式对晶圆进行研磨,在暴露定位点或者故障点(即测试地址)之后,采用纳米探针对定位点或者故障点进行测试分析。
失效分析的测试地址通常位于晶圆边缘区域的***栅极(Peripheral Gate,PG)层,在所述***栅极层上通常还形成有多个金属互连层,因此,在失效分析之前需要对晶圆进行研磨,以暴露所述***栅极层。但是,在对晶圆研磨的过程中,由于晶圆边缘区域的研磨速度较快,导致在晶圆的边缘区域易形成倾斜面(即具有坡度),使得与测试地址相邻的一层金属互连层不能被完全清楚,残留的金属层易与其他具有不定性因素的金属导电连接而引起栅极本体漏电(Gate-Body Leakage),最终影响测试结果的准确性和可靠性。而且,采用传统的晶圆研磨方法研磨之后,只能暴露出小部分的测试地址,残留的金属互连层之间会出现破坏性的桥接,进而也会引起栅极本体的漏电。
因此,如何改善晶圆研磨质量,提高后续失效分析的准确性和可靠性,是当前亟待解决的技术问题。
发明内容
本申请一些实施例提供的一种晶圆研磨方法及晶圆失效分析方法,用于解决晶圆研磨质量较差的问题,以提高后续失效分析的准确性和可靠性。
根据一些实施例,本申请提供了一种晶圆研磨方法,包括如下步骤:
提供包括多个裸芯片的初始晶圆,且位于所述初始晶圆边缘的裸芯片中具 有测试地址;
拆分并重组多个所述裸芯片,形成重组晶圆,使得具有所述测试地址的裸芯片位于所述重组晶圆的中部;
进行至少一次如下循环步骤,所述循环步骤包括:
于所述重组晶圆暴露的当前层上形成保护层,所述保护层至少位于所述测试地址上方;
研磨所述重组晶圆中未被所述保护层覆盖的所述当前层,暴露与所述当前层相邻的下一层;
去除所述保护层和所述保护层下方残留的所述当前层,暴露位于所述保护层下方的所述下一层;
判断所述测试地址是否暴露,若否,则以暴露的所述下一层作为下一次循环步骤的当前层。
根据另一些实施例,本申请还提供了一种晶圆失效分析方法,包括如下步骤:
采用上述任一项所述的晶圆研磨方法对晶圆进行研磨,暴露测试地址;
采用纳米探针对所述测试地址进行失效测试。
本申请一些实施例提供的晶圆研磨方法及晶圆失效分析方法,通过对待研磨的初始晶圆进行拆分重组,将具有测试地址的裸芯片的位置调整至重组晶圆的中部,从而避免了因具有测试地址的裸芯片处于边缘位置而导致易出现研磨坡度的问题。而且,本申请通过在研磨其他区域的过程中,覆盖保护层于测试地址上方,在其他区域研磨之后,去除保护层,单独再对测试地址上方的区域进行小范围的研磨,从而能够使得测试地址能够完整、平坦的暴露,测试地址上方也不会出现金属互连层桥接的问题,减少甚至是避免了栅极本体的漏电问题。
附图1是本申请具体实施方式中晶圆研磨方法的流程图;
附图2A-2H是本申请具体实施方式在研磨晶圆的过程中主要的示意图。
下面结合附图对本申请提供的晶圆研磨方法及晶圆失效分析方法的具体实施方式做详细说明。
本具体实施方式提供了一种晶圆研磨方法,附图1是本申请具体实施方式中晶圆研磨方法的流程图,附图2A-2H是本申请具体实施方式在研磨晶圆的过程中主要的示意图。如图1、图2A-图2H所示,本具体实施方式提供的晶圆研磨方法,包括如下步骤:
步骤S11,提供包括多个裸芯片的初始晶圆20,且位于所述初始晶圆20边缘的裸芯片中具有测试地址21,如图2A所示。
具体来说,所述初始晶圆20上具有呈阵列排布的多个所述裸芯片,图1以所述初始晶圆20中包括呈二维阵列排布的16个裸芯片(即第一裸芯片200至第十六裸芯片215),其中,位于所述初始晶圆20边缘的所述第十六裸芯片215中具有用于失效分析的测试地址21。每个所述裸芯片中具有呈阵列排布的多个有源区(Active Area,AA),每个所述有源区中具有若干沿垂直于所述初始晶圆20的方向叠置的多个半导体层,例如***栅极层、位于所述***栅极层上方的栅极接触层、位于所述栅极接触层上方的第一金属互连层、位于所述第一金属互连层上方的第一接触插塞、位于所述第一接触插塞上方的第二金属互连层、位于所述第二金属互连层上方的第二接触插塞等。为了确保测试结果的准确性,通常将所述测试地址21设置在所述裸芯片的内部,避免所述测试地址21受外界环境的影响,例如,所述测试地址21可以为所述***栅极层或者所述栅极接触层。本具体实施方式中所述的多个是指两个及两个以上。
步骤S12,拆分并重组多个所述裸芯片,形成重组晶圆30,使得具有所述测试地址21的裸芯片位于所述重组晶圆30的中部,如图2B所示。
在一示例中,所述初始晶圆20上具有若干条用于分割相邻所述裸芯片的切割道22;形成重组晶圆30的具体步骤包括:
沿所述切割道22切割所述初始晶圆20,形成多个切割块,每个所述切割块中具有若干所述裸芯片;
拼接多个所述切割块,形成重组晶圆30,使得具有所述测试地址21的所述裸芯片位于所述重组晶圆30的中部。
由于在化学机械研磨的过程中,晶圆边缘位置研磨速度较快,从而易在晶圆的边缘形成坡度。本具体实施方式通过沿所述切割道切割所述初始晶圆20,将所述初始晶圆20分割为多个切割块,然后通过排列、重组,形成所述重组晶圆30,使得具有所述测试地址21的所述裸芯片的位置位于所述重组晶圆30的中部,从而避免了所述测试地址21位于晶圆边缘而易在研磨过程中出现研磨坡度的问题。本具体实施方式中沿所述切割道22切割所述初始晶圆20,可以是仅沿一条切割道22切割所述初始晶圆20,形成两个切割块;或者,也可以是沿多条切割道22切割所述初始晶圆20,形成多个切割块。
在一示例中,形成多个切割块的具体步骤包括:
沿位于所述初始晶圆20中间的切割道切割所述初始晶圆20,形成第一切割块231和第二切割块232,所述第一切割块231的边缘包括具有所述测试地址21的所述裸芯片。
为了简化切割、重组步骤,本具体实施方式沿所述初始晶圆20的中间切割所述初始晶圆20,将所述初始晶圆20等分为所述第一切割块231和所述第二切割块232。之后,将所述第一切割块231中具有所述测试地址21的一侧边缘与所述第二切割块232的边缘拼接,形成所述重组晶圆30,如图2B所示。
在一示例中,拼接所述第一切割块231和所述第二切割块232的具体步骤包括:
提供基底24;
粘贴所述第一切割块231和所述第二切割块232于所述基底24表面,并粘合所述第一切割块231和所述第二切割块232。
在一示例中,粘贴所述第一切割块231和所述第二切割块232于所述基底24表面,并粘合所述第一切割块231和所述第二切割块232的具体步骤包括:
涂布第一固化胶于所述基底24表面;
放置所述第一切割块231和所述第二切割块232于所述基底24表面,且所述第一切割块231的边缘与所述第二切割块232的边缘对齐连接;
烘烤所述第一固化胶。
具体来说,所述基底24用于支撑和承载所述第一切割块231和所述第二 切割块232。在所述基底24表面用于承载所述第一切割块231和所述第二切割块232的区域涂布所述第一固化胶之后,将所述第一切割块231和所述第二切割块232对齐放置在所述基底24表面,且所述第一切割块231中具有所述测试地址21的边缘与所述第二切割块232的边缘对齐连接。之后,烘烤所述基底24,使得所述第一固化胶固化。烘烤时间根据所述第一固化胶的种类以及涂布的所述第一固化胶的剂量确定,例如可以是20分钟。烘烤之后自然冷却所述基底,例如放置冷却5分钟。
在所述重组晶圆30中,所述第二切割块232与所述第一切割块231具有所述测试地址21的边缘连接,一方面,可以避免所述第一切割块231在研磨过程中因受压力而导致碎裂的问题;另一方面,所述第二切割块232还可以提高所述测试地址21上方区域研磨过程中的平整度,以及后续在所述测试地址21上方形成保护层26时对所述保护层26进行支撑,确保所述保护层26能够有效覆盖所述测试地址21上方的区域。
在一示例中,粘合后的所述第二切割块232的顶面低于所述第一切割块231的顶面或者粘合后的所述第二切割块232的顶面与所述第一切割块231的顶面平齐。
具体来说,通过使得所述重组晶圆30中所述第二切割块232的顶面低于或者平齐于所述第一切割块231的顶面,可以提高后续形成的所述保护层26的平整度,从而进一步改善最终的晶圆研磨效果。
进行至少一次如下循环步骤,所述循环步骤包括:
步骤S13,于所述重组晶圆30暴露的当前层25上形成保护层26,所述保护层26至少位于所述测试地址21上方,如图2C所示。
在一示例中,于所述重组晶圆30暴露的当前层25上形成保护层26的具体步骤包括:
涂布第二固化胶于所述重组晶圆30暴露的当前层25上;
烘烤所述第二固化胶,形成保护层26。
具体来说,所述第二切割块232的存在,可以有效的避免所述第二固化胶在烘烤过程中自所述第一切割块231表面被吸附至所述基底24表面,确保能 够有效的在所述第一切割块231表面形成所述保护层26。
在一示例中,所述第一固化胶和所述第二固化胶的类型相同。
在一示例中,所述第一固化胶和所述第二固化胶均为由环氧树脂与固化剂构成的混合胶。
在一示例中,所述保护层26覆盖具有所述测试地址21的裸芯片、所述第一切割块231和所述第二切割块232之间的间隙、以及所述第二切割块232。
具体来说,通过将所述第一固化胶和所述第二固化胶的类型设置为相同,在涂布所述第二固化胶的过程中,可以在所述第一切割块231和所述第二切割块232之间连接缝隙处补充上所述第二固化胶,确保所述保护层26在所述第一切割块231与所述第二切割块232之间平坦过渡。所述第一固化胶和所述第二固化胶的类型相同,均为环氧树脂与固化剂按重量比9:1混合制成。
步骤S14,研磨所述重组晶圆30中未被所述保护层26覆盖的所述当前层25,暴露与所述当前层26相邻的下一层27,如图2D所示。
步骤S15,去除所述保护层26和所述保护层26下方残留的所述当前层25,暴露位于所述保护层26下方的所述下一层27,如图2F所示。
步骤S16,判断所述测试地址21是否暴露,若否,则以暴露的所述下一层27作为下一次循环步骤的当前层。若判断确认所述测试地址已经完全暴露,则进行步骤S17,即结束所述循环步骤。
在一示例中,研磨所述重组晶圆30中未被所述保护层26覆盖的所述当前层25的具体步骤包括:
自所述第一切割块231的边缘开始、沿所述第一切割块231指向所述第二切割块232的方向研磨所述第一切割块231中未被所述保护层26覆盖的所述当前层25。
具体来说,沿图2C中箭头所示的方向,自所述第一切割块231远离所述第二切割块232的边缘开始对所述第一切割块231中未被所述保护层26覆盖的区域进行化学机械研磨。在对所述当前层25进行研磨的过程中,研磨液可以根据所述当前层25的具体材料进行选择。例如所述当前层25为第三层金属互连层,则可以采用粒径为0.5μm、PH为9的二氧化硅和活性剂的混合液体 作为研磨液。
在一示例中,去除所述保护层26和所述保护层26下方残留的所述当前层25的具体步骤包括:
判断暴露的所述下一层27的边缘与所述测试地址21之间的横向距离是否在预设范围内,若是,去除所述保护层26和所述保护层26下方残留的所述当前层25,所述预设范围为大于或者等于1个裸芯片的长度且小于或者等于3个裸芯片的长度之和。
具体来说,为了避免在研磨未被所述保护层26覆盖的所述当前层25时对所述测试地址21上方的所述保护层26造成损伤,从而影响所述保护层26对所述测试地址21的保护作用,在暴露的所述下一层27朝向所述第二切割块232的边缘271与所述测试地址21之间的横向距离是否进入所述预设范围,若是,则在停止当前化学机械研磨进程之后,去除所述保护层26和所述保护层26下方残留的所述当前层25。所述重组晶圆30上的各裸芯片的尺寸均相同。例如,当暴露的所述下一层27的边缘与所述测试地址21之间的横向距离等于2个裸芯片的长度之和时,则停止当前化学机械研磨进程。所述裸芯片的长度是指所述裸芯片在沿所述第一切割块231指向所述第二切割块232方向上的长度。所述下一层27的边缘与所述测试地址21之间的横向距离是指,暴露的所述第一层27朝向所述第二切割块232的边缘271在所述基底24上的投影与所述测试地址21在所述基底24上的投影之间的距离。
在一示例中,去除所述保护层26和所述保护层26下方残留的所述当前层25的具体步骤包括:
采用砂纸研磨去除所述保护层26;
采用研磨机去除残留的所述当前层25。
在一示例中,所述砂纸是粒径为0.5μm或者1μm的钻石砂纸。
在一示例中,所述研磨机的研磨转速在150转/分以下。
具体来说,可以先采用粒径为0.5μm或者1μm的钻石砂纸轻轻的磨掉所有的所述保护层26,暴露位于所述保护层26下方的所述当前层25。然后,所述研磨机以150转/分以下的研磨转速轻抛暴露的所述当前层25,直至暴露位 于所述保护层26所在位置下方的所述下一层27。
图2G为研磨后暴露出的所述测试地址21的示意图。如图2G所示,采用本具体实施方式提供的晶圆研磨方法,可以使得***栅极层28上方的栅极接触层29完全暴露,从而确保了后续晶圆失效分析的顺利进行。图2H为研磨后的栅极本体漏电示意图,图2H中的横坐标表示栅极施加电压(V)的大小,纵坐标表示栅极本体漏电流(A)的大小。由图2H可知,采用本具体实施方式提供的晶圆研磨方法,可以将栅极本体的漏电流从μA级降到pA级,极大的改善了栅极本体的漏电流问题。
不仅如此,本申请还提供了一种晶圆失效分析方法。本具体实施方式可以采用如图1、图2A-图2H所示的晶圆研磨方法对进行失效分析的晶圆进行研磨。所述晶圆失效分析方法,包括如下步骤:
采用上述任一项所述的晶圆研磨方法对晶圆进行研磨,暴露测试地址;
采用纳米探针对所述测试地址进行失效测试。
本具体实施方式提供的晶圆研磨方法及晶圆失效分析方法,通过对待研磨的初始晶圆进行拆分重组,将具有测试地址的裸芯片的位置调整至重组晶圆的中部,从而避免了因具有测试地址的裸芯片处于边缘位置而导致易出现研磨坡度的问题。而且,本申请通过在研磨其他区域的过程中,覆盖保护层于测试地址上方,在其他区域研磨之后,去除保护层,单独再对测试地址上方的区域进行小范围的研磨,从而能够使得测试地址能够完整、平坦的暴露,测试地址上方也不会出现金属互连层桥接的问题,减少甚至是避免了栅极本体的漏电问题。
以上所述仅是本申请的优选实施方式,应当指出,对于本技术领域的普通技术人员,在不脱离本申请原理的前提下,还可以做出若干改进和润饰,这些改进和润饰也应视为本申请的保护范围。
Claims (16)
- 一种晶圆研磨方法,包括如下步骤:提供包括多个裸芯片的初始晶圆,且位于所述初始晶圆边缘的裸芯片中具有测试地址;拆分并重组多个所述裸芯片,形成重组晶圆,使得具有所述测试地址的裸芯片位于所述重组晶圆的中部;进行至少一次如下循环步骤,所述循环步骤包括:于所述重组晶圆暴露的当前层上形成保护层,所述保护层至少位于所述测试地址上方;研磨所述重组晶圆中未被所述保护层覆盖的所述当前层,暴露与所述当前层相邻的下一层;去除所述保护层和所述保护层下方残留的所述当前层,暴露位于所述保护层下方的所述下一层;判断所述测试地址是否暴露,若否,则以暴露的所述下一层作为下一次循环步骤的当前层。
- 根据权利要求1所述的晶圆研磨方法,其中,所述初始晶圆上具有若干条用于分割相邻所述裸芯片的切割道;形成重组晶圆的具体步骤包括:沿所述切割道切割所述初始晶圆,形成多个切割块,每个所述切割块中具有若干所述裸芯片;拼接多个所述切割块,形成重组晶圆,使得具有所述测试地址的所述裸芯片位于所述重组晶圆的中部。
- 根据权利要求2所述的晶圆研磨方法,其中,形成多个切割块的具体步骤包括:沿位于所述初始晶圆中间的切割道切割所述初始晶圆,形成第一切割块和第二切割块,所述第一切割块的边缘包括具有所述测试地址的所述裸芯片。
- 根据权利要求3所述的晶圆研磨方法,其中,拼接所述第一切割块和所述第二切割块的具体步骤包括:提供基底;粘贴所述第一切割块和所述第二切割块于所述基底表面,并粘合所述第一切割块和所述第二切割块。
- 根据权利要求4所述的晶圆研磨方法,其中,粘贴所述第一切割块和所述第二切割块于所述基底表面,并粘合所述第一切割块和所述第二切割块的具体步骤包括:涂布第一固化胶于所述基底表面;放置所述第一切割块和所述第二切割块于所述基底表面,且所述第一切割块的边缘与所述第二切割块的边缘对齐连接;烘烤所述第一固化胶。
- 根据权利要求4所述的晶圆研磨方法,其中,粘合后的所述第二切割块的顶面低于所述第一切割块的顶面或者粘合后的所述第二切割块的顶面与所述第一切割块的顶面平齐。
- 根据权利要求5所述的晶圆研磨方法,其中,于所述重组晶圆暴露的当前层上形成保护层的具体步骤包括:涂布第二固化胶于所述重组晶圆暴露的当前层上;烘烤所述第二固化胶,形成保护层。
- 根据权利要求7所述的晶圆研磨方法,其中,所述第一固化胶和所述第二固化胶的类型相同。
- 根据权利要求7所述的晶圆研磨方法,其中,所述第一固化胶和所述第二固化胶均为由环氧树脂与固化剂构成的混合胶。
- 根据权利要求4所述的晶圆研磨方法,其中,所述保护层覆盖具有所述测试地址的裸芯片、所述第一切割块和所述第二切割块之间的间隙、以及所述第二切割块。
- 根据权利要求4所述的晶圆研磨方法,其中,研磨所述重组晶圆中未被所述保护层覆盖的所述当前层的具体步骤包括:自所述第一切割块的边缘开始、沿所述第一切割块指向所述第二切割块的方向研磨所述第一切割块中未被所述保护层覆盖的所述当前层。
- 根据权利要求1所述的晶圆研磨方法,其中,去除所述保护层和所述保护层下方残留的所述当前层的具体步骤包括:判断暴露的所述下一层的边缘与所述测试地址之间的横向距离是否在预设范围内,若是,去除所述保护层和所述保护层下方残留的所述当前层,所述预设范围为大于或者等于1个裸芯片的长度且小于或者等于3个裸芯片的长度之和。
- 根据权利要求7所述的晶圆研磨方法,其中,去除所述保护层和所述保护层下方残留的所述当前层的具体步骤包括:采用砂纸研磨去除所述保护层;采用研磨机去除残留的所述当前层。
- 根据权利要求13所述的晶圆研磨方法,其中,所述砂纸是粒径为0.5μm或者1μm的钻石砂纸。
- 根据权利要求13所述的晶圆研磨方法,其中,所述研磨机的研磨转速在150转/分以下。
- 一种晶圆失效分析方法,包括如下步骤:采用如权利要求1-15中任一项所述的晶圆研磨方法对晶圆进行研磨,暴露测试地址;采用纳米探针对所述测试地址进行失效测试。
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