TW200811936A - Sawing method for a wafer - Google Patents

Sawing method for a wafer Download PDF

Info

Publication number
TW200811936A
TW200811936A TW095130525A TW95130525A TW200811936A TW 200811936 A TW200811936 A TW 200811936A TW 095130525 A TW095130525 A TW 095130525A TW 95130525 A TW95130525 A TW 95130525A TW 200811936 A TW200811936 A TW 200811936A
Authority
TW
Taiwan
Prior art keywords
wafer
protective layer
active surface
cutting
dicing
Prior art date
Application number
TW095130525A
Other languages
Chinese (zh)
Other versions
TWI317973B (en
Inventor
Fu-Tang Chu
Chi-Yuam Chung
Ji-Ping Teng
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW095130525A priority Critical patent/TWI317973B/en
Priority to US11/785,710 priority patent/US20080045124A1/en
Publication of TW200811936A publication Critical patent/TW200811936A/en
Application granted granted Critical
Publication of TWI317973B publication Critical patent/TWI317973B/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B7/00—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor
    • B24B7/20—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground
    • B24B7/22—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain
    • B24B7/228—Machines or devices designed for grinding plane surfaces on work, including polishing plane glass surfaces; Accessories therefor characterised by a special design with respect to properties of the material of non-metallic articles to be ground for grinding inorganic material, e.g. stone, ceramics, porcelain for grinding thin, brittle parts, e.g. semiconductors, wafers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B1/00—Processes of grinding or polishing; Use of auxiliary equipment in connection with such processes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B28—WORKING CEMENT, CLAY, OR STONE
    • B28D—WORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00—Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer

Abstract

The present invention relates to a sawing method for a wafer. The sawing method of the invention comprises: (a) providing a wafer, the wafer having an active surface and a back surface, the active surface having a plurality of sawing lines; (b) coating a protection layer on the active surface of the wafer and on the sawing lines; (c) tapping a grinding tape under the protection layer; (d) grinding the back surface of the wafer to thin the wafer; (e) removing the grinding tape; and (f) cutting the wafer to form a plurality of dice. Whereby, the problems of die cracking, die scratching die contamination and peeling of the surface of the sawing lines can be avoided.

Description

200811936 九、發明說明·· 【發明所屬之技術領域】 本發明係關於一種晶圓切割方法，詳古夕 # 0日^ ^ 叶〇 <，係關於一種 塗佈一保護層於晶圓表面之晶圓切割方法。 【先前技術】200811936 IX. INSTRUCTIONS · TECHNICAL FIELD OF THE INVENTION The present invention relates to a wafer dicing method, which is related to coating a protective layer on a wafer surface. Wafer cutting method. [Prior Art]

參考圖i至圖4’為習知晶圓切割方法之示意圖。參考圖 1’首先，提供一晶圓10,該晶圓10具一主動表面1〇1及一 背面102，該主動面101具有複數個切割道（圖中未示接 著，貼附-研磨膠帶U於該主動表面1〇1下，用以於接續 之研磨過程中保護該主動面101。 參考圖2，研磨該晶圓10之該背面1〇2以薄化該晶圓1〇。 在該習知晶圓切割方法中，該晶圓10係利用一研磨機（圖 中未示）上之磨輪研磨該晶圓10之背面102,以薄化該晶圓 10。接著，去除該研磨膠帶U，如圖3所示。最後，利用 一刀具沿著該主動面1〇1上之切割道切割該晶圓1〇，以形 成複數個晶片12，如圖4所示。 由於習知晶圓切割方法，在薄化該晶圓1〇後進行切割 時，並無任何保護層保護該晶圓丨〇，以致於切割時會於該 等切割道表面產生剝離情形，更有可能產生更大之剝離範 圍，而損壞到該等切割道附近之部分該主動面1〇1，而造 成該晶圓10之主動表面1〇1刮傷。再者，在研磨步驟之 後，需先移除該研磨膠帶丨丨再進行切割該晶圓1〇之動作， 故切割該晶圓10以形成複數個晶片時，亦會造成該等晶片 之主動表面受到污染。 103770.doc 200811936 因此’有必要提供一種創新具有進步性之晶圓切割方 法，以解決上述問題。 【發明内容】 本’X月之目的在於提供一種晶圓切割方法，其包括:⑷ 提供一晶圓，該晶圓具一主動表面及一相對應之背面，該 主動表面具有複數個切割道；(b)塗佈一保護層於該晶圓之 該主動表面及該等切割道；（e)貼附_研磨膠帶於該保護層 下，⑷研磨該晶圓之該背面以薄化該晶圓；⑷去除該研 磨膠帶；及（f)切割該晶圓以形成複數個晶片。 本發明晶圓切割方法，在薄化該晶圓後，仍然具有該保 濩層，因此，在進行該晶圓之切割時，該保護層可用以保 護該晶圓，使切割時於該等切割道表面不會產生剝離情 形，更不會產生更大之剝離範圍，而損壞到該等切割道附 近之部分該主動面，使該晶圓之主動表面造成到傷。再 者，在切割該晶圓之後才移除該保護層，故切割該晶圓以 形成複數個晶片時，亦可避免該等晶片之主動表面受到污 染。 【實施方式】 參考圖5至圖1 〇，為本發明晶圓切割方法之示意圖。來 考圖5 ’首先’ ^供一晶圓20’該晶圓20具一主動表面2〇1 及一背面202，該主動表面具有複數個切割道（圖未示出）。 參考圖6，塗佈一保護層21於該主動表面201及該等切割 道，該保護層21係完全覆蓋該主動表面2〇1及該等切割 道。在該實施例中，該保護層21係以旋轉塗佈方式設塗佈 103770.doc 200811936 於該主動表面201及該等切割道。該保護層21係為一種液 態膠’在本實施例中，該液態膠為環氧樹脂。 在塗佈該保護層21步驟之後，更包括了一烘烤之步驟， 以固化該保護層21，藉以保護該晶圓2〇。由於塗佈於該主 動表面201之該保護層21係為一液態物質，故該保護層21 可完全覆蓋該晶圓20之該主動表面201及該等切割道，且 該保護層21利用其液態之特性，不僅可緊密包覆該主動表 面201及該等切割道，亦可使該保護層21形成平坦之表 面。 參考圖7，貼附一研磨膠帶22於該保護層以下，更增加 對該晶圓2G之保護性。參考圖8，該晶圓2()係利用一研磨 機（圖中未示）上之磨輪，研磨該晶圓2〇之該背面2〇2以薄化 該晶圓20,在研磨該晶圓2〇時，緊密包覆之該保護層21及 該研磨膠帶22則提供該晶圓2G之邊緣支樓力，以避免該晶 圓20產生破片，或避免使晶圓2〇之該主動表面2〇ι受到損 傷。參考圖9，去除該研磨膠帶22。接著，利用一刀具沿 著該主動面2〇1上之切割道切割該晶圓2〇，以形成複數個 晶片23’如圖10所示。最後，在切割該晶圓2〇步驟之後， 更可利用一溶劑將該保護層21移除，如圖u所示。 本發明晶圓切割方法，在薄化該晶圓2()後，仍然具有該 保護層2卜目此，在進行該晶圓2〇之切割時，該保護層21 可用以保護該晶圓20 ’使切割時於該等切割道表面不會產 旬離h形更不會產生更大之剝離範圍，而損壞到該等 d C附近之。卩分该主動面2〇丨，使該晶圓π之主動表面 103770.doc 200811936 201造成刮傷。再者，在切割該晶圓20之後才移除該保護 層21，故切割該晶圓20以形成該等晶片23時，亦可避免該 等晶片23之主動表面201受到污染。 准上述實;^例僅為說明本發明之原理及其功效，而非用 於限制本發明。因此，習於此技術之人士可在不違背本發 明之精神對上述實施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖1顯示習用晶圓貼附研磨膠帶之示意圖； 圖2顯示習用研磨晶圓之示意圖； 圖3顯示習用移除研磨膠帶之示意圖； 圖4顯示習用切割晶圓之示意圖； 圖5顯示本發明晶圓之示意圖； 圖6顯示本發明晶圓塗佈保護層之示意圖； 圖7顯示本發明晶圓貼附研磨膠帶之示意圖； 圖8顯示本發明研磨晶圓之示意圖； 圖9顯示本發明移除研磨膠帶之示意圖； 圖10顯示本發明切割晶圓之示意圖；及 圖11顯示本發明移除保護層之示意圖。 【主要元件符號說明】 10 晶圓 11 研磨膠帶 12 晶片 2〇 晶圓 103770.doc 200811936 21 保護層 22 研磨膠帶 23 晶片 101 主動表面 102 背面 201 主動表面 202 背面Referring to Figures i through 4', there is shown a schematic diagram of a conventional wafer dicing method. Referring to FIG. 1', first, a wafer 10 is provided. The wafer 10 has an active surface 1:1 and a back surface 102. The active surface 101 has a plurality of dicing streets (not shown, attached-grinding tape U The active surface 101 is protected during the subsequent polishing process. Referring to FIG. 2, the back surface 1 of the wafer 10 is polished to thin the wafer 1 〇. In the circular cutting method, the wafer 10 is ground on the back surface 102 of the wafer 10 by a grinding wheel on a grinder (not shown) to thin the wafer 10. Then, the polishing tape U is removed, as shown in the figure. 3. Finally, the wafer 1 is cut along a scribe line on the active surface 1〇1 by a cutter to form a plurality of wafers 12, as shown in FIG. 4. Due to the conventional wafer cutting method, thinning is performed. When the wafer is cut after 1 ,, there is no protective layer to protect the wafer defect, so that the surface of the scribe line will be peeled off when cutting, and it is more likely to produce a larger peeling range, and the damage is The active surface 1〇1 in the vicinity of the scribe lines causes the wafer 10 to be active The surface is scratched by 1〇1. Further, after the grinding step, the polishing tape is removed and then the wafer is diced, so that when the wafer 10 is cut to form a plurality of wafers, The active surface of the wafers is contaminated. 103770.doc 200811936 Therefore, it is necessary to provide an innovative and progressive wafer cutting method to solve the above problems. [Inventive content] The purpose of this 'X month is to provide a wafer. The cutting method comprises: (4) providing a wafer having an active surface and a corresponding back surface, the active surface having a plurality of dicing streets; and (b) applying a protective layer to the active layer of the wafer a surface and the dicing lines; (e) attaching _abrading tape under the protective layer, (4) grinding the back side of the wafer to thin the wafer; (4) removing the abrasive tape; and (f) cutting the wafer To form a plurality of wafers. The wafer dicing method of the present invention still has the protective layer after thinning the wafer, so that the protective layer can be used to protect the wafer during the dicing of the wafer. Cutting at the time of cutting The surface of the track will not be peeled off, and a larger peeling range will not be generated, and the active surface of the wafer will be damaged to the active surface of the wafer. Further, the crystal is cut. After the circle is removed, the protective layer is removed, so that when the wafer is cut to form a plurality of wafers, the active surface of the wafers can be prevented from being contaminated. [Embodiment] Referring to FIG. 5 to FIG. Schematic diagram of the cutting method. Referring to Figure 5 'First' ^ for a wafer 20', the wafer 20 has an active surface 2〇1 and a back surface 202 having a plurality of dicing streets (not shown). Referring to FIG. 6, a protective layer 21 is applied to the active surface 201 and the dicing streets, and the protective layer 21 completely covers the active surface 〇1 and the dicing streets. In this embodiment, the protective layer 21 is applied by spin coating to the active surface 201 and the dicing streets. The protective layer 21 is a liquid glue. In the present embodiment, the liquid glue is an epoxy resin. After the step of coating the protective layer 21, a baking step is further included to cure the protective layer 21 to protect the wafer 2 . Since the protective layer 21 coated on the active surface 201 is a liquid substance, the protective layer 21 can completely cover the active surface 201 of the wafer 20 and the dicing streets, and the protective layer 21 utilizes its liquid state. The characteristics not only can closely cover the active surface 201 and the dicing streets, but also the protective layer 21 can form a flat surface. Referring to Figure 7, a polishing tape 22 is attached below the protective layer to further enhance the protection of the wafer 2G. Referring to FIG. 8, the wafer 2() is polished by a grinding wheel on a grinder (not shown) to polish the back surface 2 of the wafer 2 to thin the wafer 20, and polish the wafer. At 2 ,, the protective layer 21 and the polishing tape 22 which are tightly coated provide the edge of the wafer 2G to prevent the wafer 20 from being fragmented, or to avoid the active surface 2 of the wafer 2 〇ι is damaged. Referring to Figure 9, the abrasive tape 22 is removed. Next, the wafer 2 is cut along a scribe line on the active surface 2〇1 by a cutter to form a plurality of wafers 23' as shown in FIG. Finally, after the step of cutting the wafer 2, the protective layer 21 can be removed with a solvent, as shown in FIG. The wafer dicing method of the present invention, after thinning the wafer 2 (), still has the protective layer 2, and the protective layer 21 can be used to protect the wafer 20 when the wafer 2 is cut. 'When cutting, the surface of the cutting path will not be produced from the h-shaped shape, and no larger peeling range will be produced, and it will be damaged to the vicinity of the d C. Dividing the active surface 2〇丨 causes the wafer π active surface 103770.doc 200811936 201 to cause scratches. Moreover, the protective layer 21 is removed after the wafer 20 is diced, so that when the wafer 20 is diced to form the wafers 23, the active surface 201 of the wafers 23 can be prevented from being contaminated. The above is merely illustrative of the principles and effects of the invention and is not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a conventional wafer attached to an abrasive tape; FIG. 2 is a schematic view showing a conventional abrasive wafer; FIG. 3 is a schematic view showing a conventional removal of the abrasive tape; 5 is a schematic view of a wafer coated protective layer of the present invention; FIG. 7 is a schematic view showing a wafer-coated protective layer of the present invention; FIG. 7 is a schematic view showing a wafer-attached abrasive tape of the present invention; 9 is a schematic view showing the removal of the abrasive tape of the present invention; FIG. 10 is a schematic view showing the dicing wafer of the present invention; and FIG. 11 is a view showing the removal of the protective layer of the present invention. [Main component symbol description] 10 Wafer 11 Abrasive tape 12 Wafer 2〇 Wafer 103770.doc 200811936 21 Protective layer 22 Abrasive tape 23 Wafer 101 Active surface 102 Back 201 Active surface 202 Back

103770.doc103770.doc

Claims (1)

200811936 十、申請專利範圍： L 一種晶圓切割方法，包含以下步驟： (a) 提供一晶圓，該晶圓具一主動表面及一相對應之背 面，該主動表面具有複數個切割道； (b) 塗佈一保護層於該晶圓之該主動表面及該等切割 道； (c)貼附一研磨膠帶於該保護層下200811936 X. Patent Application Range: L A wafer cutting method comprising the following steps: (a) providing a wafer having an active surface and a corresponding back surface, the active surface having a plurality of dicing streets; b) applying a protective layer to the active surface of the wafer and the dicing streets; (c) attaching a polishing tape under the protective layer (d) 研磨該晶圓之該背面以薄化該晶圓； (e) 去除該研磨膠帶；及 (f) 切割該晶圓以形成複數個晶片。 2· 士明求項1之方法，其中在步驟（b)中，該保護層係以旋 轉塗佈方式塗佈於該晶圓之該主動表面。 3·如：求们之方法，其中該保護層係為一種液態膠。 :长項3之方法，其中該液態膠為環氧樹脂。 月求項1之方法’其中在步驟（b)之後更包括了 一焕烤 之步驟，以固化該保護層。 /、 其中在步驟（f)之後更包括了 一移除 6·如請求項1之方法 該保護層之步驟。 項6之方法 其中該保護層係以一 浴劑移除 103770.doc(d) grinding the back side of the wafer to thin the wafer; (e) removing the abrasive tape; and (f) cutting the wafer to form a plurality of wafers. 2. The method of claim 1, wherein in step (b), the protective layer is applied to the active surface of the wafer by spin coating. 3. For example, the method of claiming, wherein the protective layer is a liquid glue. The method of long term 3, wherein the liquid glue is an epoxy resin. The method of claim 1 wherein the step (b) further comprises a step of baking to cure the protective layer. /, wherein after step (f), a step of removing the protective layer is as described in the method of claim 1. The method of item 6 wherein the protective layer is removed by a bath 103770.doc
TW095130525A 2006-08-18 2006-08-18 Sawing method for a wafer TWI317973B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW095130525A TWI317973B (en) 2006-08-18 2006-08-18 Sawing method for a wafer
US11/785,710 US20080045124A1 (en) 2006-08-18 2007-04-19 Sawing method for a wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095130525A TWI317973B (en) 2006-08-18 2006-08-18 Sawing method for a wafer

Publications (2)

Publication Number Publication Date
TW200811936A true TW200811936A (en) 2008-03-01
TWI317973B TWI317973B (en) 2009-12-01

Family

ID=39101919

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095130525A TWI317973B (en) 2006-08-18 2006-08-18 Sawing method for a wafer

Country Status (2)

Country Link
US (1) US20080045124A1 (en)
TW (1) TWI317973B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097431A (en) * 2014-05-09 2015-11-25 中芯国际集成电路制造(上海)有限公司 Wafer front protecting method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6185792B2 (en) * 2013-08-29 2017-08-23 三星ダイヤモンド工業株式会社 Semiconductor wafer cutting method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5776799A (en) * 1996-11-08 1998-07-07 Samsung Electronics Co., Ltd. Lead-on-chip type semiconductor chip package using an adhesive deposited on chip active surfaces at a wafer level and method for manufacturing same
JP2001126225A (en) * 1999-10-21 2001-05-11 Tdk Corp Method for manufacturing magnetic head slider, method for fixing bar and curing agent
KR100609011B1 (en) * 2003-12-05 2006-08-03 삼성전자주식회사 Wafer level module and fabricating method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105097431A (en) * 2014-05-09 2015-11-25 中芯国际集成电路制造(上海)有限公司 Wafer front protecting method

Also Published As

Publication number Publication date
TWI317973B (en) 2009-12-01
US20080045124A1 (en) 2008-02-21

Similar Documents

Publication Publication Date Title
US20120329369A1 (en) Substrate processing method and substrate processing apparatus
KR102024390B1 (en) Surface protective member and machining method
TWI446420B (en) Releasing carrier method for semiconductor process
TWI515783B (en) Processing method of semiconductor wafers
KR102216978B1 (en) Support plate, method of forming same, and wafer processing method
KR102432506B1 (en) Wafer processing method and intermediate member
KR20150131963A (en) Wafer processing method
TW200903606A (en) Method for holding semiconductor wafer
KR20150085474A (en) Wafer processing method
JP2007096229A (en) Wafer processing method
JP2011155112A (en) Method of processing wafer
JP5762213B2 (en) Grinding method for plate
JP2004349649A (en) Thin processing method of wafer
JP2011216763A (en) Method of processing wafer
TWI759491B (en) Wafer Processing Method
JP2013247135A (en) Wafer processing method
TW200826179A (en) Method for protecting wafer circuit surface and method for reducing wafer thickness
US11276588B2 (en) Method of processing wafer
US20140213152A1 (en) Wafer Edge Trimming Tool Using Abrasive Tape
TW200811936A (en) Sawing method for a wafer
TW201822267A (en) Wafer processing method capable of easily transferring a wafer from a protective tape for grinding to another adhesive tape
JP2012222310A (en) Method for processing wafer
TWI592982B (en) Method of manufacturing semiconductor device
JP2014120583A (en) Method of manufacturing semiconductor device
JP5500998B2 (en) Grinding method for plate