WO2022198878A1 - 半导体结构及其制作方法 - Google Patents
半导体结构及其制作方法 Download PDFInfo
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- WO2022198878A1 WO2022198878A1 PCT/CN2021/111069 CN2021111069W WO2022198878A1 WO 2022198878 A1 WO2022198878 A1 WO 2022198878A1 CN 2021111069 W CN2021111069 W CN 2021111069W WO 2022198878 A1 WO2022198878 A1 WO 2022198878A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 230000002093 peripheral effect Effects 0.000 claims abstract description 32
- 230000001681 protective effect Effects 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 204
- 238000000034 method Methods 0.000 claims description 27
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 239000002356 single layer Substances 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 11
- 229910052721 tungsten Inorganic materials 0.000 claims description 11
- 239000010937 tungsten Substances 0.000 claims description 11
- 239000004020 conductor Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 12
- 229910052719 titanium Inorganic materials 0.000 description 12
- 239000010936 titanium Substances 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052814 silicon oxide Inorganic materials 0.000 description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 10
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 239000007769 metal material Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052707 ruthenium Inorganic materials 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
Definitions
- the present application relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a manufacturing method thereof.
- the dicing method of the dicing line will cause certain mechanical stress to the front and back of the wafer, which may cause chipping at the edge of the chip.
- the chipping problem will reduce the mechanical strength of the chip.
- the initial chip edge crack will further spread in the subsequent packaging process or in the use of the chip product, which is likely to cause the chip to break, thereby causing the electrical performance of the chip to fail.
- a semiconductor structure such as a seal ring is usually designed around the chip.
- the sealing ring structure also has the ability to resist gas and liquid corrosion, and can prevent water vapor or other chemical pollution sources from penetrating into the chip to avoid damage to the chip.
- the role of the sealing ring around the chip is becoming more and more important.
- the existing sealing ring cannot provide stronger protection to the chip, and cannot meet the protection requirements of the chip.
- a semiconductor structure and a method of fabricating the same are provided.
- the application provides a semiconductor structure including:
- the substrate includes a peripheral region and a chip region;
- a first dielectric layer located on the peripheral region and the chip region of the substrate
- a protection structure and a functional structure respectively located in the first dielectric layer of the peripheral region and the chip region;
- the protection structure includes a first subsection, a second subsection and a third subsection stacked in sequence
- the functional structure includes a fourth subsection and a fifth subsection stacked in sequence, the first subsection
- the overall height of the second subsection and the third subsection is the same as the overall height of the fourth subsection and the fifth subsection.
- the present application also provides a method for fabricating a semiconductor structure, comprising the following steps:
- a substrate including a peripheral region and a chip region
- the protection structure includes a first subsection, a second subsection and a third subsection stacked in sequence
- the functional structure includes a fourth subsection and a fifth subsection stacked in sequence, the first subsection
- the overall height of the second subsection and the third subsection is the same as the overall height of the fourth subsection and the fifth subsection.
- the semiconductor structure provided by the embodiment of the present application is more stable, the interception area is larger, and the protection effect on the chip is stronger.
- the semiconductor structure formed by the manufacturing method of the semiconductor structure provided in the embodiment of the present application is more stable, has a larger interception area, has a stronger protection effect on the chip, and has a simple process flow.
- FIG. 1 is a flowchart of a method for fabricating a semiconductor structure provided in an embodiment of the present application
- FIG. 2 is a schematic cross-sectional view of an underlying dielectric layer provided in an embodiment of the application
- step S2 is a schematic cross-sectional view of the structure obtained in step S2 in the method for fabricating a semiconductor structure provided in an embodiment of the present application;
- step S3 is a flowchart of step S3 in the method for fabricating a semiconductor structure provided in an embodiment of the present application;
- step S32 is a schematic cross-sectional view of the structure obtained in step S32 in the method for fabricating a semiconductor structure provided in an embodiment of the present application;
- step S35 is a schematic cross-sectional view of the structure obtained in step S35 in the method for fabricating a semiconductor structure provided in an embodiment of the present application;
- FIG. 7 is a schematic cross-sectional view of the structure obtained in step S38 in the method for fabricating a semiconductor structure provided in an embodiment of the present application.
- step S3 is a schematic cross-sectional view of a structure obtained in step S3 in a method for fabricating a semiconductor structure provided in an embodiment of the present application, and is also a schematic diagram of a semiconductor structure provided in an embodiment of the present application;
- step S4 is a schematic cross-sectional view of the structure obtained in step S4 in the method for fabricating a semiconductor structure provided in an embodiment of the present application;
- step S6 is a schematic cross-sectional view of the structure obtained in step S6 in the method for fabricating a semiconductor structure provided in an embodiment of the present application;
- FIG. 11 is a schematic cross-sectional view of a structure obtained in step S7 in a method for fabricating a semiconductor structure provided in an embodiment of the present application;
- step S8 is a schematic cross-sectional view of a structure obtained in step S8 in a method for fabricating a semiconductor structure provided in an embodiment of the present application;
- step S9 is a schematic cross-sectional view of the structure obtained in step S9 in the method for fabricating a semiconductor structure provided in an embodiment of the present application;
- step S10 is a schematic cross-sectional view of the structure obtained in step S10 in the method for fabricating a semiconductor structure provided in an embodiment of the present application, and is also a schematic diagram of the semiconductor structure provided in an embodiment of the present application.
- first doping type becomes the second doping type
- second doping type can be the first doping type
- the first doping type and the second doping type are different doping types, for example,
- the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
- Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., in This may be used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that in addition to the orientation shown in the figures, spatially relative terms encompass different orientations of the device in use and operation. For example, if the device in the figures is turned over, elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. In addition, the device may also be otherwise oriented (eg, rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
- Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of embodiments of the application (and intermediate structures) such that variations in the shapes shown due to, for example, manufacturing techniques and/or tolerances are contemplated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due, for example, to manufacturing techniques. Thus, the regions shown in the figures are schematic in nature and their shapes do not represent the actual shape of a region of a device and do not limit the scope of the present application.
- an embodiment of the present application provides a method for fabricating a semiconductor structure, including the following steps:
- S1 provide a substrate (not shown in the figure), the substrate includes a peripheral area and a chip area;
- the protection structure 21 includes a first sub-section 211, a second sub-section 212 and a third sub-section 213 stacked in sequence
- the functional structure 22 includes a fourth sub-section 224 and a fifth sub-section 225 stacked in sequence
- the first sub-section The total height of 211 , the second subsection 212 and the third subsection 213 is the same as the overall height of the fourth subsection 224 and the fifth subsection 225 .
- the formed semiconductor structure is more stable, the interception area is larger, the protection effect on the chip is stronger, and the process flow is simple.
- the substrate may include, but is not limited to, a silicon substrate; in other embodiments, the substrate may also be a gallium nitride substrate, an indium phosphide substrate, a sapphire substrate, or the like.
- step S2 the following steps may be included before step S2:
- An underlying dielectric layer 1 is formed on the peripheral region and the chip region of the substrate, as shown in FIG. 2 .
- an underlying dielectric layer 1 may be formed on the substrate. As shown in FIG. 2 , an underlying metal layer 11 and an interconnect structure 12 are formed in the underlying dielectric layer 1 . Specifically, in one of the embodiments, through holes are formed in the peripheral region and the chip region of the underlying dielectric layer 1, respectively, and inside the through holes are the interconnect structure 12 and the underlying metal layer 11 stacked sequentially from bottom to top.
- the interconnection structure 12 may be a single-layer structure, a stacked-layer structure, or other structures, and the structure of the interconnection structure 12 is not limited in this embodiment.
- the interconnect structure 12 may include one or more of titanium, titanium nitride, tungsten, etc., and the material of the interconnect structure 12 is not limited in this embodiment.
- the interconnect structure 12 includes a conductive metal and a barrier layer, the conductive metal may include but not limited to tungsten, ruthenium, etc., and the barrier layer may include but not limited to titanium nitride, titanium, and the like.
- step S2 may include the following steps:
- a first dielectric layer 2 is formed on the peripheral region and the chip region of the underlying dielectric layer 1 .
- step S3 may include the following steps:
- the width of the first opening 201 is the same as the width of the fourth opening 204 ; the width of the second opening 202 is the same as the width of the fifth opening 205 .
- the opening depth of the first opening 201 is the same as that of the fourth opening 204 ; the opening depth of the second opening 202 is the same as that of the fifth opening 205 .
- the opening depth of the first opening 201 is greater than the opening depth of the second opening 202 ; the opening depth of the second opening 202 is greater than the opening depth of the third opening 203 .
- the width of the first opening 201 is smaller than the width of the second opening 202
- the width of the second opening 202 is smaller than the width of the third opening 203
- the width of the fourth opening 204 The width is smaller than the width of the fifth opening 205 .
- the total depth of the first opening 201 , the second opening 202 and the third opening 203 is the same as the total depth of the fourth opening 204 and the fifth opening 205 .
- the conductive material in the first opening 201 is the first sub-section 211
- the conductive material in the second opening 202 is the second sub-section 212
- the conductive material in the third opening 203 is the third sub-section 213
- the conductive material in the fourth opening 204 is the fourth sub-portion 224
- the conductive material in the fifth opening 205 is the fifth sub-portion 225 .
- the material of the protection structure 21 may include, but is not limited to, copper.
- the conductive material may be copper, which is simultaneously formed in the first opening 201 , the second opening 202 , the third opening 203 , the fourth opening 204 , the fifth opening 205 and above the first dielectric layer 2 by means of electroplating
- the initial copper layer, and then the initial copper layer above the first dielectric layer 2 is removed by chemical mechanical polishing to form a protection structure 21 and a functional structure 22 respectively, as shown in FIG. 8 .
- the protection structure 21 can be formed separately in the copper metal interconnection layer, so as to enhance the protection effect of the copper metal guard ring and save the production cost at the same time.
- the formed first dielectric layer 2 is a single-layer structure; the formed protection structure 21 includes N sub-sections stacked in sequence, where N is an integer greater than 3.
- the formed first dielectric layer 2 may have a single-layer structure or a laminated structure, and the structure of the first dielectric layer 2 is not limited in this embodiment.
- the first dielectric layer 2 may be a silicon nitride layer and a silicon oxide layer stacked in sequence from bottom to top; the formed protection structure 21 is located in the silicon oxide layer.
- the formed semiconductor structure has more sub-sections, so that the intercepting area is increased, so that the protection effect of the structure on the chip is further enhanced.
- the widths of the N sub-sections stacked in sequence increase in sequence.
- the formed semiconductor structure has N sub-sections stacked in sequence, and the widths are sequentially increased, so that the structure is more stable.
- step S3 it may further include:
- the second dielectric layer 3 is a single-layer structure; in other embodiments, the second dielectric layer 3 may also be a laminated structure. In this embodiment, the structure and arrangement of the second dielectric layer 3 are not Not limited.
- the second dielectric layer 3 may include one or more of a silicon nitride layer, a silicon oxide layer, and the like, and the material of the second dielectric layer 3 is not limited in this embodiment.
- the second dielectric layer 3 may be a silicon nitride layer and a silicon oxide layer stacked in sequence from bottom to top.
- step S4 it may further include:
- the second dielectric layer 3 is etched using the sixth opening pattern and the seventh opening pattern, and a sixth opening 306 and a seventh opening 307 are formed in the second dielectric layer 3, respectively. As shown in FIG. 10, the sixth opening 306 and The seventh openings 307 are located in the peripheral area and the chip area, respectively.
- step S6 it may further include:
- the top layer interconnection structure 31 may be a single-layer structure, a stacked layer structure or other structures, and the structure and arrangement of the top layer interconnection structure 31 are not limited in this embodiment.
- the top layer interconnection structure 31 may include one or more of aluminum, titanium, titanium nitride or tungsten, etc.
- the material of the top layer interconnection structure 31 is not limited in this embodiment.
- the top interconnect structure 31 includes a titanium metal layer and a tungsten metal layer stacked sequentially from bottom to top.
- step S7 it may further include:
- the formed top metal material layer 4 has a single-layer structure or a stacked structure, and the structure and arrangement of the top metal material layer 4 are not limited in this embodiment.
- the top metal material layer 4 may include a stacked structure in which titanium layers and aluminum layers are alternately stacked in sequence, or a stacked structure in which titanium nitride layers and aluminum layers are alternately stacked in sequence.
- the bottom layer and the top layer are both titanium layers or titanium nitride layers.
- step S8 it may further include:
- top metal material layer 4 is etched to form the top metal layer 41, and part of the second dielectric layer 3 is exposed, as shown in FIG. 13 .
- step S9 it may further include:
- the formed top dielectric layer 5 may have a single-layer structure or a stacked structure, and the structure of the top dielectric layer 5 is not limited in this embodiment.
- the top dielectric layer 5 may be a silicon oxide layer and a silicon nitride layer stacked in sequence from bottom to top.
- steps in the flowcharts of FIG. 1 and FIG. 4 are displayed in sequence according to the arrows, these steps are not necessarily executed in the sequence indicated by the arrows. Unless explicitly stated herein, the execution of these steps is not strictly limited to the order, and these steps may be performed in other orders. Moreover, at least a part of the steps in FIG. 1 and FIG. 4 may include multiple steps or multiple stages. These steps or stages are not necessarily executed and completed at the same time, but may be executed at different times. The order of execution is also not necessarily sequential, but may be performed alternately or alternately with other steps or at least a portion of the steps or stages within the other steps.
- the present application provides a semiconductor structure, including:
- the substrate includes a peripheral area and a chip area;
- the first dielectric layer 2 is located on the peripheral region and the chip region of the substrate;
- the protection structure 21 and the functional structure 22 are respectively located in the first dielectric layer 2 of the peripheral area and the chip area;
- the protection structure 21 includes a first sub-section 211, a second sub-section 212 and a third sub-section 213 stacked in sequence, the functional structure includes a fourth sub-section 224 and a fifth sub-section 225 stacked in sequence, and the first sub-section 211 , the overall height of the second subsection 212 and the third subsection 213 is the same as the overall height of the fourth subsection 224 and the fifth subsection 225 .
- the semiconductor structure provided in the above embodiment has a more stable structure, a larger interception area, and a stronger protection effect on the chip.
- the substrate may include, but is not limited to, a silicon substrate; in other embodiments, the substrate may also be a gallium nitride substrate, an indium phosphide substrate, a sapphire substrate, or the like.
- a bottom dielectric layer 1 is formed on the substrate, a first dielectric layer 2 is formed on the peripheral region and the chip region of the bottom dielectric layer 1, and the bottom dielectric layer 1 is formed with a bottom metal layer 11 and Interconnect structure 12 .
- through holes are formed in the peripheral region and the chip region of the underlying dielectric layer 1, respectively, and inside the through holes are the interconnect structure 12 and the underlying metal layer 11 stacked sequentially from bottom to top.
- the interconnection structure 12 may be a single-layer structure or a stacked-layer structure, and the structure of the interconnection structure 12 is not limited in this embodiment.
- the material of the interconnection structure 12 may include one or more of titanium, titanium nitride, tungsten, etc., and the material of the interconnection structure 12 is not limited in this embodiment.
- the interconnect structure 12 includes a conductive metal and a barrier layer, the conductive metal includes tungsten, ruthenium, etc., and the barrier layer includes titanium nitride, titanium, and the like.
- the first dielectric layer 2 is a single-layer structure; in other embodiments, the first dielectric layer 2 may also be a laminated structure. In this embodiment, the structure and arrangement of the first dielectric layer 2 are not Not limited.
- the first dielectric layer 2 may include one or more of a silicon nitride layer, a silicon oxide layer, and the like, and the material of the first dielectric layer 2 is not limited in this embodiment.
- the first dielectric layer 2 may be a silicon nitride layer and a silicon oxide layer stacked in sequence from bottom to top; the formed protection structure 21 is located in the silicon oxide layer.
- the width of the second sub-portion 212 is greater than the width of the first sub-portion 211 ; the width of the third sub-portion 213 is greater than the width 212 of the second sub-portion.
- the width of the first sub-section 211 is the same as the width of the fourth sub-section 224 ; the width of the second sub-section 212 is the same as the width of the fifth sub-section 225 .
- first sub-section 211 , the second sub-section 212 and the third sub-section 213 are integrally formed; the fourth sub-section 224 and the fifth sub-section 225 are integrally formed.
- the protective structure 21 includes N subsections stacked in sequence, and N is an integer greater than 3.
- the semiconductor structure provided in the above-mentioned embodiment continues to expand the interception area through more sub-sections, so that the protection effect of the structure on the chip is further enhanced.
- the widths of the N sub-sections stacked in sequence increase in sequence.
- the widths of the N sub-sections stacked in sequence increase in sequence, so that the structure is more stable.
- the first sub-section 211, the second sub-section 212 and the third sub-section 213 are all annular wall structures; the fourth sub-section 224 is a conductive plug structure; the fifth sub-section 225 It is a conductive wire structure.
- the semiconductor structure further includes a bottom metal layer under the protective structure 21 .
- the material of the underlying metal layer may include, but is not limited to, tungsten.
- the semiconductor structure further includes:
- the second dielectric layer 3 is located on the first dielectric layer 2 .
- the second dielectric layer 3 is a single-layer structure; in other embodiments, the first dielectric layer 2 may also be a laminated structure. In this embodiment, the structure and arrangement of the second dielectric layer 3 are not Not limited.
- the second dielectric layer 3 may include one or more of a silicon nitride layer, a silicon oxide layer, and the like, and the material of the second dielectric layer 3 is not limited in this embodiment. Specifically, in one of the embodiments, the second dielectric layer 3 may be a silicon nitride layer and a silicon oxide layer stacked in sequence from bottom to top.
- the semiconductor structure further includes:
- the seventh opening 307, the sixth opening 306 and the seventh opening 307 are all located in the second dielectric layer 3, and are located in the peripheral area and the chip area respectively;
- the top layer interconnect structure 31 is located in the sixth opening 306 and the seventh opening 307 .
- the top layer interconnection structure 31 may be a single-layer structure, a stacked layer structure or other structures, and the structure and arrangement of the top layer interconnection structure 31 are not limited in this embodiment.
- the top layer interconnect structure 31 may include one or more of titanium, titanium nitride or tungsten, etc.
- the material of the top layer interconnect structure 31 is not limited in this embodiment.
- the top interconnect structure 31 includes a titanium metal layer and a tungsten metal layer stacked sequentially from bottom to top.
- the semiconductor structure further includes:
- the top metal layer 41 is located on the upper surface of the second dielectric layer 3 .
- the top metal layer 41 has a single-layer structure or a stacked structure, and the structure and arrangement of the top metal layer 41 are not limited in this embodiment.
- the top metal layer 41 may include a stacked structure in which titanium layers and aluminum layers are alternately stacked in sequence, or a stacked structure in which titanium nitride layers and aluminum layers are alternately stacked in sequence. Both the bottom layer and the top layer are titanium layers or titanium nitride layers.
- the semiconductor structure further includes:
- the top dielectric layer 5 is located on the upper surface of the second dielectric layer 3 and the top metal layer 41 .
- the formed top dielectric layer 5 may have a single-layer structure or a stacked structure, and the structure of the top dielectric layer 5 is not limited in this embodiment.
- the top dielectric layer 5 may be a silicon oxide layer and a silicon nitride layer stacked in sequence from bottom to top.
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Abstract
本申请的实施例涉及一种半导体结构及其制作方法,包括:衬底,所述衬底包括***区和芯片区;第一介质层,位于所述衬底的所述***区和所述芯片区上;保护结构和功能结构,分别位于所述***区和所述芯片区的所述第一介质层中;其中,所述保护结构包括依次堆叠的第一子部分、第二子部分和第三子部分,所述功能结构包括依次堆叠的第四子部分和第五子部分,所述第一子部分、所述第二子部分和所述第三子部分的总高度与所述第四子部分和所述第五子部分的总高度相同。
Description
相关申请的交叉引用
本申请要求于2021年3月24日提交中国专利局、申请号为2021103158426、发明名称为“半导体结构及其制作方法”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本申请涉及半导体制造技术领域,特别是涉及一种半导体结构及其制作方法。
在对晶圆进行切割时,切割道的切割方式会对晶圆的正面和背面产生一定的机械应力,这样可能会在芯片(chip)的边缘产生崩角。崩角问题会降低芯片的机械强度,一开始的芯片边缘裂隙在后面的封装工艺中或在芯片产品的使用中会进一步扩散,从而很可能造成芯片断裂,从而导致芯片的电学性能失效。为了保护芯片内部电路、防止划片损伤、提高芯片可靠性,通常会在芯片***设计密封环(Seal Ring)这样的半导体结构。并且,密封环结构还具有抵抗气液侵蚀的能力,可以阻挡水汽或其他化学污染源向芯片渗透以避免损伤芯片。
目前,随着半导体器件尺寸的不断减小,芯片***的密封环的作用越来越重要。然而,现有的密封环由于稳固性差及拦截面积小,无法对芯片提供更强的保护作用,已无法满足芯片的保护需求。
发明内容
根据本申请的各种实施例,提供一种半导体结构及其制作方法。
本申请提供了一种半导体结构,包括:
衬底,所述衬底包括***区和芯片区;
第一介质层,位于所述衬底的所述***区和所述芯片区上;
保护结构和功能结构,分别位于所述***区和所述芯片区的所述第一介质层中;
其中,所述保护结构包括依次堆叠的第一子部分、第二子部分和第三子部分,所述功能结构包括依次堆叠的第四子部分和第五子部分,所述第一子部分、所述第二子部分和所述第三子部分的总高度与所述第四子部分和所述第五子部分的总高度相同。
本申请还提供了一种半导体结构的制作方法,包括如下步骤:
提供衬底,所述衬底包括***区和芯片区;
在所述衬底的所述***区和所述芯片区上形成第一介质层;
在所述***区和所述芯片区的所述第一介质层中分别形成保护结构和功能结构;
其中,所述保护结构包括依次堆叠的第一子部分、第二子部分和第三子部分,所述功能结构包括依次堆叠的第四子部分和第五子部分,所述第一子部分、所述第二子部分和所述第三子部分的总高度与所述第四子部分和所述第五子部分的总高度相同。
本申请实施例提供的半导体结构更加稳固,拦截面积更大,对芯片的保护作用更强。
本申请实施例提供的半导体结构的制作方法形成的半导体结构更加稳固,拦截面积更大,对芯片的保护作用更强,并且工艺流程简单。
为了更清楚地说明本申请实施例或传统技术中的技术方案,下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本申请一个实施例中提供的半导体结构的制作方法的流程图;
图2为本申请一个实施例中提供的底层介质层的截面示意图;
图3为本申请一个实施例中提供的半导体结构的制作方法中步骤S2所得结构的截面示意图;
图4为本申请一个实施例中提供的半导体结构的制作方法中步骤S3的流程图;
图5为本申请一个实施例中提供的半导体结构的制作方法中步骤S32所得结构的截面示意图;
图6为本申请一个实施例中提供的半导体结构的制作方法中步骤S35所得结构的截面示意图;
图7为本申请一个实施例中提供的半导体结构的制作方法中步骤S38所得结构的截面示意图。
图8为本申请一个实施例中提供的半导体结构的制作方法中步骤S3所得结构的截面示意图,同时也是本申请一个实施例中提供的半导体结构的示意图;
图9为本申请一个实施例中提供的半导体结构的制作方法中,步骤S4所得结构的截面示意图;
图10为本申请一个实施例中提供的半导体结构的制作方法中步骤S6所得结构的截面示意图;
图11为本申请一个实施例中提供的半导体结构的制作方法中步骤S7所得结构的截面示意图;
图12为本申请一个实施例中提供的半导体结构的制作方法中步骤S8所得结构的截面示意图;
图13为本申请一个实施例中提供的半导体结构的制作方法中步骤S9所得结构的截面示意图;
图14为本申请一个实施例中提供的半导体结构的制作方法中步骤S10所得结构的截面示意图,同时也是本申请一个实施例中提供的半导体结构的示 意图。
为了便于理解本申请,下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是,本申请可以以许多不同的形式来实现,并不限于本文所描述的实施例。相反地,提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义,本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本申请。
应当明白,当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时,其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层,或者可以存在居间的元件或层。相反,当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时,则不存在居间的元件或层。应当明白,尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分,这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此,在不脱离本申请教导之下,下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分;举例来说,可以将第一掺杂类型成为第二掺杂类型,且类似地,可以将第二掺杂类型成为第一掺杂类型;第一掺杂类型与第二掺杂类型为不同的掺杂类型,譬如,第一掺杂类型可以为P型且第二掺杂类型可以为N型,或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等,在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白,除了图中所示的取向以外,空间关系术语 还包括使用和操作中的器件的不同取向。例如,如果附图中的器件翻转,描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此,示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外,器件也可以包括另外地取向(譬如,旋转90度或其它取向),并且在此使用的空间描述语相应地被解释。
在此使用时,单数形式的“一”、“一个”和“所述/该”也可以包括复数形式,除非上下文清楚指出另外的方式。还应明白,当术语“组成”和/或“包括”在该说明书中使用时,可以确定所述特征、整数、步骤、操作、元件和/或部件的存在,但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时,在此使用时,术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本申请的实施例(和中间结构)的示意图的横截面图来描述申请的实施例,这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此,本申请的实施例不应当局限于在此所示的区的特定形状,而是包括由于例如制造技术导致的形状偏差。因此,图中显示的区实质上是示意性的,它们的形状并不表示器件的区的实际形状,且并不限定本申请的范围。
请参考图1,本申请实施例提供一种半导体结构的制作方法,包括如下步骤:
S1:提供衬底(图中未示出),衬底包括***区和芯片区;
S2:在衬底的***区和芯片区上形成第一介质层2;
S3:在***区和芯片区的第一介质层2中分别形成保护结构21和功能结构22;
其中,保护结构21包括依次堆叠的第一子部分211、第二子部分212和第三子部分213,功能结构22包括依次堆叠的第四子部分224和第五子部分225,第一子部分211、第二子部分212和第三子部分213的总高度与第四子部分224和第五子部分225的总高度相同。
上述实施例中的半导体结构的制作方法,其形成的半导体结构更加稳固,拦截面积更大,对芯片的保护作用更强,并且工艺流程简单。
在其中一个实施例中,衬底可以包括但不仅限于硅衬底;在其他实施例中,衬底还可以为氮化镓衬底、磷化铟衬底或蓝宝石衬底等等。
在其中一个实施例中,步骤S2之前可以包括如下步骤:
在衬底的***区和芯片区上形成底层介质层1,如图2所示。
需要说明的是,衬底上可以形成有底层介质层1,如图2所示,所述底层介质层1内形成有底层金属层11及互连结构12。具体的,在其中一个实施例中,底层介质层1的***区和芯片区内分别形成有通孔,通孔内为由下至上依次叠置的互连结构12及底层金属层11。
在其中一个实施例中,互连结构12可以为单层结构、叠层结构或其他结构,本实施例对于互连结构12的结构并不做限定。在其中一个实施例中,互连结构12可以包括钛、氮化钛或钨等等中的一种或几种,本实施例对于互连结构12的材料并不做限定。在其中一个实施例中,互连结构12包括导电金属和阻挡层,导电金属可以包括但不仅限于钨、钌等,阻挡层可以包括但不仅限于氮化钛,钛等。
上述实施例中,步骤S2可以包括如下步骤:
如图3所示,在底层介质层1的***区和芯片区上形成第一介质层2。
对于步骤S3,如图4所示,在其中一个实施例中,步骤S3可以包括如下步骤:
S31:在第一介质层2上形成具有第一开口图案和第四开口图案的第一掩膜层,第一开口图案和第四开口图案分别位于***区和芯片区;
S32:利用第一开口图案和第四开口图案刻蚀第一介质层2,于第一介质层2中分别形成第一开口201和第四开口204,如图5所示;
S33:去除第一掩膜层并在第一开口201和第四开口204中形成第一填充层;
S34:在第一介质层2上形成具有第二开口图案和第五开口图案的第二掩 膜层,第二开口图案和第五开口图案分别暴露第一开口201和第四开口204中的第一填充层,且第二开口图案的宽度大于第一开口201的宽度,第五图案的宽度大于第四开口204的宽度;
S35:利用第二开口图案和第五开口图案刻蚀第一介质层2,于第一介质层2中分别形成第二开口202和第五开口205,如图6所示;
S36:去除第二掩膜层,并在第二开口202和第五开口205中形成第二填充层;
S37:在第一介质层2形成具有第三开口图案的第三掩膜层,第三开口图案暴露第二开口202中的第二填充层,且第三开口图案的宽度大于第二开口202的宽度;
S38:利用第三开口图案刻蚀第一介质层2,于第一介质层2中形成第三开口203,如图7所示;
S39:同时在第一开口201、第二开口202、第三开口203、第四开口204和第五开口205中填充导电材料分别形成保护结构21和功能结构22,如图8所示。
在其中一个实施例中,第一开口201的宽度与第四开口204的宽度相同;第二开口202的宽度与第五开口205的宽度相同。
进一步的,在其中一个实施例中,第一开口201的开口深度与第四开口204的开口深度相同;第二开口202的开口深度与第五开口205的开口深度相同。
在其中一个实施例中,第一开口201的开口深度大于第二开口202的开口深度;第二开口202的开口深度大于第三开口203的开口深度。
在其中一个实施例中,所述第一开口201的宽度小于所述第二开口202的宽度,所述第二开口202的宽度小于所述第三开口203的宽度;所述第四开口204的宽度小于所述第五开口205的宽度。
在其中一个实施例中,所述第一开口201、第二开口202及所述第三开口203的总深度与所述第四开口204及所述第五开口205的总深度相同。
其中,第一开口201中的导电材料即为第一子部分211,第二开口202中的导电材料即为第二子部分212,第三开口203中的导电材料即为第三子部分213,第四开口204中的导电材料即为第四子部分224,第五开口205中的导电材料即为第五子部分225。
具体的,在其中一个实施例中,保护结构21的材质可以包括但不仅限于铜。
具体的,所述导电材料可以为铜,通过电镀的方式同时在第一开口201、第二开口202、第三开口203、第四开口204、第五开口205内以及第一介质层2上方形成初始铜层,然后通过化学机械研磨的方式去除第一介质层2上方的初始铜层,以分别形成保护结构21和功能结构22,如图8所示。保护结构21可以单独形成在铜金属互连层中,以增强铜金属保护环的保护效果,同时节约生产成本。
在其中一个实施例中,形成的第一介质层2为单层结构;形成的保护结构21包括依次堆叠的N个子部分,其中N为大于3的整数。
在其中一个实施例中,形成的第一介质层2可以为单层结构或叠层结构,本实施例对于第一介质层2的结构并不做限定。具体的,在其中一个实施例中,第一介质层2可以为由下至上依次叠置的氮化硅层及氧化硅层;形成的保护结构21位于氧化硅层中。
上述实施例中提供的半导体结构的制作方法,其形成的半导体结构具有更多的子部分,使其拦截面积增大,使得该结构对芯片的保护作用进一步地增强。
在其中一个实施例中,依次堆叠的N个子部分的宽度依次增大。
上述实施例中提供的半导体结构的制作方法,其形成的半导体结构具有依次堆叠的N个子部分,且宽度依次增大,使得该结构更加稳固。
在其中一个实施例中,步骤S3之后,还可以包括:
S4:在第一介质层2上形成第二介质层3,如图9所示。
在其中一个实施例中,第二介质层3为单层结构;在其他实施例中,第 二介质层3还可以是叠层结构,本实施例对于第二介质层3的结构和排布并不做限定。在其中一个实施例中,第二介质层3可以包括氮化硅层、氧化硅层等等中的一种或几种,本实施例对于第二介质层3的材质并不做限定。具体的,在其中一个实施例中,第二介质层3可以为由下至上依次叠置的氮化硅层及氧化硅层。
在其中一个实施例中,步骤S4之后,还可以包括:
S5:在第二介质层3上形成具有第六开口图案和第七开口图案的第四掩膜层,第六开口图案和第七开口图案分别位于***区和芯片区;
S6:利用第六开口图案和第七开口图案刻蚀第二介质层3,于第二介质层3中分别形成第六开口306和第七开口307,如图10所示,第六开口306和第七开口307分别位于***区和芯片区。
在其中一个实施例中,步骤S6之后,还可以包括:
S7:在第六开口306及第七开口307内形成顶层互连结构31,如图11所示。
在其中一个实施例中,顶层互连结构31可以为单层结构、叠层结构或其他结构,本实施例对于顶层互连结构31的结构和排布并不做限定。在其中一个实施例中,顶层互连结构31可以包括铝、钛、氮化钛或钨等等中的一种或几种,本实施例对于顶层互连结构31的材料并不做限定。在其中一个实施例中,顶层互连结构31包括由下至上依次叠置的钛金属层及钨金属层。
在其中一个实施例中,步骤S7之后,还可以包括:
S8:在第二介质层3上形成顶层金属材料层4,如图12所示。
在其中一个实施例中,形成的顶层金属材料层4为单层结构或叠层结构,本实施例对于顶层金属材料层4的结构和排布并不做限定。在其中一个实施例中,顶层金属材料层4可以包括钛层与铝层依次交替叠置的叠层结构或氮化钛层与铝层依次交替叠置的叠层结构,所述顶层金属材料层的底层和顶层均为钛层或氮化钛层。
在其中一个实施例中,步骤S8之后,还可以包括:
S9:刻蚀顶层金属材料层4以形成顶层金属层41,并暴露出部分第二介质层3,如图13所示。
在其中一个实施例中,步骤S9之后,还可以包括:
S10:在第二介质层3及顶层金属层41上形成顶层介质层5,如图14所示。
在其中一个实施例中,形成的顶层介质层5可以为单层结构或叠层结构,本实施例对于顶层介质层5的结构并不做限定。具体的,在其中一个实施例中,顶层介质层5可以为由下至上依次叠置的氧化硅层及氮化硅层。
应该理解的是,虽然图1及图4的流程图中的各个步骤按照箭头的指示依次显示,但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明,这些步骤的执行并没有严格的顺序限制,这些步骤可以以其它的顺序执行。而且,图1及图4中的至少一部分步骤可以包括多个步骤或者多个阶段,这些步骤或者阶段并不必然是在同一时刻执行完成,而是可以在不同的时刻执行,这些步骤或者阶段的执行顺序也不必然是依次进行,而是可以与其它步骤或者其它步骤中的步骤或者阶段的至少一部分轮流或者交替地执行。
请继续参阅图8,本申请提供一种半导体结构,包括:
衬底,衬底包括***区和芯片区;
第一介质层2,位于衬底的***区和芯片区上;
保护结构21和功能结构22,分别位于***区和芯片区的第一介质层2中;
其中,保护结构21包括依次堆叠的第一子部分211、第二子部分212和第三子部分213,功能结构包括依次堆叠的第四子部分224和第五子部分225,第一子部分211、第二子部分212和第三子部分213的总高度与第四子部分224和第五子部分225的总高度相同。
上述实施例中提供的半导体结构,其结构更加稳固,拦截面积更大,对芯片的保护作用更强。
在其中一个实施例中,衬底可以包括但不仅限于硅衬底;在其他实施例中,衬底还可以为氮化镓衬底、磷化铟衬底或蓝宝石衬底等等。
在其中一个实施例中,衬底上形成有底层介质层1,在底层介质层1的***区和芯片区上形成第一介质层2,所述底层介质层1内形成有底层金属层11及互连结构12。具体的,在其中一个实施例中,底层介质层1的***区和芯片区内分别形成有通孔,通孔内为由下至上依次叠置的互连结构12及底层金属层11。
在其中一个实施例中,互连结构12可以为单层结构或叠层结构,本实施例对于互连结构12的结构并不做限定。在其中一个实施例中,互连结构12的材料可以包括钛、氮化钛或钨等等中的一种或几种,本实施例对于互连结构12的材料并不做限定。在其中一个实施例中,互连结构12包括导电金属和阻挡层,导电金属包括钨、钌等,阻挡层包括氮化钛,钛等。
在其中一个实施例中,第一介质层2为单层结构;在其他实施例中,第一介质层2还可以是叠层结构,本实施例对于第一介质层2的结构和排布并不做限定。在其中一个实施例中,第一介质层2可以包括氮化硅层、氧化硅层等等中的一种或几种,本实施例对于第一介质层2的材质并不做限定。具体的,在其中一个实施例中,第一介质层2可以为由下至上依次叠置的氮化硅层及氧化硅层;形成的保护结构21位于氧化硅层中。
在其中一个实施例中,第二子部分212的宽度大于第一子部分211的宽度;第三子部分213的宽度大于第二子部分的宽度212。
在其中一个实施例中,第一子部分211的宽度与第四子部分224的宽度相同;第二子部分212的宽度与第五子部分225的宽度相同。
在其中一个实施例中,第一子部分211、第二子部分212和第三子部分213为一体成型;第四子部分224和第五子部分225为一体成型。
在其中一个实施例中,保护结构21包括依次堆叠的N个子部分,N大于3的整数。
上述实施例中提供的半导体结构,通过更多的子部分,继续扩大拦截面 积,使得该结构对芯片的保护作用进一步地增强。
在其中一个实施例中,依次堆叠的N个子部分的宽度依次增大。
上述实施例中提供的半导体结构,依次堆叠的N个子部分的宽度依次增大,使得该结构更加稳固。
具体的,在其中一个实施例中,第一子部分211、第二子部分212和第三子部分213均为环状壁结构;第四子部分224为导电插塞结构;第五子部分225为导电线结构。
在其中一个实施例中,半导体结构还包括位于保护结构21下方的底部金属层。具体的,底层金属层的材质可以包括但不仅限于钨。
请继续参阅图9,在其中一个实施例中,半导体结构还包括:
第二介质层3,位于第一介质层2上。
在其中一个实施例中,第二介质层3为单层结构;在其他实施例中,第一介质层2还可以是叠层结构,本实施例对于第二介质层3的结构和排布并不做限定。在其中一个实施例中,第二介质层3可以包括氮化硅层、氧化硅层等等中的一种或几种,本实施例对于第二介质层3的材质并不做限定。具体的,在其中一个实施例中,第二介质层3可以为由下至上依次叠置的氮化硅层及氧化硅层。
请参阅图11,在其中一个实施例中,半导体结构还包括:
第六开口306;
第七开口307,第六开口306和第七开口307均位于所述第二介质层3内,且分别位于***区和芯片区;
顶层互连结构31,位于第六开口306和第七开口307内。
在其中一个实施例中,顶层互连结构31可以为单层结构、叠层结构或其他结构,本实施例对于顶层互连结构31的结构和排布并不做限定。在其中一个实施例中,顶层互连结构31可以包括钛、氮化钛或钨等等中的一种或几种,本实施例对于顶层互连结构31的材料并不做限定。在其中一个实施例中,顶层互连结构31包括由下至上依次叠置的钛金属层及钨金属层。
请继续参阅图12,在其中一个实施例中,半导体结构还包括:
顶层金属层41,位于第二介质层3的上表面。
在其中一个实施例中,顶层金属层41为单层结构或叠层结构,本实施例对于顶层金属层41的结构和排布并不做限定。在其中一个实施例中,顶层金属层41可以包括钛层与铝层依次交替叠置的叠层结构或氮化钛层与铝层依次交替叠置的叠层结构,所述顶层金属材料层的底层和顶层均为钛层或氮化钛层。
请继续参阅图14,在其中一个实施例中,半导体结构还包括:
顶层介质层5,位于第二介质层3及顶层金属层41的上表面。
在其中一个实施例中,形成的顶层介质层5可以为单层结构或叠层结构,本实施例对于顶层介质层5的结构并不做限定。具体的,在其中一个实施例中,顶层介质层5可以为由下至上依次叠置的氧化硅层及氮化硅层。
上所述实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对申请专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本申请构思的前提下,还可以做出若干变形和改进,这些都属于本申请的保护范围。因此,本申请专利的保护范围应以所附权利要求为准。
Claims (15)
- 一种半导体结构,包括:衬底,所述衬底包括***区和芯片区;第一介质层,位于所述衬底的所述***区和所述芯片区上;保护结构和功能结构,分别位于所述***区和所述芯片区的所述第一介质层中;其中,所述保护结构包括依次堆叠的第一子部分、第二子部分和第三子部分,所述功能结构包括依次堆叠的第四子部分和第五子部分,所述第一子部分、所述第二子部分和所述第三子部分的总高度与所述第四子部分和所述第五子部分的总高度相同。
- 根据权利要求1所述的半导体结构,其中,所述第二子部分的宽度大于所述第一子部分的宽度;所述第三子部分的宽度大于所述第二子部分的宽度。
- 根据权利要求2所述的半导体结构,其中,所述第一子部分的宽度与所述第四子部分的宽度相同;所述第二子部分的宽度与所述第五子部分的宽度相同。
- 根据权利要求1所述的半导体结构,其中,所述第一子部分、所述第二子部分和所述第三子部分为一体成型;所述第四子部分和所述第五子部分为一体成型。
- 根据权利要求1所述的半导体结构,其中,所述第一介质层为单层结构。
- 根据权利要求1所述的半导体结构,其中,所述保护结构包括依次堆叠的N个子部分,所述N为大于3的整数。
- 根据权利要求6所述的半导体结构,其中,所述依次堆叠的N个子部分的宽度依次增大。
- 根据权利要求1所述的半导体结构,其中,所述第一子部分、所述第二子部分和所述第三子部分均为环状壁结构;所述第四子部分为导电插塞结构;所述第五子部分为导电线结构。
- 根据权利要求4所述的半导体结构,其中,还包括:分别位于所述保护结构下方的底部金属层和上方的顶层互连结构;所述保护结构的材质包括铜;所述底部金属层的材质包括钨;所述顶层互连结构的材质包括钨或铝。
- 一种半导体结构的制作方法,包括:提供衬底,所述衬底包括***区和芯片区;在所述衬底的所述***区和所述芯片区上形成第一介质层;在所述***区和所述芯片区的所述第一介质层中分别形成保护结构和功能结构;其中,所述保护结构包括依次堆叠的第一子部分、第二子部分和第三子部分,所述功能结构包括依次堆叠的第四子部分和第五子部分,所述第一子部分、所述第二子部分和所述第三子部分的总高度与所述第四子部分和所述第五子部分的总高度相同。
- 根据权利要求10所述的半导体结构的制作方法,其中,所述在所述***区和所述芯片区的所述第一介质层中分别形成保护结构和功能结构,包括:在所述第一介质层上形成具有第一开口图案和第四开口图案的第一掩膜层,所述第一开口图案和所述第四开口图案分别位于所述***区和所述芯片区;利用所述第一开口图案和所述第四开口图案刻蚀所述第一介质层,于所述第一介质层中分别形成第一开口和第四开口;去除所述第一掩膜层并在所述第一开口和所述第四开口中形成第一填充层;在所述第一介质层上形成具有第二开口图案和第五开口图案的第二掩膜层,所述第二开口图案和所述第五开口图案分别暴露所述第一开口和所述第 四开口中的所述第一填充层,且所述第二开口图案的宽度大于所述第一开口的宽度,所述第五图案的宽度大于所述第四开口的宽度;利用所述第二开口图案和所述第五开口图案刻蚀所述第一介质层,于所述第一介质层中分别形成第二开口和第五开口;去除所述第二掩膜层并在所述第二开口和所述第五开口中形成第二填充层;在所述第一介质层形成具有第三开口图案的第三掩膜层,所述第三开口图案暴露所述第二开口中所述第二填充层,且所述第三开口图案的宽度大于所述第二开口的宽度;利用所述第三开口图案刻蚀所述第一介质层,于所述第一介质层中形成第三开口;同时在所述第一开口、所述第二开口、所述第三开口、所述第四开口和所述第五开口中填充导电材料分别形成所述保护结构和所述功能结构。
- 根据权利要求11述的半导体结构的制作方法,其中,所述第一开口的宽度与所述第四开口的宽度相同;所述第二开口的宽度与所述第五开口的宽度相同。
- 根据权利要求12所述的半导体结构的制作方法,其中,所述第一开口的开口深度与所述第四开口的开口深度相同;所述第二开口的开口深度与所述第五开口的开口深度相同。
- 根据权利要求10所述的半导体结构的制作方法,其中,形成的所述第一介质层为单层结构;形成的所述保护结构包括依次堆叠的N个子部分,所述N为大于3的整数。
- 根据权利要求14所述的半导体结构的制作方法,其中,所述依次堆叠的N个子部分的宽度依次增大。
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