WO2022179196A1 - 电路板及电子设备 - Google Patents

电路板及电子设备 Download PDF

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Publication number
WO2022179196A1
WO2022179196A1 PCT/CN2021/130803 CN2021130803W WO2022179196A1 WO 2022179196 A1 WO2022179196 A1 WO 2022179196A1 CN 2021130803 W CN2021130803 W CN 2021130803W WO 2022179196 A1 WO2022179196 A1 WO 2022179196A1
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WIPO (PCT)
Prior art keywords
layer
circuit board
circuit
substrate
electromagnetic interference
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Application number
PCT/CN2021/130803
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English (en)
French (fr)
Inventor
蒲乾林
李飞
王梓鉴
陆旭
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/799,917 priority Critical patent/US20230345619A1/en
Publication of WO2022179196A1 publication Critical patent/WO2022179196A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0215—Grounding of printed circuits by connection to external grounding means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0277—Bendability or stretchability details
    • H05K1/028—Bending or folding regions of flexible printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/043—Stacked PCBs with their backs attached to each other without electrical connection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/07—Electric details
    • H05K2201/0707—Shielding
    • H05K2201/0715—Shielding provided by an outer layer of PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09327—Special sequence of power, ground and signal layers in multilayer PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/421—Blind plated via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4691—Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the technical field of circuit boards, and in particular, relate to a circuit board and an electronic device.
  • circuit boards are an important part of electronic products.
  • it is necessary to open the cover layer covering the circuit layer to expose the grounding circuit of the circuit layer, so as to connect with the electromagnetic interference shielding film or the conductive layer. Local warping, uneven uneven problem.
  • Embodiments of the present disclosure provide a circuit board, including a first circuit board, the first circuit board including a first substrate and a first circuit layer disposed on a first side surface of the first substrate, the first circuit The layer includes a first ground circuit; the circuit board further includes a first protective layer and a first electromagnetic interference shielding layer sequentially stacked on the side of the first circuit layer away from the first substrate; the first The protective layer is provided with a first opening, the first opening exposes at least a part of the first grounding line, the first opening is filled with a first conductive material, and the surface of the first conductive material is in contact with the The height difference of the surface of the first protective layer away from the first substrate is 0 micrometers to 2 micrometers, and the first conductive material connects the first electromagnetic interference shielding layer and the first grounding line.
  • Embodiments of the present disclosure further provide an electronic device, including the circuit board described in any embodiment.
  • 1a is a schematic cross-sectional structure diagram of a circuit board of some technologies
  • Fig. 1b is a schematic structural diagram of the circuit board of Fig. 1a after the double-sided tape is attached;
  • FIG. 2 is a schematic cross-sectional structure diagram of a circuit board according to some exemplary embodiments
  • FIG. 3 is a schematic plan view of the circuit board of other exemplary embodiments.
  • FIG. 4 is a schematic cross-sectional structure diagram of the position A-A in FIG. 3 .
  • Figure 1a is a schematic diagram of the cross-sectional structure of some circuit boards. Because the circuit boards need to have high electromagnetic shielding and signal anti-interference capabilities, an electromagnetic interference shielding film (referred to as EMI film) will be attached to the surface. ) 13. By opening a window on the cover film (CVL) 12 of the circuit board, the EMI film 13 is connected to the ground wire of the circuit layer (the circuit layer is arranged on the substrate 10) 11, so as to realize the electromagnetic shielding function of the EMI film 13. . In this grounding method, at the grounding position of the EMI film 13 , a local level difference (height difference) will be formed here due to the opening of the cover film 12 .
  • EMI film electromagnetic interference shielding film
  • FIG. 1a which is a schematic diagram of the circuit board in FIG. 1a after attaching the double-sided tape
  • FIG. 1b which is a schematic diagram of the circuit board in FIG. 1a after attaching the double-sided tape
  • bubbles and trapped air will be formed between the double-sided tape 001 and the EMI film 13 corresponding to the opening position M of the cover film 12, resulting in the passage of air on the circuit board.
  • the double-sided tape 001 When the double-sided tape 001 is attached to the back of the flexible organic light emitting diode (OLED) screen, trapped air and air bubbles will cause deformation of the local material, resulting in poor film printing; After the film 13 is attached, the circuit board in the window area (for example, when the circuit board is a flexible circuit board) will warp due to the pulling of the stress, which affects the assembly of the module.
  • OLED organic light emitting diode
  • Embodiments of the present disclosure provide a circuit board, including a first circuit board, the first circuit board including a first substrate and a first circuit layer disposed on a first side surface of the first substrate, the first circuit The layer includes a first ground circuit; the circuit board further includes a first protective layer and a first electromagnetic interference shielding layer sequentially stacked on the side of the first circuit layer away from the first substrate; the first The protective layer is provided with a first opening, the first opening exposes at least a part of the first grounding line, the first opening is filled with a first conductive material, and the surface of the first conductive material is in contact with the The height difference of the surface of the first protective layer away from the first substrate is 0 micrometers to 2 micrometers, and the first conductive material connects the first electromagnetic interference shielding layer and the first grounding line.
  • the first conductive material is filled in the first opening of the first protective layer, and the height difference between the surface of the first conductive material and the surface of the first protective layer away from the first substrate is 0 ⁇ m
  • the first conductive material fills up the step difference at the first opening of the first protective layer, which ensures that the surface of the first protective layer is flat and does not increase the thickness of the circuit board.
  • the surface of the first electromagnetic interference shielding layer is also flat, so that when the double-sided tape or other adhesive layers are attached to the first electromagnetic interference shielding layer, no air bubbles will be generated between the two.
  • the first conductive material fills up the step difference at the first opening of the first protective layer, and after the first electromagnetic interference shielding layer is attached to the first protective layer, the circuit board (for example, the circuit board is flexible When the circuit board is used), the stress balance is achieved at the first opening to prevent the circuit board from lifting.
  • the first conductive material connects the first electromagnetic interference shielding layer and the first grounding line, so that the shielding function of the first electromagnetic interference shielding layer can be realized.
  • the height difference between the surface of the first conductive material and the surface of the first protective layer away from the first substrate is 0 ⁇ m to 2 ⁇ m, that is, the height difference between the surface of the first conductive material and the surface of the first protective layer is 0 ⁇ m to 2 ⁇ m.
  • the surface remote from the first substrate may be flush, or the surface of the first conductive material may be 0 to 2 microns higher or lower than the surface of the first protective layer remote from the first substrate.
  • the circuit board in the embodiment of the present disclosure may be a flexible circuit board (FPC), a printed circuit board (PCB), or a rigid-flex circuit board (RFPC), and the type of the circuit board is not limited in the embodiment of the present disclosure.
  • FPC flexible circuit board
  • PCB printed circuit board
  • RFPC rigid-flex circuit board
  • the circuit board in the embodiment of the present disclosure may be a single-sided circuit board, a double-sided circuit board, or a multi-layer circuit board, and the number of layers of the circuit layer may be one or more layers, which is not limited in the embodiment of the present disclosure.
  • FIG. 2 is a schematic cross-sectional structure diagram of a circuit board in some exemplary embodiments.
  • the circuit board includes a first circuit board 31, the first circuit board 31 includes a first substrate 311 and a first circuit layer 312 disposed on a first side of the first substrate 311, the first circuit layer 312 includes a first ground circuit; the circuit board further includes a first protective layer 71 and a first electromagnetic interference shielding layer 61 stacked on the side of the first circuit layer 312 away from the first substrate 311 in sequence;
  • the first protective layer 71 is provided with a first opening, the first opening exposes at least a part of the first ground line, the first opening is filled with a first conductive material 91 , and the first conductive material 91 is filled in the first opening.
  • the height difference between the surface of the material 91 and the surface of the first protective layer 71 away from the first substrate 311 is 0 ⁇ m to 2 ⁇ m (in the example of FIG.
  • the surface is flush with the surface of the first protective layer 71 away from the first substrate 311 ), and the first conductive material 91 connects the first electromagnetic interference shielding layer 61 and the first ground line.
  • the first circuit board 31 may further include a second circuit layer 313 disposed on the second side surface of the first substrate 311, and the second circuit layer 313 includes a second ground circuit; the The circuit board may further include a second protective layer 72 and a second electromagnetic interference shielding layer 62 stacked on the side of the second circuit layer 313 away from the first substrate 311 in sequence; There is a second opening, the second opening exposes at least a part of the second grounding line, the second opening is filled with a second conductive material 92, and the surface of the second conductive material 92 is in contact with the first ground circuit.
  • the height difference between the surfaces of the two protective layers 72 away from the first substrate 311 is 0 ⁇ m to 2 ⁇ m, and the second conductive material 92 connects the second electromagnetic interference shielding layer 62 and the second ground line.
  • the first protective layer 71 may be provided with one or more first openings, and the shapes of the first openings may be rectangles, circles, polygons, irregular shapes, etc.
  • the embodiment does not limit the number and shape of the first openings.
  • the material of the first substrate 311 may be polyimide (PI), polyetheretherketone, or polyester.
  • the material of the first wiring layer 312 and the second wiring layer 313 may be copper.
  • the first conductive material 91 may be a metal material, for example, any one or more of gold, silver, and copper.
  • the first conductive material 91 can be filled in the first opening through an electroplating process or a coating process, for example, metal copper can be filled in the first opening through an electroplating process, or silver paste can be dot-coated on the first opening through a coating process.
  • the silver paste is solidified in an opening to ensure that the height difference between the surface of the first conductive material 91 and the surface of the first protective layer 71 away from the first substrate 311 is 0 micrometers to 2 micrometers.
  • the material and formation method of the second conductive material 92 may be the same as the first conductive material 91 .
  • the first electromagnetic interference shielding layer 61 may be a first electromagnetic interference shielding film, and the first electromagnetic interference shielding film may include a protective film and a shielding function sequentially stacked on one side of the protective film layer and conductive adhesive layer.
  • the first electromagnetic interference shielding film can be attached to the first protective layer 71 through a thermocompression bonding process and is in contact with the first conductive material 91, and the shielding functional layer is connected to the first conductive material 91 through a conductive adhesive layer, so that the shielding function The layer is connected to the first ground line.
  • the first protective layer 71 may include a first cover layer 712 and a first adhesive layer 711 , and the first adhesive layer 711 is located on the first cover Between the layer 712 and the first circuit layer 312 , the first cover layer 712 is bonded to the first circuit layer 312 through the first adhesive layer 711 .
  • the process of forming the first protective layer 71 may include: affixing a first cover film with the first opening on the surface of the first circuit layer 312 , where the first cover film includes a first cover layer 712 and the first adhesive layer 711 provided on one side of the first cover layer 712, the first cover film can be thermally pressed on the first circuit layer 312 by a thermal pressing process (lamination process), During the bonding process, the first adhesive layer 711 is melted and the first cover layer 712 is bonded on the first circuit layer 312 .
  • the first conductive material 91 is first filled in the first opening to fill up the level difference of the first protective layer 71 at the first opening, and then, the first protective layer 71 and the first conductive material 91 are formed between the first protective layer 71 and the first conductive material 91
  • a first electromagnetic interference shielding layer (the first electromagnetic interference shielding layer may be an EMI film) 61 is attached thereon.
  • the second protective layer 72 may include a second cover layer 722 and a second adhesive layer 721, and the second adhesive layer 721 is located between the second cover layer 722 and the second adhesive layer 721. between the three circuit layers 322 .
  • the arrangement of the second protective layer 72 and the second electromagnetic interference shielding layer 62 may be the same as the arrangement of the first protective layer 71 and the first electromagnetic interference shielding layer 61 .
  • the first conductive material 91 is filled in the first opening of the first protective layer 71 , and the surface of the first conductive material 91 and the surface of the first protective layer 71 away from the first substrate 311 are The height difference is 0 micrometers to 2 micrometers. In this way, the first conductive material 91 fills up the step difference at the first opening of the first protective layer 71 to ensure that the surface of the first protective layer 71 is flat and does not increase the thickness of the circuit board. After an electromagnetic interference shielding layer 61 is attached to the first protective layer 71, the surface of the first electromagnetic interference shielding layer 61 is also flat.
  • the surface of the second electromagnetic interference shielding layer 62 is also flat.
  • the first double-sided tape 01 and the first double-sided tape 01 are formed between the electromagnetic interference shielding layers 61, and between the second double-sided tape 02 and the second electromagnetic interference shielding layer 62, no air bubbles or trapped air will be generated, so that the circuit board is attached to the flexible When the OLED screen is on the back, it will not cause poor film printing.
  • the first conductive material 91 fills up the level difference at the first opening of the first protective layer 71, and after the first electromagnetic interference shielding layer 61 is attached to the first protective layer 71, the circuit board (such as a circuit board When it is a flexible circuit board), the stress balance is achieved at the first opening to prevent the circuit board from tilting at the first opening.
  • the circuit board (for example, when the circuit board is a flexible circuit board) can achieve stress balance at the second opening to prevent the circuit board from lifting at the second opening.
  • FIG. 3 is a schematic plan view of the circuit board of some other exemplary embodiments.
  • the circuit board may be a rigid-flex board, and the circuit board may include a main body part 21 , a bendable part 22 located on the first side of the main body part 21 , and a flexible part 22 located on the first side of the main body part 21 .
  • the main body portion 21 may include a plurality of circuit layers, a surface of the main body portion 21 may be provided with a component area 211 , and the component area 211 may be provided with components such as chips, capacitors, and resistors.
  • the main body portion 21 may be provided with a connector 212, and the connector 212 may be connected to an external circuit.
  • the bendable portion 22 can be bent, the bendable portion 22 can be provided with a grounding area 221, and at least part of the grounding circuit of the circuit board can be exposed at the grounding area 221 by the film layer overlying the grounding circuit. At least part of the grounding line of the circuit board can be connected to the electromagnetic interference shielding layer of the circuit board to realize the electromagnetic shielding function of the electromagnetic interference shielding layer.
  • the binding part 23 is used to realize the binding connection between the circuit board and the external circuit.
  • the circuit board when the circuit board is applied to the display device, the circuit board can be bound and connected to the display panel through the binding part 23 , and the circuit board can be connected to the main board of the display device through the connector 212 .
  • One or more openings may also be provided on the circuit board to avoid some components or structures of the display device.
  • FIG. 4 is a schematic cross-sectional structure diagram of the position A-A in FIG. 3 .
  • the circuit board of this embodiment includes a first circuit board 31 , the first circuit board 31 includes a first substrate 311 and a first circuit layer 312 disposed on a first side surface of the first substrate 311 , the first circuit board 312 .
  • the circuit layer 312 includes a first ground circuit; the circuit board further includes a first protective layer 71 and a first electromagnetic interference shielding layer stacked on the side of the first circuit layer 312 away from the first substrate 311 in sequence 61; the first protective layer 71 is provided with a first opening, the first opening exposes at least a part of the first ground line, the first opening is filled with a first conductive material 91, the first opening is The height difference between the surface of a conductive material 91 and the surface of the first protective layer 71 away from the first substrate 311 is 0 ⁇ m to 2 ⁇ m (in the example of FIG.
  • the height difference is 0 ⁇ m, that is, the first conductive material 91 is flush with the surface of the first protective layer 71 away from the first substrate 311 ), the first conductive material 91 connects the first electromagnetic interference shielding layer 61 and the first grounding line .
  • the first conductive material 91 is filled in the first opening of the first protective layer 71, and the height of the surface of the first conductive material 91 and the surface of the first protective layer 71 away from the first substrate 311 The difference is 0 micrometers to 2 micrometers. In this way, the first conductive material 91 fills the step difference at the first opening of the first protective layer 71 to ensure that the surface of the first protective layer 71 is flat and does not increase the thickness of the circuit board. After the electromagnetic interference shielding layer 61 is attached to the first protective layer 71 , it can ensure that the surface of the first electromagnetic interference shielding layer 61 is also flat.
  • the first conductive material 91 fills up the level difference at the first opening of the first protective layer 71 , after the first electromagnetic interference shielding layer (in some examples, an EMI film) 61 is attached to the first protective layer 71 , the circuit board (for example, when the circuit board at the first opening is a flexible circuit board) can achieve stress balance at the first opening, and prevent the circuit board from lifting at the first opening.
  • the first electromagnetic interference shielding layer in some examples, an EMI film
  • the first conductive material 91 may be a metal material, such as any one or more of gold, silver, and copper.
  • the first conductive material 91 can be filled in the first opening through an electroplating process or a coating process, for example, metal copper can be filled in the first opening through an electroplating process, or silver paste can be dot-coated on the first opening through a coating process. inside an opening and solidify the silver paste.
  • the first conductive material 91 is formed in the first opening by an electroplating process or a coating process, which can meet the needs of different level difference filling of different circuit boards, and can ensure that the surface of the first conductive material 91 and The height difference of the surface of the first protective layer 71 away from the first substrate 311 is 0 micrometers to 2 micrometers, which can ensure reliable connection between the conductive first electromagnetic interference shielding layer 61 and the first grounding line.
  • the first protective layer 71 may be provided with one or more first openings, and the shapes of the first openings may be rectangles, circles, polygons, irregular shapes, etc. The number and shape are not limited.
  • the area where the first opening is located is the grounding area 221 in FIG. 3 .
  • the first electromagnetic interference shielding layer 61 may be a first electromagnetic interference shielding film, and the first electromagnetic interference shielding film may include a protective film and a shielding function sequentially stacked on one side of the protective film layer and conductive adhesive layer.
  • the first electromagnetic interference shielding film can be attached to the first protective layer 71 through a thermocompression bonding process and is in contact with the first conductive material 91, and the shielding functional layer is connected to the first conductive material 91 through a conductive adhesive layer, so that the shielding function The layer is connected to the first ground line.
  • the first protective layer 71 may include a first cover layer 712 and a first adhesive layer 711 , and the first adhesive layer 711 is located between the first cover layer 712 and the first adhesive layer 711 . Between a circuit layer 312 , the first cover layer 712 is bonded to the first circuit layer 312 through the first adhesive layer 711 .
  • the material of the first cover layer 712 may be polyimide, and the material of the first adhesive layer 711 may be epoxy resin or acrylic.
  • the process of forming the first protective layer 71 may include: affixing a first cover film with a first opening on the surface of the first circuit layer 312, where the first cover film includes the first cover layer 712 and a
  • the first adhesive layer 711 on one side of the cover layer 712 can be thermally pressed on the first circuit layer 312 by a thermal pressing process. During the thermal pressing process, the first adhesive layer 711 is melted and formed. The first cover layer 712 is bonded on the first circuit layer 312 .
  • the first conductive material 91 is first filled in the first opening to fill up the level difference of the first protective layer 71 at the first opening, and then, the first protective layer 71 and the first conductive material 91 are formed between the first protective layer 71 and the first conductive material 91 A first electromagnetic interference shielding layer 61 is attached thereon.
  • the thickness of the first substrate 311 may be 10 ⁇ m to 15 ⁇ m, such as 12.5 ⁇ m; the thickness of the first circuit layer 312 may be 10 ⁇ m to 15 ⁇ m, such as 12 ⁇ m; the first protection The layer 71 includes a first cover layer 712 and a first adhesive layer 711.
  • the thickness of the first protective layer 71 may be 25 microns to 35 microns, for example, the thickness of the first cover layer 712 is 12.5 microns, and the first adhesive layer 711
  • the thickness of the first protective layer 71 is 20 microns, that is, the thickness of the first protective layer 71 is 32.5 microns, then the thickness of the first conductive material 91 is 30.5 microns to 34.5 microns, such as 32.5 microns; the thickness of the first electromagnetic interference shielding layer 61 can be 10 microns to 20 microns, such as 16 microns.
  • the first circuit board 31 may further include a second circuit layer 313 disposed on the second side of the first substrate 311 , the second circuit layer 313 includes a second grounding circuit; the circuit board further includes a first insulating layer 51, a second electromagnetic interference shielding layer 62 and The conductive layer 81; the first insulating layer 51 and the second electromagnetic interference shielding layer 62 are provided with a second opening (the second opening penetrates the first insulating layer 51 and the second electromagnetic interference shielding layer 62), the second The opening exposes at least a part of the second ground line, the second opening is filled with a second conductive material 92 , and the surface of the second conductive material 92 is far from the second electromagnetic interference shielding layer 62 .
  • the height difference of the surface of the first substrate 311 is 0 ⁇ m to 2 ⁇ m (in the example of FIG. 4 , the height difference is 0 ⁇ m, that is, the surface of the second conductive material 92 and the second electromagnetic interference shielding layer 62 are far away from the first The surface of the substrate 311 is flush), and the second conductive material 92 connects the conductive layer 81 and the second ground line.
  • the second conductive material 92 may be a metal material, for example, any one or more of gold, silver, and copper.
  • the second conductive material 92 can be filled in the second opening by an electroplating process or a coating process, for example, metal copper can be filled in the second opening by an electroplating process, or silver paste can be dot-coated on the first opening by a coating process. inside the two openings and solidify the silver paste.
  • the second conductive material 92 is formed in the second opening by an electroplating process or a coating process, which can meet the needs of different level difference filling of different circuit boards, and can ensure that the surface of the second conductive material 92 and The height difference between the surface of the second electromagnetic interference shielding layer 62 away from the first substrate 311 is 0 micrometers to 2 micrometers, so as to ensure reliable connection between the conductive layer 81 and the second grounding line and realize the grounding of the conductive layer 81 .
  • the material of the first insulating layer 51 may be insulating ink, such as PSR ink.
  • the material of the second electromagnetic interference shielding layer 62 may be a metal material, such as silver, and the second electromagnetic interference shielding layer 62 may be formed by an electroplating process.
  • the material of the conductive layer 81 may be conductive glue.
  • the first insulating layer 51 may be a cover film with the second opening, the cover film includes an insulating film and an adhesive layer disposed on one side of the insulating film, and the cover film is laminated on the first insulating film through the adhesive layer. on the second circuit layer 313.
  • the circuit board may include a main body part 21 and a bendable part 22 located on a first side of the main body part 21 , and the main body part 21 may It includes a plurality of stacked circuit boards, each of which includes a substrate and at least one circuit layer disposed on the substrate, the plurality of circuit boards include the first circuit board 31, the first circuit The board 31 extends to the bendable portion 22 ; the first protective layer 71 , the first electromagnetic interference shielding layer 61 and the first opening are all located on the bendable portion 22 .
  • the first substrate 311 , the first circuit layer 312 and the second circuit layer 313 of the first circuit board 31 may all extend to the bendable portion 22 , that is, the main body portion 21 and the bendable portion 22 Both include the first circuit board 31 .
  • the main body portion 21 and the bendable portion 22 may both include the first insulating layer 51 , the second electromagnetic interference shielding layer 62 and the conductive layer 81 .
  • the second opening may be located in the main body part 21 or the bendable part 22 .
  • the number of circuit layers of the bendable portion 22 is less than the number of circuit layers of the main body portion 21 , and the number of circuit layers of the bendable portion 22 is less to facilitate bending.
  • the thickness of the second circuit layer 313 may be 15 ⁇ m to 25 ⁇ m, such as 21 ⁇ m; the thickness of the first insulating layer 51 may be 20 ⁇ m to 30 ⁇ m, such as 25 ⁇ m; the second electromagnetic interference The thickness of the shielding layer 62 can be 10 microns to 20 microns, such as 16 microns; the total thickness of the first insulating layer 51 and the second electromagnetic interference shielding layer 62 is, for example, 41 microns, and the thickness of the second conductive material 92 is 39 microns to 16 microns.
  • the thickness of the conductive layer 81 may be different between the main body part 21 and the bendable part 22, for example, the thickness of the conductive layer 81 of the main body part 21
  • the thickness of the conductive layer 81 of the bent portion 22 may be 20 micrometers to 40 micrometers, such as 30 micrometers.
  • the circuit board may further include a binding portion 23 located on a second side of the main body portion 21 opposite to the first side; the circuit boards include The second circuit board 32 , the second substrate 321 of the second circuit board 32 and at least one circuit layer extend to the binding portion 23 , and the lines of the second circuit board 32 that extend to the binding portion 23
  • the layer is provided with exposed bonding pins (positions indicated by reference numeral 322 in FIG. 4 ), which are configured for bonding connection with external circuits.
  • the binding portion 23 may include a third circuit layer 322 (the third circuit layer 322 is a layer of the second circuit board 32 ) sequentially stacked on the first side surface of the second substrate 321 .
  • the binding portion 23 may further include a third protective layer 73 disposed on the second side surface of the second substrate 321 .
  • the second protective layer 72 may include a second cover layer 722 and a second adhesive layer 721, and the second adhesive layer 721 is located between the second cover layer 722 and the second adhesive layer 721. between the three circuit layers 322 .
  • the third protective layer 73 may include a third cover layer 732 and a third adhesive layer 731 , and the third adhesive layer 731 is located between the third cover layer 732 and the second substrate 321 .
  • the materials of the second cover layer 722 and the third cover layer 732 may both be polyimide.
  • the materials of the second adhesive layer 721 and the third adhesive layer 731 may be epoxy resin or acrylic.
  • the formation process of the second protection layer 72 and the third protection layer 73 may be the same.
  • the surface of the third circuit layer 322 is affixed with a second protection layer.
  • the second cover film with three openings the second cover film includes a second cover layer 722 and a second adhesive layer 721 provided on one side of the second cover layer 722, and the second cover film can be heated by a thermocompression bonding process Pressed on the third circuit layer 322, the second adhesive layer 721 is melted and the second cover layer 722 is adhered to the third circuit layer 322 during the hot pressing process, and the third openings The binding pins are exposed.
  • the thickness of the second substrate 321 may be 10 ⁇ m to 30 ⁇ m, such as 20 ⁇ m; the thickness of the third circuit layer 322 may be 10 ⁇ m to 20 ⁇ m, such as 16 ⁇ m; the second protective layer 72 Including the second cover layer 722 and the second adhesive layer 721, the thickness of the second protective layer 72 can be 25 microns to 35 microns, for example, the thickness of the second cover layer 722 is 12.5 microns, the thickness of the second adhesive layer 721 is 20 microns; the third protective layer 73 includes a third covering layer 732 and a third adhesive layer 731, the thickness of the third protective layer 73 may be 25 microns to 35 microns, for example, the thickness of the third covering layer 732 is 12.5 microns , the thickness of the third adhesive layer 731 is 20 microns.
  • the plurality of circuit boards may further include a third circuit board 33 , the first circuit board 31 , the second circuit board 32 and the third circuit board
  • the boards 33 can be stacked in sequence, and two adjacent circuit boards are bonded by an adhesive layer.
  • the side surface of the second substrate 321 with the third circuit layer 322 may be disposed toward the first circuit board 31 .
  • the first circuit board 31 and the second circuit board 32 can be bonded by the first adhesive layer 41
  • the third circuit board 33 and the second circuit board 32 can be bonded by the second circuit board 32.
  • the adhesive layer 42 is bonded.
  • the second circuit board 32 in the main body portion 21 may include a third circuit layer 322 and a fourth circuit layer 323 respectively provided on two side surfaces of the second substrate 321 ,
  • the third circuit layer 322 may be located on the first side of the second substrate 321 facing the first circuit board 31
  • the fourth circuit layer 323 may be located on the second side of the second substrate 321 facing the third circuit board 33 .
  • the first circuit layer 312 of the first circuit board 31 is located on the first side of the first substrate 311 facing the second circuit board 32
  • the second circuit layer 313 of the first circuit board 31 is located on the first substrate 311 away from the second circuit. on the second side of the plate 32 .
  • the third circuit board 33 includes a third substrate 331, and a fifth circuit layer 332 and a sixth circuit layer 333 respectively disposed on two sides of the third substrate 331.
  • the fifth circuit layer 332 may be located on the third circuit board 331.
  • the sixth circuit layer 333 may be located on the second side of the third substrate 331 facing away from the second circuit board 32 .
  • the first adhesive layer 41 can be adhered between the first circuit layer 312 of the first circuit board 31 and the third circuit layer 322 of the second circuit board 32, and the second adhesive layer 42 can be adhered to Between the fourth circuit layer 323 of the second circuit board 32 and the fifth circuit layer 332 of the third circuit board 33 .
  • the number of circuit layers of the main body portion 21 of the circuit board in this example is six, and each of the three circuit boards includes a substrate and two circuit layers respectively disposed on two side surfaces of the substrate. In other examples, the number of layers of the circuit layers of the main body portion 21 can be designed as required, for example, three layers, four layers, and the like.
  • the material of the substrate of each of the three circuit boards may be polyimide, polyether ether ketone or polyester, and the material of each circuit layer may be copper.
  • the forming process of each circuit board may include: providing a base material, the base material including an insulating substrate and a copper layer covering both surfaces of the insulating substrate (there may be an adhesive layer or no layer between the insulating substrate and the copper layer). If the thickness of the copper layer of the substrate cannot reach the required thickness of the circuit layer, a copper layer of a certain thickness can be electroplated on the copper layer of the substrate; the copper layers on the two surfaces are exposed, developed, and etched. Form the required wiring layers.
  • the main body portion 21 may further include a second insulating layer 52 and a third electromagnetic interference shielding layer stacked on a side of the third circuit board 33 away from the second circuit board 32 in sequence.
  • the second insulating layer 52 may be disposed on the sixth circuit layer 333 of the third circuit board 33 , and the material of the second insulating layer 52 may be insulating ink, such as PSR ink.
  • the second insulating layer 52 may be a cover film, the cover film includes an insulating film and an adhesive layer disposed on one side of the insulating film, and the cover film is laminated on the sixth circuit layer 333 through the adhesive layer.
  • the third electromagnetic interference shielding layer 63 and the first electromagnetic interference shielding layer 61 may be integrally connected.
  • the third electromagnetic interference shielding layer 63 and the first electromagnetic interference shielding layer 61 are the same electromagnetic interference shielding film.
  • the interference shielding film is attached to the main body portion 21 and the bendable portion 22, or the third electromagnetic interference shielding layer 63 and the first electromagnetic interference shielding layer 61 are both of the same metal material, and can be formed on the main body by the same electroplating process at the same time. part 21 and the bendable part 22. As shown in FIG.
  • the surface of the circuit board close to the third circuit board 33 has a certain height difference between the main body portion 21 and the bendable portion 22 , and the portion of the main body portion 21 protruding from the bendable portion 22 includes The multiple circuit layers of the second circuit board 32 and the third circuit board 33, the end faces of the multiple circuit layers close to the bendable portion 22 are seen to be bare in FIG.
  • the material forming the insulating layer and the adhesive layer will partially overflow the edge of the circuit board, so that the multiple The end face of the circuit layer close to the bendable portion 22 is covered, so that the third electromagnetic interference shielding layer 63 and the first electromagnetic interference shielding layer 61 formed subsequently will not be in contact with the multiple circuit layers close to the bendable portion 22. face contact.
  • the thickness of the fourth circuit layer 323 may be 10 ⁇ m to 20 ⁇ m, such as 16 ⁇ m; the thickness of the third substrate 331 may be 10 ⁇ m to 15 ⁇ m, such as 12.5 ⁇ m; the fifth circuit layer 332 The thickness of the sixth circuit layer 333 may be 15 microns to 25 microns, such as 21 microns; the thickness of the second insulating layer 52 may be 20 microns to 30 microns, such as 25 microns.
  • the thickness of the third electromagnetic interference shielding layer 63 may be 10 ⁇ m to 20 ⁇ m, such as 16 ⁇ m; the thickness of the first adhesive layer 41 may be 30 ⁇ m to 50 ⁇ m, such as 40 ⁇ m; the thickness of the second adhesive layer 42 The thickness may be 30 microns to 50 microns, such as 40 microns.
  • the circuit boards of the embodiments of the present disclosure can be applied to various display modules (eg, OLED display modules, LCD display modules, etc.).
  • the circuit board may include a display circuit, and may also include a touch control circuit, and the display circuit and the touch control circuit may be arranged on different circuit layers.
  • the circuit board is bound and connected to the display panel of the display module through the binding portion 23, and the bendable portion 22 of the circuit board can be bent to the back of the display panel and fixed on the back of the display panel.
  • Embodiments of the present disclosure further provide an electronic device, including the circuit board described in any embodiment.
  • the electronic device may be a display device, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator, and other products or components with a display function.
  • the electronic device may be a touch display device.
  • connection means a fixed connection, or a detachable connection, or Connected integrally;
  • installed may be directly connected, or indirectly connected through an intermediary, or the internal communication of two elements.

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Abstract

一种电路板及电子设备，所述电路板包括第一线路板，第一线路板包括第一基板和设于第一基板的第一侧面上的第一线路层，第一线路层包括第一接地线路；所述电路板还包括依次叠设于第一线路层的远离第一基板的一侧的第一保护层和第一电磁干扰屏蔽层；第一保护层设有第一开口，第一开口将第一接地线路的至少一部分暴露出，第一开口内填充有第一导电材料，第一导电材料的表面与第一保护层的远离第一基板的表面的高度差为0微米至2微米，第一导电材料将第一电磁干扰屏蔽层和第一接地线路连接。

Description

电路板及电子设备
本申请要求于2021年2月25日提交中国专利局、申请号为202110215290.1、发明名称为“一种电路板及电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于电路板技术领域，具体涉及一种电路板及电子设备。
背景技术
目前，电子产品在生活中的使用越来越广泛，电路板是电子产品的重要部分。一些技术中，为了实现电路板的接地、电磁屏蔽等，需要将覆盖线路层的覆盖层开窗使线路层的接地线路露出，以与电磁干扰屏蔽膜或者导电层连接，但是，会造成电路板局部翘起、凹凸不平等问题。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供一种电路板，包括第一线路板，所述第一线路板包括第一基板和设于所述第一基板的第一侧面上的第一线路层，所述第一线路层包括第一接地线路；所述电路板还包括依次叠设于所述第一线路层的远离所述第一基板的一侧的第一保护层和第一电磁干扰屏蔽层；所述第一保护层设有第一开口，所述第一开口将所述第一接地线路的至少一部分暴露出，所述第一开口内填充有第一导电材料，所述第一导电材料的表面与所述第一保护层的远离所述第一基板的表面的高度差为0微米至2微米，所述第一导电材料将所述第一电磁干扰屏蔽层和所述第一接地线路连接。
本公开实施例还提供一种电子设备，包括任一实施例所述的电路板。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。附图中部件的形状和大小不反映真实比例，目的只是示意说明本公开内容。
图1a为一些技术的电路板的剖面结构示意图；
图1b为图1a的电路板在贴附双面胶带后的结构示意图；
图2为一些示例性实施例的电路板的剖面结构示意图；
图3为另一些示例性实施例的电路板的平面结构示意图；
图4为图3中A-A位置的剖面结构示意图。
具体实施方式
本领域的普通技术人员应当理解，可以对本公开实施例的技术方案进行修改或者等同替换，而不脱离本公开实施例技术方案的精神和范围，均应涵盖在本公开的权利要求范围当中。
一些技术中，如图1a所示，图1a为一些电路板的剖面结构示意图，电路板因需要具有较高的电磁屏蔽、信号抗干扰能力，会在表面贴附电磁干扰屏蔽膜(简称EMI膜)13，通过在电路板的覆盖膜(简称CVL)12上开窗，使EMI膜13与线路层(线路层设于基板10上)11的地线相接，实现EMI膜13的电磁屏蔽功能。此种接地方式，在EMI膜13的接地位置，由于覆盖膜12开窗，此处会形成局部段差(高度差)。一方面，如图1a所示，由于现在的消费类电子产品对电路板的屏蔽要求更高，电路板上EMI膜13的接地点数量多，面积小，导致电路板表面凹凸不平，且无法从EMI膜13外表面填补段差。这种情况下，如图1b所示，图1b为图1a的电路板在贴附双面胶带后的结构示意图，当在电路板表面(即EMI膜13外表面)贴附厚度较薄的双面胶带001或其他粘结层时，由于电路板表面不平整，双面胶带001和EMI膜13之间对应于覆盖膜12开窗的位置M就会形成气泡和困气，导致在电路板通过双面胶带001贴附到柔性有机发光二极管(OLED)屏背面时，困气和气泡就会造成局部位置材料变形，引发膜印不良；另一方面，因 覆盖膜12开窗区域存在段差，EMI膜13贴附后，由于应力的拉扯会使得开窗区的电路板(比如电路板为柔性电路板时)发生翘起而影响模组的装配。
本公开实施例提供一种电路板，包括第一线路板，所述第一线路板包括第一基板和设于所述第一基板的第一侧面上的第一线路层，所述第一线路层包括第一接地线路；所述电路板还包括依次叠设于所述第一线路层的远离所述第一基板的一侧的第一保护层和第一电磁干扰屏蔽层；所述第一保护层设有第一开口，所述第一开口将所述第一接地线路的至少一部分暴露出，所述第一开口内填充有第一导电材料，所述第一导电材料的表面与所述第一保护层的远离所述第一基板的表面的高度差为0微米至2微米，所述第一导电材料将所述第一电磁干扰屏蔽层和所述第一接地线路连接。
本公开实施例的电路板，通过在第一保护层的第一开口内填充第一导电材料，且第一导电材料的表面与第一保护层的远离第一基板的表面的高度差为0微米至2微米，这样，一方面，第一导电材料将第一保护层的第一开口处的段差填补，保证了第一保护层表面平整，且不增加电路板厚度，后续在第一电磁干扰屏蔽层贴附于第一保护层上后，第一电磁干扰屏蔽层表面同样平整，如此，在第一电磁干扰屏蔽层上贴附双面胶带或其他粘结层时两者之间不会产生气泡或困气，从而在电路板通过双面胶带或其他粘结层贴附到柔性OLED屏背面时，不会造成膜印不良。另一方面，第一导电材料将第一保护层的第一开口处的段差填补，后续在第一电磁干扰屏蔽层贴附于第一保护层上后，可以使电路板(比如电路板为柔性电路板时)在第一开口处达到应力平衡，防止电路板发生翘起。此外，第一导电材料将第一电磁干扰屏蔽层和第一接地线路连接，可以实现第一电磁干扰屏蔽层的屏蔽功能。
本公开实施例的电路板，第一导电材料的表面与第一保护层的远离第一基板的表面的高度差为0微米至2微米，即，第一导电材料的表面与第一保护层的远离第一基板的表面可以平齐，或者，第一导电材料的表面高于或低于第一保护层的远离第一基板的表面0微米至2微米。
本公开实施例的电路板可以为柔性电路板(FPC)、印刷电路板(PCB)或者软硬结合电路板(RFPC)，本公开实施例对电路板的类型并不限定。
本公开实施例的电路板可以为单面电路板、双面电路板或者多层电路板， 线路层的层数可以为一层或多层，本公开实施例对此并不限定。
在一些示例性实施例中，如图2所示，图2为一些示例性实施例的电路板的剖面结构示意图。所述电路板包括第一线路板31，所述第一线路板31包括第一基板311和设于所述第一基板311的第一侧面上的第一线路层312，所述第一线路层312包括第一接地线路；所述电路板还包括依次叠设于所述第一线路层312的远离所述第一基板311的一侧的第一保护层71和第一电磁干扰屏蔽层61；所述第一保护层71设有第一开口，所述第一开口将所述第一接地线路的至少一部分暴露出，所述第一开口内填充有第一导电材料91，所述第一导电材料91的表面与所述第一保护层71的远离所述第一基板311的表面的高度差为0微米至2微米(图2的示例中高度差为0微米，即第一导电材料91的表面与所述第一保护层71的远离所述第一基板311的表面平齐)，所述第一导电材料91将所述第一电磁干扰屏蔽层61和所述第一接地线路连接。
本实施例中，所述第一线路板31还可以包括设于所述第一基板311的第二侧面上的第二线路层313，所述第二线路层313包括第二接地线路；所述电路板还可以包括依次叠设于所述第二线路层313的远离所述第一基板311的一侧的第二保护层72和第二电磁干扰屏蔽层62；所述第二保护层72设有第二开口，所述第二开口将所述第二接地线路的至少一部分暴露出，所述第二开口内填充有第二导电材料92，所述第二导电材料92的表面与所述第二保护层72的远离所述第一基板311的表面的高度差为0微米至2微米，所述第二导电材料92将所述第二电磁干扰屏蔽层62和所述第二接地线路连接。
本实施例的一个示例中，如图2所示，第一保护层71可以设有一个或多个第一开口，第一开口的形状可以为矩形、圆形、多边形、不规则图形等，本实施例对第一开口的数目和形状不限。本实施例的一个示例中，第一基板311的材料可以为聚酰亚胺(PI)、聚醚醚酮或者涤纶。第一线路层312和第二线路层313的材料可以为铜。本实施例的一个示例中，第一导电材料91可以为金属材料，比如，金、银、铜中的任一种或多种。可通过电镀工艺或涂覆工艺将第一导电材料91填充于第一开口内，比如，可通过电镀工艺将金属铜填充于第一开口内，或者可通过涂覆工艺将银浆点涂于第一开口内并使 银浆固化，保证第一导电材料91的表面与第一保护层71的远离所述第一基板311的表面的高度差为0微米至2微米。第二导电材料92的材料和形成方式可与第一导电材料91相同。
本实施例的一个示例中，所述第一电磁干扰屏蔽层61可以为第一电磁干扰屏蔽膜，第一电磁干扰屏蔽膜可以包括保护膜、依次叠设于保护膜的一侧面上的屏蔽功能层和导电胶层。第一电磁干扰屏蔽膜可通过热压合工艺贴附于所述第一保护层71上并与第一导电材料91接触，屏蔽功能层通过导电胶层与第一导电材料91连接，从而屏蔽功能层与第一接地线路连接。
本实施例的一个示例中，如图2所示，所述第一保护层71可以包括第一覆盖层712和第一粘胶层711，所述第一粘胶层711位于所述第一覆盖层712和所述第一线路层312之间，第一覆盖层712通过第一粘胶层711粘接于第一线路层312上。本实施例的一个示例中，形成第一保护层71的过程可以包括：在第一线路层312的表面贴上具有所述第一开口的第一覆盖膜，第一覆盖膜包括第一覆盖层712和设于第一覆盖层712的一侧面上的第一粘胶层711，可采用热压合工艺(层压工艺)将第一覆盖膜热压合在第一线路层312上，热压合过程中第一粘胶层711融化并将第一覆盖层712粘接在第一线路层312上。形成第一保护层71后，先在第一开口内部填充第一导电材料91以将第一保护层71在第一开口处的段差填补，然后，在第一保护层71和第一导电材料91上贴附第一电磁干扰屏蔽层(第一电磁干扰屏蔽层可为EMI膜)61。
本实施例的一个示例中，所述第二保护层72可以包括第二覆盖层722和第二粘胶层721，所述第二粘胶层721位于所述第二覆盖层722和所述第三线路层322之间。第二保护层72和第二电磁干扰屏蔽层62的设置方式可与第一保护层71和第一电磁干扰屏蔽层61的设置方式相同。
本公开实施例的电路板，通过在第一保护层71的第一开口内填充第一导电材料91，且第一导电材料91的表面与第一保护层71的远离第一基板311的表面的高度差为0微米至2微米，这样，第一导电材料91将第一保护层71的第一开口处的段差填补，保证了第一保护层71表面平整，且不增加电路板厚度，在第一电磁干扰屏蔽层61贴附于第一保护层71上后，第一电磁 干扰屏蔽层61表面同样平整，同理，在第二电磁干扰屏蔽层62贴附于第二保护层72上后，第二电磁干扰屏蔽层62表面同样平整。如此，在第一电磁干扰屏蔽层61上贴附第一双面胶01后，以及在第二电磁干扰屏蔽层62上贴附第二双面胶02后，第一双面胶01与第一电磁干扰屏蔽层61之间，以及第二双面胶02与第二电磁干扰屏蔽层62之间不会产生气泡或困气，从而在电路板通过双面胶带或其他粘结层贴附到柔性OLED屏背面时，不会造成膜印不良。此外，第一导电材料91将第一保护层71的第一开口处的段差填补，后续在第一电磁干扰屏蔽层61贴附于第一保护层71上后，可以使电路板(比如电路板为柔性电路板时)在第一开口处实现应力平衡，防止电路板在第一开口处发生翘起，同理，后续在第二电磁干扰屏蔽层62贴附于第二保护层72上后，可以使电路板(比如电路板为柔性电路板时)在第二开口处实现应力平衡，防止电路板在第二开口处发生翘起。
在另一些示例性实施例中，如图3所示，图3为另一些示例性实施例的电路板的平面结构示意图。所述电路板可以为软硬结合板，所述电路板可以包括主体部21、位于所述主体部21的第一侧的可弯折部22，以及位于所述主体部21的与第一侧相对的第二侧的绑定部23。所述主体部21可以包括多个线路层，所述主体部21的一个表面可以设有元器件区211，元器件区211可以设置芯片、电容、电阻等元器件。所述主体部21可以设有连接器212，连接器212可以与外部电路连接。所述可弯折部22可以弯折，所述可弯折部22可以设有接地区221，电路板的至少部分接地线路可以在接地区221被接地线路上方覆盖的膜层暴露出，暴露出的至少部分接地线路可以与电路板的电磁干扰屏蔽层连接，实现电磁干扰屏蔽层的电磁屏蔽功能。所述绑定部23用于实现电路板与外部电路的绑定连接。在一些示例中，当电路板应用于显示装置时，可通过绑定部23将电路板绑定连接在显示面板上，通过连接器212将电路板与显示装置的主板连接。电路板上还可以设有一个或多个开孔，以避让显示装置的一些部件或结构。
在一些示例性实施例中，如图4所示，图4为图3中A-A位置的剖面结构示意图。本实施例的电路板包括第一线路板31，所述第一线路板31包括第一基板311和设于所述第一基板311的第一侧面上的第一线路层312，所 述第一线路层312包括第一接地线路；所述电路板还包括依次叠设于所述第一线路层312的远离所述第一基板311的一侧的第一保护层71和第一电磁干扰屏蔽层61；所述第一保护层71设有第一开口，所述第一开口将所述第一接地线路的至少一部分暴露出，所述第一开口内填充有第一导电材料91，所述第一导电材料91的表面与所述第一保护层71的远离所述第一基板311的表面的高度差为0微米至2微米(图4的示例中高度差为0微米，即第一导电材料91的表面与所述第一保护层71的远离所述第一基板311的表面平齐)，所述第一导电材料91将所述第一电磁干扰屏蔽层61和所述第一接地线路连接。
本实施例的电路板，通过在第一保护层71的第一开口内填充第一导电材料91，且第一导电材料91的表面与第一保护层71的远离第一基板311的表面的高度差为0微米至2微米，这样，第一导电材料91将第一保护层71的第一开口处的段差填补，保证了第一保护层71表面平整，且不增加电路板厚度，在第一电磁干扰屏蔽层61贴附于第一保护层71上后，可保证第一电磁干扰屏蔽层61表面同样平整。此外，第一导电材料91将第一保护层71的第一开口处的段差填补，后续在第一电磁干扰屏蔽层(一些示例中可为EMI膜)61贴附于第一保护层71上后，可以使电路板(比如第一开口处电路板为柔性电路板时)在第一开口处实现应力平衡，防止电路板在第一开口处发生翘起。
本实施例的一个示例中，所述第一导电材料91可以为金属材料，比如，金、银、铜中的任一种或多种。可通过电镀工艺或涂覆工艺将第一导电材料91填充于第一开口内，比如，可通过电镀工艺将金属铜填充于第一开口内，或者可通过涂覆工艺将银浆点涂于第一开口内并使银浆固化。采用电镀工艺或涂覆工艺在第一开口内形成第一导电材料91，可以满足不同电路板的不同段差填补需求的情况，不同段差填补需求的情况下均可以保证第一导电材料91的表面与第一保护层71的远离所述第一基板311的表面的高度差为0微米至2微米，可保证导第一电磁干扰屏蔽层61和所述第一接地线路可靠连接。
本实施例的一个示例中，第一保护层71可以设有一个或多个第一开口，第一开口的形状可以为矩形、圆形、多边形、不规则图形等，本实施例对第 一开口的数目和形状不限。在一些示例中，第一开口的所在区域即为图3中的接地区221。
本实施例的一个示例中，所述第一电磁干扰屏蔽层61可以为第一电磁干扰屏蔽膜，第一电磁干扰屏蔽膜可以包括保护膜、依次叠设于保护膜的一侧面上的屏蔽功能层和导电胶层。第一电磁干扰屏蔽膜可通过热压合工艺贴附于所述第一保护层71上并与第一导电材料91接触，屏蔽功能层通过导电胶层与第一导电材料91连接，从而屏蔽功能层与第一接地线路连接。
本实施例的一个示例中，所述第一保护层71可以包括第一覆盖层712和第一粘胶层711，所述第一粘胶层711位于所述第一覆盖层712和所述第一线路层312之间，第一覆盖层712通过第一粘胶层711粘接于第一线路层312上。其中，第一覆盖层712的材料可以为聚酰亚胺，第一粘胶层711的材料可以为环氧树脂或亚克力。示例性地，形成第一保护层71的过程可以包括：在第一线路层312的表面贴上具有第一开口的第一覆盖膜，第一覆盖膜包括第一覆盖层712和设于第一覆盖层712的一侧面上的第一粘胶层711，可采用热压合工艺将第一覆盖膜热压合在第一线路层312上，热压合过程中第一粘胶层711融化并将第一覆盖层712粘接在第一线路层312上。形成第一保护层71后，先在第一开口内部填充第一导电材料91以将第一保护层71在第一开口处的段差填补，然后，在第一保护层71和第一导电材料91上贴附第一电磁干扰屏蔽层61。
本实施例的一个示例中，所述第一基板311的厚度可以为10微米至15微米，比如12.5微米；第一线路层312的厚度可以为10微米至15微米，比如12微米；第一保护层71包括第一覆盖层712和第一粘胶层711，第一保护层71的厚度可以为25微米至35微米，比如，第一覆盖层712的厚度为12.5微米，第一粘胶层711的厚度为20微米，即第一保护层71的厚度为32.5微米，则第一导电材料91的厚度为30.5微米至34.5微米，比如为32.5微米；第一电磁干扰屏蔽层61的厚度可以为10微米至20微米，比如16微米。
在一些示例性实施例中，如图4所示，所述第一线路板31还可以包括设于所述第一基板311的第二侧面上的第二线路层313，所述第二线路层313包括第二接地线路；所述电路板还包括依次叠设于所述第二线路层313的远 离所述第一基板311的一侧的第一绝缘层51、第二电磁干扰屏蔽层62和导电层81；所述第一绝缘层51和所述第二电磁干扰屏蔽层62设有第二开口(第二开口贯穿第一绝缘层51和第二电磁干扰屏蔽层62)，所述第二开口将所述第二接地线路的至少一部分暴露出，所述第二开口内填充有第二导电材料92，所述第二导电材料92的表面与所述第二电磁干扰屏蔽层62的远离所述第一基板311的表面的高度差为0微米至2微米(图4的示例中高度差为0微米，即第二导电材料92的表面与第二电磁干扰屏蔽层62的远离所述第一基板311的表面平齐)，所述第二导电材料92将所述导电层81和所述第二接地线路连接。
本实施例的一个示例中，所述第二导电材料92可以为金属材料，比如，金、银、铜中的任一种或多种。可通过电镀工艺或涂覆工艺将第二导电材料92填充于第二开口内，比如，可通过电镀工艺将金属铜填充于第二开口内，或者可通过涂覆工艺将银浆点涂于第二开口内并使银浆固化。采用电镀工艺或涂覆工艺在第二开口内形成第二导电材料92，可以满足不同电路板的不同段差填补需求的情况，不同段差填补需求的情况下均可以保证第二导电材料92的表面与第二电磁干扰屏蔽层62的远离第一基板311的表面的高度差为0微米至2微米，从而可保证导电层81和第二接地线路可靠连接，实现导电层81的接地。
本实施例的一个示例中，第一绝缘层51的材料可以为绝缘油墨，比如PSR油墨。第二电磁干扰屏蔽层62的材料可以为金属材料，比如银，可通过电镀工艺形成第二电磁干扰屏蔽层62。所述导电层81的材料可以为导电胶。在其他示例中，第一绝缘层51可以为具有所述第二开口的覆盖膜，覆盖膜包括绝缘膜和设于绝缘膜一侧面上的粘胶层，覆盖膜通过粘胶层压合于第二线路层313上。
在一些示例性实施例中，如图3、图4所示，所述电路板可以包括主体部21和位于所述主体部21的第一侧的可弯折部22，所述主体部21可以包括叠设的多个线路板，每个所述线路板包括基板和设于所述基板上的至少一个线路层，所述多个线路板包括所述第一线路板31，所述第一线路板31延伸至所述可弯折部22；所述第一保护层71、所述第一电磁干扰屏蔽层61和 所述第一开口均位于所述可弯折部22。
本实施例的一个示例中，第一线路板31的第一基板311、第一线路层312和第二线路层313可均延伸至可弯折部22，即主体部21和可弯折部22均包括第一线路板31。本实施例的一个示例中，所述主体部21和所述可弯折部22可以均包括所述第一绝缘层51、所述第二电磁干扰屏蔽层62和所述导电层81。所述第二开口可以位于所述主体部21或者所述可弯折部22。所述可弯折部22的线路层的层数少于主体部21的线路层的层数，可弯折部22的线路层的层数较少以利于实现弯折。
本实施例的一个示例中，第二线路层313的厚度可以为15微米至25微米，比如21微米；第一绝缘层51的厚度可以为20微米至30微米，比如25微米；第二电磁干扰屏蔽层62的厚度可以为10微米至20微米，比如16微米；第一绝缘层51和第二电磁干扰屏蔽层62的总厚度比如为41微米，则第二导电材料92的厚度为39微米至43微米，比如为41微米；导电层81的厚度在主体部21和可弯折部22可以不同，比如，主体部21的导电层81的厚度可以为100微米至200微米，比如150微米，可弯折部22的导电层81的厚度可以为20微米至40微米，比如30微米。
在一些示例性实施例中，如图4所示，所述电路板还可以包括位于所述主体部21的与第一侧相对的第二侧的绑定部23；所述多个线路板包括第二线路板32，所述第二线路板32的第二基板321和至少一个线路层延伸至所述绑定部23，所述第二线路板32的延伸至所述绑定部23的线路层设有裸露的绑定引脚(图4中标号322所指的位置)，所述绑定引脚配置为与外部电路绑定连接。
本实施例的一个示例中，所述绑定部23可以包括依次叠设于所述第二基板321的第一侧面上的第三线路层322(第三线路层322为第二线路板32的一个线路层)和第二保护层72，所述第三线路层322的远离所述主体部21的一端设有所述绑定引脚，所述第二保护层72将所述绑定引脚暴露出；所述绑定部23还可以包括设于所述第二基板321的第二侧面上的第三保护层73。
本实施例的一个示例中，所述第二保护层72可以包括第二覆盖层722和第二粘胶层721，所述第二粘胶层721位于所述第二覆盖层722和所述第 三线路层322之间。所述第三保护层73可以包括第三覆盖层732和第三粘胶层731，所述第三粘胶层731位于所述第三覆盖层732和所述第二基板321之间。其中，第二覆盖层722、第三覆盖层732的材料可以均为聚酰亚胺。第二粘胶层721、第三粘胶层731的材料可以为环氧树脂或亚克力。示例性地，所述第二保护层72和所述第三保护层73的形成过程可以相同，以第二保护层72的形成过程为例说明，在第三线路层322的表面贴上具有第三开口的第二覆盖膜，第二覆盖膜包括第二覆盖层722和设于第二覆盖层722的一侧面上的第二粘胶层721，可采用热压合工艺将第二覆盖膜热压合在第三线路层322上，热压合过程中第二粘胶层721融化并将第二覆盖层722粘接在第三线路层322上，且第三开口将第三线路层322的所述绑定引脚暴露出。
本实施例的一个示例中，第二基板321的厚度可以为10微米至30微米，比如20微米；第三线路层322的厚度可以为10微米至20微米，比如16微米；第二保护层72包括第二覆盖层722和第二粘胶层721，第二保护层72的厚度可以为25微米至35微米，比如，第二覆盖层722的厚度为12.5微米，第二粘胶层721的厚度为20微米；第三保护层73包括第三覆盖层732和第三粘胶层731，第三保护层73的厚度可以为25微米至35微米，比如，第三覆盖层732的厚度为12.5微米，第三粘胶层731的厚度为20微米。
在一些示例性实施例中，如图4所示，所述多个线路板还可以包括第三线路板33，所述第一线路板31、所述第二线路板32和所述第三线路板33可以依次层叠设置，相邻的两个线路板之间通过粘接层粘接，所述第一基板311的设有第一线路层312的第一侧面朝向所述第二线路板32设置。所述第二基板321的设有第三线路层322的侧面可以朝向第一线路板31设置。其中，所述主体部21内，第一线路板31与第二线路板32之间可通过第一粘接层41粘接，第三线路板33与第二线路板32之间可通过第二粘接层42粘接。
本实施例的一个示例中，所述主体部21内所述第二线路板32可以包括分别设于所述第二基板321的两个侧面上的第三线路层322和第四线路层323，第三线路层322可以位于第二基板321的朝向第一线路板31的第一侧面上，第四线路层323可以位于第二基板321的朝向第三线路板33的第二侧面上。第一线路板31的第一线路层312位于第一基板311的朝向第二线路板 32的第一侧面上，第一线路板31的第二线路层313位于第一基板311的背离第二线路板32的第二侧面上。所述第三线路板33包括第三基板331，以及分别设于所述第三基板331的两个侧面上的第五线路层332和第六线路层333，第五线路层332可以位于第三基板331的朝向第二线路板32的第一侧面上，第六线路层333可以位于第三基板331的背离第二线路板32的第二侧面上。本示例中，第一粘接层41可以粘接在第一线路板31的第一线路层312和第二线路板32的第三线路层322之间，第二粘接层42可以粘接在第二线路板32的第四线路层323和第三线路板33的第五线路层332之间。本示例的电路板的主体部21的线路层的层数为六层，三个线路板中每个线路板均包括一个基板和分别设于基板两个侧面上的两个线路层。在其他示例中，可根据需要设计主体部21的线路层的层数，比如，可以为三次、四层等。三个线路板中每个线路板的基板的材料可以为聚酰亚胺、聚醚醚酮或者涤纶，每个线路层的材料可以为铜。在一些示例中，每个线路板的形成过程可以包括：提供基材，基材包括绝缘基板和覆盖在绝缘基板两个表面上的铜层(绝缘基板和铜层之间可以有胶层或无胶层)，如果基材的铜层厚度不能达到所需线路层厚度，可在基材的铜层上电镀一定厚度的铜层；对两个表面的铜层采用曝光、显影、刻蚀等工序形成所需线路层。
本实施例的一个示例中，所述主体部21还可以包括依次叠设于所述第三线路板33的远离所述第二线路板32一侧的第二绝缘层52和第三电磁干扰屏蔽层63。第二绝缘层52可设于第三线路板33的第六线路层333上，第二绝缘层52的材料可以为绝缘油墨，比如PSR油墨。在其他示例中，第二绝缘层52可以为覆盖膜，覆盖膜包括绝缘膜和设于绝缘膜一侧面上的粘胶层，覆盖膜通过粘胶层压合于第六线路层333上。所述第三电磁干扰屏蔽层63和所述第一电磁干扰屏蔽层61可以一体连接，比如，第三电磁干扰屏蔽层63和第一电磁干扰屏蔽层61为同一个电磁干扰屏蔽膜，该电磁干扰屏蔽膜贴附在主体部21和可弯折部22上，或者第三电磁干扰屏蔽层63和第一电磁干扰屏蔽层61均为同种金属材料，可通过同一次电镀工艺同时形成在主体部21和可弯折部22上。如图4所示，电路板的靠近第三线路板33的表面在主体部21和可弯折部22之间存在一定的高度段差，主体部21的凸出于可弯折部22的部分包括第二线路板32和第三线路板33的多个线路层，此多个线路层的 靠近可弯折部22的端面在图4中看着是裸露的，但是在实际的电路板制作过程中，在线路层表面形成绝缘层过程中，以及将相邻线路板之间采用粘接层粘接过程中，形成绝缘层和粘接层的材料会有部分溢出线路板边缘从而将所述多个线路层的靠近可弯折部22的端面覆盖，这样，后续形成的第三电磁干扰屏蔽层63和第一电磁干扰屏蔽层61不会与所述多个线路层的靠近可弯折部22的端面接触。
本实施例的一个示例中，第四线路层323的厚度可以为10微米至20微米，比如16微米；第三基板331的厚度可以为10微米至15微米，比如12.5微米；第五线路层332的厚度可以为10微米至20微米，比如12微米；第六线路层333的厚度可以为15微米至25微米，比如21微米；第二绝缘层52的厚度可以为20微米至30微米，比如25微米；第三电磁干扰屏蔽层63的厚度可以为10微米至20微米，比如16微米；第一粘接层41的厚度可以为30微米至50微米，比如40微米；第二粘接层42的厚度可以为30微米至50微米，比如40微米。
本公开实施例的电路板可以适用于多种显示模组(比如OLED显示模组、LCD显示模组等)。电路板可以包括显示电路，还可以包括触控电路，显示电路和触控电路可以设置在不同的线路层。电路板通过绑定部23与显示模组的显示面板绑定连接，电路板的可弯折部22可以弯折至显示面板的背面并固定在显示面板的背面。
本公开实施例还提供一种电子设备，包括任一实施例所述的电路板。电子设备可以为显示装置，比如手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等具有显示功能的产品或部件。在一些示例中，电子设备可以为触控显示装置。
在附图中，有时为了明确起见，夸大表示了构成要素的大小、层的厚度或区域。因此，本公开的实施方式并不一定限定于该尺寸，附图中每个部件的形状和大小不反映真实比例。此外，附图示意性地示出了一些例子，本公开的实施方式不局限于附图所示的形状或数值。
在本文描述中，术语“上”、“下”、“左”、“右”、“顶”、“内”、“外”、“轴向”、“四角”等指示的方位或位置关系为基于附图所示的方 位或位置关系，仅是为了便于描述本公开实施例的简化描述，而不是指示或暗示所指的结构具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本文描述中，除非另有明确的规定和限定，术语“连接”、“固定连接”、“安装”、“装配”应做广义理解，例如，可以是固定连接，或是可拆卸连接，或一体地连接；术语“安装”、“连接”、“固定连接”可以是直接相连，或通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据情况理解上述术语在本公开实施例中的含义。

Claims (13)

  1. 一种电路板，包括第一线路板，所述第一线路板包括第一基板和设于所述第一基板的第一侧面上的第一线路层，所述第一线路层包括第一接地线路；
    所述电路板还包括依次叠设于所述第一线路层的远离所述第一基板的一侧的第一保护层和第一电磁干扰屏蔽层；
    所述第一保护层设有第一开口，所述第一开口将所述第一接地线路的至少一部分暴露出，所述第一开口内填充有第一导电材料，所述第一导电材料的表面与所述第一保护层的远离所述第一基板的表面的高度差为0微米至2微米，所述第一导电材料将所述第一电磁干扰屏蔽层和所述第一接地线路连接。
  2. 如权利要求1所述的电路板，其中：所述第一线路板还包括设于所述第一基板的第二侧面上的第二线路层，所述第二线路层包括第二接地线路；
    所述电路板还包括依次叠设于所述第二线路层的远离所述第一基板的一侧的第一绝缘层、第二电磁干扰屏蔽层和导电层；
    所述第一绝缘层和所述第二电磁干扰屏蔽层设有第二开口，所述第二开口将所述第二接地线路的至少一部分暴露出，所述第二开口内填充有第二导电材料，所述第二导电材料的表面与所述第二电磁干扰屏蔽层的远离所述第一基板的表面的高度差为0微米至2微米，所述第二导电材料将所述导电层和所述第二接地线路连接。
  3. 如权利要求2所述的电路板，其中：所述第二导电材料为金属材料；或/和，所述导电层的材料为导电胶。
  4. 如权利要求1所述的电路板，其中：所述第一导电材料为金属材料。
  5. 如权利要求1所述的电路板，其中：所述第一保护层包括第一覆盖层和第一粘胶层，所述第一粘胶层位于所述第一覆盖层和所述第一线路层之间。
  6. 如权利要求2所述的电路板，包括主体部和位于所述主体部的第一侧的可弯折部，所述主体部包括叠设的多个线路板，每个所述线路板包括基板和设于所述基板上的至少一个线路层，所述多个线路板包括所述第一线路板， 所述第一线路板延伸至所述可弯折部；
    所述第一保护层、所述第一电磁干扰屏蔽层和所述第一开口均位于所述可弯折部。
  7. 如权利要求6所述的电路板，其中：所述主体部和所述可弯折部均包括所述第一绝缘层、所述第二电磁干扰屏蔽层和所述导电层，所述第二开口位于所述主体部。
  8. 如权利要求6所述的电路板，还包括位于所述主体部的与第一侧相对的第二侧的绑定部；
    所述多个线路板包括第二线路板，所述第二线路板的第二基板和至少一个线路层延伸至所述绑定部，所述第二线路板的延伸至所述绑定部的线路层设有裸露的绑定引脚，所述绑定引脚配置为与外部电路绑定连接。
  9. 如权利要求8所述的电路板，其中：所述绑定部包括依次叠设于所述第二基板的第一侧面上的第三线路层和第二保护层，所述第三线路层的远离所述主体部的一端设有所述绑定引脚，所述第二保护层将所述绑定引脚暴露出；所述绑定部还包括设于所述第二基板的第二侧面上的第三保护层。
  10. 如权利要求9所述的电路板，其中：所述第二保护层包括第二覆盖层和第二粘胶层，所述第二粘胶层位于所述第二覆盖层和所述第三线路层之间；或/和，所述第三保护层包括第三覆盖层和第三粘胶层，所述第三粘胶层位于所述第三覆盖层和所述第二基板之间。
  11. 如权利要求8所述的电路板，其中：所述多个线路板还包括第三线路板，所述第一线路板、所述第二线路板和所述第三线路板依次层叠设置，相邻的两个线路板之间通过粘接层粘接，所述第一基板的第一侧面朝向所述第二线路板设置。
  12. 如权利要求11所述的电路板，其中：所述主体部内所述第二线路板包括分别设于所述第二基板的两个侧面上的第三线路层和第四线路层，所述第三线路板包括第三基板，以及分别设于所述第三基板的两个侧面上的第五线路层和第六线路层；
    所述主体部还包括依次叠设于所述第三线路板的远离所述第二线路板一 侧的第二绝缘层和第三电磁干扰屏蔽层，所述第三电磁干扰屏蔽层和所述第一电磁干扰屏蔽层一体连接。
  13. 一种电子设备，包括权利要求1至12任一项所述的电路板。
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CN112822834A (zh) * 2021-02-25 2021-05-18 京东方科技集团股份有限公司 一种电路板及电子设备
CN114710879B (zh) * 2022-03-29 2024-01-30 电子科技大学 一种柔性电路板及其制作方法、显示屏和电子设备
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN207995488U (zh) * 2018-01-09 2018-10-19 昆山龙腾光电有限公司 电路板、显示面板及显示装置
CN109496063A (zh) * 2018-12-27 2019-03-19 武汉天马微电子有限公司 电磁屏蔽膜及其制造方法、柔性电路板及其制造方法
CN111465175A (zh) * 2020-04-23 2020-07-28 京东方科技集团股份有限公司 电路板及其制备方法、电子设备
US20200367393A1 (en) * 2018-01-30 2020-11-19 Samsung Electronics Co., Ltd. Electromagnetic wave shielding structure and manufacturing method therefor
CN112822834A (zh) * 2021-02-25 2021-05-18 京东方科技集团股份有限公司 一种电路板及电子设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN207995488U (zh) * 2018-01-09 2018-10-19 昆山龙腾光电有限公司 电路板、显示面板及显示装置
US20200367393A1 (en) * 2018-01-30 2020-11-19 Samsung Electronics Co., Ltd. Electromagnetic wave shielding structure and manufacturing method therefor
CN109496063A (zh) * 2018-12-27 2019-03-19 武汉天马微电子有限公司 电磁屏蔽膜及其制造方法、柔性电路板及其制造方法
CN111465175A (zh) * 2020-04-23 2020-07-28 京东方科技集团股份有限公司 电路板及其制备方法、电子设备
CN112822834A (zh) * 2021-02-25 2021-05-18 京东方科技集团股份有限公司 一种电路板及电子设备

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