WO2022164240A1 - Capacitor, manufacturing method therefor, and capacitor electrode - Google Patents

Capacitor, manufacturing method therefor, and capacitor electrode Download PDF

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Publication number
WO2022164240A1
WO2022164240A1 PCT/KR2022/001525 KR2022001525W WO2022164240A1 WO 2022164240 A1 WO2022164240 A1 WO 2022164240A1 KR 2022001525 W KR2022001525 W KR 2022001525W WO 2022164240 A1 WO2022164240 A1 WO 2022164240A1
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Prior art keywords
electrode
dielectric
capacitor
lattice
cross
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PCT/KR2022/001525
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French (fr)
Korean (ko)
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안범모
박승호
변성현
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(주)포인트엔지니어링
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Publication of WO2022164240A1 publication Critical patent/WO2022164240A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G13/00—Apparatus specially adapted for manufacturing capacitors; Processes specially adapted for manufacturing capacitors not provided for in groups H01G4/00 - H01G11/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics

Definitions

  • the present invention relates to a capacitor, a method for manufacturing the same, and an electrode for a capacitor.
  • a multi-layered ceramic capacitor which is one of multilayer chip electronic components, is used in various electronic devices due to its small size, high capacity, and easy mounting.
  • the multilayer ceramic capacitor has a structure in which a plurality of dielectric layers and internal electrodes of different polarities are alternately disposed between the dielectric layers.
  • multilayer ceramic capacitors are also trending to be miniaturized, and for miniaturization, a high-capacity multilayer ceramic capacitor is implemented by thinning a dielectric layer and increasing the number of stacked internal electrodes.
  • the multilayer ceramic capacitor includes a plurality of dielectric layers and first and second internal electrodes formed on the dielectric layers, the plurality of dielectric layers having internal electrodes formed thereon are stacked so that the first and second internal electrodes face each other with one dielectric layer interposed therebetween. are placed
  • Patent Document 1 Korean Patent Publication No. 10-2192426
  • Patent Document 2 Korean Patent Publication No. 10-2189805
  • the present invention has been devised to solve the problems of the prior art, and the present invention is to provide a capacitor in which at least one electrode of the capacitor is formed in a three-dimensional grid shape to increase capacitance, a manufacturing method thereof, and an electrode for a capacitor The purpose.
  • a capacitor according to the present invention includes a grid-type first electrode; a dielectric formed on the surface of the first electrode; and a second electrode formed on the surface of the dielectric.
  • the lattice-type first electrode may include: an intersecting electrode unit including a 1-1 electrode and a 1-2 electrode intersecting the 1-1 electrode; and a side common electrode part provided outside the cross electrode part.
  • the side common electrode part may include: a 1-1 common electrode part connected to a plurality of the 1-1 electrodes; and a first-second common electrode unit connected to the plurality of first-second electrodes.
  • a through portion formed between the adjacent first-first electrodes and the adjacent first-second electrodes is included.
  • the lattice-type first electrode may include: an intersecting electrode unit including a 1-1 electrode and a 1-2 electrode intersecting the 1-1 electrode; and a lower common electrode part provided on a lower surface of the cross electrode part.
  • the dielectric is also formed on the surface of the lower common electrode part.
  • the method of manufacturing a capacitor according to the present invention comprises the steps of forming a lattice-type first electrode by filling the openings with a metal in a substrate having a plurality of openings crossing each other; removing at least a portion of the substrate to expose a surface of the lattice-type first electrode; forming a dielectric on the exposed surface of the lattice-type first electrode; and forming a second electrode on the dielectric.
  • the substrate is an anodized film substrate composed of an anodized film material.
  • the capacitor according to the present invention comprises: a first electrode including a cross electrode part provided while a plurality of 1-1 electrodes and a plurality of 1-2 electrodes cross each other to form a lattice room; a dielectric formed on a surface of the cross electrode part; and a second electrode formed on the dielectric.
  • the first electrode includes a concave-convex portion formed on the side of the grid.
  • the dielectric is formed while entirely surrounding the surface of the cross electrode, and the second electrode is formed while completely enclosing the surface of the dielectric formed on the surface of the cross electrode.
  • the capacitor according to the present invention a grid-type first electrode; and a unit capacitor including a dielectric formed on a surface of the first electrode and a second electrode formed on the surface of the dielectric, wherein the unit capacitors are connected in series with each other.
  • the capacitor according to the present invention a grid-type first electrode; and a unit capacitor including a dielectric formed on a surface of the first electrode and a second electrode formed on the surface of the dielectric, wherein the unit capacitors are connected in parallel to each other.
  • the capacitor according to the present invention a grid-type first electrode; and a unit capacitor including a dielectric formed on a surface of the first electrode and a second electrode formed on the surface of the dielectric, wherein the unit capacitors are connected in series and parallel to each other.
  • the electrode for a capacitor according to the present invention a plurality of 1-1 electrodes and a plurality of 1-2 electrodes cross each other to form a lattice room, the intersecting electrode portion provided; and a side common electrode part provided outside the cross electrode part.
  • the electrode for a capacitor according to the present invention a plurality of 1-1 electrodes and a plurality of 1-2 electrodes cross each other to form a lattice room, the intersecting electrode portion provided; and a lower common electrode part provided on a lower surface of the cross electrode part.
  • the present invention provides a capacitor in which capacitance is increased by forming at least one electrode of the capacitor in a three-dimensional lattice shape, a method for manufacturing the same, and an electrode for the capacitor.
  • FIG. 1 is a perspective view of a capacitor according to a first preferred embodiment of the present invention
  • Fig. 2 is a cross-sectional view taken along line A-A' of Fig. 1;
  • FIG. 3 is a view showing an anodized film for the first preferred embodiment of the present invention.
  • FIGS. 4 to 13 are views illustrating a method of manufacturing a capacitor according to a first preferred embodiment of the present invention.
  • FIG. 14 is a view showing a unit capacitor according to a first preferred embodiment of the present invention.
  • 15 is a diagram illustrating an electrically parallel connection of unit capacitors according to a first exemplary embodiment of the present invention.
  • 16 is a diagram illustrating an electrically connected unit capacitor in series according to the first preferred embodiment of the present invention.
  • FIG. 17 is a view showing a capacitor according to a second preferred embodiment of the present invention.
  • 18 to 23 are views illustrating a method of manufacturing a capacitor according to a second preferred embodiment of the present invention.
  • 24 is a view showing a modified example of the second preferred embodiment of the present invention.
  • Embodiments described herein will be described with reference to cross-sectional and/or perspective views, which are ideal illustrative drawings of the present invention.
  • the thicknesses of films and regions shown in these drawings are exaggerated for effective description of technical content.
  • the shape of the illustrative drawing may be modified due to manufacturing technology and/or tolerance.
  • the number of moldings shown in the drawings is only partially shown in the drawings by way of example. Accordingly, embodiments of the present invention are not limited to the specific form shown, but also include changes in the form generated according to the manufacturing process.
  • a capacitor according to a preferred embodiment of the present invention includes a unit capacitor. Also, the capacitor according to the preferred embodiment of the present invention includes a multilayer capacitor. Also, the capacitor according to the preferred embodiment of the present invention may include a form in which a plurality of unit capacitors are combined.
  • the capacitor 100 includes a lattice-type first electrode 200 , a dielectric 300 formed on the surface of the lattice-type first electrode 200 , and a second electrode formed on the surface of the dielectric 300 . It includes two electrodes 400 .
  • metal 12 is filled in the openings 11 to form a lattice-type first electrode 200 in a substrate 10 having a plurality of openings 11 intersecting each other.
  • At least one electrode has a three-dimensional grid shape.
  • the grid-type electrode includes a structure in which a plurality of detailed electrodes having a predetermined height cross each other to form a grid room, thereby extending the surface area of the electrode three-dimensionally. Since the dielectric 300 and another electrode are sequentially formed on the surface of the grid electrode, the capacitance of the capacitor 100 can be improved.
  • Fig. 1 is a perspective view of a capacitor according to a first preferred embodiment of the present invention
  • Fig. 2 is a sectional view taken along line A-A' of Fig. 1
  • Fig. 3 is a view showing an anodized film for a first preferred embodiment of the present invention.
  • 4 to 13 are views illustrating a method of manufacturing a capacitor according to a first preferred embodiment of the present invention
  • FIG. 14 is a view showing a unit capacitor according to a first preferred embodiment of the present invention
  • FIG. 15 is a diagram illustrating an electrically parallel connection of unit capacitors according to a first preferred embodiment of the present invention
  • FIG. 16 is a diagram illustrating an electrically series connection of unit capacitors according to a first preferred embodiment of the present invention. It is a drawing.
  • the capacitor according to the first preferred embodiment of the present invention includes a grid-type first electrode 200; a dielectric 300 formed on the surface of the first electrode 200; and a second electrode 400 formed on the surface of the dielectric 300 .
  • the grid-type first electrode 200 includes a cross electrode part 210 and a side common electrode part 220 .
  • the cross electrode part 210 is provided while a plurality of first-first electrodes 211 and a plurality of first-second electrodes 213 cross each other to form a lattice room 240 .
  • the lattice-type first electrode 200 is formed of a conductive metal, and may be silver (Ag), nickel (Ni), copper (Cu), tin (Sn), indium oxide (ITO), palladium (Pd), or an alloy thereof. and the present invention is not limited thereto.
  • the 1-1 electrode 211 and the 1-2 electrode 213 are formed as planar electrodes having a predetermined height.
  • the 1-1 electrode 211 and the 1-2 electrode 213 are formed to have a height of several tens of ⁇ m, and preferably have a height of 1 ⁇ m or more and 300 ⁇ m or less.
  • the 1-1 electrode 211 and the 1-2 electrode 213 cross each other to form a lattice room 240 between the 1-1 electrode 211 and the 1-2 electrode 213 adjacent to each other. do.
  • the 1-1 electrode 211 and the 1-2 electrode 213 may cross each other in a '+' shape, and in this case, the lattice room 240 may be formed in a rectangular shape.
  • the angle at which the first-first electrode 211 and the first-second electrode 213 intersect each other is not limited to 90°, and the lattice room 240 is not limited to a rectangular shape.
  • the side common electrode part 220 is provided outside the cross electrode part 210 .
  • the side common electrode part 220 is formed to have substantially the same height as that of the cross electrode part 210 . Therefore, the side common electrode part 220 is formed to have a height of several tens of ⁇ m, and preferably has a height of 1 ⁇ m or more and 300 ⁇ m or less.
  • the side common electrode part 220 includes a 1-1 common electrode part 221 and a 1-2 common electrode part 223 .
  • the 1-1 common electrode part 221 is connected to the plurality of 1-1 electrodes 211
  • the 1-2 common electrode part 223 is connected to the plurality of 1-2 electrodes 213 .
  • a cross electrode part 210 in which a 1-1 electrode 211 and a 1-2 electrode 213 cross in a cross shape ('+' shape) is provided inside. and a side common electrode part 220 of a closed shape (' ⁇ ' shape) is formed on the outside of the cross electrode part 210 .
  • the cross electrode part 210 and the side common electrode part 220 are integrally formed with each other to become the first lattice electrode 200 of the capacitor 100 .
  • the dielectric 300 is formed on the surface of the lattice-type first electrode 200 .
  • the dielectric 300 is entirely formed on the exposed surface of the lattice-type first electrode 200 .
  • the dielectric 300 is formed while entirely surrounding the surface of the cross electrode part 210 .
  • the dielectric 300 is also formed on the surface of the side common electrode part 220 , and is preferably formed entirely on the surface except for the outer surface of the side common electrode part 220 .
  • Dielectric 300 is tantalum oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), ziconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), barium titanate (BaTiO 3 ) )-based or strontium titanate (SrTiO 3 )-based powder or at least one of a composite dielectric thereof, and preferably a material capable of exhibiting sufficient capacitance.
  • the dielectric 300 may be formed through a deposition process (CVD, PVD, or ALD).
  • the second electrode 400 is formed on the surface of the dielectric 300 .
  • the second electrode 400 is formed on the surface of the dielectric 300 in the region where the dielectric 300 is formed.
  • the second electrode 400 is formed while completely surrounding the surface of the dielectric 300 formed on the cross electrode part 210 . It is also formed on the surface of the dielectric 300 formed on the surface of the side common electrode part 220 , and is preferably formed entirely on the surface except for the outer surface of the side common electrode part 220 .
  • the second electrode 400 is formed of a conductive metal, and may be silver (Ag), nickel (Ni), copper (Cu), tin (Sn), indium oxide (ITO), palladium (Pd), or an alloy thereof. The present invention is not limited thereto.
  • the second electrode 400 may be formed of the same material as the lattice-type first electrode 200 .
  • the lattice-type first electrode 200 is configured such that its surface is exposed from the upper surface, the side surfaces and the lower surface of the lattice room 240 , and the dielectric 300 is formed on the exposed surface of the grid-type first electrode 200 , The dielectric 300 is also formed by exposing the surface on the upper surface, the side surface and the lower surface of the lattice room 240 .
  • the second electrode 400 is formed on the exposed surface of the dielectric 300
  • the second electrode 400 is also formed by exposing its surface on the upper surface, the side surface and the lower surface of the lattice chamber 240 .
  • the capacitor 100 includes a lattice-type first electrode 200 with a three-dimensionally extended surface area of the electrode, and a lattice-type first electrode 200 having a three-dimensionally extended surface.
  • the capacitor 100 includes a through portion 250 formed between adjacent first-first electrodes 211 and adjacent first-second electrodes 213 . .
  • a lattice room 240 is formed between the adjacent 1-1 electrodes 211 and the adjacent 1-2 electrodes 213 , and the lattice room 240 is opened up and down to form a through part 250 . is formed As the lattice room 240 is formed in the configuration of the through part 250 , heat dissipation according to an increase in the temperature of the capacitor 300 may be more effectively achieved. In addition, cooling of the capacitor 300 may be more effectively achieved by using a cooling fluid (gas, liquid) passing through the through portion 250 .
  • a cooling fluid gas, liquid
  • the anodization film 10 refers to a film formed by anodizing a metal, which is a base material, and the pores mean a hole formed in the process of forming an anodization film by anodizing the metal.
  • the base metal is aluminum (Al) or an aluminum alloy
  • an anodization film made of aluminum oxide (Al 2 0 3 ) material is formed on the surface of the base material.
  • the anodized film formed as above is vertically divided into a barrier layer 12 in which pores P are not formed and a porous layer 11 in which pores P are formed.
  • the anodized film 10 may be formed in a structure in which the barrier layer 12 formed during anodization remains as it is and seals one end of the upper and lower ends of the pores P.
  • the pores P have a diameter of 1 nm or more and 100 nm or less.
  • the anodized film has a coefficient of thermal expansion of 2-3 ppm/°C. For this reason, when exposed to a high temperature environment, thermal deformation due to temperature is small. Therefore, even if the manufacturing environment of the capacitor is a high temperature environment, it is possible to manufacture a precise capacitor without thermal deformation, and it is possible to provide a capacitor with high durability even if the usage environment is a high temperature environment.
  • Such an anodized film 10 is used as a substrate in manufacturing the capacitor 100 according to the first preferred embodiment of the present invention.
  • a method of manufacturing the capacitor 100 according to the first preferred embodiment of the present invention using the anodized film 10 will be described.
  • FIG. 4 is a view showing an anodization film 10 having a seed layer 20 on its lower surface.
  • FIG. 4A is a plan view and
  • FIG. 4B is a cross-sectional view taken along line A-A' of FIG.
  • an anodization film 10 is prepared first, and a seed layer 20 is provided on a lower surface of the anodization film 10 .
  • the seed layer 20 may be made of copper (Cu).
  • the anodization film 10 is prepared by removing the base material after forming by anodizing the base metal.
  • the seed layer 20 may be formed through a deposition process (CVD, PVD, or ALD).
  • FIG. 5 is a view showing the formation of the opening 15 in the anodized film 10.
  • FIG. 5A is a plan view and
  • FIG. 5B is a cross-sectional view taken along line A-A' of FIG. 5A.
  • an opening 15 is formed in the anodized film 10 .
  • the opening 15 may be formed by etching the anodization layer 10 .
  • a photoresist is provided on the upper surface of the anodization film 10, more preferably the upper surface of the barrier layer 12, and patterned. (15) is formed.
  • an exposure and development process may be performed after the photosensitive material is provided on the upper surface of the anodized film 10 before the opening 15 is formed. At least a portion of the photosensitive material may be patterned and removed while forming an open area by an exposure and development process.
  • the anodic oxide layer 10 is etched through the open region from which the photosensitive material has been removed by the patterning process, and a part thereof is removed to form the opening 15 .
  • An opening 15 having a vertical inner wall is provided by wet etching the anodization film 10 with an etching solution.
  • the reason for forming the photoresist on the upper surface of the barrier layer 12 is that when the photoresist 20 is formed on the upper surface of the porous layer 11, it is not easy to remove the photoresist 20 after the patterning process. , This is to prevent the photoresist 20 residues that are not completely removed when the photoresist 20 is removed from remaining inside the pores P of the porous layer 11 and later released.
  • a trench 19 is provided in the side wall of the opening 15 .
  • the trench 19 may be a pore-type trench 19a formed while the pores P formed during the production of the anodization film are opened during the etching process.
  • the width and depth of the pore-type trench 19a have a range of 10 nm or more and 1 ⁇ m or less.
  • the trench 19 may include an etching-type trench 19b formed during the etching process of the anodization layer 10 separately from the pore-type trench 19a.
  • the anodic oxide layer 10 reacts with the etching solution in the open region of the photoresist and is etched in a vertical direction along the shape of the open pattern of the photoresist to form the opening 15 .
  • the side wall of the opening 15 of the anodization film is also formed with a concave-convex pattern in the horizontal section when the anodization film is etched by the concave-convex pattern boundary of the photoresist. and the concave-convex portion on the side wall of the opening 15 becomes the etched trench 19b.
  • a plurality of pore-type trenches 19a are formed on the wall surface of the etching-type trenches 19b. Since the pore-shaped trench 19a is formed along the wall surface of the etched trench 19b, the trench 19 includes the pore-shaped trench 19a and the etched trench 19b from a macroscopic point of view.
  • the width and depth of the etching-type trench 19b are formed to be larger than the width and depth of the fore-type trench 19a.
  • the width and depth of the etched trench 19b are in the range of 100 nm or more and 30 ⁇ m or less.
  • the trench 19 corresponds to the pore-type trench 19a formed while the pores P formed during the production of the anodization film are opened during the etching process and the concave-convex pattern interface of the photoresist. and an etched trench 19b to be formed.
  • FIG. 6 and 7 are views illustrating that the conductive metal 16 is filled in the opening 15 of the anodization film 10.
  • FIG. 6A is a plan view
  • FIG. 6B is a cross-sectional view taken along line A-A' of FIG. 6A.
  • 7 is a perspective view of FIG. 6 ;
  • the conductive metal 16 is filled in the opening 15 .
  • the conductive metal 16 filled in the opening 15 may be formed by a plating method.
  • the conductive metal 16 may be filled in the opening 15 by electrolytic plating using the seed layer 20 provided on the lower surface of the anodized layer 10 .
  • a planarization process is performed.
  • the conductive metal 16 protruding from the top surface of the anodic oxide layer 10 is removed and planarized through a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the conductive metal 16 filled in the opening 15 may be silver (Ag), nickel (Ni), copper (Cu), tin (Sn), indium oxide (ITO), palladium (Pd), or an alloy thereof.
  • the present invention is not limited thereto.
  • the conductive metal 16 filled in the opening 15 becomes the lattice type first electrode 200 .
  • the grid-type first electrode 200 includes a cross electrode part 210 and a side common electrode part 220 .
  • the cross electrode part 210 is provided while a plurality of first-first electrodes 211 and a plurality of first-second electrodes 213 cross each other to form a lattice room 240 .
  • the trench 19 includes a pore-type trench 19a and an etched trench 19b
  • the first electrode 200 includes a pore-type trench 19a and an etched trench 19b.
  • the conductive metal 16 is formed on the surface of the trench 19 on the side of the lattice chamber 240 of the first electrode 200 to form an uneven portion.
  • the conductive metal 16 is formed on the surface of the pore-type trench 19a to form the pore-type uneven portions
  • the conductive metal 16 is formed on the surface of the etch-type trench 19b to form the etching-type uneven portions.
  • the surface area of the first electrode 200 becomes larger.
  • the seed layer 20 provided under the anodization layer 10 is removed.
  • the seed layer 20 may be removed using a copper (Cu) etchant.
  • FIG. 8 and 9 are views illustrating the removal of the anodization film 10 present on the inside of the side common electrode part 220.
  • FIG. 8A is a plan view
  • FIG. 8B is a cross-sectional view taken along line A-A' of FIG. 8A
  • FIG. 9 is a perspective view of FIG. 8 .
  • the anodic oxide layer 10 present inside the side common electrode part 220 of the lattice-type first electrode 200 is removed.
  • a photoresist is provided on the upper surface of the anodized film 10 filled with the conductive metal 16 and patterned, and then the anodized film 10 in the patterned and open area reacts with the etching solution to react with the side common electrode part ( The anodization film 10 inside the 220 is removed. As a result, the surface of the grid-type first electrode 200 is exposed to the outside.
  • FIG. 10 and 11 are views illustrating the formation of a dielectric 300 on the surface of the exposed grid-type first electrode 200
  • FIG. 10A is a plan view
  • FIG. 10B is a cross-sectional view taken along line A-A' of FIG. 10A
  • FIG. 10 is a perspective view.
  • the dielectric 300 is formed on the exposed surface of the lattice-type first electrode 200 .
  • the dielectric 300 is tantalum oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ). ), titanium oxide (TiO 2 ), ziconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), barium titanate (BaTiO 3 ) based or strontium titanate (SrTiO 3 ) based powder or at least one of a composite dielectric thereof and a material capable of exhibiting sufficient capacitance is preferable.
  • the dielectric 300 may be formed through a deposition process (CVD, PVD, or ALD).
  • FIG. 12 and 13 are views illustrating that a conductive metal 17 is formed on the surface of the dielectric 300.
  • FIG. 12A is a plan view
  • FIG. 12B is a cross-sectional view taken along line A-A' of FIG. 12A
  • FIG. is a perspective view.
  • a conductive metal 17 is formed on the surface of the dielectric 300 .
  • the second electrode 400 is formed on the conductive metal 17 .
  • the conductive metal 17 is formed while completely surrounding the surface of the dielectric 300 formed on the cross electrode part 210 .
  • the conductive metal 17 is also formed on the surface of the dielectric 300 formed on the surface of the side common electrode part 220 .
  • the capacitor 100 according to the first preferred embodiment of the present invention has a structure in which the anodization film 10 is provided on the outside of the side common electrode part 220 . includes In this case, the anodization layer 10 provided on the outside of the side common electrode part 220 may insulate the outer surface of the side common electrode part 220 . Meanwhile, after removing the second electrode 400 and the dielectric 300 from at least a portion of the upper and lower surfaces for wiring connection, the lattice-shaped first electrode 200 may be exposed to connect with the wiring.
  • FIG. 14 is a view illustrating that the outer surface of the side common electrode part 220 is exposed by removing the anodization film 10 on the outer surface of the side common electrode part 220 .
  • One external electrode is connected to the outer surface of the exposed side common electrode part 220 , and another external electrode is formed on the second electrode 400 to form a capacitor.
  • the lattice-type first electrode 200 and the second electrode 400 are provided to face each other with the dielectric 300 interposed therebetween. Since the first electrode 200 is a three-dimensional electrode configured in a grid shape and the second electrode 400 is formed along the surface of the first electrode 200, the second electrode 400 also becomes a three-dimensional electrode configured in a grid shape. . When a voltage is applied through an external electrode to the two first and second electrodes 200 and 400 formed in such a grid shape, charges are accumulated between the first electrode 211 and the second electrode 231 facing each other, In this case, the capacitance of the unit capacitor is proportional to the area of the overlapping regions of the first electrode 200 and the second electrode 400 . Here, since the first electrode 200 and the second electrode 400 are three-dimensional electrodes configured in a grid shape, the capacitance of the unit capacitor can be greatly improved.
  • the unit capacitors may be electrically connected to each other in series, in parallel, or in series and parallel.
  • FIG. 15 shows a grid-type first electrode 200 , a dielectric 300 formed on the surface of the first electrode 200 , and a second electrode 400 formed on the surface of the dielectric 300 . It is a diagram showing a structure in which the included unit capacitors are connected to each other in parallel.
  • FIG. 16 shows a grid-type first electrode 200 , a dielectric 300 formed on the surface of the first electrode 200 , and a second electrode 400 formed on the surface of the dielectric 300 . It is a diagram showing a structure in which the included unit capacitors are connected in series to each other.
  • the withstand voltage characteristic of the capacitor 100 may be improved. Also, according to a structure in which a plurality of unit capacitors are connected in parallel to each other, the capacitance of the capacitor 100 may be further increased.
  • the capacitor 100 and a manufacturing method thereof according to a second preferred embodiment of the present invention will be described.
  • the embodiments to be described below will be mainly described with respect to the characteristic components compared to the first embodiment, and descriptions of the same or similar components as those of the first embodiment will be omitted.
  • FIG. 17 is a view showing a capacitor according to a second preferred embodiment of the present invention
  • FIGS. 18 to 23 are views showing a method of manufacturing a capacitor according to a second preferred embodiment of the present invention.
  • FIG. 17A is a perspective view of the capacitor 100 according to the second embodiment
  • FIG. 17B is a cross-sectional view taken along line A-A' of FIG. 17A.
  • the capacitor 100 according to the second preferred embodiment of the present invention includes a grid-type first electrode 200 , a dielectric 300 formed on the surface of the first electrode 200 , and a dielectric 300 formed on the surface of the dielectric 300 .
  • a second electrode 400 is included.
  • the capacitor 100 according to the second embodiment is different from the capacitor 100 according to the first embodiment in that the lower surface of the lattice room 240 is used as an electrode.
  • the grid-type first electrode 200 includes a cross electrode part 210 and a lower common electrode part 230 .
  • the cross electrode part 210 is provided while a plurality of first-first electrodes 211 and a plurality of first-second electrodes 213 cross each other to form a lattice room 240 .
  • the lower common electrode part 230 is provided on the lower surface of the cross electrode part 210 .
  • the lattice room 240 formed between the adjacent first-first electrodes 211 and the adjacent first-second electrodes 213 has a structure in which the lower part is blocked by the lower common electrode part 230 . becomes
  • the cross electrode part 210 and the lower common electrode part 230 are formed of a conductive metal, and include silver (Ag), nickel (Ni), copper (Cu), tin (Sn), indium oxide (ITO), and palladium (Pd). ) or an alloy thereof, and the present invention is not limited thereto.
  • the dielectric 300 is formed while entirely surrounding the surface of the cross electrode part 210 . In addition, the dielectric 300 is also formed on the upper surface of the lower common electrode part 220 .
  • the second electrode 400 is formed on the surface of the dielectric 300 in the region where the dielectric 300 is formed.
  • FIG. 18 is a view showing an anodized film 10 having a seed layer 20 thereon.
  • FIG. 18A is a plan view and
  • FIG. 18B is a cross-sectional view taken along line A-A' of FIG. 18A.
  • an anodization film 10 is prepared first, and a seed layer 20 is provided on a lower surface of the anodization film 10 .
  • the seed layer 20 may be made of copper (Cu).
  • the seed layer 20 may constitute the lower common electrode part 230 .
  • the present invention is not limited thereto, and after the seed layer 20 is removed after electroplating, which will be described later, a metal layer may be deposited on the region where the seed layer 20 was, so that the metal layer may constitute the lower common electrode unit 230 . .
  • FIG. 19 is a view showing the anodized film 10 having an opening 15 formed therein.
  • FIG. 19A is a plan view and
  • FIG. 19B is a cross-sectional view taken along line A-A' of FIG. 19A.
  • an opening 15 is formed in the anodization layer 10 .
  • the opening 15 may be formed by etching the anodization layer 10 .
  • a photoresist is provided on the upper surface of the anodization film 10 and patterned, and then the anodization film 10 in the patterned and open area reacts with the etching solution to form the opening 15 .
  • an exposure and development process may be performed after the photosensitive material is provided on the upper surface of the anodized film 10 before the opening 15 is formed. At least a portion of the photosensitive material may be patterned and removed while forming an open area by an exposure and development process.
  • the anodic oxide layer 10 is etched through the open region from which the photosensitive material has been removed by the patterning process, and a part thereof is removed to form the opening 15 .
  • An opening 15 having a vertical inner wall is provided by wet etching the anodization film 10 with an etching solution.
  • FIG. 20 is a view illustrating that the conductive metal 16 is filled in the opening 15 of the anodized film 10.
  • FIG. 20A is a plan view
  • FIG. 20B is a cross-sectional view taken along line A-A' of FIG. 20A.
  • the conductive metal 16 is filled in the opening 15 .
  • the conductive metal 16 filled in the opening 15 may be formed by a plating method.
  • the conductive metal 16 may be filled in the opening 15 by electrolytic plating using the seed layer 20 provided on the lower surface of the anodized layer 10 .
  • a planarization process is performed.
  • the conductive metal 16 protruding from the top surface of the anodic oxide layer 10 is removed and planarized through a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the conductive metal 16 filled in the opening 15 may be silver (Ag), nickel (Ni), copper (Cu), tin (Sn), indium oxide (ITO), palladium (Pd), or an alloy thereof.
  • the present invention is not limited thereto.
  • the conductive metal 16 filled in the opening 15 becomes the lattice type first electrode 200 .
  • the grid-type first electrode 200 includes a cross electrode part 210 and a side common electrode part 220 .
  • the cross electrode part 210 is provided while a plurality of first-first electrodes 211 and a plurality of first-second electrodes 213 cross each other to form a lattice room 240 .
  • the lattice room 240 has an open upper portion and a closed lower portion.
  • FIG. 21 is a view illustrating the removal of the anodization film 10 present inside the side common electrode part 220 of the lattice-type first electrode 200.
  • FIG. 21A is a plan view
  • FIG. 21B is a view A- of FIG. 21A.
  • A' is a cross-sectional view.
  • the anodic oxide layer 10 present inside the side common electrode part 220 of the lattice-type first electrode 200 is removed.
  • a photoresist is provided on the upper surface of the anodized film 10 filled with the conductive metal 16 and patterned, and then the anodized film 10 in the patterned and open area reacts with the etching solution to react with the side common electrode part ( The anodization film 10 inside the 220 is removed. As a result, the surface of the grid-type first electrode 200 is exposed to the outside.
  • FIG. 22 is a view illustrating the formation of the dielectric 300 on the exposed surface of the lattice-type first electrode 200.
  • FIG. 22A is a plan view and
  • FIG. 22B is a cross-sectional view taken along line A-A' of FIG. 22A.
  • the dielectric 300 is formed on the exposed surface of the lattice-type first electrode 200 .
  • the dielectric 300 is formed on the surfaces of the exposed cross electrode part 210 , the side common electrode part 220 , and the lower common electrode part 230 . It is different from the dielectric 300 formation region of the first embodiment in that the dielectric 300 is also formed on the surface of the lower common electrode part 230 .
  • FIG. 23 is a view showing the formation of a conductive metal 17 on the surface of the dielectric 300.
  • FIG. 23A is a plan view and
  • FIG. 23B is a cross-sectional view taken along line A-A' of FIG. 23A.
  • a conductive metal 17 is formed on the surface of the dielectric 300 .
  • the second electrode 400 is formed on the conductive metal 17 .
  • the conductive metal 17 is entirely formed on the surface of the dielectric 300 formed on the cross electrode portion 210 .
  • the conductive metal 17 is formed on the surface of the dielectric 300 formed on the surface of the side common electrode part 220 and also on the surface of the dielectric 300 formed on the surface of the lower common electrode part 230 . do.
  • the capacitor 100 according to the second preferred embodiment of the present invention has a structure in which the anodization film 10 is provided on the outside of the side common electrode part 220 .
  • the anodization layer 10 provided on the outside of the side common electrode part 220 may insulate the outer surface of the side common electrode part 220 .
  • FIG. 24 is a view showing a modified example of the second preferred embodiment of the present invention.
  • the basic configuration is the same as that of the second embodiment described above, but a modified example of the second embodiment is that the second electrode 400 is formed while filling the entire interior of the grid room 240 .
  • the structure of the second embodiment in which the entire interior of the lattice room 240 is not filled.
  • At least one electrode has a three-dimensional grid shape.
  • the grid-type electrode includes a structure in which a plurality of electrode plates having a predetermined height cross each other to form a grid room, thereby extending the surface area of the electrode three-dimensionally. Since the dielectric 300 and another electrode are sequentially formed on the surface of the grid electrode, the capacitance of the capacitor 100 can be improved.

Abstract

The present invention provides a capacitor having one or more electrodes formed in a three-dimensional grid shape to increase capacitance, a manufacturing method therefor, and a capacitor electrode.

Description

커패시터, 그 제조방법 및 커패시터용 전극Capacitor, manufacturing method thereof, and electrode for capacitor
본 발명은 커패시터, 그 제조방법 및 커패시터용 전극에 관한 것이다.The present invention relates to a capacitor, a method for manufacturing the same, and an electrode for a capacitor.
적층 칩 전자 부품의 하나인 적층 세라믹 커패시터(MLCC: multi-layered ceramic capacitor)는 소형이면서 고용량이 보장되고 실장이 용이하다는 장점으로 인하여 다양한 전자 장치에 사용된다. 적층 세라믹 커패시터는, 복수의 유전체층과 상기 유전체층 사이에 상이한 극성의 내부 전극이 번갈아 배치된 구조를 가진다. 최근 전자기기들이 소형화되는 경향에 따라 적층 세라믹 커패시터도 소형화되는 경향을 따르고 있으며, 이에 소형화를 위해 유전체층을 박막화하고 내부 전극의 적층 수를 높임으로써 고용량의 적층 세라믹 커패시터를 구현하고 있다. A multi-layered ceramic capacitor (MLCC), which is one of multilayer chip electronic components, is used in various electronic devices due to its small size, high capacity, and easy mounting. The multilayer ceramic capacitor has a structure in which a plurality of dielectric layers and internal electrodes of different polarities are alternately disposed between the dielectric layers. Recently, with the trend of miniaturization of electronic devices, multilayer ceramic capacitors are also trending to be miniaturized, and for miniaturization, a high-capacity multilayer ceramic capacitor is implemented by thinning a dielectric layer and increasing the number of stacked internal electrodes.
적층 세라믹 커패시터는 복수의 유전체층과 유전체층 상에 형성된 제1,2내부 전극을 포함하며 내부 전극이 형성된 복수의 유전체층이 적층되어 형성되며 제1,2내부 전극은 하나의 유전체층을 사이에 두고 서로 대향되도록 배치된다. The multilayer ceramic capacitor includes a plurality of dielectric layers and first and second internal electrodes formed on the dielectric layers, the plurality of dielectric layers having internal electrodes formed thereon are stacked so that the first and second internal electrodes face each other with one dielectric layer interposed therebetween. are placed
그러나 이러한 커패시터는 내부 전극이 2차원 평면 형태이기 때문에 정전용량을 키우는데 한계가 있다. However, these capacitors have a limit in increasing the capacitance because the internal electrode has a two-dimensional planar shape.
[선행기술문헌][Prior art literature]
[특허문헌][Patent Literature]
(특허문헌 1) 한국 등록특허공보 등록번호 제10-2192426호(Patent Document 1) Korean Patent Publication No. 10-2192426
(특허문헌 2) 한국 등록특허공보 등록번호 제10-2189805호(Patent Document 2) Korean Patent Publication No. 10-2189805
본 발명은 종래기술의 문제점을 해결하기 위하여 안출된 것으로서, 본 발명은 커패시터의 적어도 하나의 전극을 3차원의 격자 모양으로 형성하여 정전용량을 키운 커패시터, 그 제조방법 및 커패시터용 전극을 제공하는 것을 목적으로 한다. The present invention has been devised to solve the problems of the prior art, and the present invention is to provide a capacitor in which at least one electrode of the capacitor is formed in a three-dimensional grid shape to increase capacitance, a manufacturing method thereof, and an electrode for a capacitor The purpose.
이러한 본 발명의 목적을 달성하기 위해, 본 발명에 따른 커패시터는, 격자형 제1전극; 상기 제1전극의 표면상에 형성된 유전체;및 상기 유전체의 표면상에 형성된 제2전극;을 포함한다.In order to achieve the object of the present invention, a capacitor according to the present invention includes a grid-type first electrode; a dielectric formed on the surface of the first electrode; and a second electrode formed on the surface of the dielectric.
또한, 상기 격자형 제1전극은, 제1-1전극과 상기 제1-1전극과 교차되는 제1-2전극을 포함하는 교차 전극부; 및 상기 교차 전극부의 외측에 구비되는 측부 공통 전극부를 포함한다.In addition, the lattice-type first electrode may include: an intersecting electrode unit including a 1-1 electrode and a 1-2 electrode intersecting the 1-1 electrode; and a side common electrode part provided outside the cross electrode part.
또한, 상기 측부 공통 전극부는, 복수개의 상기 제1-1전극과 연결되는 제1-1공통 전극부; 및 복수개의 상기 제1-2전극과 연결되는 제1-2공통 전극부를 포함한다.In addition, the side common electrode part may include: a 1-1 common electrode part connected to a plurality of the 1-1 electrodes; and a first-second common electrode unit connected to the plurality of first-second electrodes.
또한, 인접하는 제1-1전극들과 인접하는 제1-2전극들 사이에 형성되는 관통부를 포함한다.In addition, a through portion formed between the adjacent first-first electrodes and the adjacent first-second electrodes is included.
또한, 상기 격자형 제1전극은, 제1-1전극과 상기 제1-1전극과 교차되는 제1-2전극을 포함하는 교차 전극부; 및 상기 교차 전극부의 하면에 구비되는 하부 공통 전극부를 포함한다.In addition, the lattice-type first electrode may include: an intersecting electrode unit including a 1-1 electrode and a 1-2 electrode intersecting the 1-1 electrode; and a lower common electrode part provided on a lower surface of the cross electrode part.
또한, 상기 유전체는 상기 하부 공통 전극부의 표면상에도 형성된다.In addition, the dielectric is also formed on the surface of the lower common electrode part.
한편, 본 발명에 따른 커패시터의 제조방법은, 서로 교차하는 복수개의 개구부가 구비된 기판에서 상기 개구부에 금속을 충진하여 격자형 제1전극을 형성하는 단계; 상기 기판의 적어도 일부를 제거하여 상기 격자형 제1전극의 표면을 노출하는 단계; 상기 노출된 격자형 제1전극의 표면에 유전체를 형성하는 단계; 및 상기 유전체 상에 제2전극을 형성하는 단계;를 포함한다.On the other hand, the method of manufacturing a capacitor according to the present invention comprises the steps of forming a lattice-type first electrode by filling the openings with a metal in a substrate having a plurality of openings crossing each other; removing at least a portion of the substrate to expose a surface of the lattice-type first electrode; forming a dielectric on the exposed surface of the lattice-type first electrode; and forming a second electrode on the dielectric.
또한, 상기 기판은 양극산화막 재질로 구성되는 양극산화막 기판이다.In addition, the substrate is an anodized film substrate composed of an anodized film material.
한편, 본 발명에 따른 커패시터는, 복수개의 제1-1전극과 복수개의 제1-2전극이 서로 교차하여 격자방을 형성하면서 구비되는 교차 전극부를 포함하는 제1전극; 상기 교차 전극부 표면상에 형성되는 유전체; 및 상기 유전체상에 형성되는 제2전극;을 포함한다.On the other hand, the capacitor according to the present invention comprises: a first electrode including a cross electrode part provided while a plurality of 1-1 electrodes and a plurality of 1-2 electrodes cross each other to form a lattice room; a dielectric formed on a surface of the cross electrode part; and a second electrode formed on the dielectric.
또한, 상기 제1전극의 격자방 측면에 형성된 요철부를 포함한다.In addition, the first electrode includes a concave-convex portion formed on the side of the grid.
또한, 상기 유전체는 상기 교차 전극부의 표면을 전체적으로 감싸면서 형성되고, 상기 제2전극은 상기 교차 전극부의 표면에 형성된 유전체의 표면을 전체적으로 감싸면서 형성된다.In addition, the dielectric is formed while entirely surrounding the surface of the cross electrode, and the second electrode is formed while completely enclosing the surface of the dielectric formed on the surface of the cross electrode.
한편, 본 발명에 따른 커패시터는, 격자형 제1전극; 상기 제1전극의 표면상에 형성된 유전체;및 상기 유전체의 표면상에 형성된 제2전극;을 포함하는 단위 커패시터를 포함하되, 상기 단위 커패시터들이 서로 직렬연결된다.On the other hand, the capacitor according to the present invention, a grid-type first electrode; and a unit capacitor including a dielectric formed on a surface of the first electrode and a second electrode formed on the surface of the dielectric, wherein the unit capacitors are connected in series with each other.
한편, 본 발명에 따른 커패시터는, 격자형 제1전극; 상기 제1전극의 표면상에 형성된 유전체;및 상기 유전체의 표면상에 형성된 제2전극;을 포함하는 단위 커패시터를 포함하되, 상기 단위 커패시터들이 서로 병렬연결된다.On the other hand, the capacitor according to the present invention, a grid-type first electrode; and a unit capacitor including a dielectric formed on a surface of the first electrode and a second electrode formed on the surface of the dielectric, wherein the unit capacitors are connected in parallel to each other.
한편, 본 발명에 따른 커패시터는, 격자형 제1전극; 상기 제1전극의 표면상에 형성된 유전체;및 상기 유전체의 표면상에 형성된 제2전극;을 포함하는 단위 커패시터를 포함하되, 상기 단위 커패시터들이 서로 직렬 및 병렬연결된다.On the other hand, the capacitor according to the present invention, a grid-type first electrode; and a unit capacitor including a dielectric formed on a surface of the first electrode and a second electrode formed on the surface of the dielectric, wherein the unit capacitors are connected in series and parallel to each other.
한편, 본 발명에 따른 커패시터용 전극은, 복수개의 제1-1전극과 복수개의 제1-2전극이 서로 교차하여 격자방을 형성하면서 구비되는 교차 전극부; 및 상기 교차 전극부의 외측에 구비되는 측부 공통 전극부;를 포함한다.On the other hand, the electrode for a capacitor according to the present invention, a plurality of 1-1 electrodes and a plurality of 1-2 electrodes cross each other to form a lattice room, the intersecting electrode portion provided; and a side common electrode part provided outside the cross electrode part.
한편, 본 발명에 따른 커패시터용 전극은, 복수개의 제1-1전극과 복수개의 제1-2전극이 서로 교차하여 격자방을 형성하면서 구비되는 교차 전극부; 및 상기 교차 전극부의 하면에 구비되는 하부 공통 전극부;를 포함한다. On the other hand, the electrode for a capacitor according to the present invention, a plurality of 1-1 electrodes and a plurality of 1-2 electrodes cross each other to form a lattice room, the intersecting electrode portion provided; and a lower common electrode part provided on a lower surface of the cross electrode part.
본 발명은 커패시터의 적어도 하나의 전극을 3차원의 격자 모양으로 형성하여 정전용량을 키운 커패시터, 그 제조방법 및 커패시터용 전극을 제공한다.The present invention provides a capacitor in which capacitance is increased by forming at least one electrode of the capacitor in a three-dimensional lattice shape, a method for manufacturing the same, and an electrode for the capacitor.
도 1은 본 발명의 바람직한 제1실시예에 따른 커패시터의 사시도.1 is a perspective view of a capacitor according to a first preferred embodiment of the present invention;
도 2는 도 1의 A-A'단면도.Fig. 2 is a cross-sectional view taken along line A-A' of Fig. 1;
도 3은 본 발명의 바람직한 제1실시예를 위한 양극산화막을 도시한 도면.3 is a view showing an anodized film for the first preferred embodiment of the present invention.
도 4 내지 도 13은 본 발명의 바람직한 제1실시예에 따른 커패시터의 제조방법을 도시한 도면.4 to 13 are views illustrating a method of manufacturing a capacitor according to a first preferred embodiment of the present invention.
도 14는 본 발명의 바람직한 제1실시예에 따른 단위 커패시터를 도시한 도면.14 is a view showing a unit capacitor according to a first preferred embodiment of the present invention.
도 15는 본 발명의 바람직한 제1실시예에 따른 단위 커패시터를 전기적으로 병렬 연결한 것을 도시한 도면.15 is a diagram illustrating an electrically parallel connection of unit capacitors according to a first exemplary embodiment of the present invention.
도 16은 본 발명의바람직한 제1실시예에 따른 단위 커패시터를 전기적으로 직렬 연결한 것을 도시한 도면.16 is a diagram illustrating an electrically connected unit capacitor in series according to the first preferred embodiment of the present invention.
도 17은 본 발명의 바람직한 제2실시예에 따른 커패시터를 도시한 도면.17 is a view showing a capacitor according to a second preferred embodiment of the present invention.
도 18 내지 도 23은 본 발명의 바람직한 제2실시예에 따른 커패시터의 제조방법을 도시한 도면.18 to 23 are views illustrating a method of manufacturing a capacitor according to a second preferred embodiment of the present invention.
도 24는 본 발명의 바람직한 제2실시예의 변형례를 도시한 도면.24 is a view showing a modified example of the second preferred embodiment of the present invention.
이하의 내용은 단지 발명의 원리를 예시한다. 그러므로 당업자는 비록 본 명세서에 명확히 설명되거나 도시되지 않았지만 발명의 원리를 구현하고 발명의 개념과 범위에 포함된 다양한 장치를 발명할 수 있는 것이다. 또한, 본 명세서에 열거된 모든 조건부 용어 및 실시 예들은 원칙적으로, 발명의 개념이 이해되도록 하기 위한 목적으로만 명백히 의도되고, 이와 같이 특별히 열거된 실시 예들 및 상태들에 제한적이지 않는 것으로 이해되어야 한다.The following is merely illustrative of the principles of the invention. Therefore, those skilled in the art will be able to devise various devices that, although not explicitly described or shown herein, embody the principles of the invention and are included in the spirit and scope of the invention. In addition, it should be understood that all conditional terms and examples listed herein are, in principle, expressly intended only for the purpose of understanding the inventive concept and are not limited to the specifically enumerated embodiments and states as such. .
상술한 목적, 특징 및 장점은 첨부된 도면과 관련한 다음의 상세한 설명을 통하여 보다 분명해질 것이며, 그에 따라 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 발명의 기술적 사상을 용이하게 실시할 수 있을 것이다.The above-described objects, features, and advantages will become more apparent through the following detailed description in relation to the accompanying drawings, and accordingly, those of ordinary skill in the art to which the invention pertains will be able to easily practice the technical idea of the invention. .
본 명세서에서 기술하는 실시 예들은 본 발명의 이상적인 예시 도인 단면도 및/또는 사시도들을 참고하여 설명될 것이다. 이러한 도면들에 도시된 막 및 영역들의 두께 등은 기술적 내용의 효과적인 설명을 위해 과장된 것이다. 제조 기술 및/또는 허용 오차 등에 의해 예시도의 형태가 변형될 수 있다. 또한 도면에 도시된 성형물의 개수는 예시적으로 일부만을 도면에 도시한 것이다. 따라서, 본 발명의 실시 예들은 도시된 특정 형태로 제한되는 것이 아니라 제조 공정에 따라 생성되는 형태의 변화도 포함하는 것이다. Embodiments described herein will be described with reference to cross-sectional and/or perspective views, which are ideal illustrative drawings of the present invention. The thicknesses of films and regions shown in these drawings are exaggerated for effective description of technical content. The shape of the illustrative drawing may be modified due to manufacturing technology and/or tolerance. In addition, the number of moldings shown in the drawings is only partially shown in the drawings by way of example. Accordingly, embodiments of the present invention are not limited to the specific form shown, but also include changes in the form generated according to the manufacturing process.
다양한 실시예들을 설명함에 있어서, 동일한 기능을 수행하는 구성요소에 대해서는 실시예가 다르더라도 편의상 동일한 명칭 및 동일한 참조번호를 부여하기로 한다. 또한, 이미 다른 실시예에서 설명된 구성 및 작동에 대해서는 편의상 생략하기로 한다.In describing various embodiments, components performing the same function will be given the same names and the same reference numbers for convenience even if the embodiments are different. In addition, configurations and operations already described in other embodiments will be omitted for convenience.
본 발명의 바람직한 실시예에 따른 커패시터는 단위 커패시터를 포함한다. 또한 본 발명의 바람직한 실시예에 따른 커패시터는 적층 커패시터를 포함한다. 또한, 본 발명의 바람직한 실시예에 따른 커패시터는 단위 커패시터들이 여러 개 결합된 형태를 포함할 수 있다.A capacitor according to a preferred embodiment of the present invention includes a unit capacitor. Also, the capacitor according to the preferred embodiment of the present invention includes a multilayer capacitor. Also, the capacitor according to the preferred embodiment of the present invention may include a form in which a plurality of unit capacitors are combined.
본 발명의 바람직한 실시예에 따른 커패시터(100)는 격자형 제1전극(200), 격자형 제1전극(200)의 표면상에 형성된 유전체(300) 및 유전체(300)의 표면상에 형성된 제2전극(400)을 포함한다. 본 발명의 바람직한 실시예에 따른 커패시터의 제조방법은 서로 교차하는 복수개의 개구부(11)가 구비된 기판(10)에서 개구부(11)에 금속(12)을 충진하여 격자형 제1전극(200)을 형성하는 단계, 기판(10)의 적어도 일부를 제거하여 격자형 제1전극(200)의 표면을 노출하는 단계, 노출된 격자형 제1전극(200)의 표면에 유전체(300)를 형성하는 단계 및 유전체(300) 상에 제2전극(400)을 형성하는 단계를 포함한다. The capacitor 100 according to a preferred embodiment of the present invention includes a lattice-type first electrode 200 , a dielectric 300 formed on the surface of the lattice-type first electrode 200 , and a second electrode formed on the surface of the dielectric 300 . It includes two electrodes 400 . In the method of manufacturing a capacitor according to a preferred embodiment of the present invention, in a substrate 10 having a plurality of openings 11 intersecting each other, metal 12 is filled in the openings 11 to form a lattice-type first electrode 200 . A step of exposing the surface of the lattice-type first electrode 200 by removing at least a portion of the substrate 10 , and forming the dielectric 300 on the exposed surface of the lattice-type first electrode 200 . and forming the second electrode 400 on the dielectric 300 .
본 발명의 바람직한 실시예에 따른 커패시터(100)는 적어도 하나의 전극이 3차원의 격자형 모양을 가진다. 격자형 전극은 소정의 높이를 가지는 복수개의 세부 전극이 서로 교차하여 격자방을 형성하는 구조를 포함하며 이를 통해 전극의 표면적을 3차원적으로 확장하게 된다. 격자형 전극의 표면에는 유전체(300)와 또 다른 전극이 순차적으로 형성됨으로써 커패시터(100)의 정전용량을 향상시킬 수 있게 된다. In the capacitor 100 according to the preferred embodiment of the present invention, at least one electrode has a three-dimensional grid shape. The grid-type electrode includes a structure in which a plurality of detailed electrodes having a predetermined height cross each other to form a grid room, thereby extending the surface area of the electrode three-dimensionally. Since the dielectric 300 and another electrode are sequentially formed on the surface of the grid electrode, the capacitance of the capacitor 100 can be improved.
먼저, 본 발명에 따른 제1실시예에 대해 살펴본다. First, a first embodiment according to the present invention will be described.
도 1은 본 발명의 바람직한 제1실시예에 따른 커패시터의 사시도이고, 도2는 도 1의 A-A'단면도이며, 도 3은 본 발명의 바람직한 제1실시예를 위한 양극산화막을 도시한 도면이고, 도 4 내지 도 13은 본 발명의 바람직한 제1실시예에 따른 커패시터의 제조방법을 도시한 도면이며, 도 14는 본 발명의 바람직한 제1실시예에 따른 단위 커패시터를 도시한 도면이고, 도 15는 본 발명의 바람직한 제1실시예에 따른 단위 커패시터를 전기적으로 병렬 연결한 것을 도시한 도면이며, 도 16은 본 발명의바람직한 제1실시예에 따른 단위 커패시터를 전기적으로 직렬 연결한 것을 도시한 도면이다.Fig. 1 is a perspective view of a capacitor according to a first preferred embodiment of the present invention, Fig. 2 is a sectional view taken along line A-A' of Fig. 1, and Fig. 3 is a view showing an anodized film for a first preferred embodiment of the present invention. 4 to 13 are views illustrating a method of manufacturing a capacitor according to a first preferred embodiment of the present invention, and FIG. 14 is a view showing a unit capacitor according to a first preferred embodiment of the present invention, and FIG. 15 is a diagram illustrating an electrically parallel connection of unit capacitors according to a first preferred embodiment of the present invention, and FIG. 16 is a diagram illustrating an electrically series connection of unit capacitors according to a first preferred embodiment of the present invention. It is a drawing.
도 1, 도 2 및 도9를 참조하면, 본 발명의 바람직한 제1실시예에 따른 커패시터는, 격자형 제1전극(200); 제1전극(200)의 표면상에 형성된 유전체(300); 및 유전체(300)의 표면상에 형성된 제2전극(400)을 포함한다. 1, 2 and 9, the capacitor according to the first preferred embodiment of the present invention includes a grid-type first electrode 200; a dielectric 300 formed on the surface of the first electrode 200; and a second electrode 400 formed on the surface of the dielectric 300 .
격자형 제1전극(200)은, 교차 전극부(210)와 측부 공통 전극부(220)를 포함한다. 교차 전극부(210)는 복수개의 제1-1전극(211)과 복수개의 제1-2전극(213)이 서로 교차하여 격자방(240)을 형성하면서 구비된다. The grid-type first electrode 200 includes a cross electrode part 210 and a side common electrode part 220 . The cross electrode part 210 is provided while a plurality of first-first electrodes 211 and a plurality of first-second electrodes 213 cross each other to form a lattice room 240 .
격자형 제1전극(200)은 도전성 금속으로 형성되며, 은(Ag), 니켈(Ni), 구리(Cu), 주석(Sn), 산화인듐(ITO), 팔라듐(Pd) 또는 이들의 합금일 수 있으며 본 발명이 이에 한정되는 것은 아니다. The lattice-type first electrode 200 is formed of a conductive metal, and may be silver (Ag), nickel (Ni), copper (Cu), tin (Sn), indium oxide (ITO), palladium (Pd), or an alloy thereof. and the present invention is not limited thereto.
제1-1전극(211)과 제1-2전극(213)은 소정의 높이를 가지는 평면 전극으로 형성된다. 제1-1전극(211)과 제1-2전극(213)는 수십 ㎛의 높이로 형성되며, 바람직하는 1㎛이상 300㎛이하의 높이로 형성된다. The 1-1 electrode 211 and the 1-2 electrode 213 are formed as planar electrodes having a predetermined height. The 1-1 electrode 211 and the 1-2 electrode 213 are formed to have a height of several tens of μm, and preferably have a height of 1 μm or more and 300 μm or less.
제1-1전극(211)과 제1-2전극(213)은 서로 교차하여 서로 인접하는 제1-1전극(211) 및 제1-2전극(213) 사이에 격자방(240)을 형성한다. 제1-1전극(211)과 제1-2전극(213)은 '+'형태로 서로 교차할 수 있으며 이 경우 격자방(240)은 사각의 형태로 형성될 수 있다. 제1-1전극(211)과 제1-2전극(213)이 서로 교차하는 각도는 90°에 한정되는 것은 것은 아니며 격자방(240)은 사각의 형태로 한정되는 것도 아니다.The 1-1 electrode 211 and the 1-2 electrode 213 cross each other to form a lattice room 240 between the 1-1 electrode 211 and the 1-2 electrode 213 adjacent to each other. do. The 1-1 electrode 211 and the 1-2 electrode 213 may cross each other in a '+' shape, and in this case, the lattice room 240 may be formed in a rectangular shape. The angle at which the first-first electrode 211 and the first-second electrode 213 intersect each other is not limited to 90°, and the lattice room 240 is not limited to a rectangular shape.
측부 공통 전극부(220)는 교차 전극부(210)의 외측에 구비된다. The side common electrode part 220 is provided outside the cross electrode part 210 .
측부 공통 전극부(220)는 교차 전극부(210)의 높이와 실질적으로 동일한 높이로 형성된다. 따라서 측부 공통 전극부(220)는 수십 ㎛의 높이로 형성되며, 바람직하는 1㎛이상 300㎛이하의 높이로 형성된다. The side common electrode part 220 is formed to have substantially the same height as that of the cross electrode part 210 . Therefore, the side common electrode part 220 is formed to have a height of several tens of μm, and preferably has a height of 1 μm or more and 300 μm or less.
측부 공통 전극부(220)는 제1-1공통 전극부(221)와 제1-2공통 전극부(223)을 포함한다. 제1-1공통 전극부(221)는 복수개의 제1-1전극(211)과 연결되고, 제1-2공통 전극부(223)는 복수개의 제1-2전극(213)과 연결된다. The side common electrode part 220 includes a 1-1 common electrode part 221 and a 1-2 common electrode part 223 . The 1-1 common electrode part 221 is connected to the plurality of 1-1 electrodes 211 , and the 1-2 common electrode part 223 is connected to the plurality of 1-2 electrodes 213 .
도 1을 참조하면, 커패시터(100)는 제1-1전극(211)과 제1-2전극(213)이 십자가 형태로 교차('+' 형상)하는 교차 전극부(210)가 내측에 구비되고 교차 전극부(210)의 외측에는 폐쇄 형태('ㅁ'자 형상)의 측부 공통 전극부(220)가 형성된다. 이를 통해 교차 전극부(210)와 측부 공통 전극부(220)는 서로 일체적으로 형성되어 커패시터(100)의 격자형 제1전극(200)이 된다. Referring to FIG. 1 , in the capacitor 100 , a cross electrode part 210 in which a 1-1 electrode 211 and a 1-2 electrode 213 cross in a cross shape ('+' shape) is provided inside. and a side common electrode part 220 of a closed shape ('ㅁ' shape) is formed on the outside of the cross electrode part 210 . Through this, the cross electrode part 210 and the side common electrode part 220 are integrally formed with each other to become the first lattice electrode 200 of the capacitor 100 .
격자형 제1전극(200)의 표면상에는 유전체(300)가 형성된다. 유전체(300)은 노출된 격자형 제1전극(200)의 표면에 전체적으로 형성된다. 유전체(300)는 교차 전극부(210)의 표면을 전체적으로 감싸면서 형성된다. 또한 유전체(300)는 측부 공통 전극부(220)의 표면에도 형성되며, 바람직하게는 측부 공통 전극부(220)의 외측면을 제외한 표면에 전체적으로 형성된다. The dielectric 300 is formed on the surface of the lattice-type first electrode 200 . The dielectric 300 is entirely formed on the exposed surface of the lattice-type first electrode 200 . The dielectric 300 is formed while entirely surrounding the surface of the cross electrode part 210 . In addition, the dielectric 300 is also formed on the surface of the side common electrode part 220 , and is preferably formed entirely on the surface except for the outer surface of the side common electrode part 220 .
유전체(300)는 탄탈 옥사이드(Ta2O5), 알루미늄 옥사이드(Al2O3), 티타늄 옥사이드(TiO2), 지코늄 옥사이드(ZrO2), 하프늄 옥사이드(HfO2), 티탄산바륨(BaTiO3)계 또는 티탄산스트론튬(SrTiO3)계 분말 또는 이들의 복합 유전체 중 적어도 하나를 포함하며, 충분한 정전용량을 발휘할 수 있는 재질인 것이 바람직하다. 유전체(300)는 증착공정(CVD, PVD, ALD)을 통해 형성될 수 있다. Dielectric 300 is tantalum oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), ziconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), barium titanate (BaTiO 3 ) )-based or strontium titanate (SrTiO 3 )-based powder or at least one of a composite dielectric thereof, and preferably a material capable of exhibiting sufficient capacitance. The dielectric 300 may be formed through a deposition process (CVD, PVD, or ALD).
유전체(300)의 표면상에는 제2전극(400)이 형성된다. 제2전극(400)은 유전체(300)가 형성된 영역에서 유전체(300)의 표면 상에 형성된다. 제2전극(400)은 교차 전극부(210)상에 형성된 유전체(300)의 표면을 전체적으로 감싸면서 형성된다. 또한, 측부 공통 전극부(220)의 표면상에 형성된 유전체(300)의 표면에도 형성되며, 바람직하게는 측부 공통 전극부(220)의 외측면을 제외한 표면에 전체적으로 형성된다.The second electrode 400 is formed on the surface of the dielectric 300 . The second electrode 400 is formed on the surface of the dielectric 300 in the region where the dielectric 300 is formed. The second electrode 400 is formed while completely surrounding the surface of the dielectric 300 formed on the cross electrode part 210 . It is also formed on the surface of the dielectric 300 formed on the surface of the side common electrode part 220 , and is preferably formed entirely on the surface except for the outer surface of the side common electrode part 220 .
제2전극(400)은 도전성 금속으로 형성되며, 은(Ag), 니켈(Ni), 구리(Cu), 주석(Sn), 산화인듐(ITO), 팔라듐(Pd) 또는 이들의 합금일 수 있으며 본 발명이 이에 한정되는 것은 아니다. 제2전극(400)은 격자형 제1전극(200)과 동일한 재질로 형성될 수 있다. The second electrode 400 is formed of a conductive metal, and may be silver (Ag), nickel (Ni), copper (Cu), tin (Sn), indium oxide (ITO), palladium (Pd), or an alloy thereof. The present invention is not limited thereto. The second electrode 400 may be formed of the same material as the lattice-type first electrode 200 .
격자형 제1전극(200)은 상면, 격자방(240)의 측면 및 하면에서 그 표면이 노출되어 구성되고, 유전체(300)는 격자형 제1전극(200)의 노출 표면 상에 형성되므로, 유전체(300) 역시 상면, 격자방(240)의 측면 및 하면에서 그 표면이 노출되어 형성된다. 또한 제2전극(400)은 유전체(300)의 노출 표면 상에 형성되므로 제2전극(400) 역시 상면, 격자방(240)의 측면 및 하면에서 그 표면이 노출되어 형성된다.The lattice-type first electrode 200 is configured such that its surface is exposed from the upper surface, the side surfaces and the lower surface of the lattice room 240 , and the dielectric 300 is formed on the exposed surface of the grid-type first electrode 200 , The dielectric 300 is also formed by exposing the surface on the upper surface, the side surface and the lower surface of the lattice room 240 . In addition, since the second electrode 400 is formed on the exposed surface of the dielectric 300 , the second electrode 400 is also formed by exposing its surface on the upper surface, the side surface and the lower surface of the lattice chamber 240 .
본 발명의 바람직한 제1실시예에 따른 커패시터(100)는 전극의 표면적이 3차원적으로 확장된 격자형 제1전극(200)을 포함하고, 3차원적으로 확장된 표면을 가지는 격자형 제1전극(200)의 표면상에 유전체(300)와 제2전극(400)을 형성함으로써 커패시터(100)의 정전용량을 향상시킬 수 있게 된다. The capacitor 100 according to the first preferred embodiment of the present invention includes a lattice-type first electrode 200 with a three-dimensionally extended surface area of the electrode, and a lattice-type first electrode 200 having a three-dimensionally extended surface. By forming the dielectric 300 and the second electrode 400 on the surface of the electrode 200 , the capacitance of the capacitor 100 can be improved.
본 발명의 바람직한 제1실시예에 따른 커패시터(100)는 인접하는 제1-1전극(211)들과 인접하는 제1-2전극(213)들 사이에 형성되는 관통부(250)를 포함한다. 인접하는 제1-1전극(211)들과 인접하는 제1-2전극(213)들 사이는 격자방(240)이 형성되고, 격자방(240)은 상,하로 오픈되어 관통부(250)가 형성된다. 격자방(240)이 관통부(250)의 구성으로 형성됨에 따라 커패시터(300)의 온도 상승에 따른 방열을 보다 효과적으로 달성할 수 있다. 또한 관통부(250)를 통과하는 냉각 유체(기체, 액체)를 이용하여 커패시터(300)의 냉각을 보다 효과적으로 달성할 수 있다.The capacitor 100 according to the first preferred embodiment of the present invention includes a through portion 250 formed between adjacent first-first electrodes 211 and adjacent first-second electrodes 213 . . A lattice room 240 is formed between the adjacent 1-1 electrodes 211 and the adjacent 1-2 electrodes 213 , and the lattice room 240 is opened up and down to form a through part 250 . is formed As the lattice room 240 is formed in the configuration of the through part 250 , heat dissipation according to an increase in the temperature of the capacitor 300 may be more effectively achieved. In addition, cooling of the capacitor 300 may be more effectively achieved by using a cooling fluid (gas, liquid) passing through the through portion 250 .
이하, 도 3 내지 도 13을 참조하여 본 발명의 바람직한 제1실시예에 따른 커패시터(100)의 제조방법에 대해 설명한다. Hereinafter, a method of manufacturing the capacitor 100 according to the first preferred embodiment of the present invention will be described with reference to FIGS. 3 to 13 .
도 3은 제1실시예에 따른 커패시터(100)의 제조방법에 사용되는 양극산화막(10)을 도시한 도면이다. 양극산화막(10)은 양극산화막은 모재인 금속을 양극산화하여 형성된 막을 의미하고, 포어는 금속을 양극산화하여 양극산화막을 형성하는 과정에서 형성되는 구멍을 의미한다. 예컨대, 모재인 금속이 알루미늄(Al) 또는 알루미늄 합금인 경우, 모재를 양극산화하면 모재의 표면에 알루미늄 산화물(Al203) 재질의 양극산화막이 형성된다. 위와 같이 형성된 양극산화막은 수직적으로 내부에 포어(P)가 형성되지 않은 배리어층(12)과, 내부에 포어(P)가 형성된 다공층(11)으로 구분된다. 배리어층(12)과 다공층(11)을 갖는 양극산화막이 표면에 형성된 모재에서, 모재를 제거하게 되면, 알루미늄 산화물(Al203) 재질의 양극산화막만이 남게 된다.3 is a view showing the anodization film 10 used in the method of manufacturing the capacitor 100 according to the first embodiment. The anodization film 10 refers to a film formed by anodizing a metal, which is a base material, and the pores mean a hole formed in the process of forming an anodization film by anodizing the metal. For example, when the base metal is aluminum (Al) or an aluminum alloy, when the base material is anodized, an anodization film made of aluminum oxide (Al 2 0 3 ) material is formed on the surface of the base material. The anodized film formed as above is vertically divided into a barrier layer 12 in which pores P are not formed and a porous layer 11 in which pores P are formed. When the base material is removed from the base material on which the anodized film having the barrier layer 12 and the porous layer 11 is formed on the surface, only the anodized film made of aluminum oxide (Al 2 O 3 ) material remains.
양극산화막(10)은 양극산화시 형성된 배리어층(12)이 그대로 남아 포어(P)의 상, 하 중 일단부를 밀폐하는 구조로 형성될 수 있다. 포어(P)는 1 ㎚ 이상 100 ㎚ 이하의 직경을 가진다. The anodized film 10 may be formed in a structure in which the barrier layer 12 formed during anodization remains as it is and seals one end of the upper and lower ends of the pores P. The pores P have a diameter of 1 nm or more and 100 nm or less.
양극산화막은 2~3ppm/℃의 열팽창 계수를 갖는다. 이로 인해 고온의 환경에 노출될 경우, 온도에 의한 열변형이 적다. 따라서 커패시터의 제작 환경이 비록 고온의 환경이라 하더라도 열 변형없이 정밀한 커패시터를 제작할 수 있고, 사용환경이 고온의 환경이라 하더라도 내구성이 높은 커패시터를 제공할 수 있게 된다. The anodized film has a coefficient of thermal expansion of 2-3 ppm/°C. For this reason, when exposed to a high temperature environment, thermal deformation due to temperature is small. Therefore, even if the manufacturing environment of the capacitor is a high temperature environment, it is possible to manufacture a precise capacitor without thermal deformation, and it is possible to provide a capacitor with high durability even if the usage environment is a high temperature environment.
이와 같은 양극산화막(10)은 본 발명의 바람직한 제1실시예의 커패시터(100)를 제조함에 있어서 기판으로 이용된다. 이하에서는 양극산화막(10)을 이용하여 본 발명의 바람직한 제1실시예에 따른 커패시터(100)의 제조방법에 대해 설명한다. Such an anodized film 10 is used as a substrate in manufacturing the capacitor 100 according to the first preferred embodiment of the present invention. Hereinafter, a method of manufacturing the capacitor 100 according to the first preferred embodiment of the present invention using the anodized film 10 will be described.
도 4는 하면에 시드층(20)이 구비된 양극산화막(10)을 도시한 도면으로서, 도 4a는 평면도이고 도 4b는 도 4a의 A-A'단면도이다. 4 is a view showing an anodization film 10 having a seed layer 20 on its lower surface. FIG. 4A is a plan view and FIG. 4B is a cross-sectional view taken along line A-A' of FIG.
도 4를 참조하면, 먼저 양극산화막(10)을 준비하고 양극산화막(10)의 하면에는 시드층(20)을 구비한다. 시드층(20)은 구리(Cu) 재질일 수 있다. 양극산화막(10)은 모재인 금속을 양극산화하여 형성한 후 모재를 제거함으로써 준비된다. 시드층(20)은 증착공정(CVD, PVD, ALD)을 통해 형성될 수 있다. Referring to FIG. 4 , an anodization film 10 is prepared first, and a seed layer 20 is provided on a lower surface of the anodization film 10 . The seed layer 20 may be made of copper (Cu). The anodization film 10 is prepared by removing the base material after forming by anodizing the base metal. The seed layer 20 may be formed through a deposition process (CVD, PVD, or ALD).
도 5는 양극산화막(10)에 개구부(15)를 형성한 것을 도시한 도면으로서, 도 5a는 평면도이고 도 5b는 도 5a의 A-A'단면도이다. FIG. 5 is a view showing the formation of the opening 15 in the anodized film 10. FIG. 5A is a plan view and FIG. 5B is a cross-sectional view taken along line A-A' of FIG. 5A.
도 5를 참조하면, 양극산화막(10)에 개구부(15)를 형성한다. 개구부(15)는 양극산화막(10)을 에칭하여 형성될 수 있다. 이를 위해 양극산화막(10)의 상면, 보다 바람직하게는 배리어층(12)의 상면에 포토 레지스트를 구비하고 이를 패터닝한 다음, 패터닝되어 오픈된 영역의 양극산화막(10)이 에칭 용액과 반응하여 개구부(15)가 형성된다. 구체적으로 설명하면, 개구부(15)을 형성하기 전의 양극산화막(10)의 상면에 감광성 재료를 구비한 다음 노광 및 현상 공정이 수행될 수 있다. 감광성 재료는 노광 및 현상 공정에 의해 오픈영역을 형성하면서 적어도 일부가 패터닝되어 제거될 수 있다. 양극산화막(10)은 패터닝 과정에 의해 감광성 재료가 제거된 오픈영역을 통해 에칭 공정이 수행되어 그 일부가 제거되어 개구부(15)를 형성하게 된다. 양극산화막(10)을 에칭 용액으로 습식 에칭함으로써 수직한 내벽을 가지는 개구부(15)가 구비된다.Referring to FIG. 5 , an opening 15 is formed in the anodized film 10 . The opening 15 may be formed by etching the anodization layer 10 . To this end, a photoresist is provided on the upper surface of the anodization film 10, more preferably the upper surface of the barrier layer 12, and patterned. (15) is formed. Specifically, an exposure and development process may be performed after the photosensitive material is provided on the upper surface of the anodized film 10 before the opening 15 is formed. At least a portion of the photosensitive material may be patterned and removed while forming an open area by an exposure and development process. The anodic oxide layer 10 is etched through the open region from which the photosensitive material has been removed by the patterning process, and a part thereof is removed to form the opening 15 . An opening 15 having a vertical inner wall is provided by wet etching the anodization film 10 with an etching solution.
여기서 배리어층(12)의 상면에 포토레지스트를 형성하는 이유는, 다공층(11)의 상면에 포토레지스트(20)를 형성할 경우에는 패터닝 공정 이후에 포토레지스트(20)의 제거가 용이하지 않고, 포토레지스트(20)의 제거시 완벽하게 제거되지 못한 포토제지스트(20) 찌꺼기들이 다공층(11)의 포어(P) 내부에 잔존하고 있다가 추후에 방출되는 것을 방지하기 위함이다. Here, the reason for forming the photoresist on the upper surface of the barrier layer 12 is that when the photoresist 20 is formed on the upper surface of the porous layer 11, it is not easy to remove the photoresist 20 after the patterning process. , This is to prevent the photoresist 20 residues that are not completely removed when the photoresist 20 is removed from remaining inside the pores P of the porous layer 11 and later released.
개구부(15)의 측면벽에는 트렌치(19)가 구비된다. 트렌치(19)는 양극산화막 제조시 형성된 포어(P)가 에칭 과정에서 오픈되면서 형성되는 포어형 트렌치(19a)일 수 있다. 이 경우, 포어형 트렌치(19a)의 폭과 깊이는 10 ㎚ 이상 1㎛ 이하의 범위를 가진다. A trench 19 is provided in the side wall of the opening 15 . The trench 19 may be a pore-type trench 19a formed while the pores P formed during the production of the anodization film are opened during the etching process. In this case, the width and depth of the pore-type trench 19a have a range of 10 nm or more and 1 μm or less.
트렌치(19)는 포어형 트렌치(19a)와는 별개로, 양극산화막(10)의 에칭 과정에서 형성되는 에칭형 트렌치(19b)를 포함할 수 있다. The trench 19 may include an etching-type trench 19b formed during the etching process of the anodization layer 10 separately from the pore-type trench 19a.
양극산화막(10)은 포토레지스트의 오픈 영역에서 에칭 용액과 반응하면서 포토레지스트의 오픈 패턴의 형상을 따라 수직한 방향으로 에칭되면서 개구부(15)가 형성된다. 포토레지스트를 패터닝할 때에 포토레지스트의 오픈 영역의 패턴 경계가 요철의 형태를 갖도록 하면, 포토레지스트의 요철 패턴 경계면에 의해 양극산화막 에칭시 양극산화막의 개구부(15)의 측면벽도 수평 단면에서 요철 패턴을 가지게 되며 개구부(15)의 측면벽에서의 요철부가 에칭형 트렌치(19b)가 된다. 에칭형 트렌치(19b)의 벽면에는 포어형 트렌치(19a)가 복수개 형성된다. 포어형 트렌치(19a)는 에칭형 트렌치(19b)의 벽면을 따라 형성되므로, 거시적인 관점에서 트렌치(19)는 포어형 트렌치(19a)와 에칭형 트렌치(19b)를 포함하게 된다. 에칭형 트렌치(19b)의 폭과 깊이는 포어형 트렌치(19a)의 폭과 깊이보다 더 크게 형성된다. 바람직하게는 에칭형 트렌치(19b)의 폭과 깊이는 100㎚ 이상 30㎛이하의 범위를 가진다. The anodic oxide layer 10 reacts with the etching solution in the open region of the photoresist and is etched in a vertical direction along the shape of the open pattern of the photoresist to form the opening 15 . When the photoresist is patterned, if the pattern boundary of the open region of the photoresist has a concave-convex shape, the side wall of the opening 15 of the anodization film is also formed with a concave-convex pattern in the horizontal section when the anodization film is etched by the concave-convex pattern boundary of the photoresist. and the concave-convex portion on the side wall of the opening 15 becomes the etched trench 19b. A plurality of pore-type trenches 19a are formed on the wall surface of the etching-type trenches 19b. Since the pore-shaped trench 19a is formed along the wall surface of the etched trench 19b, the trench 19 includes the pore-shaped trench 19a and the etched trench 19b from a macroscopic point of view. The width and depth of the etching-type trench 19b are formed to be larger than the width and depth of the fore-type trench 19a. Preferably, the width and depth of the etched trench 19b are in the range of 100 nm or more and 30 μm or less.
이상과 같이, 트렌치(19)는 양극산화막 제조시 형성된 포어(P)가 에칭 과정에서 오픈되면서 형성되는 포어형 트렌치(19a)와 포토레지스트의 요철 패턴 경계면에 대응하여 양극산화막(10)의 에칭시 형성되는 에칭형 트렌치(19b)를 포함한다. As described above, the trench 19 corresponds to the pore-type trench 19a formed while the pores P formed during the production of the anodization film are opened during the etching process and the concave-convex pattern interface of the photoresist. and an etched trench 19b to be formed.
도 6 및 도 7은 양극산화막(10)의 개구부(15)의 내부에 도전성 금속(16)을 충진한 것을 도시한 도면으로서, 도 6a는 평면도이고 도 6b는 도 6a의 A-A'단면도이며 도 7은 도 6의 사시도이다.6 and 7 are views illustrating that the conductive metal 16 is filled in the opening 15 of the anodization film 10. FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along line A-A' of FIG. 6A. 7 is a perspective view of FIG. 6 ;
도 6 및 도 7을 참조하면, 개구부(15)의 내부에 도전성 금속(16)을 충진한다. 개구부(15)의 내부에 충진되는 도전성 금속(16)은 도금 방법에 의해 형성될 수 있다. 양극산화막(10)의 하면에 구비된 시드층(20)를 이용하여 전해 도금함으로써 개구부(15)의 내부에 도전성 금속(16)을 충진할 수 있다. 다만 이러한 제조 방법으로만 한정되는 것은 아니고 증착 방법을 이용하는 것도 가능하다. 도금 공정이 완료되면 평탄화 공정을 수행한다. 화학적 기계적 연마(CMP) 공정을 통해 양극산화막(10)의 상면으로 돌출된 도전성 금속(16)을 제거하면서 평탄화시킨다.6 and 7 , the conductive metal 16 is filled in the opening 15 . The conductive metal 16 filled in the opening 15 may be formed by a plating method. The conductive metal 16 may be filled in the opening 15 by electrolytic plating using the seed layer 20 provided on the lower surface of the anodized layer 10 . However, it is not limited only to this manufacturing method, and it is also possible to use a deposition method. When the plating process is completed, a planarization process is performed. The conductive metal 16 protruding from the top surface of the anodic oxide layer 10 is removed and planarized through a chemical mechanical polishing (CMP) process.
개구부(15)에 충진된 도전성 금속(16)은 은(Ag), 니켈(Ni), 구리(Cu), 주석(Sn), 산화인듐(ITO), 팔라듐(Pd) 또는 이들의 합금일 수 있으며 본 발명이 이에 한정되는 것은 아니다. The conductive metal 16 filled in the opening 15 may be silver (Ag), nickel (Ni), copper (Cu), tin (Sn), indium oxide (ITO), palladium (Pd), or an alloy thereof. The present invention is not limited thereto.
개구부(15)에 충진된 도전성 금속(16)은 격자형 제1전극(200)이 된다. 격자형 제1전극(200)은, 교차 전극부(210)와 측부 공통 전극부(220)를 포함한다. 교차 전극부(210)는 복수개의 제1-1전극(211)과 복수개의 제1-2전극(213)이 서로 교차하여 격자방(240)을 형성하면서 구비된다. The conductive metal 16 filled in the opening 15 becomes the lattice type first electrode 200 . The grid-type first electrode 200 includes a cross electrode part 210 and a side common electrode part 220 . The cross electrode part 210 is provided while a plurality of first-first electrodes 211 and a plurality of first-second electrodes 213 cross each other to form a lattice room 240 .
본 발명의 바람직한 실시예에 따른 트렌치(19)는 포어형 트렌치(19a)와 에칭형 트렌치(19b)를 포함하고, 제1전극(200)이 포어형 트렌치(19a)와 에칭형 트렌치(19b)의 표면상에 형성된다. 제1전극(200)의 격자방(240) 측면에는 트렌치(19)의 표면에 도전성 금속(16)이 형성되어 요철부가 형성된다. 구체적으로, 포어형 트렌치(19a)의 표면에 도전성 금속(16)이 형성되어 포어형 요철부가 형성되고, 에칭형 트렌치(19b)의 표면에 도전성 금속(16)이 형성되어 에칭형 요철부가 형성됨으로써, 제1전극(200)의 표면적이 더욱 커지게 된다. The trench 19 according to the preferred embodiment of the present invention includes a pore-type trench 19a and an etched trench 19b, and the first electrode 200 includes a pore-type trench 19a and an etched trench 19b. formed on the surface of The conductive metal 16 is formed on the surface of the trench 19 on the side of the lattice chamber 240 of the first electrode 200 to form an uneven portion. Specifically, the conductive metal 16 is formed on the surface of the pore-type trench 19a to form the pore-type uneven portions, and the conductive metal 16 is formed on the surface of the etch-type trench 19b to form the etching-type uneven portions. , the surface area of the first electrode 200 becomes larger.
이후 양극산화막(10)의 하부에 구비된 시드층(20)은 제거된다. 시드층(20)은 구리(Cu) 에천트를 이용하여 제거될 수 있다. Thereafter, the seed layer 20 provided under the anodization layer 10 is removed. The seed layer 20 may be removed using a copper (Cu) etchant.
도 8 및 도 9는 측부 공통 전극부(220)의 내측에 존재하는 양극산화막(10)을 제거한 것을 도시한 도면으로서, 도 8a는 평면도이고 도 8b는 도 8a의 A-A'단면도이며 도 9는 도 8의 사시도이다. 8 and 9 are views illustrating the removal of the anodization film 10 present on the inside of the side common electrode part 220. FIG. 8A is a plan view, FIG. 8B is a cross-sectional view taken along line A-A' of FIG. 8A, and FIG. 9 is a perspective view of FIG. 8 .
도 8 및 도 9를 참조하면, 격자형 제1전극(200)의 측부 공통 전극부(220)의 내측에 존재하는 양극산화막(10)을 제거한다. 이를 위해 도전성 금속(16)이 충진된 양극산화막(10)의 상면에 포토 레지스트를 구비하고 이를 패터닝한 다음, 패터닝되어 오픈된 영역의 양극산화막(10)이 에칭 용액과 반응하여 측부 공통 전극부(220)의 내측의 양극산화막(10)이 제거된다. 그 결과 격자형 제1전극(200)의 표면이 외부로 노출되게 된다.Referring to FIGS. 8 and 9 , the anodic oxide layer 10 present inside the side common electrode part 220 of the lattice-type first electrode 200 is removed. To this end, a photoresist is provided on the upper surface of the anodized film 10 filled with the conductive metal 16 and patterned, and then the anodized film 10 in the patterned and open area reacts with the etching solution to react with the side common electrode part ( The anodization film 10 inside the 220 is removed. As a result, the surface of the grid-type first electrode 200 is exposed to the outside.
도 10 및 도 11은 노출된 격자형 제1전극(200)의 표면에 유전체(300)를 형성한 것을 도면으로서, 도 10a는 평면도이고 도 10b는 도 10a의 A-A'단면도이며 도 11은 도 10의 사시도이다. 10 and 11 are views illustrating the formation of a dielectric 300 on the surface of the exposed grid-type first electrode 200, FIG. 10A is a plan view, FIG. 10B is a cross-sectional view taken along line A-A' of FIG. 10A, and FIG. 10 is a perspective view.
도 10 및 도 11을 참조하면, 노출된 격자형 제1전극(200)의 표면에 유전체(300)를 형성한다 유전체(300)는 탄탈 옥사이드(Ta2O5), 알루미늄 옥사이드(Al2O3), 티타늄 옥사이드(TiO2), 지코늄 옥사이드(ZrO2), 하프늄 옥사이드(HfO2), 티탄산바륨(BaTiO3)계 또는 티탄산스트론튬(SrTiO3)계 분말 또는 이들의 복합 유전체 중 적어도 하나를 포함하며, 충분한 정전용량을 발휘할 수 있는 재질인 것이 바람직하다. 유전체(300)는 증착공정(CVD, PVD, ALD)을 통해 형성될 수 있다. 10 and 11 , the dielectric 300 is formed on the exposed surface of the lattice-type first electrode 200 . The dielectric 300 is tantalum oxide (Ta 2 O 5 ), aluminum oxide (Al 2 O 3 ). ), titanium oxide (TiO 2 ), ziconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), barium titanate (BaTiO 3 ) based or strontium titanate (SrTiO 3 ) based powder or at least one of a composite dielectric thereof and a material capable of exhibiting sufficient capacitance is preferable. The dielectric 300 may be formed through a deposition process (CVD, PVD, or ALD).
도 12 및 도 13은 유전체(300)의 표면상에는 도전성 금속(17)을 형성한 것을 도시한 도면으로서, 도 12a는 평면도이고 도 12b는 도 12a의 A-A'단면도이며 도 13은 도 12의 사시도이다. 12 and 13 are views illustrating that a conductive metal 17 is formed on the surface of the dielectric 300. FIG. 12A is a plan view, FIG. 12B is a cross-sectional view taken along line A-A' of FIG. 12A, and FIG. is a perspective view.
도 12 및 도 13을 참조하면, 유전체(300)의 표면상에는 도전성 금속(17)을 형성한다. 도전성 금속(17)은 제2전극(400)이 형성된다. 도전성 금속(17)은 교차 전극부(210)상에 형성된 유전체(300)의 표면을 전체적으로 감싸면서 형성된다. 또한, 도전성 금속(17)은 측부 공통 전극부(220)의 표면상에 형성된 유전체(300)의 표면에도 형성된다.12 and 13 , a conductive metal 17 is formed on the surface of the dielectric 300 . The second electrode 400 is formed on the conductive metal 17 . The conductive metal 17 is formed while completely surrounding the surface of the dielectric 300 formed on the cross electrode part 210 . In addition, the conductive metal 17 is also formed on the surface of the dielectric 300 formed on the surface of the side common electrode part 220 .
이후 테두리측의 유전체(300), 제2전극(400) 및 양극산화막(10)을 제거하여 본 발명의 바람직한 제1실시예에 따른 커패시터(100)를 완성하게 된다. 한편 이와는 다르게 양극산화막(10)은 제거되지 않을 수 있으며, 따라서 본 발명의 바람직한 제1실시예에 따른 커패시터(100)는 측부 공통 전극부(220)의 외측에 양극산화막(10)이 구비된 구조를 포함한다. 이 경우 측부 공통 전극부(220)의 외측에 구비된 양극산화막(10)은 측부 공통 전극부(220)의 외측면을 절연시키는 기능을 수행할 수 있다. 한편 배선연결을 위해 상면 및 하면 중 적어도 일부에서 제2전극(400) 및 유전체(300) 부분을 제거한 후 격자형 제1전극(200) 부분을 노출시켜 배선과 연결할 수 있다. Thereafter, the dielectric 300 , the second electrode 400 , and the anodization film 10 on the edge are removed to complete the capacitor 100 according to the first preferred embodiment of the present invention. On the other hand, unlike this, the anodization film 10 may not be removed. Therefore, the capacitor 100 according to the first preferred embodiment of the present invention has a structure in which the anodization film 10 is provided on the outside of the side common electrode part 220 . includes In this case, the anodization layer 10 provided on the outside of the side common electrode part 220 may insulate the outer surface of the side common electrode part 220 . Meanwhile, after removing the second electrode 400 and the dielectric 300 from at least a portion of the upper and lower surfaces for wiring connection, the lattice-shaped first electrode 200 may be exposed to connect with the wiring.
도 14는 측부 공통 전극부(220)의 외측면의 양극산화막(10)을 제거하여 측부 공통 전극부(220)의 외측면이 노출된 것을 도시한 도면이다. 노출된 측부 공통 전극부(220)의 외측면에 하나의 외부 전극을 연결하고, 제2전극(400)에 다른 하나의 외부 전극을 형성하여 커패시터를 형성하게 된다. FIG. 14 is a view illustrating that the outer surface of the side common electrode part 220 is exposed by removing the anodization film 10 on the outer surface of the side common electrode part 220 . One external electrode is connected to the outer surface of the exposed side common electrode part 220 , and another external electrode is formed on the second electrode 400 to form a capacitor.
격자형 제1전극(200)과 제2전극(400)은 유전체(300)을 사이에 두고 서로 대향되게 구비된다. 제1전극(200)은 격자형으로 구성된 3차원 전극이고 제2전극(400)은 제1전극(200)의 표면을 따라 형성되므로 제2전극(400) 역시 격자형으로 구성된 3차원 전극이 된다. 이러한 격자형으로 형성되는 2개의 제1, 2전극(200, 400)에 외부 전극을 통해 전압을 인가하면 서로 대향하는 제1전극(211)과 제2전극(231) 사이에 전하가 축적되고, 이때 단위 커패시터의 정전 용량은 제1전극(200) 및 제2전극(400)의 서로 중첩되는 영역의 면적과 비례하게 된다. 여기서 제1전극(200) 및 제2전극(400)은 격자형으로 구성되는 3차원 전극이기 때문에 단위 커패시터의 정전용량을 크게 향상시킬 수 있게 된다. The lattice-type first electrode 200 and the second electrode 400 are provided to face each other with the dielectric 300 interposed therebetween. Since the first electrode 200 is a three-dimensional electrode configured in a grid shape and the second electrode 400 is formed along the surface of the first electrode 200, the second electrode 400 also becomes a three-dimensional electrode configured in a grid shape. . When a voltage is applied through an external electrode to the two first and second electrodes 200 and 400 formed in such a grid shape, charges are accumulated between the first electrode 211 and the second electrode 231 facing each other, In this case, the capacitance of the unit capacitor is proportional to the area of the overlapping regions of the first electrode 200 and the second electrode 400 . Here, since the first electrode 200 and the second electrode 400 are three-dimensional electrodes configured in a grid shape, the capacitance of the unit capacitor can be greatly improved.
단위 커패시터는 전기적으로 서로 직렬 연결되거나 병렬 연결되거나 직렬 및 병렬 연결될 수 있다. 도 15를 참조하면, 도 15는 격자형 제1전극(200), 제1전극(200)의 표면상에 형성된 유전체(300) 및 유전체(300)의 표면상에 형성된 제2전극(400)을 포함하는 단위 커패시터들이 서로 병렬 연결되는 구조를 도시한 도면이다. 도 16을 참조하면, 도 16은 격자형 제1전극(200), 제1전극(200)의 표면상에 형성된 유전체(300) 및 유전체(300)의 표면상에 형성된 제2전극(400)을 포함하는 단위 커패시터들이 서로 직렬 연결되는 구조를 도시한 도면이다. The unit capacitors may be electrically connected to each other in series, in parallel, or in series and parallel. Referring to FIG. 15 , FIG. 15 shows a grid-type first electrode 200 , a dielectric 300 formed on the surface of the first electrode 200 , and a second electrode 400 formed on the surface of the dielectric 300 . It is a diagram showing a structure in which the included unit capacitors are connected to each other in parallel. Referring to FIG. 16 , FIG. 16 shows a grid-type first electrode 200 , a dielectric 300 formed on the surface of the first electrode 200 , and a second electrode 400 formed on the surface of the dielectric 300 . It is a diagram showing a structure in which the included unit capacitors are connected in series to each other.
복수개의 단위 커패시터들이 서로 직렬 연결되는 구조에 따르면 커패시터(100)의 내전압특성을 향상시킬 수 있다. 또한 복수개의 단위 커패시터들이 서로 병렬 연결되는 구조에 따르면 커패시터(100)의 정전용량을 더욱 크게할 수 있다. According to a structure in which a plurality of unit capacitors are connected in series to each other, the withstand voltage characteristic of the capacitor 100 may be improved. Also, according to a structure in which a plurality of unit capacitors are connected in parallel to each other, the capacitance of the capacitor 100 may be further increased.
한편, 단위 커패시터(10)들을 서로 직렬 연결 또는 병렬 연결하는 다양한 구조들은 본 발명의 바람직한 제1실시예에 따른 단위 커패시터의 개시 구성에 기초하여 통상의 기술자가 배선구조를 적절하게 형성하므로써 쉽게 도출할 수 있는 구조를 모두 포함한다. On the other hand, various structures for connecting the unit capacitors 10 to each other in series or in parallel can be easily derived by a person skilled in the art based on the initial configuration of the unit capacitor according to the first preferred embodiment of the present invention by appropriately forming the wiring structure. Includes all possible structures.
이하, 본 발명의 바람직한 제2실시예에 따른 커패시터(100) 및 그 제조방법에 대해 설명한다. 단, 이하 설명되는 실시예들은 상기 제1실시예와 비교하여 특징적인 구성요소들을 중심으로 설명하겠으며, 제1실시예와 동일하거나 유사한 구성요소들에 대한 설명은 생략한다. Hereinafter, the capacitor 100 and a manufacturing method thereof according to a second preferred embodiment of the present invention will be described. However, the embodiments to be described below will be mainly described with respect to the characteristic components compared to the first embodiment, and descriptions of the same or similar components as those of the first embodiment will be omitted.
도 17은 본 발명의 바람직한 제2실시예에 따른 커패시터를 도시한 도면이고, 도 18 내지 도 23은 본 발명의 바람직한 제2실시예에 따른 커패시터의 제조방법을 도시한 도면이다.17 is a view showing a capacitor according to a second preferred embodiment of the present invention, and FIGS. 18 to 23 are views showing a method of manufacturing a capacitor according to a second preferred embodiment of the present invention.
도 17을 참조하면, 도 17a는 제2실시예에 따른 커패시터(100)의 사시도이고, 도 17b는 도 17a의 A-A'단면도이다.Referring to FIG. 17, FIG. 17A is a perspective view of the capacitor 100 according to the second embodiment, and FIG. 17B is a cross-sectional view taken along line A-A' of FIG. 17A.
본 발명의 바람직한 제2실시예에 따른 커패시터(100)는, 격자형 제1전극(200), 제1전극(200)의 표면상에 형성된 유전체(300) 및 유전체(300)의 표면상에 형성된 제2전극(400)를 포함한다. 제2실시예에 따른 커패시터(100)는, 제1실시예에 따른 커패시터(100)와는 달리, 격자방(240)의 하면을 전극으로 이용한다는 점에서 차이가 있다. The capacitor 100 according to the second preferred embodiment of the present invention includes a grid-type first electrode 200 , a dielectric 300 formed on the surface of the first electrode 200 , and a dielectric 300 formed on the surface of the dielectric 300 . A second electrode 400 is included. The capacitor 100 according to the second embodiment is different from the capacitor 100 according to the first embodiment in that the lower surface of the lattice room 240 is used as an electrode.
격자형 제1전극(200)은, 교차 전극부(210)와 하부 공통 전극부(230)를 포함한다. 교차 전극부(210)는 복수개의 제1-1전극(211)과 복수개의 제1-2전극(213)이 서로 교차하여 격자방(240)을 형성하면서 구비된다. The grid-type first electrode 200 includes a cross electrode part 210 and a lower common electrode part 230 . The cross electrode part 210 is provided while a plurality of first-first electrodes 211 and a plurality of first-second electrodes 213 cross each other to form a lattice room 240 .
하부 공통 전극부(230)는 교차 전극부(210)의 하면에 구비된다. 인접하는 제1-1전극(211)들과 인접하는 제1-2전극(213)들 사이에 형성되는 격자방(240)은 하부 공통 전극부(230)에 의해 그 하부가 막혀있는 형태의 구조가 된다. The lower common electrode part 230 is provided on the lower surface of the cross electrode part 210 . The lattice room 240 formed between the adjacent first-first electrodes 211 and the adjacent first-second electrodes 213 has a structure in which the lower part is blocked by the lower common electrode part 230 . becomes
교차 전극부(210)와 하부 공통 전극부(230)는 도전성 금속으로 형성되며, 은(Ag), 니켈(Ni), 구리(Cu), 주석(Sn), 산화인듐(ITO), 팔라듐(Pd) 또는 이들의 합금일 수 있으며 본 발명이 이에 한정되는 것은 아니다. The cross electrode part 210 and the lower common electrode part 230 are formed of a conductive metal, and include silver (Ag), nickel (Ni), copper (Cu), tin (Sn), indium oxide (ITO), and palladium (Pd). ) or an alloy thereof, and the present invention is not limited thereto.
유전체(300)는 교차 전극부(210)의 표면을 전체적으로 감싸면서 형성된다. 또한 유전체(300)는 하부 공통 전극부(220)의 상부 표면에도 형성된다. The dielectric 300 is formed while entirely surrounding the surface of the cross electrode part 210 . In addition, the dielectric 300 is also formed on the upper surface of the lower common electrode part 220 .
제2전극(400)은 유전체(300)가 형성된 영역에서 유전체(300)의 표면 상에 형성된다. The second electrode 400 is formed on the surface of the dielectric 300 in the region where the dielectric 300 is formed.
이하 도 18 내지 도 23을 참조하여, 본 발명의 바람직한 제2실시예에 따른 커패시터(100)의 제조방법에 대해 설명한다. Hereinafter, a method of manufacturing the capacitor 100 according to a second preferred embodiment of the present invention will be described with reference to FIGS. 18 to 23 .
도 18은 하부에 시드층(20)이 구비된 양극산화막(10)을 도시한 도면으로서, 도 18a는 평면도이고 도 18b는 도 18a의 A-A'단면도이다. 18 is a view showing an anodized film 10 having a seed layer 20 thereon. FIG. 18A is a plan view and FIG. 18B is a cross-sectional view taken along line A-A' of FIG. 18A.
도 18을 참조하면, 먼저 양극산화막(10)을 준비하고 양극산화막(10)의 하면에는 시드층(20)을 구비한다. 시드층(20)은 구리(Cu) 재질일 수 있다. 여기서의 시드층(20)은 하부 공통 전극부(230)를 구성할 수 있다. 물론 이에 한정되는 것은 아니고 시드층(20)은 후술하는 전기 도금 이후에 제거된 후 시드층(20)이 있던 영역에 금속층을 증착하여 해당 금속층이 하부 공통 전극부(230)를 구성하도록 할 수도 있다. Referring to FIG. 18 , an anodization film 10 is prepared first, and a seed layer 20 is provided on a lower surface of the anodization film 10 . The seed layer 20 may be made of copper (Cu). Here, the seed layer 20 may constitute the lower common electrode part 230 . Of course, the present invention is not limited thereto, and after the seed layer 20 is removed after electroplating, which will be described later, a metal layer may be deposited on the region where the seed layer 20 was, so that the metal layer may constitute the lower common electrode unit 230 . .
도 19는 개구부(15)가 형성된 양극산화막(10)을 도시한 도면으로서, 도 19a는 평면도이고 도 19b는 도 19a의 A-A'단면도이다.19 is a view showing the anodized film 10 having an opening 15 formed therein. FIG. 19A is a plan view and FIG. 19B is a cross-sectional view taken along line A-A' of FIG. 19A.
도 19를 참조하면, 양극산화막(10)에 개구부(15)를 형성한다. 개구부(15)는 양극산화막(10)을 에칭하여 형성될 수 있다. 이를 위해 양극산화막(10)의 상면에 포토 레지스트를 구비하고 이를 패터닝한 다음, 패터닝되어 오픈된 영역의 양극산화막(10)이 에칭 용액과 반응하여 개구부(15)가 형성된다. 구체적으로 설명하면, 개구부(15)을 형성하기 전의 양극산화막(10)의 상면에 감광성 재료를 구비한 다음 노광 및 현상 공정이 수행될 수 있다. 감광성 재료는 노광 및 현상 공정에 의해 오픈영역을 형성하면서 적어도 일부가 패터닝되어 제거될 수 있다. 양극산화막(10)은 패터닝 과정에 의해 감광성 재료가 제거된 오픈영역을 통해 에칭 공정이 수행되어 그 일부가 제거되어 개구부(15)를 형성하게 된다. 양극산화막(10)을 에칭 용액으로 습식 에칭함으로써 수직한 내벽을 가지는 개구부(15)가 구비된다.Referring to FIG. 19 , an opening 15 is formed in the anodization layer 10 . The opening 15 may be formed by etching the anodization layer 10 . To this end, a photoresist is provided on the upper surface of the anodization film 10 and patterned, and then the anodization film 10 in the patterned and open area reacts with the etching solution to form the opening 15 . Specifically, an exposure and development process may be performed after the photosensitive material is provided on the upper surface of the anodized film 10 before the opening 15 is formed. At least a portion of the photosensitive material may be patterned and removed while forming an open area by an exposure and development process. The anodic oxide layer 10 is etched through the open region from which the photosensitive material has been removed by the patterning process, and a part thereof is removed to form the opening 15 . An opening 15 having a vertical inner wall is provided by wet etching the anodization film 10 with an etching solution.
도 20은 양극산화막(10)의 개구부(15) 내부에 도전성 금속(16)을 충진한 것을 도시한 도면으로서, 도 20a는 평면도이고 도 20b는 도 20a의 A-A'단면도이다.FIG. 20 is a view illustrating that the conductive metal 16 is filled in the opening 15 of the anodized film 10. FIG. 20A is a plan view, and FIG. 20B is a cross-sectional view taken along line A-A' of FIG. 20A.
도 20을 참조하면, 개구부(15)의 내부에 도전성 금속(16)을 충진한다. 개구부(15)의 내부에 충진되는 도전성 금속(16)은 도금 방법에 의해 형성될 수 있다. 양극산화막(10)의 하면에 구비된 시드층(20)를 이용하여 전해 도금함으로써 개구부(15)의 내부에 도전성 금속(16)을 충진할 수 있다. 다만 이러한 제조 방법으로만 한정되는 것은 아니고 증착 방법을 이용하는 것도 가능하다. 도금 공정이 완료되면 평탄화 공정을 수행한다. 화학적 기계적 연마(CMP) 공정을 통해 양극산화막(10)의 상면으로 돌출된 도전성 금속(16)을 제거하면서 평탄화시킨다.Referring to FIG. 20 , the conductive metal 16 is filled in the opening 15 . The conductive metal 16 filled in the opening 15 may be formed by a plating method. The conductive metal 16 may be filled in the opening 15 by electrolytic plating using the seed layer 20 provided on the lower surface of the anodized layer 10 . However, it is not limited only to this manufacturing method, and it is also possible to use a deposition method. When the plating process is completed, a planarization process is performed. The conductive metal 16 protruding from the top surface of the anodic oxide layer 10 is removed and planarized through a chemical mechanical polishing (CMP) process.
개구부(15)에 충진된 도전성 금속(16)은 은(Ag), 니켈(Ni), 구리(Cu), 주석(Sn), 산화인듐(ITO), 팔라듐(Pd) 또는 이들의 합금일 수 있으며 본 발명이 이에 한정되는 것은 아니다. The conductive metal 16 filled in the opening 15 may be silver (Ag), nickel (Ni), copper (Cu), tin (Sn), indium oxide (ITO), palladium (Pd), or an alloy thereof. The present invention is not limited thereto.
개구부(15)에 충진된 도전성 금속(16)은 격자형 제1전극(200)이 된다. 격자형 제1전극(200)은, 교차 전극부(210)와 측부 공통 전극부(220)를 포함한다. 교차 전극부(210)는 복수개의 제1-1전극(211)과 복수개의 제1-2전극(213)이 서로 교차하여 격자방(240)을 형성하면서 구비된다. 격자방(240)은 상부는 개구되고 하부는 밀폐는 형태로 구성된다. The conductive metal 16 filled in the opening 15 becomes the lattice type first electrode 200 . The grid-type first electrode 200 includes a cross electrode part 210 and a side common electrode part 220 . The cross electrode part 210 is provided while a plurality of first-first electrodes 211 and a plurality of first-second electrodes 213 cross each other to form a lattice room 240 . The lattice room 240 has an open upper portion and a closed lower portion.
도 21은 격자형 제1전극(200)의 측부 공통 전극부(220)의 내측에 존재하는 양극산화막(10)을 제거한 것을 도시한 도면으로서, 도 21a는 평면도이고 도 21b는 도 21a의 A-A'단면도이다.21 is a view illustrating the removal of the anodization film 10 present inside the side common electrode part 220 of the lattice-type first electrode 200. FIG. 21A is a plan view, and FIG. 21B is a view A- of FIG. 21A. A' is a cross-sectional view.
도 21을 참조하면, 격자형 제1전극(200)의 측부 공통 전극부(220)의 내측에 존재하는 양극산화막(10)을 제거한다. 이를 위해 도전성 금속(16)이 충진된 양극산화막(10)의 상면에 포토 레지스트를 구비하고 이를 패터닝한 다음, 패터닝되어 오픈된 영역의 양극산화막(10)이 에칭 용액과 반응하여 측부 공통 전극부(220)의 내측의 양극산화막(10)이 제거된다. 그 결과 격자형 제1전극(200)의 표면이 외부로 노출되게 된다.Referring to FIG. 21 , the anodic oxide layer 10 present inside the side common electrode part 220 of the lattice-type first electrode 200 is removed. To this end, a photoresist is provided on the upper surface of the anodized film 10 filled with the conductive metal 16 and patterned, and then the anodized film 10 in the patterned and open area reacts with the etching solution to react with the side common electrode part ( The anodization film 10 inside the 220 is removed. As a result, the surface of the grid-type first electrode 200 is exposed to the outside.
도 22는 노출된 격자형 제1전극(200)의 표면에 유전체(300)를 형성한 것을 도시한 도면으로서, 도 22a는 평면도이고 도 22b는 도 22a의 A-A'단면도이다.22 is a view illustrating the formation of the dielectric 300 on the exposed surface of the lattice-type first electrode 200. FIG. 22A is a plan view and FIG. 22B is a cross-sectional view taken along line A-A' of FIG. 22A.
도 22를 참조하면, 노출된 격자형 제1전극(200)의 표면에 유전체(300)를 형성한다. 유전체(300)는 노출된 교차 전극부(210), 측부 공통 전극부(220) 및 하부 공통 전극부(230)의 표면 상에 형성된다. 유전체(300)가 하부 공통 전극부(230)의 표면 상에도 형성된다는 점에서 제1실시예의 유전체(300) 형성 영역과 차이가 있다.Referring to FIG. 22 , the dielectric 300 is formed on the exposed surface of the lattice-type first electrode 200 . The dielectric 300 is formed on the surfaces of the exposed cross electrode part 210 , the side common electrode part 220 , and the lower common electrode part 230 . It is different from the dielectric 300 formation region of the first embodiment in that the dielectric 300 is also formed on the surface of the lower common electrode part 230 .
도 23은 유전체(300)의 표면상에는 도전성 금속(17)을 형성한 것을 도시한 도면으로서, 도 23a는 평면도이고 도 23b는 도 23a의 A-A'단면도이다.23 is a view showing the formation of a conductive metal 17 on the surface of the dielectric 300. FIG. 23A is a plan view and FIG. 23B is a cross-sectional view taken along line A-A' of FIG. 23A.
도 23을 참조하면, 유전체(300)의 표면상에는 도전성 금속(17)을 형성한다. 도전성 금속(17)은 제2전극(400)이 형성된다. 도전성 금속(17)은 교차 전극부(210)상에 형성된 유전체(300)의 표면에 전체적으로 형성된다. 또한, 도전성 금속(17)은 측부 공통 전극부(220)의 표면상에 형성된 유전체(300)의 표면에도 형성되며, 하부 공통 전극부(230)의 표면상에 형성된 유전체(300)의 표면에도 형성된다.Referring to FIG. 23 , a conductive metal 17 is formed on the surface of the dielectric 300 . The second electrode 400 is formed on the conductive metal 17 . The conductive metal 17 is entirely formed on the surface of the dielectric 300 formed on the cross electrode portion 210 . In addition, the conductive metal 17 is formed on the surface of the dielectric 300 formed on the surface of the side common electrode part 220 and also on the surface of the dielectric 300 formed on the surface of the lower common electrode part 230 . do.
이후 양극산화막(10)을 제거하여 본 발명의 바람직한 제2실시예에 따른 커패시터(100)를 완성하게 된다. 한편 이와는 다르게 양극산화막(10)은 제거되지 않을 수 있으며, 따라서 본 발명의 바람직한 제2실시예에 따른 커패시터(100)는 측부 공통 전극부(220)의 외측에 양극산화막(10)이 구비된 구조를 포함한다. 이 경우 측부 공통 전극부(220)의 외측에 구비된 양극산화막(10)은 측부 공통 전극부(220)의 외측면을 절연시키는 기능을 수행할 수 있다.Thereafter, the anodization film 10 is removed to complete the capacitor 100 according to the second preferred embodiment of the present invention. On the other hand, unlike this, the anodization film 10 may not be removed. Therefore, the capacitor 100 according to the second preferred embodiment of the present invention has a structure in which the anodization film 10 is provided on the outside of the side common electrode part 220 . includes In this case, the anodization layer 10 provided on the outside of the side common electrode part 220 may insulate the outer surface of the side common electrode part 220 .
도 24는 본 발명의 바람직한 제2실시예의 변형례를 도시한 도면이다. 도 24를 참조하면, 기본 구성은 앞서 설명한 제2실시예의 구조와 동일하지만, 제2실시예의 변형례는 제2전극(400)이 격자방(240)의 내부 전체를 채우면서 형성되는 구성이라는 점에서 격자방(240)의 내부 전체를 채우지 않는 제2실시예의 구조와 차이가 있다. 24 is a view showing a modified example of the second preferred embodiment of the present invention. Referring to FIG. 24 , the basic configuration is the same as that of the second embodiment described above, but a modified example of the second embodiment is that the second electrode 400 is formed while filling the entire interior of the grid room 240 . There is a difference from the structure of the second embodiment in which the entire interior of the lattice room 240 is not filled.
이상과 같이, 본 발명의 바람직한 실시예에 따른 커패시터(100)는 적어도 하나의 전극이 3차원의 격자형 모양을 가진다. 격자형 전극은 소정의 높이를 가지는 복수개의 전극판들이 서로 교차하여 격자방을 형성하는 구조를 포함하며 이를 통해 전극의 표면적을 3차원적으로 확장하게 된다. 격자형 전극의 표면에는 유전체(300)와 또 다른 전극이 순차적으로 형성됨으로써 커패시터(100)의 정전용량을 향상시킬 수 있게 된다. As described above, in the capacitor 100 according to the preferred embodiment of the present invention, at least one electrode has a three-dimensional grid shape. The grid-type electrode includes a structure in which a plurality of electrode plates having a predetermined height cross each other to form a grid room, thereby extending the surface area of the electrode three-dimensionally. Since the dielectric 300 and another electrode are sequentially formed on the surface of the grid electrode, the capacitance of the capacitor 100 can be improved.
앞선 설명에서는 본 발명의 바람직한 실시예로서 제1, 2실시예만을 예로서 설명하고 제1,2실시예의 구성들을 조합하는 다른 실시예 내지는 변형례의 구성은 편의상 설명을 생략하였으나, 이러한 실시예 내지는 변형례 역시 본 발명의 바람직한 실시예가 될 수 있음은 분명하다.In the preceding description, only the first and second embodiments as preferred embodiments of the present invention are described as examples, and descriptions of the configurations of other embodiments or modifications combining the configurations of the first and second embodiments are omitted for convenience, but these embodiments or It is clear that modifications may also be preferred embodiments of the present invention.
전술한 바와 같이, 본 발명의 바람직한 실시 예를 참조하여 설명하였지만, 해당 기술분야의 통상의 기술자는 하기의 특허 청구범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 또는 변형하여 실시할 수 있다.As described above, although described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify the present invention within the scope without departing from the spirit and scope of the present invention described in the claims below. Or it can be carried out by modification.
[부호의 설명][Explanation of code]
100: 커패시터100: capacitor
200: 격자형 제1전극200: lattice type first electrode
300: 유전체 300: dielectric
400: 제2전극400: second electrode

Claims (16)

  1. 격자형 제1전극;a lattice type first electrode;
    상기 제1전극의 표면상에 형성된 유전체;및a dielectric formed on the surface of the first electrode; and
    상기 유전체의 표면상에 형성된 제2전극;을 포함하는, 커패시터.A capacitor comprising a; a second electrode formed on the surface of the dielectric.
  2. 제1항에 있어서,According to claim 1,
    상기 격자형 제1전극은,The lattice type first electrode,
    제1-1전극과 상기 제1-1전극과 교차되는 제1-2전극을 포함하는 교차 전극부; 및an intersecting electrode unit including a 1-1 electrode and a 1-2 electrode intersecting the 1-1 electrode; and
    상기 교차 전극부의 외측에 구비되는 측부 공통 전극부를 포함하는, 커패시터.and a side common electrode part provided outside the cross electrode part.
  3. 제2항에 있어서,3. The method of claim 2,
    상기 측부 공통 전극부는,The side common electrode part,
    복수개의 상기 제1-1전극과 연결되는 제1-1공통 전극부; 및a 1-1 common electrode unit connected to the plurality of 1-1 electrodes; and
    복수개의 상기 제1-2전극과 연결되는 제1-2공통 전극부를 포함하는, 커패시터.A capacitor comprising: a first-second common electrode portion connected to the plurality of first-second electrodes.
  4. 제2항에 있어서,3. The method of claim 2,
    인접하는 제1-1전극들과 인접하는 제1-2전극들 사이에 형성되는 관통부를 포함하는, 커패시터.A capacitor comprising a through portion formed between adjacent first-first electrodes and adjacent first-second electrodes.
  5. 제1항에 있어서,According to claim 1,
    상기 격자형 제1전극은,The lattice type first electrode,
    제1-1전극과 상기 제1-1전극과 교차되는 제1-2전극을 포함하는 교차 전극부; 및an intersecting electrode unit including a 1-1 electrode and a 1-2 electrode intersecting the 1-1 electrode; and
    상기 교차 전극부의 하면에 구비되는 하부 공통 전극부를 포함하는, 커패시터.and a lower common electrode part provided on a lower surface of the cross electrode part.
  6. 제5항에 있어서,6. The method of claim 5,
    상기 유전체는 상기 하부 공통 전극부의 표면상에도 형성되는, 커패시터.and the dielectric is also formed on a surface of the lower common electrode part.
  7. 서로 교차하는 복수개의 개구부가 구비된 기판에서 상기 개구부에 금속을 충진하여 격자형 제1전극을 형성하는 단계;forming a lattice-type first electrode by filling the openings with a metal in a substrate having a plurality of openings crossing each other;
    상기 기판의 적어도 일부를 제거하여 상기 격자형 제1전극의 표면을 노출하는 단계;removing at least a portion of the substrate to expose a surface of the lattice-type first electrode;
    상기 노출된 격자형 제1전극의 표면에 유전체를 형성하는 단계; 및forming a dielectric on the exposed surface of the lattice-type first electrode; and
    상기 유전체 상에 제2전극을 형성하는 단계;를 포함하는 커패시터의 제조방법.and forming a second electrode on the dielectric.
  8. 제7항에 있어서,8. The method of claim 7,
    상기 기판은 양극산화막 재질로 구성되는 양극산화막 기판인, 커패시터의 제조방법.The method for manufacturing a capacitor, wherein the substrate is an anodized film substrate composed of an anodized film material.
  9. 복수개의 제1-1전극과 복수개의 제1-2전극이 서로 교차하여 격자방을 형성하면서 구비되는 교차 전극부를 포함하는 제1전극;a first electrode including a cross electrode part provided while a plurality of first-1-1 electrodes and a plurality of first-second electrodes cross each other to form a lattice room;
    상기 교차 전극부 표면상에 형성되는 유전체; 및a dielectric formed on a surface of the cross electrode part; and
    상기 유전체상에 형성되는 제2전극;을 포함하는, 커패시터. A capacitor comprising a; a second electrode formed on the dielectric.
  10. 제9항에 있어서,10. The method of claim 9,
    상기 제1전극의 격자방 측면에 형성된 요철부를 포함하는, 커패시터.and a concave-convex portion formed on a lattice side of the first electrode.
  11. 제9항에 있어서,10. The method of claim 9,
    상기 유전체는 상기 교차 전극부의 표면을 전체적으로 감싸면서 형성되고, 상기 제2전극은 상기 교차 전극부의 표면에 형성된 유전체의 표면을 전체적으로 감싸면서 형성되는, 커패시터.The dielectric is formed while entirely surrounding the surface of the cross electrode, and the second electrode is formed while completely surrounding the surface of the dielectric formed on the surface of the cross electrode.
  12. 격자형 제1전극; 상기 제1전극의 표면상에 형성된 유전체;및 상기 유전체의 표면상에 형성된 제2전극;을 포함하는 단위 커패시터를 포함하되,a lattice type first electrode; A unit capacitor comprising: a dielectric formed on the surface of the first electrode; and a second electrode formed on the surface of the dielectric;
    상기 단위 커패시터들이 서로 직렬연결되는, 커패시터.A capacitor in which the unit capacitors are connected in series with each other.
  13. 격자형 제1전극; 상기 제1전극의 표면상에 형성된 유전체;및 상기 유전체의 표면상에 형성된 제2전극;을 포함하는 단위 커패시터를 포함하되,a lattice type first electrode; A unit capacitor comprising: a dielectric formed on the surface of the first electrode; and a second electrode formed on the surface of the dielectric;
    상기 단위 커패시터들이 서로 병렬연결되는, 커패시터.A capacitor in which the unit capacitors are connected in parallel to each other.
  14. 격자형 제1전극; 상기 제1전극의 표면상에 형성된 유전체;및 상기 유전체의 표면상에 형성된 제2전극;을 포함하는 단위 커패시터를 포함하되,a lattice type first electrode; A unit capacitor comprising: a dielectric formed on the surface of the first electrode; and a second electrode formed on the surface of the dielectric;
    상기 단위 커패시터들이 서로 직렬 및 병렬연결되는, 커패시터.A capacitor in which the unit capacitors are connected in series and parallel to each other.
  15. 복수개의 제1-1전극과 복수개의 제1-2전극이 서로 교차하여 격자방을 형성하면서 구비되는 교차 전극부; 및a plurality of first-first electrodes and a plurality of first-second electrodes intersecting each other to form a lattice room; and
    상기 교차 전극부의 외측에 구비되는 측부 공통 전극부;를 포함하는, 커패시터용 전극.and a side common electrode part provided outside the cross electrode part.
  16. 복수개의 제1-1전극과 복수개의 제1-2전극이 서로 교차하여 격자방을 형성하면서 구비되는 교차 전극부; 및a plurality of first-first electrodes and a plurality of first-second electrodes intersecting each other to form a lattice room; and
    상기 교차 전극부의 하면에 구비되는 하부 공통 전극부;를 포함하는, 커패시터용 전극.and a lower common electrode part provided on a lower surface of the cross electrode part.
PCT/KR2022/001525 2021-02-01 2022-01-27 Capacitor, manufacturing method therefor, and capacitor electrode WO2022164240A1 (en)

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