KR20110071416A - Metal-insulator-metal capacitor manufacturing method for semiconductor device - Google Patents

Metal-insulator-metal capacitor manufacturing method for semiconductor device Download PDF

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KR20110071416A
KR20110071416A KR1020090127980A KR20090127980A KR20110071416A KR 20110071416 A KR20110071416 A KR 20110071416A KR 1020090127980 A KR1020090127980 A KR 1020090127980A KR 20090127980 A KR20090127980 A KR 20090127980A KR 20110071416 A KR20110071416 A KR 20110071416A
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dielectric film
film
layer
dielectric
semiconductor device
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KR1020090127980A
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Korean (ko)
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김형윤
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주식회사 동부하이텍
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A metal-insulator-metal capacitor manufacturing method for a semiconductor device is provided to prevent the increase of a leakage current due to the thickness of a dielectric layer by using an insulating layer as a SiN-SiON-SiN multi layer. CONSTITUTION: In a metal-insulator-metal capacitor manufacturing method for a semiconductor device, a bottom conductive layer is laminated on a semiconductor substrate. A first dielectric layer(41), a second dielectric layer(42), and a third dielectric layer(43) are successively laminated on the bottom conductive layer. The top conductive layer and an insulating protection layer are laminated on the third dielectric layer. The photograph / etching process is performed to pattern the top electrode and first to third dielectric layer. The photograph / etching process is performed after coating photoresist on the insulating protection layer to pattern the bottom electrode.

Description

반도체 소자의 ＭＩＭ 커패시터 형성방법{Metal-insulator-metal capacitor manufacturing method for semiconductor device}MIM capacitor formation method of a semiconductor device {Metal-insulator-metal capacitor manufacturing method for semiconductor device}

본 발명은 반도체 소자의 MIM 커패시터 형성방법에 관한 것으로, 더욱 상세하게는 유전막의 두께가 감소하더라도 누설전류가 증가하거나 항복전압이 감소하지 않는 반도체 소자의 MIM 커패시터 형성방법에 관한 것이다.The present invention relates to a method of forming a MIM capacitor of a semiconductor device, and more particularly, to a method of forming a MIM capacitor of a semiconductor device in which leakage current does not increase or breakdown voltage does not decrease even when the thickness of the dielectric film is reduced.

일반적으로 안정적인 특성을 요구하는 CMOS 로직 소자에 적용되는 아날로그 커패시터(analog capacitor)는 PIP(poly-insulator-poly), PIM(poly-insulator-metal), MIP(metal-insulator-poly), MIM(metal-insulator-metal, 이하 'MIM'이라 한다) 등 다양한 구조로 형성되며, A/D 컨버터나 스위칭 커패시터 필터 분야의 핵심 기술로서 응용되고 있다. In general, analog capacitors applied to CMOS logic devices requiring stable characteristics include poly-insulator-poly (PIP), poly-insulator-metal (PIM), metal-insulator-poly (MIP), and metal (IMM). It is formed in various structures such as -insulator-metal, hereinafter referred to as 'MIM', and is applied as a core technology in the field of A / D converter or switching capacitor filter.

도 1은 종래의 MIM 커패시터의 단면도이다.1 is a cross-sectional view of a conventional MIM capacitor.

도 1을 참조하면 MIM 커패시터는 소정의 하부 구조물, 즉 반도체 기본 소자(미도시) 및 금속배선(미도시)이 형성되고 절연층(20)이 증착된 반도체 기판(10) 상에 하부 전극(30), 유전막(40a), 상부 전극(50)이 순차로 증착되어 있다.Referring to FIG. 1, a MIM capacitor includes a lower electrode 30 on a semiconductor substrate 10 having a predetermined lower structure, that is, a semiconductor basic device (not shown) and a metal wiring (not shown), and an insulating layer 20 deposited thereon. ), The dielectric film 40a and the upper electrode 50 are sequentially deposited.

상기 하부 전극(30)은 일반 금속 배선층과 동일한 막으로 사용한다. 즉, 제1 Ti/TiN 층, Al-Cu층, 제2 Ti/TiN 층을 순차 적층하여 형성되는 복합막을 사용한다. 상기 유전막(40a)은 통상적으로 0.1 ㎛ 이하의 단일막으로서, 질화실리콘막(SiN)이나 산질화실리콘막(SiON)으로 이루어진다. 상기 상부 전극(50)은 금속층이며, 후속되는 사진공정이 쉬워지도록 하기 위하여 통상적으로 0.2㎛ 이하의 Ti/TiN의 복합막으로 이루어진다.The lower electrode 30 is used as the same film as the general metal wiring layer. That is, a composite film formed by sequentially stacking a first Ti / TiN layer, an Al-Cu layer, and a second Ti / TiN layer is used. The dielectric film 40a is typically a single film having a thickness of 0.1 μm or less, and includes a silicon nitride film (SiN) or a silicon oxynitride film (SiON). The upper electrode 50 is a metal layer, and is usually made of a composite film of Ti / TiN of 0.2 μm or less in order to facilitate a subsequent photographic process.

커패시터의 정전용량(C)은 The capacitance of the capacitor (C)

Figure 112009078918770-PAT00001
Figure 112009078918770-PAT00001

로 구해지며, 여기서 ε은 유전율, A는 단면적, 그리고 T는 유전막(40a)의 두께이다. 따라서 정전용량을 증가시키기 위해서는 단면적(A) 또는 ε(유전율)을 증가시키거나 유전막(40a)의 두께(T)를 감소시켜야 한다.Where ε is the permittivity, A is the cross-sectional area, and T is the thickness of the dielectric film 40a. Therefore, in order to increase the capacitance, it is necessary to increase the cross-sectional area A or ε (dielectric constant) or decrease the thickness T of the dielectric film 40a.

그러나, 반도체가 고집적화 될수록 MIM 커패시터의 단면적(A)이 감소하게 되므로 감소한 단면적(A)으로 동일한 정전용량을 구현하기 위해서는 유전막(40a)의 두께(T)를 감소시키거나 유전율(ε)이 큰 새로운 물질을 증착하여야 한다.However, as the semiconductor becomes more integrated, the cross-sectional area (A) of the MIM capacitor decreases, so in order to achieve the same capacitance with the reduced cross-sectional area (A), the thickness T of the dielectric film 40a or the new dielectric constant (ε) is large. The material must be deposited.

정전용량(C)은 증가시키기 위하여 유전막(40a)의 두께를 감소시키는 경우에는 또 다른 문제가 발생한다. 즉, 유전막(40a)의 두께 감소로 인한 MIM 커패시터에서의 누설 전류가 증가하거나 항복전압(breakdown voltage)이 감소하는 문제가 발생한다.Another problem arises when the thickness of the dielectric film 40a is reduced to increase the capacitance C. That is, a problem arises in that the leakage current in the MIM capacitor increases or the breakdown voltage decreases due to the decrease in the thickness of the dielectric film 40a.

본 발명은 상술한 제반 문제점을 해결하고자 안출된 것으로, 유전막의 두께가 감소하더라도 누설전류가 증가하거나 항복전압이 감소하지 않는 반도체 소자의 MIM 커패시터 형성방법을 제공함에 그 목적이 있다.The present invention has been made to solve the above-mentioned problems, and an object thereof is to provide a method of forming a MIM capacitor of a semiconductor device in which a leakage current does not increase or a breakdown voltage does not decrease even when the thickness of the dielectric film is reduced.

상술한 바와 같은 목적을 구현하기 위한 본 발명의 반도체 소자의 MIM 커패시터 형성방법은, 반도체 기본소자 및 금속배선이 형성되고 절연층이 증착된 반도체 기판상에 하부 도전층을 적층하는 제1단계; 상기 하부 도전층 위에 제1유전막, 제2유전막 및 제3유전막을 순차 적층하는 제2단계; 상기 제3유전막 위에 상부 도전층, 절연보호막을 순차 적층하는 제3단계; 상부 전극 형성을 위하여 상기 절연보호막 위에 포토리지스트를 도포한 후, 사진/식각 공정을 진행하여 상부 전극 및 상기 제1유전막 내지 제3유전막을 패터닝하는 제4단계; 하부 전극 형성을 위하여 상기 절연보호막 위에 포토리지스트를 도포한 후 사진/식각 공정을 진행하여 하부 전극을 패터닝하는 제5단계; 및 절연층을 증착하고 평탄화한 후 비아 콘택 및 금속배선 공정을 진행하는 제6단계를 포함하여 이루어진 것을 특징으로 한다.A method of forming a MIM capacitor of a semiconductor device of the present invention for realizing the above object includes a first step of stacking a lower conductive layer on a semiconductor substrate on which a semiconductor basic device and a metal wiring are formed and an insulating layer is deposited; A second step of sequentially stacking a first dielectric film, a second dielectric film, and a third dielectric film on the lower conductive layer; A third step of sequentially stacking an upper conductive layer and an insulating protective film on the third dielectric film; Applying a photoresist on the insulating protective film to form an upper electrode, and then performing a photo / etch process to pattern the upper electrode and the first to third dielectric layers; A fifth step of patterning the lower electrode by applying a photoresist on the insulating protective film to form a lower electrode and then performing a photo / etch process; And a sixth step of performing the via contact and the metallization process after depositing and planarizing the insulating layer.

또한, 상기 제1유전막, 제2유전막 및 제3유전막은 각각 SiN막, SiON막 및 SiN막으로 이루어진 것을 특징으로 한다.The first dielectric film, the second dielectric film, and the third dielectric film may be formed of a SiN film, a SiON film, and a SiN film, respectively.

또한, 상기 제2유전막은 상기 제1유전막의 O2 또는 N2O 플라즈마 처리에 의 해 형성되는 것을 특징으로 한다.The second dielectric film may be formed by O 2 or N 2 O plasma treatment of the first dielectric film.

또한, 상기 제1유전막 내지 제3유전막의 적층은 인시츄(in-situ)로 실시되는 것을 특징으로 한다.In addition, the first to third dielectric film is laminated in the in-situ (in-situ) is characterized in that.

또한, 상기 O2 또는 N2O 플라즈마 처리는 인시츄(in-situ)로 실시되는 것을 특징으로 한다.In addition, the O 2 or N 2 O plasma treatment is characterized in that it is carried out in-situ (in-situ).

본 발명에 따른 반도체 소자의 MIM 커패시터 형성방법에 의하면 절연막으로 SiN 단일막을 사용하지 않고 SiN-SiON-SiN 다중막을 사용함으로써 유전막의 두께가 감소하더라도 누설전류가 증가하거나 항복전압이 감소하지 않는 안정한 MIM 커패시터가 형성된다.According to the method for forming a MIM capacitor of a semiconductor device according to the present invention, by using a SiN-SiON-SiN multilayer instead of using a SiN single layer as an insulating layer, a stable MIM capacitor does not increase leakage current or decrease breakdown voltage even if the thickness of the dielectric film is reduced. Is formed.

이하 첨부 도면을 참조하여 본 발명의 바람직한 실시예에 대한 구성 및 작용을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the preferred embodiment of the present invention.

본 발명의 바람직한 실시예에 따른 MIM 커패시터 형성방법은 제1단계 내지 제6단계를 포함하여 이루어진다. Method for forming a MIM capacitor according to a preferred embodiment of the present invention comprises a first step to sixth step.

제1단계는 반도체 기본 소자 및 배선이 형성되고 절연층이 증착된 반도체 기판상에 하부 도전층(30)을 적층하는 단계이다. 여기서 상기 하부 도전층(30)의 구성은 종래의 기술과 동일하므로 설명의 중복을 피하기 위하여 상세한 설명은 생략한다.The first step is to deposit the lower conductive layer 30 on the semiconductor substrate on which the semiconductor basic element and the wiring are formed and the insulating layer is deposited. In this case, since the configuration of the lower conductive layer 30 is the same as in the related art, a detailed description thereof will be omitted in order to avoid duplication of description.

제2단계는 상기 하부 도전층 위에 제1유전막(41), 제2유전막(42) 및 제3유전막(43)을 적층하는 단계이다. In the second step, the first dielectric layer 41, the second dielectric layer 42, and the third dielectric layer 43 are stacked on the lower conductive layer.

종래의 유전막(도 1, 40a)은 통상적으로 0.1㎛ 이하의 단일막으로서, SiN 막이나 SiON 막으로 이루어진다. 본 발명에 따른 유전막(40b)은 유전막의 두께감소에 따른 누설전류의 증가 및 항복전압의 감소를 피하기 위하여 유전막을 다중막으로 형성된다. Conventional dielectric films (FIGS. 1 and 40A) are typically a single film of 0.1 mu m or less, and are made of a SiN film or a SiON film. The dielectric film 40b according to the present invention is formed of multiple layers of dielectric films in order to avoid an increase in leakage current and a decrease in breakdown voltage due to a decrease in the thickness of the dielectric film.

도 2a에 도시된 바와 같이, 하부 도전층(미도시) 위에 제1유전막(41)을 적층한다. 제1유전막(41)은 SiN 막으로 구성하는 것이 바람직하다.As shown in FIG. 2A, a first dielectric layer 41 is stacked on a lower conductive layer (not shown). It is preferable that the first dielectric film 41 is made of a SiN film.

다음으로, 상기 제1유전막(41) 위에 제2유전막(42)을 적층한다. 제2유전막(42)은 SiON 막으로 구성하는 것이 바람직하다. 통상적으로 SiON 막은 SiN 막보다 항복전압이 높기 때문이다. 제2유전막(42)을 별도로 적층하는 것도 가능하지만, 이미 적층되어 있는 제1유전막(41)을 이용하여 제2유전막(42)을 형성시킬 수도 있다.Next, a second dielectric film 42 is stacked on the first dielectric film 41. It is preferable that the second dielectric film 42 is made of a SiON film. This is because the SiON film usually has a higher breakdown voltage than the SiN film. Although the second dielectric film 42 can be laminated separately, the second dielectric film 42 can also be formed using the first dielectric film 41 already stacked.

도 2b에 도시된 바와 같이, SiN으로 이루어진 제1유전막(41)을 O2 또는 N2O 플라즈마 처리하면 상기 SiN 막의 상부에 SiON 막이 형성된다. 이때 형성되는 SiON 막의 두께는 30 ~ 50Å 정도가 바람직하다. 또한, 상기 제1유전막(41)의 O2 또는 N2O 플라즈마 처리는 인-시츄(in-situ)로 진행되는 것이 바람직하다.As shown in FIG. 2B, when the first dielectric film 41 made of SiN is subjected to O 2 or N 2 O plasma treatment, a SiON film is formed on the SiN film. At this time, the thickness of the SiON film formed is preferably about 30 ~ 50 Pa. In addition, the O 2 or N 2 O plasma treatment of the first dielectric layer 41 may be performed in-situ.

다음으로, 상기 제2유전막(42) 위에 제3유전막(43)을 적층한다. 제3유전막(43)은 상기 제1유전막(41)과 동일하게 SiN으로 구성하는 것이 바람직하다. 도 2c에 제1유전막(41), 제2유전막(42) 및 제3유전막(43)이 적층된 본 발명에 따른 유전막(40b)의 단면이 도시되어 있다. 또한, 상기 제1유전막 내지 제3유전막의 적층단계는 인-시츄(in-situ)로 진행되는 것이 바람직하다.Next, a third dielectric film 43 is stacked on the second dielectric film 42. It is preferable that the third dielectric film 43 is made of SiN in the same manner as the first dielectric film 41. 2C shows a cross section of the dielectric film 40b according to the present invention in which the first dielectric film 41, the second dielectric film 42, and the third dielectric film 43 are stacked. In addition, the stacking step of the first to third dielectric film is preferably carried out in-situ (in-situ).

제3단계는 상기 제3유전막 위에 상부 도전층(50), 절연보호막(100)을 순차로 적층하는 단계이며, 제4단계는 상부 전극 형성을 위하여 상기 절연보호막 위에 포토리지스트를 도포한 후, 사진/식각 공정을 진행하여 상부 전극(100) 및 상기 제1유전막 내지 제3유전막(40b)을 패터닝하는 단계이며, 제5단계는 하부 전극 형성을 위하여 상기 절연보호막 위에 포토리지스트를 도포한 후 사진/식각 공정을 진행하여 하부 전극(30)을 패터닝하는 단계이며, 마지막 단계인 제6단계는 절연층(70)을 증착하고 평탄화한 후 비아 콘택(80) 및 금속배선(90) 공정을 진행하는 단계이다.In the third step, the upper conductive layer 50 and the insulating protective film 100 are sequentially stacked on the third dielectric film. In the fourth step, after the photoresist is applied on the insulating protective film to form the upper electrode, After the photo / etching process, the upper electrode 100 and the first to third dielectric layers 40b are patterned. The fifth step is to apply photoresist on the insulating protective layer to form the lower electrode. The lower electrode 30 is patterned by performing a photo / etching process, and the final step, the sixth step, processes the via contact 80 and the metallization 90 after depositing and planarizing the insulating layer 70. It's a step.

상기 제3단계 내지 제6단계는 종래의 MIM 커패시터의 형성방법과 동일하므로 상세한 설명은 생략한다.Since the third to sixth steps are the same as the conventional method of forming the MIM capacitor, a detailed description thereof will be omitted.

본 발명은 상기 실시 예에 한정되지 않고 본 발명의 기술적 요지를 벗어나지 아니하는 범위 내에서 다양하게 수정·변형되어 실시될 수 있음은 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 있어서 자명한 것이다.It will be apparent to those skilled in the art that the present invention is not limited to the above embodiments and can be practiced in various ways without departing from the technical spirit of the present invention. will be.

도 1은 종래의 MIM 커패시터의 단면도,1 is a cross-sectional view of a conventional MIM capacitor,

도 2a ~ 도 2c는 본 발명에 따른 SiN-SiON-SiN 다중막으로 구성된 유전막의 형성방법을 나타내는 단면도이다.2A to 2C are cross-sectional views illustrating a method of forming a dielectric film composed of a SiN-SiON-SiN multilayer according to the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

10 : 반도체 기판 20, 70 : 절연층10: semiconductor substrate 20, 70: insulating layer

30 : 하부 도전층 40a, 40b : 유전막30: lower conductive layer 40a, 40b: dielectric film

50 : 상부 도전층 60 : 감광막50: upper conductive layer 60: photosensitive film

80 : 비아 콘택 90 : 금속배선80: via contact 90: metal wiring

100 : 절연보호막100: insulation protective film

Claims (5)

반도체 기본소자 및 금속배선이 형성되고 절연층이 증착된 반도체 기판상에 하부 도전층을 적층하는 제1단계;Stacking a lower conductive layer on a semiconductor substrate on which a semiconductor basic device and a metal wiring are formed and an insulating layer is deposited; 상기 하부 도전층 위에 제1유전막, 제2유전막 및 제3유전막을 순차 적층하는 제2단계; A second step of sequentially stacking a first dielectric film, a second dielectric film, and a third dielectric film on the lower conductive layer; 상기 제3유전막 위에 상부 도전층, 절연보호막을 순차 적층하는 제3단계;A third step of sequentially stacking an upper conductive layer and an insulating protective film on the third dielectric film; 상부 전극 형성을 위하여 상기 절연보호막 위에 포토리지스트를 도포한 후, 사진/식각 공정을 진행하여 상부 전극 및 상기 제1유전막 내지 제3유전막을 패터닝하는 제4단계; Applying a photoresist on the insulating protective film to form an upper electrode, and then performing a photo / etch process to pattern the upper electrode and the first to third dielectric layers; 하부 전극 형성을 위하여 상기 절연보호막 위에 포토리지스트를 도포한 후 사진/식각 공정을 진행하여 하부 전극을 패터닝하는 제5단계; 및 A fifth step of patterning the lower electrode by applying a photoresist on the insulating protective film to form a lower electrode and then performing a photo / etch process; And 절연층을 증착하고 평탄화한 후 비아 콘택 및 금속배선 공정을 진행하는 제6단계를 포함하여 이루어진 것을 특징으로 하는 반도체 소자의 MIM 커패시터 형성방법.And depositing and planarizing the insulating layer, and performing a via contact and metallization process. 제1항에 있어서, The method of claim 1, 상기 제2단계에서 상기 제1유전막 내지 제3유전막은 각각 SiN막, SiON막 및 SiN막으로 이루어진 것을 특징으로 하는 반도체 소자의 MIM 커패시터 형성방법.The method of forming a MIM capacitor of a semiconductor device, characterized in that in the second step, the first to third dielectric films each comprise a SiN film, a SiON film, and a SiN film. 제1항 또는 제2항에 있어서, The method according to claim 1 or 2, 상기 제2단계에서 상기 제2유전막은 상기 제1유전막의 O2 또는 N2O 플라즈마 처리에 의해 형성되는 것을 특징으로 하는 반도체 소자의 MIM 커패시터 형성방법.In the second step, the second dielectric film is formed by O 2 or N 2 O plasma treatment of the first dielectric film MIM capacitor forming method of a semiconductor device, characterized in that. 제1항 또는 제2항에 있어서, The method according to claim 1 or 2, 상기 제2단계에서 상기 제1유전막 내지 제3유전막의 적층은 인시츄(in-situ)로 실시되는 것을 특징으로 하는 반도체 소자의 MIM 커패시터 형성방법.The method of forming a MIM capacitor of a semiconductor device, characterized in that the stacking of the first dielectric film to the third dielectric film is performed in-situ in the second step. 제3항에 있어서, The method of claim 3, wherein 상기 제2단계에서 상기 O2 또는 N2O 플라즈마 처리는 인시츄(in-situ)로 실시되는 것을 특징으로 하는 반도체 소자의 MIM 커패시터 형성방법.The method of forming a MIM capacitor of a semiconductor device, characterized in that the O 2 or N 2 O plasma treatment in the second step is carried out in-situ.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102751177A (en) * 2012-07-26 2012-10-24 上海宏力半导体制造有限公司 Capacitor structure and preparation method thereof
CN112420925A (en) * 2019-08-23 2021-02-26 台湾积体电路制造股份有限公司 Semiconductor device, capacitor structure and forming method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102751177A (en) * 2012-07-26 2012-10-24 上海宏力半导体制造有限公司 Capacitor structure and preparation method thereof
CN112420925A (en) * 2019-08-23 2021-02-26 台湾积体电路制造股份有限公司 Semiconductor device, capacitor structure and forming method thereof

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