WO2022161174A1 - Component carrier comprising identification mark - Google Patents

Component carrier comprising identification mark Download PDF

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Publication number
WO2022161174A1
WO2022161174A1 PCT/CN2022/071660 CN2022071660W WO2022161174A1 WO 2022161174 A1 WO2022161174 A1 WO 2022161174A1 CN 2022071660 W CN2022071660 W CN 2022071660W WO 2022161174 A1 WO2022161174 A1 WO 2022161174A1
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WO
WIPO (PCT)
Prior art keywords
electrically conductive
conductive layer
identification mark
component carrier
identification
Prior art date
Application number
PCT/CN2022/071660
Other languages
French (fr)
Inventor
Chun Chieh Chen
Qiwei Wang
Original Assignee
AT&S (Chongqing) Company Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&S (Chongqing) Company Limited filed Critical AT&S (Chongqing) Company Limited
Priority to CN202280016402.3A priority Critical patent/CN116830811A/en
Priority to JP2023545383A priority patent/JP2024504747A/en
Publication of WO2022161174A1 publication Critical patent/WO2022161174A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09918—Optically detected marks used for aligning tool relative to the PCB, e.g. for mounting of components

Definitions

  • the present application relates to a component carrier comprising an identification mark.
  • component carriers equipped with one or more components and increasing miniaturization of such components as well as a rising number of components to be connected to the component carriers such as printed circuit boards
  • increasingly more powerful array-like components or packages having several components are being employed, which have a plurality of contacts or connections, with ever smaller spacing between these contacts.
  • component carriers shall be mechanically robust and electrically reliable so as to be operable even under harsh conditions. More and more functions are integrated in a component carrier.
  • identification marks can be formed within a layer structure of the component carrier.
  • the identification mark may be measured by a respective detection device, such as an x-ray detector, wherein on the basis of the measured picture of the identification marks, a respective alignment of the component carrier can be determined.
  • the picture of the identification mark (e.g. the contrast and the profile in the picture of the identification mark) becomes more and more undefined.
  • a component carrier comprises a stack of at four electrically insulating layer structures and at least five electrically conductive layer structure stacked along a stacking direction above each other in an alternating manner.
  • One of the electrically conductive layer structures forms a first outer electrically conductive layer of the stack and another one of the electrically conductive layer structures forms a second outer electrically conductive layer of the stack, wherein the first outer electrically conductive layer and the second outer electrically conductive layer are opposed outer layers of the stack.
  • the component carrier further comprises a first identification mark being detectable by a detection device, wherein the first identification mark is formed in an electrically conductive layer structure.
  • the first identification mark is formed in an electrically conductive layer structure being arranged closest to the first outer electrically conductive layer
  • a second identification mark being detectable by a detection device, wherein the second identification mark is formed in an electrically conductive layer structure.
  • the second identification mark is formed in an electrically conductive layer structure being arranged closest to the second outer electrically conductive layer. The first identification mark and the second identification mark are formed in stacking direction above each other.
  • a method for manufacturing the above described component carrier is described. Electrically insulating layer structures and at least five electrically conductive layer structure are stacked along a stacking direction above each other in an alternating manner, such that one of the electrically conductive layer structures forms a first outer electrically conductive layer of the stack and another one of the electrically conductive layer structures forms a second outer electrically conductive layer of the stack, wherein the first outer electrically conductive layer and the second outer electrically conductive layer are opposed outer layers of the stack. Furthermore, a first identification mark being detectable by a detection device is formed in an electrically conductive layer structure.
  • the first identification mark is formed in an electrically conductive layer structure being arranged closest to the first outer electrically conductive layer.
  • a second identification mark being detectable by a detection device is formed in an electrically conductive layer structure.
  • the second identification mark is formed in an electrically conductive layer structure being arranged closest to the second outer electrically conductive layer. The first identification mark and the second identification mark are formed in stacking direction above each other.
  • component carrier may particularly denote any support structure which is capable of accommodating one or more components thereon and/or therein for providing mechanical support and/or electrical connectivity.
  • a component carrier may be configured as a mechanical and/or electronic carrier for components.
  • a component carrier may be one of a printed circuit board, an organic interposer, a metal core substrate, an inorganic substrate and an IC (integrated circuit) substrate.
  • Acomponent carrier may also be a hybrid board combining different ones of the above-mentioned types of component carriers.
  • component carrier material may particularly denote a connected arrangement of one or more electrically insulating layer structures and/or one or more electrically conductive layer structures as used in component carrier technology. More specifically, such component carrier material may be material as used for printed circuit boards (PCBs) or IC substrates. In particular, electrically conductive material of such a component carrier material may comprise copper. Electrically insulating material of the component carrier material may comprise resin, in particular epoxy resin, optionally in combination with reinforcing particles such as glass fibres or glass spheres.
  • the component carrier is a laminate-type component carrier.
  • the component carrier is a compound of multiple layer structures which are stacked and connected together by applying a pressing force and/or heat.
  • the at least one electrically insulating layer structure comprises at least one of the group consisting of a resin or a polymer, such as epoxy resin, cyanate ester resin, benzocyclobutene resin, bismaleimide-triazine resin, polyphenylene derivate (e.g. based on polyphenylenether, PPE) , polyimide (PI) , polyamide (PA) , liquid crystal polymer (LCP) , polytetrafluoroethylene (PTFE) and/or a combination thereof.
  • Reinforcing structures such as webs, fibers, spheres or other kinds of filler particles, for example made of glass (multilayer glass) in order to form a composite, could be used as well.
  • prepreg A semi-cured resin in combination with a reinforcing agent, e.g. fibers impregnated with the above-mentioned resins is called prepreg.
  • FR4 FR4
  • FR5 which describe their flame retardant properties.
  • prepreg particularly FR4 are usually preferred for rigid PCBs, other materials, in particular epoxy-based build-up materials (such as build-up films) or photoimageable dielectric materials, may be used as well.
  • high-frequency materials such as polytetrafluoroethylene, liquid crystal polymer and/or cyanate ester resins, may be preferred.
  • LTCC low temperature cofired ceramics
  • other low, very low or ultra-low DK materials may be applied in the component carrier as electrically insulating structures.
  • the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten and magnesium.
  • copper is usually preferred, other materials or coated versions thereof are possible as well, in particular coated with supra-conductive material or conductive polymers, such as graphene or poly (3, 4-ethylenedioxythiophene) (PEDOT) , respectively.
  • PEDOT polyethylenedioxythiophene
  • the first identification mark and the second identification mark are formed in stacking direction above each other.
  • a stack may be formed of a plurality of electrically insulating layer structures and a plurality of electrically conductive layer structures, wherein in spaced apart electrically conductive layer structures of the stack respective identification marks are formed. If the first identification mark and the second identification mark are formed above each other in stacking direction, a proper picture of the alignment of the identification marks taken by the detection device can be provided. In other words, the first identification mark and the second identification mark are formed in such a manner, that on a projection plane having a projection normal parallel to the stacking direction, the identification mark and the further identification mark fully overlap each other.
  • the identification marks are formed in one of the electrically conductive layer structures. Specifically, by the present approach, the identification marks are formed in one of the electrically conductive layer structures closest to the outer electrically conductive layers respectively. Hence, it is easier for the (e.g. x-ray) detection device to detect the circumferential shape and the orientation of the identification mark, respectively.
  • At least one of the first and second identification mark comprises an inner volume which is free of a material of the electrically conductive layer structure.
  • the inner volume of the identification mark is hollow and for example copper free.
  • the inner volume of the identification mark is filled with an electrically insulating material.
  • the electrically insulating material may be similar to the electrically insulating layer structure laminated on top of the respective electrically conductive layer structure, such as polypropylene (PP) .
  • the identification mark comprises a triangular shape.
  • a triangular shape it is easier to detect the orientation and the alignment of the identification mark and the component carrier, respectively.
  • the identification mark comprises an arrow shape.
  • an arrow shape it is easier to detect the orientation and the alignment of the identification mark and the component carrier, respectively.
  • the identification mark comprises three identification points forming a triangular shape, wherein each identification point comprises an inner volume being free of the electrically conductive material.
  • An orientation of the identification mark is also possible by providing for example hollow points or profiles (circular, elliptical or rectangular) that are arranged with respect to each other in such a manner, that a specific direction can be determined.
  • the three identification points may be formed at corners of a virtual triangle.
  • the identification mark is formed at edges sections of the one electrically conductive layer structure.
  • the identification mark is formed at corner sections of the one electrically conductive layer structure.
  • the first identification mark and the second identification mark comprise identical circumferential shapes.
  • both identification marks in particular the first dentification mark and the second identification mark, have a triangular shape or are arrow shaped.
  • the second identification mark is filled with the electrically conductive material.
  • the second identification mark comprises only a circumferential extension or path being free of an electrically conductive material.
  • the detection device detects only the circumferential path of the identification mark.
  • the second identification mark and the above described identification mark having an inner volume being free of the electrically conductive material are formed above each other, an overlay and a matching, respectively, of both identification marks on a picture taken from the detection device can be detected.
  • the second identification mark comprises an inner volume being free of the electrically conductive material.
  • the component carrier further comprises a detach core layer, wherein the detach core layer is detachably arranged between the at least one electrically insulating layer structure and the at least one electrically conductive layer structure on the one side and the at least one further electrically insulating layer structure and at least one further electrically conductive layer structure on the other side.
  • a respective stack of electrically conductive and electrically insulating layer structures can be formed layerwise.
  • respective electrically conductive layer structures being arranged on opposing sides of the detach core layer a first identification mark and a second identification mark may be arranged.
  • the detach core layer can be removed (for example by applying heat or a chemical solution) , such that two stack sections, respectively, can be formed in one common manufacturing/lamination step.
  • the orientation of the respective component carrier can be detected before and after removing the detach core layer.
  • the first identification mark is arranged closest to the first outer electrically conductive layer, and/or the second identification mark is arranged closest to the second outer electrically conductive layer.
  • the component carrier further comprises further first identification marks and/or further second identification marks formed in each of the other electrically conductive layer structures except the first and second outer electrically conductive layers.
  • the component carrier further comprises further identification marks being detectable by a detection device, wherein the further identification marks are formed in a respective electrically conductive layer structure being arranged closest to the first outer electrically conductive layer or the second outer electrically conductive layer.
  • the stack comprises a mirror plane being parallel to the stacking direction, wherein the further identification marks are arranged with respect to the mirror plane at an opposite side with respect to the first identification mark.
  • the stack comprises a mirror plane being parallel to the stacking direction, wherein the further identification marks are arranged with respect to the mirror plane at the same side with respect to the second identification mark.
  • the further identification mark comprises an inner volume being free of the electrically conductive material.
  • further identification marks are formed in each of the other electrically conductive layer structures except the first and second outer electrically conductive layers.
  • the further identification mark comprises an inner volume being free of the electrically conductive material.
  • the further identification mark comprises a triangular shape.
  • the further identification mark comprises an arrow shape.
  • the further identification mark comprises three identification points forming a triangular shape, wherein each identification point comprises an inner volume being free of the electrically conductive material.
  • the further identification mark is formed at edges sections of the one electrically conductive layer structure.
  • the further identification mark is formed at corner sections of the electrically conductive layer structure.
  • the further identification mark, the first identification mark and/or the second identification mark comprise identical circumferential shapes.
  • the further identification mark is filled with the electrically conductive material.
  • the further identification mark comprises an inner volume being free of the electrically conductive material.
  • the component carrier is shaped as a plate. This contributes to the compact design, wherein the component carrier nevertheless provides a large basis for mounting components thereon. Furthermore, in particular a naked die as example for an embedded electronic component, can be conveniently embedded, thanks to its small thickness, into a thin plate such as a printed circuit board.
  • the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (in particular an IC substrate) , and an interposer.
  • the term “printed circuit board” may particularly denote a plate-shaped component carrier which is formed by laminating several electrically conductive layer structures with several electrically insulating layer structures, for instance by applying pressure and/or by the supply of thermal energy.
  • the electrically conductive layer structures are made of copper
  • the electrically insulating layer structures may comprise resin and/or glass fibers, so-called prepreg or FR4 material.
  • the various electrically conductive layer structures may be connected to one another in a desired way by forming holes through the laminate, for instance by laser drilling or mechanical drilling, and by partially or fully filling them with electrically conductive material (in particular copper) , thereby forming vias or any other through-hole connections.
  • the filled hole either connects the whole stack, (through-hole connections extending through several layers or the entire stack) , or the filled hole connects at least two electrically conductive layers, called via.
  • optical interconnections can be formed through individual layers of the stack in order to receive an electro-optical circuit board (EOCB) .
  • EOCB electro-optical circuit board
  • a printed circuit board is usually configured for accommodating one or more components on one or both opposing surfaces of the plate-shaped printed circuit board. They may be connected to the respective main surface by soldering.
  • Adielectric part of a PCB may be composed of resin with reinforcing fibers (such as glass fibers) .
  • a substrate may particularly denote a small component carrier.
  • a substrate may be a, in relation to a PCB, comparably small component carrier onto which one or more components may be mounted and that may act as a connection medium between one or more chip (s) and a further PCB.
  • a substrate may have substantially the same size as a component (in particular an electronic component) to be mounted thereon (for instance in case of a Chip Scale Package (CSP) ) .
  • CSP Chip Scale Package
  • a substrate can be understood as a carrier for electrical connections or electrical networks as well as component carrier comparable to a printed circuit board (PCB) , however with a considerably higher density of laterally and/or vertically arranged connections.
  • Lateral connections are for example conductive paths, whereas vertical connections may be for example drill holes.
  • These lateral and/or vertical connections are arranged within the substrate and can be used to provide electrical, thermal and/or mechanical connections of housed components or unhoused components (such as bare dies) , particularly of IC chips, with a printed circuit board or intermediate printed circuit board.
  • the term “substrate” also includes “IC substrates” .
  • a dielectric part of a substrate may be composed of resin with reinforcing particles (such as reinforcing spheres, in particular glass spheres) .
  • the substrate or interposer may comprise or consist of at least a layer of glass, silicon (Si) and/or a photoimageable or dry-etchable organic material like epoxy-based build-up material (such as epoxy-based build-up film) or polymer compounds (which may or may not include photo-and/or thermosensitive molecules) like polyimide or polybenzoxazole.
  • Si silicon
  • a photoimageable or dry-etchable organic material like epoxy-based build-up material (such as epoxy-based build-up film) or polymer compounds (which may or may not include photo-and/or thermosensitive molecules) like polyimide or polybenzoxazole.
  • At least one component may be embedded in the component carrier and/or may be surface mounted on the component carrier.
  • a component can be selected from a group consisting of an electrically non-conductive inlay, an electrically conductive inlay (such as a metal inlay, preferably comprising copper or aluminum) , a heat transfer unit (for example a heat pipe) , a light guiding element (for example an optical waveguide or a light conductor connection) , an electronic component, or combinations thereof.
  • An inlay can be for instance a metal block, with or without an insulating material coating (IMS-inlay) , which could be either embedded or surface mounted for the purpose of facilitating heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W/mK.
  • Such materials are often based, but not limited to metals, metal-oxides and/or ceramics as for instance copper, aluminium oxide (Al2O3) or aluminum nitride (AlN) .
  • metals, metal-oxides and/or ceramics as for instance copper, aluminium oxide (Al2O3) or aluminum nitride (AlN) .
  • Al2O3 aluminium oxide
  • AlN aluminum nitride
  • a component can be an active electronic component (having at least one p-n-junction implemented) , a passive electronic component such as a resistor, an inductance, or capacitor, an electronic chip, a storage device (for instance a DRAM or another data memory) , a filter, an integrated circuit (such as field-programmable gate array (FPGA) , programmable array logic (PAL) , generic array logic (GAL) and complex programmable logic devices (CPLDs) ) , a signal processing component, apower management component (such as a field-effect transistor (FET) , metal-oxide-semiconductor field-effect transistor (MOSFET) , complementary metal–oxide–semiconductor (CMOS) , junction field-effect transistor (JFET) , or insulated-gate field-effect transistor (IGFET) , all based on semiconductor materials such as silicon carbide (SiC) , gallium arsenide (GaAs) , gallium n
  • a magnetic element can be used as a component.
  • a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, for instance a ferrite core) or may be a paramagnetic element.
  • the component may also be a IC substrate, an interposer or a further component carrier, for example in a board-in-board configuration.
  • the component may be surface mounted on the component carrier and/or may be embedded in an interior thereof.
  • other components in particular those which generate and emit electromagnetic radiation and/or are sensitive with regard to electromagnetic radiation propagating from an environment, may be used as component.
  • an electrically insulating solder resist may be applied to one or both opposing main surfaces of the layer stack or component carrier in terms of surface treatment. For instance, it is possible to form such a solder resist on an entire main surface and to subsequently pattern the layer of solder resist so as to expose one or more electrically conductive surface portions which shall be used for electrically coupling the component carrier to an electronic periphery. The surface portions of the component carrier remaining covered with solder resist may be efficiently protected against oxidation or corrosion, in particular surface portions containing copper.
  • Such a surface finish may be an electrically conductive cover material on exposed electrically conductive layer structures (such as pads, conductive tracks, etc., in particular comprising or consisting of copper) on a surface of a component carrier. If such exposed electrically conductive layer structures are left unprotected, then the exposed electrically conductive component carrier material (in particular copper) might oxidize, making the component carrier less reliable.
  • a surface finish may then be formed for instance as an interface between a surface mounted component and the component carrier. The surface finish has the function to protect the exposed electrically conductive layer structures (in particular copper circuitry) and enable a joining process with one or more components, for instance by soldering.
  • Examples for appropriate materials for a surface finish are Organic Solderability Preservative (OSP) , Electroless Nickel Immersion Gold (ENIG) , Electroless Nickel Immersion Palladium Immersion Gold (ENIPIG) , gold (in particular hard gold) , chemical tin, nickel-gold, nickel-palladium, etc.
  • OSP Organic Solderability Preservative
  • ENIG Electroless Nickel Immersion Gold
  • ENIPIG Electroless Nickel Immersion Palladium Immersion Gold
  • gold in particular hard gold
  • chemical tin nickel-gold
  • nickel-palladium etc.
  • Fig. 1 illustrates a schematic view of a conventional component carrier having conventional identification markers.
  • Fig. 2 illustrates a schematic view of a component carrier comprising a detach core layer and identification marks according to an exemplary embodiment.
  • Fig. 3 illustrates a schematic view of a component carrier comprising three identification marks according to an exemplary embodiment.
  • Fig. 4 illustrates a schematic view of a component carrier comprising three identification marks being arranged above each other along a stacking direction according to an exemplary embodiment.
  • Fig. 5 illustrates a schematic view of an arrow shaped identification mark according to an exemplary embodiment.
  • Fig. 6 illustrates a schematic view of an identification mark formed by three points according to an exemplary embodiment.
  • Fig. 1 illustrates a schematic view of a conventional component carrier 1000 having conventional identification markers 1001, 1002.
  • the conventional component carrier 1000 comprises a stack 101 of electrically insulating layer structures 102 and electrically conductive layer structures 103, 106 made of electrically conductive material stacked along a stacking direction 104 above each other in an alternating manner.
  • the conventional identification mark 1001 is formed with a triangular shape in the electrically conductive layer structure 103 (upper layer L6, inner pattern mirror) .
  • a further conventional identification mark 1002 is formed with a triangular shape in the electrically conductive layer structure 106 (lower layer L6) .
  • the identification markers 1001, 1002 are filled with electrically conductive material. Both conventional identification marks 1001, 1002 are not arranged above each other along the stacking direction 104 and have an offset with respect to each other along the stacking direction 104. Further, the conventional identification marks 1001, 1002 are mirrored and have the same pattern in the upper layer L6 and the lower layer L6.
  • An (e.g. x-ray) detection device takes a respective picture 110 and detects the circumferential shape and the orientation of the identification mark 107, respectively.
  • the outer covering electrically conductive layer structures 103, 106 (L7) may be a carrier copper foil which may have the thickness between 3 ⁇ m and 18 ⁇ m. Due to the thick outer covering electrically conductive layer structures 103, 106 (L7) this will impact the contrast in a picture 110 of a detection device (e.g. a x-ray detection device) . Even by adjusting an x-ray light source and contrast, in respective pictures 110 both sides of the triangle identifications markers 1001, 1002 which point to different directions before core detach, will impact a direction identification.
  • a detection device e.g. a x-ray detection device
  • Fig. 2 illustrates a schematic view of a component carrier 100 comprising a detach core layer 109 and identification marks 107, 108 according to an exemplary embodiment.
  • the component carrier 100 comprises a stack 101 of four electrically insulating layer structures 102 and at least one electrically conductive layer structure 103, 106 made of electrically conductive material stacked along a stacking direction 104 above each other in an alternating manner.
  • One of the electrically conductive layer structures 103, 106 forms a first outer electrically conductive layer 111 of the stack 101 and another one of the electrically conductive layer structures 103, 106 forms a second outer electrically conductive layer 112 of the stack 101, wherein the first outer electrically conductive layer 111 and the second outer electrically conductive layer 112 are opposed outer layers of the stack 101.
  • a first identification mark 107 is formed being detectable by a detection device.
  • the first identification mark 107 is formed in an electrically conductive layer structure 103 being arranged closest to the first outer electrically conductive layer 111. Additionally, further first identification marks 107 and/or second identification marks 108 can also be formed in each of the other electrically conductive layer structures 103, 106 except the outer electrically conductive layers 111, 112.
  • a second identification mark 108 is formed being detectable by a detection device, wherein the second identification mark 108 is formed in an electrically conductive layer structure 106 being arranged closest to the second outer electrically conductive layer 112.
  • the first identification mark 107 and the second identification mark 108 are formed in stacking direction 104 above each other.
  • the first identification mark 107 and/or the second identification mark 108 comprises an inner volume being free of the electrically conductive material.
  • the identification marks 107, 108 extend along the plane of the respective electrically conductive layer structure 103, 106 and comprise a respective normal parallel to a normal of the plane of the respective electrically conductive layer structure 103, 106.
  • the identification marks 107, 108 in the figures are shown 90° tilted. Furthermore, the electrically conductive layers 103, 106 are denoted by layer numbers L4 to L8.
  • the identification marks 107, 108 are formed at least in one of the electrically conductive layer structures 103, 106 (layer L6, inner pattern mirror) closest to the outer electrically conductive layers 111, 112, respectively.
  • the identification mark 107 comprises an inner volume which is free of a material of the electrically conductive layer structure.
  • the inner volume of the identification mark 107 is hollow and for example copper free.
  • the electrically insulating material may be similar to the electrically insulating layer structure 102 laminated on top of the respective electrically conductive layer structure 103.
  • An (e.g. x-ray) detection device takes a respective picture 110 and detects the circumferential shape and the orientation of the identification mark 107, respectively.
  • the covering electrically conductive layer structures 103, 106 (L7) may be a copper foil which may have the thickness between 3 ⁇ m and 18 ⁇ m.
  • the first identification mark 107 and the second identification mark 108 are formed in stacking direction 104 above each other.
  • the stack 101 may be formed of a plurality of electrically insulating layer structures 102, 105 and a plurality of electrically conductive layer structures 103, 106, wherein in spaced apart electrically conductive layer structures 103, 106 of the stack 101, respective identification marks 107, 108 are formed. If the first identification mark 107 and the second identification mark 108 are formed above each other in stacking direction 104, a proper picture 110 of the alignment of the identification marks 107, 108 taken by the detection device can be provided.
  • the identification marks 107, 108 comprise in the shown example a identical triangular shapes.
  • the first identification mark 107 and the second identification mark 108 are formed in such a manner, that on a projection plane having a projection normal parallel to the stacking direction 104, the first identification mark 107 and the second identification mark 108 fully overlap each other.
  • the component carrier 100 further comprises the detach core layer 109, wherein the detach core layer 109 is detachably arranged between the central electrically conductive layer structure 103(L5) on the one side and the further electrically conductive layer structure 106 (L5) on the other side.
  • a respective stack section of the stack 101 made of electrically conductive layer structures 103, 106 and electrically insulating layer structures 102, 105 can be formed layerwise.
  • respective electrically conductive layer structures 103, 106 being arranged on opposing sides of the detach core layer 109 the first identification mark 107 and the second identification mark 108 are formed.
  • the detach core layer 109 can be removed, such that two stack sections can be formed in one common manufacturing/lamination step.
  • the identification marks107, 108 the orientation of the respective component carrier 100 can be detected before and after removing the detach core layer 109.
  • the three electrically conductive layer structures 103, 106 are copper layers.
  • the identification marks 107, 108 are formed in the conductive layer structures L6, because in these layer structures L6 a pattern process is done and the identification marks 107, 108 can be formed in such a respective pattern process.
  • the conductive layer structures 103, 106 nearest to detach core layer 109, that is L5, and the top outer conductive layers 111, 112, that is L7 no pattern process is accomplished before detaching from the detach core layer 109.
  • Fig. 3 illustrates a schematic view of a component carrier 100 comprising three identification marks 107, 301 according to an exemplary embodiment.
  • the stack 101 comprising the conductive layer structures L5, L6 and L7 is a flipped stack section of the upper part of stack 101 in Fig. 2.
  • the first identification mark 107 is the same of the first identification mark 107 in Fig. 2 which may be formed in the electrically conductive layer structure 103 (L6) before detached from the detach core layer 109, while third identification marks 301 in Fig. 3 are additional marks formed in the electrically conductive layer structures L5 and L7 after detached.
  • the third identification marks 301 may have the same profile, e.g.
  • the stack 101 comprises a mirror plane 201 being parallel to the stacking direction 104, wherein the further identification marks 301 are arranged with respect to the mirror plane 201 at an opposite side with respect to the first identification mark 107.
  • the component carrier 100 shown in Fig. 3 can be formed by laminating further electrically insulating layer structures 102, 105 and further outer electrically conductive layers 302 (L4, L8) on top of the outer electrically conductive layers 111 (L5, L7) .
  • the identification mark 107 is arranged due to the flipping of the upper stack section in Fig. 2 on the right side and still formed in the electrically conductive layer structure 103 (L6) now in a center of the stack 101.
  • the additional further identification marks 301 formed in the electrically conductive layer structures 103, 106 (L5, L7) which are arranged closest to the further outer electrically conductive layer 302 (L4, L8) and hence the surface of the stack 101.
  • the further identification marks 301 may have an inner volume being free of the electrically conductive material.
  • further identification marks 301 can also be formed in each of the other electrically conductive layer structures 103, 106 except the outer electrically conductive layers 111, 112.
  • Fig. 4 illustrates a schematic view of a component carrier comprising three identification marks 108, 301 being arranged above each other along the stacking direction 104 according to an exemplary embodiment.
  • the component carrier 100 shown in Fig. 4 can be formed by laminating further electrically insulating layer structures 102, 105 and further outer electrically conductive layers 302 (L4, L8) on top of the outer electrically conductive layers 112 (L5, L7) .
  • the stack 101 comprising the conductive layer structures L5, L6 and L7 is a stack section of the lower part of stack 101 in Fig. 2.
  • the second identification mark 108 is the same of the second identification mark 108 in Fig. 2 which may be formed in the electrically conductive layer structure 103 (L6) before detached from the detach core layer 109, while third identification marks 301 in Fig. 4 are additional marks formed in the electrically conductive layer structures L5 and L7 after detached.
  • the third identification marks 301 may have the same profile, e.g. atriangular profile, and are formed in stacking direction 104 above each other, similar to the first and second identification marks 107, 108 shown in Fig. 2.
  • the stack 101 comprises a mirror plane 201 being parallel to the stacking direction 104, wherein the further identification marks 301 are arranged with respect to the mirror plane 201 at the same side with respect to the second identification mark 108. Additionally, further identification marks 301 can also be formed in each of the other electrically conductive layer structures 103, 106 except the outer electrically conductive layers 111, 112.
  • the second identification mark 108 and the third identification marks 301 having an inner volume being free of the electrically conductive material are formed above each other, an overlay and a matching, respectively, of all identification marks 108, 301 on a picture 110 taken by the detection device can be detected.
  • Fig. 5 illustrates a schematic view of an arrow shaped first identification mark 107 according to an exemplary embodiment.
  • the first identification mark 107 comprises an arrow shape.
  • the second and third identification marks 108, 301 may also have a respective shape.
  • Fig. 6 illustrates a schematic view of an identification mark 107 formed by three points according to an exemplary embodiment.
  • the three identification points form a triangular shape, wherein each identification point comprises an inner volume being free of the electrically conductive material.
  • the three identification points may be formed at corners of a virtual triangle in order to form an identification mark 107.
  • the second and third identification marks 108, 301 may also have a respective shape.

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Abstract

A component carrier comprising a stack of at least four electrically insulating layer structures and at least five electrically conductive layer structure stacked along a stacking direction above each other in an alternating manner, wherein one of the electrically conductive layer structures forms a first outer electrically conductive layer of the stack and another one of the electrically conductive layer structures forms a second outer electrically conductive layer of the stack and wherein the first outer electrically conductive layer and the second outer electrically conductive layer are opposed outer layers of the stack. The component carrier further comprises a first identification mark being detectable by a detection device, wherein the first identification mark is formed in an electrically conductive layer structure being arranged closest to the first outer electrically conductive layer, and a second identification mark being detectable by a detection device, wherein the second identification mark is formed in an electrically conductive layer structure being arranged closest to the second outer electrically conductive layer. The first identification mark and the second identification mark are formed in stacking direction above each other.

Description

COMPONENT CARRIER COMPRISING AN IDENTIFICATION MARK CROSS-REFERENCE TO RELATED APPLICATION
The present application claims priority of Utility model application CN 202120247645.0, filed on January 28, 2021. The entire disclosure of the above application is incorporated herein by reference.
FIELD
The present application relates to a component carrier comprising an identification mark.
BACKGROUND
In the context of growing product functionalities of component carriers equipped with one or more components and increasing miniaturization of such components as well as a rising number of components to be connected to the component carriers such as printed circuit boards, increasingly more powerful array-like components or packages having several components are being employed, which have a plurality of contacts or connections, with ever smaller spacing between these contacts. In particular, component carriers shall be mechanically robust and electrically reliable so as to be operable even under harsh conditions. More and more functions are integrated in a component carrier.
During manufacturing of complex component carriers, such as printed circuit boards (PCB) , it is important to align and orientate the component carrier in an accurate and exact manner. In order to align a component carrier, identification marks can be formed within a layer structure of the component carrier. The identification mark may be measured by a respective detection device, such as an x-ray detector, wherein on the basis of the measured picture of the identification marks, a respective alignment of the component carrier can be determined.
However, if the respective layer comprising the identification marks is covered during the manufacturing process by several further layers, the picture of the identification mark (e.g. the contrast and the profile in the picture of the identification mark) becomes more and more undefined.
Hence, there may be a need to provide identification marks which can be properly determined by a detection device in order to provide a proper alignment of the component carrier.
SUMMARY
According to an exemplary embodiment of the present application, a component carrier is  described. The component carrier comprises a stack of at four electrically insulating layer structures and at least five electrically conductive layer structure stacked along a stacking direction above each other in an alternating manner. One of the electrically conductive layer structures forms a first outer electrically conductive layer of the stack and another one of the electrically conductive layer structures forms a second outer electrically conductive layer of the stack, wherein the first outer electrically conductive layer and the second outer electrically conductive layer are opposed outer layers of the stack.
The component carrier further comprises a first identification mark being detectable by a detection device, wherein the first identification mark is formed in an electrically conductive layer structure. In an exemplary embodiment, the first identification mark is formed in an electrically conductive layer structure being arranged closest to the first outer electrically conductive layer, and a second identification mark being detectable by a detection device, wherein the second identification mark is formed in an electrically conductive layer structure. In an exemplary embodiment, the second identification mark is formed in an electrically conductive layer structure being arranged closest to the second outer electrically conductive layer. The first identification mark and the second identification mark are formed in stacking direction above each other.
According to an exemplary embodiment of the present application, a method for manufacturing the above described component carrier is described. Electrically insulating layer structures and at least five electrically conductive layer structure are stacked along a stacking direction above each other in an alternating manner, such that one of the electrically conductive layer structures forms a first outer electrically conductive layer of the stack and another one of the electrically conductive layer structures forms a second outer electrically conductive layer of the stack, wherein the first outer electrically conductive layer and the second outer electrically conductive layer are opposed outer layers of the stack. Furthermore, a first identification mark being detectable by a detection device is formed in an electrically conductive layer structure. In an exemplary embodiment, the first identification mark is formed in an electrically conductive layer structure being arranged closest to the first outer electrically conductive layer. A second identification mark being detectable by a detection device is formed in an electrically conductive layer structure. In an exemplary embodiment, the second identification mark is formed in an electrically conductive layer structure being arranged closest to the second outer electrically conductive layer. The first identification mark and the second identification mark are formed in  stacking direction above each other.
In the context of the present application, the term “component carrier” may particularly denote any support structure which is capable of accommodating one or more components thereon and/or therein for providing mechanical support and/or electrical connectivity. In other words, a component carrier may be configured as a mechanical and/or electronic carrier for components. In particular, a component carrier may be one of a printed circuit board, an organic interposer, a metal core substrate, an inorganic substrate and an IC (integrated circuit) substrate. Acomponent carrier may also be a hybrid board combining different ones of the above-mentioned types of component carriers.
In the context of the present application, the term “component carrier material” may particularly denote a connected arrangement of one or more electrically insulating layer structures and/or one or more electrically conductive layer structures as used in component carrier technology. More specifically, such component carrier material may be material as used for printed circuit boards (PCBs) or IC substrates. In particular, electrically conductive material of such a component carrier material may comprise copper. Electrically insulating material of the component carrier material may comprise resin, in particular epoxy resin, optionally in combination with reinforcing particles such as glass fibres or glass spheres.
In an embodiment, the component carrier is a laminate-type component carrier. In such an embodiment, the component carrier is a compound of multiple layer structures which are stacked and connected together by applying a pressing force and/or heat.
In an embodiment, the at least one electrically insulating layer structure comprises at least one of the group consisting of a resin or a polymer, such as epoxy resin, cyanate ester resin, benzocyclobutene resin, bismaleimide-triazine resin, polyphenylene derivate (e.g. based on polyphenylenether, PPE) , polyimide (PI) , polyamide (PA) , liquid crystal polymer (LCP) , polytetrafluoroethylene (PTFE) and/or a combination thereof. Reinforcing structures such as webs, fibers, spheres or other kinds of filler particles, for example made of glass (multilayer glass) in order to form a composite, could be used as well. A semi-cured resin in combination with a reinforcing agent, e.g. fibers impregnated with the above-mentioned resins is called prepreg. These prepregs are often named after their properties e.g. FR4 or FR5, which describe their flame retardant properties. Although prepreg particularly FR4 are usually preferred for rigid PCBs, other materials, in particular epoxy-based build-up materials (such as build-up films) or photoimageable dielectric materials, may be used as well. For high frequency applications,  high-frequency materials such as polytetrafluoroethylene, liquid crystal polymer and/or cyanate ester resins, may be preferred. Besides these polymers, low temperature cofired ceramics (LTCC) or other low, very low or ultra-low DK materials may be applied in the component carrier as electrically insulating structures.
In an embodiment, the at least one electrically conductive layer structure comprises at least one of the group consisting of copper, aluminum, nickel, silver, gold, palladium, tungsten and magnesium. Although copper is usually preferred, other materials or coated versions thereof are possible as well, in particular coated with supra-conductive material or conductive polymers, such as graphene or poly (3, 4-ethylenedioxythiophene) (PEDOT) , respectively.
The first identification mark and the second identification mark are formed in stacking direction above each other. Hence, a stack may be formed of a plurality of electrically insulating layer structures and a plurality of electrically conductive layer structures, wherein in spaced apart electrically conductive layer structures of the stack respective identification marks are formed. If the first identification mark and the second identification mark are formed above each other in stacking direction, a proper picture of the alignment of the identification marks taken by the detection device can be provided. In other words, the first identification mark and the second identification mark are formed in such a manner, that on a projection plane having a projection normal parallel to the stacking direction, the identification mark and the further identification mark fully overlap each other.
The identification marks are formed in one of the electrically conductive layer structures. Specifically, by the present approach, the identification marks are formed in one of the electrically conductive layer structures closest to the outer electrically conductive layers respectively. Hence, it is easier for the (e.g. x-ray) detection device to detect the circumferential shape and the orientation of the identification mark, respectively.
According to an exemplary embodiment, at least one of the first and second identification mark comprises an inner volume which is free of a material of the electrically conductive layer structure. For example, the inner volume of the identification mark is hollow and for example copper free. In an exemplary embodiment, the inner volume of the identification mark is filled with an electrically insulating material. The electrically insulating material may be similar to the electrically insulating layer structure laminated on top of the respective electrically conductive layer structure, such as polypropylene (PP) .
According to an exemplary embodiment, the identification mark comprises a triangular  shape. By providing a triangular shape it is easier to detect the orientation and the alignment of the identification mark and the component carrier, respectively.
According to a further exemplary embodiment, the identification mark comprises an arrow shape. By providing an arrow shape it is easier to detect the orientation and the alignment of the identification mark and the component carrier, respectively.
According to a further exemplary embodiment, the identification mark comprises three identification points forming a triangular shape, wherein each identification point comprises an inner volume being free of the electrically conductive material. An orientation of the identification mark is also possible by providing for example hollow points or profiles (circular, elliptical or rectangular) that are arranged with respect to each other in such a manner, that a specific direction can be determined. For example, the three identification points may be formed at corners of a virtual triangle.
According to a further exemplary embodiment, the identification mark is formed at edges sections of the one electrically conductive layer structure.
According to a further exemplary embodiment, the identification mark is formed at corner sections of the one electrically conductive layer structure.
According to a further exemplary embodiment, the first identification mark and the second identification mark comprise identical circumferential shapes. For example, both identification marks, in particular the first dentification mark and the second identification mark, have a triangular shape or are arrow shaped.
According to a further exemplary embodiment, the second identification mark is filled with the electrically conductive material. For example, the second identification mark comprises only a circumferential extension or path being free of an electrically conductive material. Hence, the detection device detects only the circumferential path of the identification mark. However, since the second identification mark and the above described identification mark having an inner volume being free of the electrically conductive material are formed above each other, an overlay and a matching, respectively, of both identification marks on a picture taken from the detection device can be detected.
According to a further exemplary embodiment, the second identification mark comprises an inner volume being free of the electrically conductive material.
According to a further exemplary embodiment, the component carrier further comprises a detach core layer, wherein the detach core layer is detachably arranged between the at least one  electrically insulating layer structure and the at least one electrically conductive layer structure on the one side and the at least one further electrically insulating layer structure and at least one further electrically conductive layer structure on the other side.
Hence, on both opposing sides of the detach core layer, a respective stack of electrically conductive and electrically insulating layer structures can be formed layerwise. In respective electrically conductive layer structures being arranged on opposing sides of the detach core layer a first identification mark and a second identification mark may be arranged. After the respective stack sections on both sides of the detach core layer are formed, the detach core layer can be removed (for example by applying heat or a chemical solution) , such that two stack sections, respectively, can be formed in one common manufacturing/lamination step. By forming the first identification mark and the second identification mark, the orientation of the respective component carrier can be detected before and after removing the detach core layer.
In an embodiment, the first identification mark is arranged closest to the first outer electrically conductive layer, and/or the second identification mark is arranged closest to the second outer electrically conductive layer.
In an embodiment, the component carrier further comprises further first identification marks and/or further second identification marks formed in each of the other electrically conductive layer structures except the first and second outer electrically conductive layers.
In an embodiment, the component carrier further comprises further identification marks being detectable by a detection device, wherein the further identification marks are formed in a respective electrically conductive layer structure being arranged closest to the first outer electrically conductive layer or the second outer electrically conductive layer.
In an embodiment, the stack comprises a mirror plane being parallel to the stacking direction, wherein the further identification marks are arranged with respect to the mirror plane at an opposite side with respect to the first identification mark.
In an embodiment, the stack comprises a mirror plane being parallel to the stacking direction, wherein the further identification marks are arranged with respect to the mirror plane at the same side with respect to the second identification mark.
In an embodiment, the further identification mark comprises an inner volume being free of the electrically conductive material.
In an embodiment, further identification marks are formed in each of the other electrically conductive layer structures except the first and second outer electrically conductive layers.
In an embodiment, the further identification mark comprises an inner volume being free of the electrically conductive material.
In an embodiment, the further identification mark comprises a triangular shape.
In an embodiment, the further identification mark comprises an arrow shape.
In an embodiment, the further identification mark comprises three identification points forming a triangular shape, wherein each identification point comprises an inner volume being free of the electrically conductive material.
In an embodiment, the further identification mark is formed at edges sections of the one electrically conductive layer structure.
In an embodiment, the further identification mark is formed at corner sections of the electrically conductive layer structure.
In an embodiment, the further identification mark, the first identification mark and/or the second identification mark comprise identical circumferential shapes.
In an embodiment, the further identification mark is filled with the electrically conductive material.
In an embodiment, the further identification mark comprises an inner volume being free of the electrically conductive material.
In an embodiment, the component carrier is shaped as a plate. This contributes to the compact design, wherein the component carrier nevertheless provides a large basis for mounting components thereon. Furthermore, in particular a naked die as example for an embedded electronic component, can be conveniently embedded, thanks to its small thickness, into a thin plate such as a printed circuit board.
In an embodiment, the component carrier is configured as one of the group consisting of a printed circuit board, a substrate (in particular an IC substrate) , and an interposer.
In the context of the present application, the term “printed circuit board” (PCB) may particularly denote a plate-shaped component carrier which is formed by laminating several electrically conductive layer structures with several electrically insulating layer structures, for instance by applying pressure and/or by the supply of thermal energy. As preferred materials for PCB technology, the electrically conductive layer structures are made of copper, whereas the electrically insulating layer structures may comprise resin and/or glass fibers, so-called prepreg or FR4 material. The various electrically conductive layer structures may be connected to one another in a desired way by forming holes through the laminate, for instance by laser drilling or  mechanical drilling, and by partially or fully filling them with electrically conductive material (in particular copper) , thereby forming vias or any other through-hole connections. The filled hole either connects the whole stack, (through-hole connections extending through several layers or the entire stack) , or the filled hole connects at least two electrically conductive layers, called via. Similarly, optical interconnections can be formed through individual layers of the stack in order to receive an electro-optical circuit board (EOCB) . Apart from one or more components which may be embedded in a printed circuit board, a printed circuit board is usually configured for accommodating one or more components on one or both opposing surfaces of the plate-shaped printed circuit board. They may be connected to the respective main surface by soldering. Adielectric part of a PCB may be composed of resin with reinforcing fibers (such as glass fibers) .
In the context of the present application, the term “substrate” may particularly denote a small component carrier. A substrate may be a, in relation to a PCB, comparably small component carrier onto which one or more components may be mounted and that may act as a connection medium between one or more chip (s) and a further PCB. For instance, a substrate may have substantially the same size as a component (in particular an electronic component) to be mounted thereon (for instance in case of a Chip Scale Package (CSP) ) . More specifically, a substrate can be understood as a carrier for electrical connections or electrical networks as well as component carrier comparable to a printed circuit board (PCB) , however with a considerably higher density of laterally and/or vertically arranged connections. Lateral connections are for example conductive paths, whereas vertical connections may be for example drill holes. These lateral and/or vertical connections are arranged within the substrate and can be used to provide electrical, thermal and/or mechanical connections of housed components or unhoused components (such as bare dies) , particularly of IC chips, with a printed circuit board or intermediate printed circuit board. Thus, the term “substrate” also includes “IC substrates” . A dielectric part of a substrate may be composed of resin with reinforcing particles (such as reinforcing spheres, in particular glass spheres) .
The substrate or interposer may comprise or consist of at least a layer of glass, silicon (Si) and/or a photoimageable or dry-etchable organic material like epoxy-based build-up material (such as epoxy-based build-up film) or polymer compounds (which may or may not include photo-and/or thermosensitive molecules) like polyimide or polybenzoxazole.
At least one component may be embedded in the component carrier and/or may be surface mounted on the component carrier. Such a component can be selected from a group consisting of  an electrically non-conductive inlay, an electrically conductive inlay (such as a metal inlay, preferably comprising copper or aluminum) , a heat transfer unit (for example a heat pipe) , a light guiding element (for example an optical waveguide or a light conductor connection) , an electronic component, or combinations thereof. An inlay can be for instance a metal block, with or without an insulating material coating (IMS-inlay) , which could be either embedded or surface mounted for the purpose of facilitating heat dissipation. Suitable materials are defined according to their thermal conductivity, which should be at least 2 W/mK. Such materials are often based, but not limited to metals, metal-oxides and/or ceramics as for instance copper, aluminium oxide (Al2O3) or aluminum nitride (AlN) . In order to increase the heat exchange capacity, other geometries with increased surface area are frequently used as well. Furthermore, a component can be an active electronic component (having at least one p-n-junction implemented) , a passive electronic component such as a resistor, an inductance, or capacitor, an electronic chip, a storage device (for instance a DRAM or another data memory) , a filter, an integrated circuit (such as field-programmable gate array (FPGA) , programmable array logic (PAL) , generic array logic (GAL) and complex programmable logic devices (CPLDs) ) , a signal processing component, apower management component (such as a field-effect transistor (FET) , metal-oxide-semiconductor field-effect transistor (MOSFET) , complementary metal–oxide–semiconductor (CMOS) , junction field-effect transistor (JFET) , or insulated-gate field-effect transistor (IGFET) , all based on semiconductor materials such as silicon carbide (SiC) , gallium arsenide (GaAs) , gallium nitride (GaN) , gallium oxide (Ga2O3) , indium gallium arsenide (InGaAs) and/or any other suitable inorganic compound) , an optoelectronic interface element, alight emitting diode, a photocoupler, a voltage converter (for example a DC/DC converter or an AC/DC converter) , a cryptographic component, a transmitter and/or receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS) , amicroprocessor, a capacitor, a resistor, an inductance, a battery, a switch, a camera, an antenna, alogic chip, and an energy harvesting unit. However, other components may be embedded in the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element may be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element or a ferrimagnetic element, for instance a ferrite core) or may be a paramagnetic element. However, the component may also be a IC substrate, an interposer or a further component carrier, for example in a board-in-board configuration. The component may be surface mounted on the component carrier and/or may be  embedded in an interior thereof. Moreover, also other components, in particular those which generate and emit electromagnetic radiation and/or are sensitive with regard to electromagnetic radiation propagating from an environment, may be used as component.
After processing interior layer structures of the component carrier, it is possible to cover (in particular by lamination) one or both opposing main surfaces of the processed layer structures symmetrically or asymmetrically with one or more further electrically insulating layer structures and/or electrically conductive layer structures. In other words, a build-up may be continued until a desired number of layers is obtained.
After having completed formation of a stack of electrically insulating layer structures and electrically conductive layer structures, it is possible to proceed with a surface treatment of the obtained layers structures or component carrier.
In particular, an electrically insulating solder resist may be applied to one or both opposing main surfaces of the layer stack or component carrier in terms of surface treatment. For instance, it is possible to form such a solder resist on an entire main surface and to subsequently pattern the layer of solder resist so as to expose one or more electrically conductive surface portions which shall be used for electrically coupling the component carrier to an electronic periphery. The surface portions of the component carrier remaining covered with solder resist may be efficiently protected against oxidation or corrosion, in particular surface portions containing copper.
It is also possible to apply a surface finish selectively to exposed electrically conductive surface portions of the component carrier in terms of surface treatment. Such a surface finish may be an electrically conductive cover material on exposed electrically conductive layer structures (such as pads, conductive tracks, etc., in particular comprising or consisting of copper) on a surface of a component carrier. If such exposed electrically conductive layer structures are left unprotected, then the exposed electrically conductive component carrier material (in particular copper) might oxidize, making the component carrier less reliable. A surface finish may then be formed for instance as an interface between a surface mounted component and the component carrier. The surface finish has the function to protect the exposed electrically conductive layer structures (in particular copper circuitry) and enable a joining process with one or more components, for instance by soldering. Examples for appropriate materials for a surface finish are Organic Solderability Preservative (OSP) , Electroless Nickel Immersion Gold (ENIG) , Electroless Nickel Immersion Palladium Immersion Gold (ENIPIG) , gold (in particular hard gold) , chemical tin, nickel-gold, nickel-palladium, etc.
The aspects defined above and further aspects of the present application are apparent from the examples of embodiment to be described hereinafter and are explained with reference to these examples of embodiment.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 illustrates a schematic view of a conventional component carrier having conventional identification markers.
Fig. 2 illustrates a schematic view of a component carrier comprising a detach core layer and identification marks according to an exemplary embodiment.
Fig. 3 illustrates a schematic view of a component carrier comprising three identification marks according to an exemplary embodiment.
Fig. 4 illustrates a schematic view of a component carrier comprising three identification marks being arranged above each other along a stacking direction according to an exemplary embodiment.
Fig. 5 illustrates a schematic view of an arrow shaped identification mark according to an exemplary embodiment.
Fig. 6 illustrates a schematic view of an identification mark formed by three points according to an exemplary embodiment.
DETAILED DESCRIPTION
The illustrations in the drawings are schematic. In different drawings, similar or identical elements are provided with the same reference signs.
Fig. 1 illustrates a schematic view of a conventional component carrier 1000 having  conventional identification markers  1001, 1002.
The conventional component carrier 1000 comprises a stack 101 of electrically insulating layer structures 102 and electrically  conductive layer structures  103, 106 made of electrically conductive material stacked along a stacking direction 104 above each other in an alternating manner.
The conventional identification mark 1001 is formed with a triangular shape in the electrically conductive layer structure 103 (upper layer L6, inner pattern mirror) . A further conventional identification mark 1002 is formed with a triangular shape in the electrically conductive layer structure 106 (lower layer L6) . The  identification markers  1001, 1002 are filled  with electrically conductive material. Both conventional identification marks 1001, 1002 are not arranged above each other along the stacking direction 104 and have an offset with respect to each other along the stacking direction 104. Further, the conventional identification marks 1001, 1002 are mirrored and have the same pattern in the upper layer L6 and the lower layer L6. An (e.g. x-ray) detection device takes a respective picture 110 and detects the circumferential shape and the orientation of the identification mark 107, respectively.
The outer covering electrically conductive layer structures 103, 106 (L7) may be a carrier copper foil which may have the thickness between 3μm and 18μm. Due to the thick outer covering electrically conductive layer structures 103, 106 (L7) this will impact the contrast in a picture 110 of a detection device (e.g. a x-ray detection device) . Even by adjusting an x-ray light source and contrast, in respective pictures 110 both sides of the  triangle identifications markers  1001, 1002 which point to different directions before core detach, will impact a direction identification.
Fig. 2 illustrates a schematic view of a component carrier 100 comprising a detach core layer 109 and identification marks 107, 108 according to an exemplary embodiment.
The component carrier 100 comprises a stack 101 of four electrically insulating layer structures 102 and at least one electrically  conductive layer structure  103, 106 made of electrically conductive material stacked along a stacking direction 104 above each other in an alternating manner. One of the electrically  conductive layer structures  103, 106 forms a first outer electrically conductive layer 111 of the stack 101 and another one of the electrically  conductive layer structures  103, 106 forms a second outer electrically conductive layer 112 of the stack 101, wherein the first outer electrically conductive layer 111 and the second outer electrically conductive layer 112 are opposed outer layers of the stack 101. A first identification mark 107 is formed being detectable by a detection device. The first identification mark 107 is formed in an electrically conductive layer structure 103 being arranged closest to the first outer electrically conductive layer 111. Additionally, further first identification marks 107 and/or second identification marks 108 can also be formed in each of the other electrically  conductive layer structures  103, 106 except the outer electrically  conductive layers  111, 112.
Furthermore, a second identification mark 108 is formed being detectable by a detection device, wherein the second identification mark 108 is formed in an electrically conductive layer structure 106 being arranged closest to the second outer electrically conductive layer 112. The first identification mark 107 and the second identification mark 108 are formed in stacking  direction 104 above each other.
The first identification mark 107 and/or the second identification mark 108 comprises an inner volume being free of the electrically conductive material. The identification marks 107, 108 extend along the plane of the respective electrically  conductive layer structure  103, 106 and comprise a respective normal parallel to a normal of the plane of the respective electrically  conductive layer structure  103, 106.
In order to show the shape of the identification marks 107, 108 in the figures, the identification marks 107, 108 in the figures are shown 90° tilted. Furthermore, the electrically  conductive layers  103, 106 are denoted by layer numbers L4 to L8.
The identification marks 107, 108 are formed at least in one of the electrically conductive layer structures 103, 106 (layer L6, inner pattern mirror) closest to the outer electrically  conductive layers  111, 112, respectively. Specifically, e.g. the identification mark 107 comprises an inner volume which is free of a material of the electrically conductive layer structure. For example, the inner volume of the identification mark 107 is hollow and for example copper free. The electrically insulating material may be similar to the electrically insulating layer structure 102 laminated on top of the respective electrically conductive layer structure 103. An (e.g. x-ray) detection device takes a respective picture 110 and detects the circumferential shape and the orientation of the identification mark 107, respectively.
The covering electrically conductive layer structures 103, 106 (L7) may be a copper foil which may have the thickness between 3μm and 18μm.
The first identification mark 107 and the second identification mark 108 are formed in stacking direction 104 above each other. Hence, the stack 101 may be formed of a plurality of electrically insulating  layer structures  102, 105 and a plurality of electrically  conductive layer structures  103, 106, wherein in spaced apart electrically  conductive layer structures  103, 106 of the stack 101, respective identification marks 107, 108 are formed. If the first identification mark 107 and the second identification mark 108 are formed above each other in stacking direction 104, a proper picture 110 of the alignment of the identification marks 107, 108 taken by the detection device can be provided.
The identification marks 107, 108 comprise in the shown example a identical triangular shapes. In other words, the first identification mark 107 and the second identification mark 108 are formed in such a manner, that on a projection plane having a projection normal parallel to the stacking direction 104, the first identification mark 107 and the second identification mark 108  fully overlap each other.
The component carrier 100 further comprises the detach core layer 109, wherein the detach core layer 109 is detachably arranged between the central electrically conductive layer structure 103(L5) on the one side and the further electrically conductive layer structure 106 (L5) on the other side. On both opposing sides of the detach core layer 109, a respective stack section of the stack 101 made of electrically  conductive layer structures  103, 106 and electrically insulating  layer structures  102, 105 can be formed layerwise. In respective electrically  conductive layer structures  103, 106 being arranged on opposing sides of the detach core layer 109 the first identification mark 107 and the second identification mark 108 are formed. After the respective stack sections on both sides of the detach core layer 109 are formed, the detach core layer 109 can be removed, such that two stack sections can be formed in one common manufacturing/lamination step. By forming the identification marks107, 108, the orientation of the respective component carrier 100 can be detected before and after removing the detach core layer 109.
In the Fig. 2 the three electrically conductive layer structures 103, 106 (L5, L6 and L7) are copper layers. The identification marks 107, 108 are formed in the conductive layer structures L6, because in these layer structures L6 a pattern process is done and the identification marks 107, 108 can be formed in such a respective pattern process. In the  conductive layer structures  103, 106 nearest to detach core layer 109, that is L5, and the top outer  conductive layers  111, 112, that is L7, no pattern process is accomplished before detaching from the detach core layer 109.
Fig. 3 illustrates a schematic view of a component carrier 100 comprising three identification marks 107, 301 according to an exemplary embodiment. The stack 101 comprising the conductive layer structures L5, L6 and L7 is a flipped stack section of the upper part of stack 101 in Fig. 2. The first identification mark 107 is the same of the first identification mark 107 in Fig. 2 which may be formed in the electrically conductive layer structure 103 (L6) before detached from the detach core layer 109, while third identification marks 301 in Fig. 3 are additional marks formed in the electrically conductive layer structures L5 and L7 after detached. The third identification marks 301 may have the same profile, e.g. a triangular profile, and are formed in stacking direction 104 above each other, similar to the first and second identification marks 107, 108 shown in Fig. 2. The stack 101 comprises a mirror plane 201 being parallel to the stacking direction 104, wherein the further identification marks 301 are arranged with respect to the mirror plane 201 at an opposite side with respect to the first identification mark 107.
The component carrier 100 shown in Fig. 3 can be formed by laminating further electrically insulating  layer structures  102, 105 and further outer electrically conductive layers 302 (L4, L8) on top of the outer electrically conductive layers 111 (L5, L7) . The identification mark 107 is arranged due to the flipping of the upper stack section in Fig. 2 on the right side and still formed in the electrically conductive layer structure 103 (L6) now in a center of the stack 101. Hence, although the central identification mark 107 is hardly visible in the picture 110 of the detection device, the additional further identification marks 301 formed in the electrically conductive layer structures 103, 106 (L5, L7) which are arranged closest to the further outer electrically conductive layer 302 (L4, L8) and hence the surface of the stack 101. Hence, a sharp representation of the shape of the further identification marks 301 in the picture 110 of the detection device is possible. The further identification marks 301 may have an inner volume being free of the electrically conductive material. Additionally, further identification marks 301 can also be formed in each of the other electrically  conductive layer structures  103, 106 except the outer electrically  conductive layers  111, 112.
Fig. 4 illustrates a schematic view of a component carrier comprising three identification marks 108, 301 being arranged above each other along the stacking direction 104 according to an exemplary embodiment. The component carrier 100 shown in Fig. 4 can be formed by laminating further electrically insulating  layer structures  102, 105 and further outer electrically conductive layers 302 (L4, L8) on top of the outer electrically conductive layers 112 (L5, L7) .
The stack 101 comprising the conductive layer structures L5, L6 and L7 is a stack section of the lower part of stack 101 in Fig. 2. The second identification mark 108 is the same of the second identification mark 108 in Fig. 2 which may be formed in the electrically conductive layer structure 103 (L6) before detached from the detach core layer 109, while third identification marks 301 in Fig. 4 are additional marks formed in the electrically conductive layer structures L5 and L7 after detached. The third identification marks 301 may have the same profile, e.g. atriangular profile, and are formed in stacking direction 104 above each other, similar to the first and second identification marks 107, 108 shown in Fig. 2. The stack 101 comprises a mirror plane 201 being parallel to the stacking direction 104, wherein the further identification marks 301 are arranged with respect to the mirror plane 201 at the same side with respect to the second identification mark 108. Additionally, further identification marks 301 can also be formed in each of the other electrically  conductive layer structures  103, 106 except the outer electrically  conductive layers  111, 112.
Since the second identification mark 108 and the third identification marks 301 having an inner volume being free of the electrically conductive material are formed above each other, an overlay and a matching, respectively, of all identification marks 108, 301 on a picture 110 taken by the detection device can be detected.
Fig. 5 illustrates a schematic view of an arrow shaped first identification mark 107 according to an exemplary embodiment. The first identification mark 107 comprises an arrow shape. The second and third identification marks 108, 301 may also have a respective shape.
Fig. 6 illustrates a schematic view of an identification mark 107 formed by three points according to an exemplary embodiment. The three identification points form a triangular shape, wherein each identification point comprises an inner volume being free of the electrically conductive material. For example, the three identification points may be formed at corners of a virtual triangle in order to form an identification mark 107. The second and third identification marks 108, 301 may also have a respective shape.
It should be noted that the term “comprising” does not exclude other elements or steps and the“a” or “an” does not exclude a plurality. Also elements described in association with different embodiments may be combined.
It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.
Implementation of the present application is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants are possible which use the solutions shown and the principle according to the present application even in the case of fundamentally different embodiments.
List of reference signs:
100 component carrier
101 stack
102 electrically insulating layer structure
103 electrically conductive layer structure
104 stacking direction
105 further electrically insulating layer structure
106 further electrically conductive layer structure
107 identification mark
108 second identification mark
109 detach core layer
110 x-ray picture
111 first outer electrically conductive layer
112 second outer electrically conductive layer
201 mirror plane
301 third, further identification mark
302 further outer electrically conductive layer.

Claims (33)

  1. Component carrier characterized in that the component carrier (100) comprises
    a stack (101) of at least four electrically insulating layer structures (102) and at least five electrically conductive layer structure (103, 106) stacked along a stacking direction (104) above each other in an alternating manner,
    wherein one of the electrically conductive layer structures (103, 106) forms a first outer electrically conductive layer (111) of the stack (101) and another one of the electrically conductive layer structures (103, 106) forms a second outer electrically conductive layer (112) of the stack (101) ,
    wherein the first outer electrically conductive layer (111) and the second outer electrically conductive layer (112) are opposed outer layers of the stack (101)
    a first identification mark (107) being detectable by a detection device,
    wherein the first identification mark (107) is formed in an electrically conductive layer structure (103, 106) ,
    a second identification mark (108) being detectable by a detection device,
    wherein the second identification mark (108) is formed in an electrically conductive layer structure (103, 106) ,
    wherein the first identification mark (107) and the second identification mark (108) are formed in stacking direction (104) above each other.
  2. Component carrier according to claim 1, characterized in that
    the first identification mark (107) comprises an inner volume being free of the electrically conductive material.
  3. Component carrier according to claim 2, characterized in that
    the first identification mark (107) comprises a triangular shape.
  4. Component carrier according to claim 2, characterized in that
    the first identification mark (107) comprises an arrow shape.
  5. Component carrier according to claim 2, characterized in that
    the first identification mark (107) comprises three identification points forming a triangular shape,
    wherein each identification point comprises an inner volume being free of the electrically conductive material.
  6. Component carrier according to claim 2, characterized in that
    the first identification mark (107) is formed at edges sections of the one electrically conductive layer structure.
  7. Component carrier according to claim 2, characterized in that
    the first identification mark (107) is formed at corner sections of the one electrically conductive layer structure.
  8. Component carrier according to claim 1, characterized in that
    the first identification mark (107) and the second identification mark (108) comprise identical circumferential shapes.
  9. Component carrier according to claim 1, characterized in that
    the second identification mark (108) is filled with the electrically conductive material.
  10. Component carrier according to claim 9,
    wherein the second identification mark (108) comprises only a circumferential path being free of an electrically conductive material.
  11. Component carrier according to claim 1, characterized in that
    the second identification mark (108) comprises an inner volume being free of the electrically conductive material.
  12. Component carrier according to claim 1, characterized in that the component carrier (100) further comprises
    a detach core layer (109) ,
    wherein the detach core layer (109) is detachably arranged between the at least one electrically insulating layer structure (102) and the at least one electrically conductive layer structure on the one side and the at least one further electrically insulating layer structure (105) and at least one further electrically conductive layer structure on the other side.
  13. Component carrier according to claim 1, characterized in that
    the first identification mark (107) is arranged closest to the first outer electrically conductive layer (111) , and/or
    the second identification mark (108) is arranged closest to the second outer electrically conductive layer (112) .
  14. Component carrier according to claim 1, characterized in that the component carrier (100) further comprises
    further first identification marks and/or further second identification marks formed in each of the other electrically conductive layer structures except the first and second outer electrically conductive layers (111, 112) .
  15. Component carrier according to claim 1, characterized in that the component carrier (100) further comprises
    further identification marks (301) being detectable by a detection device,
    wherein the further identification marks (301) are formed in a respective electrically conductive layer structure being arranged closest to the first outer electrically conductive layer (111) or the second outer electrically conductive layer (112) .
  16. Component carrier according to claim 15, characterized in that
    the stack (101) comprises a mirror plane (201) being parallel to the stacking direction (104) ,
    wherein the further identification marks (301) are arranged with respect to the mirror plane (201) at an opposite side with respect to the first identification mark (107) .
  17. Component carrier according to claim 15, characterized in that
    the stack (101) comprises a mirror plane (201) being parallel to the stacking direction (104) ,
    wherein the further identification marks (301) are arranged with respect to the mirror plane (201) at the same side with respect to the second identification mark (108) .
  18. Component carrier according to claim 15, characterized in that
    the further identification mark (301) comprises an inner volume being free of the electrically conductive material.
  19. Component carrier according to claim 15, characterized in that
    further identification marks (301) are formed in each of the other electrically conductive layer structures except the first and second outer electrically conductive layers (111, 112) .
  20. Component carrier according to claim 15, characterized in that
    the further identification mark (301) comprises a triangular shape.
  21. Component carrier according to claim 15, characterized in that
    the further identification mark (301) comprises an arrow shape.
  22. Component carrier according to claim 15, characterized in that
    the further identification mark (301) comprises three identification points forming a triangular shape,
    wherein each identification point comprises an inner volume being free of the electrically conductive material.
  23. Component carrier according to claim 15, characterized in that
    the further identification mark (301) is formed at edges sections of the one electrically conductive layer structure.
  24. Component carrier according to claim 15, characterized in that
    the further identification mark (301) is formed at corner sections of the electrically conductive layer structure (103, 106) .
  25. Component carrier according to claim 15, characterized in that
    the further identification mark (301) , the first identification mark (107) and/or the second identification mark (108) comprise identical circumferential shapes.
  26. Component carrier according to claim 15, characterized in that
    the further identification mark (301) is filled with the electrically conductive material.
  27. Component carrier according to claim 1,
    wherein the first identification mark (107) and the second identification mark (108) are formed in such a manner that on a projection plane having a projection normal parallel to the stacking direction (104) , the first identification mark (107) and the second identification mark (108) fully overlap each other.
  28. Component carrier according to claim 1,
    wherein the first outer electrically conductive layer (111) and/or the second outer electrically conductive layer (112) covering the stack (101) is a copper foil which has in particular a thickness between 3 μm and 18 μm.
  29. Method of manufacturing a component carrier (100) , the method comprises
    forming a stack (101) of at least four electrically insulating layer structures (102) and at least five electrically conductive layer structure (103, 106) stacked along a stacking direction (104) above each other in an alternating manner,
    wherein one of the electrically conductive layer structures (103, 106) forms a first outer electrically conductive layer (111) of the stack (101) and another one of the electrically conductive layer structures (103, 106) forms a second outer electrically conductive layer (112) of the stack (101) ,
    wherein the first outer electrically conductive layer (111) and the second outer electrically conductive layer (112) are opposed outer layers of the stack (101)
    providing a first identification mark (107) being detectable by a detection device, and
    forming the first identification mark (107) in an electrically conductive layer structure  (103, 106) ,
    providing a second identification mark (108) being detectable by a detection device, and
    forming the second identification mark (108) in an electrically conductive layer structure (103, 106) ,
    wherein the first identification mark (107) and the second identification mark (108) are formed in stacking direction (104) above each other.
  30. Method according to claim 29,
    forming a detach core layer (109) ,
    wherein the detach core layer (109) is detachably arranged between the at least one electrically insulating layer structure (102) and the at least one electrically conductive layer structure (103) on the one side and the at least one further electrically insulating layer structure (105) and at least one further electrically conductive layer structure (106) on the other side.
  31. Method according to claim 30,
    detecting the orientation of the respective component carrier (100) before and after removing the detach core layer (109) by forming the first identification mark (107) and the second identification mark (108) .
  32. Method according to claim 30,
    forming the second identification mark (108) in the electrically conductive layer structure (103, 106) before being detached from the detach core layer (109) .
  33. Method according to claim 32,
    forming further identification marks (301) being detectable by a detection device,
    wherein the further identification marks (301) are formed in a respective electrically conductive layer structure (103, 106) being arranged closest to the first outer electrically conductive layer (111) or the second outer electrically conductive layer (112) ,
    wherein the third identification marks (301) are additional marks formed in the electrically conductive layer structures (103, 106) after being detached from the detach core layer (109) .
PCT/CN2022/071660 2021-01-28 2022-01-12 Component carrier comprising identification mark WO2022161174A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150257256A1 (en) * 2014-03-10 2015-09-10 Shinko Electric Industries Co., Ltd. Wiring Substrate and Semiconductor Device
CN107968055A (en) * 2016-10-19 2018-04-27 台达电子国际（新加坡）私人有限公司 The method for packing of semiconductor device
CN108463047A (en) * 2017-01-13 2018-08-28 奥特斯奥地利科技与***技术有限公司 The patterned blanket layer of restriction cavity and alignment mark in base structure
CN111200899A (en) * 2018-11-20 2020-05-26 奥特斯科技(重庆)有限公司 Component carrier and method for producing the same
CN112087887A (en) * 2019-06-12 2020-12-15 奥特斯科技(重庆)有限公司 Aligning component carrier structures by combining evaluation pad and hole pattern alignment marks

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150257256A1 (en) * 2014-03-10 2015-09-10 Shinko Electric Industries Co., Ltd. Wiring Substrate and Semiconductor Device
CN107968055A (en) * 2016-10-19 2018-04-27 台达电子国际（新加坡）私人有限公司 The method for packing of semiconductor device
CN108463047A (en) * 2017-01-13 2018-08-28 奥特斯奥地利科技与***技术有限公司 The patterned blanket layer of restriction cavity and alignment mark in base structure
CN111200899A (en) * 2018-11-20 2020-05-26 奥特斯科技(重庆)有限公司 Component carrier and method for producing the same
CN112087887A (en) * 2019-06-12 2020-12-15 奥特斯科技(重庆)有限公司 Aligning component carrier structures by combining evaluation pad and hole pattern alignment marks

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