WO2022160632A1 - 半导体结构的制作方法 - Google Patents

半导体结构的制作方法 Download PDF

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Publication number
WO2022160632A1
WO2022160632A1 PCT/CN2021/109285 CN2021109285W WO2022160632A1 WO 2022160632 A1 WO2022160632 A1 WO 2022160632A1 CN 2021109285 W CN2021109285 W CN 2021109285W WO 2022160632 A1 WO2022160632 A1 WO 2022160632A1
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Prior art keywords
layer
material layer
mask
mask layer
semiconductor structure
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PCT/CN2021/109285
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English (en)
French (fr)
Inventor
夏军
宛强
徐朋辉
刘涛
李森
占康澍
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长鑫存储技术有限公司
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Priority to US17/457,273 priority Critical patent/US20220246616A1/en
Publication of WO2022160632A1 publication Critical patent/WO2022160632A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells

Definitions

  • the present application relates to the field of semiconductors, and in particular, to a method for fabricating a semiconductor structure.
  • the memory in the semiconductor structure is a memory component used to store programs and various data information. It can be divided into read-only memory and random access memory according to the type of memory used.
  • a memory typically includes a capacitor, which is used to store charge representing the stored information, and a transistor connected to the capacitor, which is a switch that controls the flow of charge into and out of the capacitor.
  • the technical problem solved by the embodiments of the present application is to provide a method for fabricating a semiconductor structure, which is beneficial to improve the dimensional accuracy of the semiconductor structure, thereby helping to improve the yield of the semiconductor structure.
  • embodiments of the present application provide a method for fabricating a semiconductor structure, including: providing a substrate, the substrate having a peripheral region and an array region; stacking an insulating layer and having a mask pattern on the substrate the mask layer; the insulating layer is etched using the mask layer as a mask to form a contact hole penetrating the insulating layer in the array region, and after the contact hole is formed, the mask layer is retained , in the direction perpendicular to the surface of the substrate, there is a thickness difference between the mask layer in the peripheral region and the mask layer in the array region; forming a first material layer, the first material layer covering at least the surface of the mask layer and the surface of the contact hole in the array region; forming a second material layer, the second material layer being located on the first material layer; using the second material layer as a mask film, and etch part of the mask layer to reduce the thickness difference between the mask layer in the peripheral region and the mask layer in the array region; remove the remaining second material layer, the remaining the
  • 1 to 5 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure
  • 6 to 14 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to the first embodiment of the present application.
  • 1 to 5 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure.
  • the process steps for forming the contact hole 15 are generally shown in FIGS. 1 to 2 .
  • a substrate 10 having a peripheral region I and an array region II thereon.
  • an insulating layer 11 and a mask layer 14 having a mask pattern are formed by stacking in sequence.
  • the mask layer 12 in the peripheral region I and the mask layer in the array region II The thickness of the mask layer 13 is the same.
  • the substrate 10 has structures such as bit lines, word lines and capacitive contact windows, and also has an electrical connection layer 19 between the substrate 10 and part of the insulating layer 11, and the electrical connection layer 19 is located between the insulating layer 11 and the peripheral region I The electrical connection layer 19 is also located between the lower electrode of the capacitor formed subsequently and the substrate 10 of the array region II.
  • the insulating layer 11 includes a first stabilizing layer 1 , a first isolating layer 2 , a second stabilizing layer 3 , a second isolating layer 4 and a supporting layer 5 that are stacked in sequence.
  • the process steps of forming the mask layer 14 with a mask pattern include: forming an initial mask layer on the insulating layer 11, and performing pattern-dry etching on the initial mask layer to form a mask layer with a mask pattern Membrane layer 14 .
  • the mask layer 14 is also damaged by etching. Since the pattern size of the pattern on the mask layer 13 of the array region II with many contact holes 15 is much smaller than the pattern size of the pattern on the mask layer 12 of the peripheral region I, that is, the mask of the peripheral region I and the array region II The pattern size of the pattern on the film layer 14 is different, so the first etching process has a higher etching rate for the mask layer 13 located in the array region II, and a higher etching rate for the mask layer 12 located in the peripheral region I. If the contact hole 15 is formed, the mask layer 13 in the array region II is etched more than the mask layer 12 in the peripheral region I, so that the mask layer 12 in the peripheral region I is thicker than the array. The thickness of the film layer 13 in zone II.
  • the process steps for forming the lower electrode of the capacitor are generally shown in FIGS. 3 to 5 .
  • the mask layer 14 (refer to FIG. 2) on the insulating layer 11 is removed by etching.
  • the thickness of the mask layer 12 in the peripheral region I is greater than the thickness of the mask layer 13 in the array region II, within the same etching time, there will be a mask layer 12 on the insulating layer 11 in the peripheral region I (refer to FIG. 1) Residual, forming bump defects 16, and part of the insulating layer 11 located in the array region II will also be etched, so that in the direction III of the substrate 10 pointing to the insulating layer 11, the width of the insulating layer 11 is gradually narrowed, not This is beneficial to ensure the dimensional accuracy of the insulating layer 11, thus affecting the dimensional accuracy of the capacitor lower electrode formed subsequently.
  • a conformal covering first material layer 17 is formed, the first material layer 17 is located at the bottom and sidewalls of the contact hole 15 (refer to FIG. 2 ), and also covers the surface of the insulating layer 11 . Due to the existence of the bump defects 16 , the first material layer 17 located in the peripheral region I will be raised at the bump defects 16 .
  • the insulating layer 11 located in the array region II includes a plurality of elongated insulating layers 19 separated by the contact holes 15. Since the width of the elongated insulating layers 19 gradually increases in the direction III of the substrate 10 toward the insulating layer 11 If it becomes narrower, the distance between the capacitor lower electrodes 18 located on the two sidewalls of the same strip-shaped insulating layer 19 in the direction III gradually decreases, which is likely to cause a short circuit between adjacent capacitor lower electrodes 18 .
  • an embodiment of the present application provides a method for fabricating a semiconductor structure.
  • a first material layer is formed on the surface of the mask layer and the surface of the contact hole in the array area, and then A second material layer is formed on the first material layer, and the second material layer is used as a mask to etch a part of the mask layer in the peripheral area, so that the top of the mask layer in the remaining peripheral area is not higher than the mask in the array area layer on top of the first material layer to reduce the thickness difference between the mask layer in the remaining peripheral area and the mask layer in the array area, so that the mask layer and part of the first material layer are subsequently removed to form the lower electrode of the capacitor.
  • the etching of the insulating layer in the array area can be avoided, and the dimensional accuracy of the insulating layer can be prevented from being reduced, which leads to the reduction of the dimensional accuracy of the lower electrode of the capacitor and the phase difference.
  • the short-circuit phenomenon between the lower electrodes of adjacent capacitors is beneficial to improve the dimensional accuracy of the lower electrodes of the capacitors, to reduce the problem of signal interference between the lower electrodes of adjacent capacitors, and to improve the yield of the semiconductor structure.
  • 6 to 14 are schematic cross-sectional structural diagrams corresponding to each step of a method for fabricating a semiconductor structure according to the first embodiment of the present application.
  • a substrate 100 is provided, the substrate 100 has a peripheral area I and an array area II; an insulating layer 101 and a mask layer 102 having a mask pattern are stacked on the substrate 100, and the mask located in the peripheral area I
  • the film layer 102 is the first mask layer 112
  • the mask layer 102 in the array region II is the second mask layer 122
  • the top of the first mask layer 112 is flush with the top of the second mask layer 122 .
  • the semiconductor structure may be a memory
  • the substrate 100 has structures such as bit lines, word lines, and capacitive contact windows.
  • the peripheral area I is located around the array area II, and the peripheral area I is used to realize the input and output circuits of the memory and For the electrical connection of other electrical components, the array area II is used to realize the electrical connection between different conductive structures in the memory.
  • the process steps of forming the insulating layer 101 include: forming a dielectric layer 161 on the substrate 100 , and forming a support layer 151 on the dielectric layer 161 .
  • the material of the dielectric layer 161 includes silicon oxide or silicon nitride, and the material of the support layer 151 can be silicon nitride or silicon carbonitride.
  • the process steps of forming the dielectric layer 161 include: sequentially stacking and forming the first stable layer 111 , the first isolation layer 121 , the second stable layer 131 and the second isolation layer 141 on the substrate 100 , which is beneficial to the subsequent formation Contact holes with larger depth and width.
  • the dielectric layer 161 may also be a single-layer structure.
  • the materials of the first stabilizing layer 111 and the second stabilizing layer 131 include silicon nitride or silicon carbonitride, and the capacitor lower electrode formed subsequently is located on the sidewalls of the second stabilizing layer 131 and the supporting layer 151 , and the second stabilizing layer Both the 131 and the supporting layer 151 can support the lower electrode of the capacitor, so as to prevent the lower electrode of the capacitor from tilting or collapsing.
  • the materials of the first stabilizing layer 111 , the second stabilizing layer 131 and the supporting layer 151 are the same, and they are all silicon nitride. In other embodiments, the materials of the first stabilizing layer 111 , the second stabilizing layer 131 and the supporting layer 151 may be different.
  • the thickness of the support layer 151 can be greater than the thickness of the first stable layer 111 and the thickness of the second stable layer 131 thickness.
  • the first isolation layer 121 and the second isolation layer 141 will be removed. Therefore, materials that can be easily removed can be used as the first isolation layer 121 and the second isolation layer 141.
  • the material of the isolation layer 141 may be silicon oxide. In this embodiment, the materials of the first isolation layer 121 and the second isolation layer 141 are the same. In other embodiments, the materials of the first isolation layer 121 and the second isolation layer 141 may be different.
  • the materials of the first isolation layer 121 and the second isolation layer 141 are the same, and both may be silicon oxide. In other embodiments, the materials of the first isolation layer 121 and the second isolation layer 141 may also be different.
  • the electrical connection layer 109 there is also an electrical connection layer 109 between the substrate 100 and part of the insulating layer 101, the electrical connection layer 109 is located between the insulating layer 101 and the substrate 100 in the peripheral region I, and the electrical connection layer 109 is also located in the subsequent formation between the lower electrode of the capacitance and the substrate 100 in the array region II.
  • the material of the electrical connection layer 109 may be polysilicon or metal material.
  • the insulating layer 101 is etched by using the mask layer 102 as a mask to form a contact hole 103 penetrating the insulating layer 101 in the array region II. After the contact hole 103 is formed, the mask layer 102 is retained. If the pattern size of the pattern on the layer 112 and the second mask layer 122 is different, there is a thickness difference between the first mask layer 112 and the second mask layer 122 in the direction III perpendicular to the surface of the substrate 100 . Specifically, the top of the first mask layer 112 is higher than the top of the second mask layer 122 .
  • the material of the mask layer 102 includes polysilicon, and in the direction perpendicular to the surface of the substrate 100 , the thickness difference between the first mask layer 112 and the second mask layer 122 may be 100 ⁇ 500 nm.
  • the thickness difference between the first mask layer 112 and the second mask layer 122 is related to the aspect ratio of the formed contact hole 103 .
  • the thickness difference is 300 nm.
  • the material of the mask layer 102 may also be other materials with a higher etching selectivity ratio between the mask layer 102 and the insulating layer 101 .
  • a first material layer 104 is formed, the first material layer 104 at least covers the surface of the second mask layer 122 and the surface of the contact hole 103 (refer to FIG. 7 ), and the first mask layer 112 and the second mask layer are subsequently removed 122, the first material layer 104 higher than the top of the insulating layer 101 will also be removed, and the remaining first material layer 104 can be used as the lower electrode of the capacitor, ensuring that the first mask layer 112 and the second mask layer 122 are both Under the premise of being completely removed without damaging the insulating layer 101 , it is beneficial to improve the dimensional accuracy of the formed lower electrode of the capacitor, thereby improving the yield of the semiconductor structure.
  • the first material layer 104 also covers the surface of the first mask layer 112 . In other embodiments, the first material layer 104 may only be located on the surface of the second mask layer 122 and the surface of the contact hole 103 .
  • the first material layer 104 may be formed by a deposition process, wherein the deposition process includes chemical vapor deposition or atomic layer deposition.
  • the first material layer 104 is a capacitor electrode material, wherein the capacitor electrode material includes a conductive material such as titanium nitride, titanium, polysilicon or tungsten.
  • the first material layer 104 is deposited on the surfaces of the first mask layer 112 and the second mask layer 122 by a deposition process.
  • a part of the first material layer 104 is also deposited at the same time. Removing to form the capacitor lower electrode is beneficial to simplify the process steps of preparing the semiconductor structure by simultaneously removing the mask layer 102 and part of the first material layer 104 under the condition that the dimensional accuracy of the capacitor lower electrode formed subsequently meets the requirements.
  • a second material layer 115 is formed, the second material layer 115 is located on the first material layer 104 in the array region II, and the first material layer 104 in the array region II is surrounded by a plurality of through holes, and the second material layer 115 When filling the plurality of through holes, the top surface of the second material layer 115 is lower than the top surface of the first material layer 104 in the peripheral region I. In other embodiments, the top surface of the second material layer 115 may also be flush with the top surface of the first material layer 104 in the peripheral region I.
  • the second material layer 115 covers the surface of the first material layer 104 in the array region II and fills the plurality of through holes surrounded by the first material layer 104 , the second material layer 115 is used to etch the first mask in the subsequent process.
  • the second material layer 115 can protect the first material layer 104 in the array region II well, so as to ensure the dimensional accuracy of the capacitor lower electrode formed subsequently.
  • the process steps of forming the second material layer 115 include: referring to FIG. 9 , forming a preliminary second material layer 125 , the preliminary second material layer 125 covers the surface of the first material layer 104 , and the top of the preliminary second material layer 125 is The surface is higher than the highest surface of the first material layer 104 ; referring to FIG. 10 , part of the initial second material layer 125 is removed to expose the highest surface of the first material layer 104 to form the second material layer 115 .
  • the second material layer 115 is a flowable medium. Since the flowable medium has better fluidity and filling properties, it is beneficial for the second material layer 115 to cover the surface of the first material layer 104 uniformly and without gaps. , and fill the contact hole 103 , when the mask layer 102 and part of the first material layer 104 are subsequently removed to form the lower electrode of the capacitor, the second material layer 115 filling the contact hole 103 can protect the substrate at the bottom of the contact hole 103 100 , so that the substrate 100 will not be in contact with residues generated when the mask layer 102 and part of the first material layer 104 are removed, thereby improving the yield of the semiconductor structure.
  • the flowable medium includes photoresist or a dielectric including Si-H bonds, Si-N bonds and N-H bonds
  • the method for forming the second material layer 115 includes a chemical vapor deposition process or a spin coating process.
  • the second material layer 115 is used as a photoresist for illustration.
  • the method for forming the initial second material layer 125 is: using a spin coating process to coat a photoresist layer on the first material layer 104 , and the top of the photoresist layer is higher than the first material layer 104 surface. Since the overall size of the semiconductor structure is relatively small in the fabrication process of the semiconductor structure, a photoresist layer is coated on the surfaces of the first material layer 104 in the peripheral region I and the first material layer 104 in the array region II, without distinguishing the peripheral regions I and the array region II, and at the same time, because the process is easier to operate, it is beneficial to simplify the process steps of preparing the semiconductor structure.
  • the second material layer 115 may also be formed only on the surface of the first material layer 104 in the array region II. Specifically, a photoresist layer may be coated only on the first material layer 104 of the array region II, and the top of the photoresist layer is lower than the top of the first material layer 104 of the array region II.
  • the process step of forming the second material layer 115 may include: on the surface of the first mask layer 112 and the first material layer 104 An initial second material layer 125 is formed on all surfaces; part of the initial second material layer 125 is removed to expose the first mask layer 112 , and the remaining initial second material layer 125 is the second material layer 115 .
  • a part of the initial second material layer 125 is removed, and the method of exposing the highest surface of the first material layer 104 is etching.
  • a dry etching process may be used to etch a part of the initial second material layer 125 until the highest surface of the first material layer 104 is exposed, and the etching gas includes oxygen, nitrogen or hydrogen.
  • the highest surface of the first material layer 104 is used as an etch stop layer, and oxygen-containing plasma is used to remove part of the initial second material layer 125 . Since the material of the initial second material layer 125 is photoresist, the oxygen-containing plasma can rapidly react with the photoresist to generate carbon dioxide, carbon monoxide and water, so the reaction between the oxygen-containing plasma and the initial second material layer 125 is adopted. Quickly, part of the initial second material layer 125 can be removed relatively quickly, which improves the efficiency of fabricating the semiconductor structure.
  • the method for removing part of the initial second material layer 125 to expose the highest surface of the first material layer 104 may also be chemical mechanical polishing.
  • a portion of the first mask layer 112 is etched to reduce the thickness difference between the first mask layer 112 and the second mask layer 122 .
  • the top a of the remaining first mask layer 112 is made not higher than the top b of the first material layer 104 on the second mask layer 122 .
  • the method further includes etching the first material layer 104 located on the first mask layer 112 .
  • the method for etching part of the first mask layer 112 and the first material layer 104 located on the first mask layer 112 is a dry etching process.
  • the material of the first mask layer 112 is polysilicon
  • the material of the first material layer 104 is titanium nitride or titanium
  • the etching rate of polysilicon by the same dry etching process is the same as the etching rate of titanium nitride or titanium. The difference in etching rate is small, and the first mask layer 112 will not be damaged, so part of the first mask layer 112 and part of the first material layer 104 can be removed simultaneously by the same etching process, which is beneficial to simplify the preparation of the semiconductor structure process steps.
  • chlorine and/or fluorine-containing plasma may be used to etch a portion of the first mask layer 112 and a portion of the first material layer 104 .
  • the material of the first mask layer 112 is polysilicon and the material of the first material layer 104 is titanium nitride or titanium, the first mask layer 112 and the first material layer 104 are both easy to interact with chlorine- and/or fluorine-containing When the plasma reacts, part of the first mask layer 112 and part of the first material layer 104 can be quickly removed, which is beneficial to improve the fabrication efficiency of the semiconductor structure.
  • the method for etching the first mask layer 112 and the first material layer 104 on the first mask layer 112 may also be a wet etching process.
  • the first material layer 104 located on the first mask layer 112 may be etched away first by using the second material layer 115 as a mask, and then the second material layer 115 and the remaining first material layers may be etched away.
  • 104 is a mask to etch a partial thickness of the first mask layer 112 so that the top of the remaining first mask layer 112 is not higher than the top of the first material layer 104 on the second mask layer 122 .
  • the top a of the remaining first mask layer 112 is not higher than the top b of the first material layer 104 on the second mask layer 122 .
  • the top of the remaining first mask layer 112 is flush with the top of the second mask layer 122 , which is beneficial to eliminate the thickness difference between the remaining first mask layer 112 and the second mask layer 122 , so that in the subsequent process steps of removing the mask layer 102 and part of the first material layer 104, the first mask layer 112, the second mask layer 122 and the first material layer 104 above the top of the insulating layer 101 can be simultaneously is completely removed, to prevent part of the first mask layer 112 from remaining on the insulating layer 101 in the peripheral region I, and to prevent part of the insulating layer 101 in the array region II from being removed, then the substrate 10 points to the direction III of the insulating layer 101 , to avoid the width of the insulating layer 101 from gradually narrowing, which is conducive to ensuring the dimensional accuracy of the insulating layer 101, thereby helping
  • the first material layer 104 is a thin layer structure, in the subsequent process steps of removing the first mask layer 112 , the second mask layer 122 and the first material layer 104 higher than the top of the insulating layer 101 , The effect of the first material layer 104 on the etching time is very small. It can be considered that in the same etching time, when the first mask layer 112 and the second mask layer 122 are completely removed, the thickness is higher than that on the top of the insulating layer 101. The first material layer 104 is also completely removed.
  • the dimensional accuracy of the capacitor lower electrode formed subsequently is improved, when the first isolation layer 121 and the second isolation layer 141 are subsequently removed to form structures such as the capacitor dielectric layer and the capacitor upper electrode, the capacitor upper electrode and the capacitor dielectric layer According to the formation of the capacitor lower electrode with higher dimensional accuracy, it is beneficial to improve the dimensional accuracy of the formed capacitor upper electrode and the capacitor dielectric layer.
  • the remaining second material layer 115 , the remaining mask layer 102 and the first material layer 104 on the remaining mask layer 102 are removed to form the capacitor lower electrode 114 .
  • the process steps of forming the capacitor lower electrode 114 include:
  • the remaining portion of the second material layer 115 is etched to expose the first material layer 104 on top of the second mask layer 122 .
  • the etching process for etching this part of the second material layer 115 is the same as the etching process for etching the part of the initial second material layer 125.
  • the first material layer 104 on top of the second mask layer 122 is For etching the stop layer, oxygen-containing plasma is used to remove the remaining part of the second material layer 115 .
  • the second material layer 115 located in the contact hole 103 (refer to FIG. 7 ) is reserved for the purpose of using the reserved second material layer 115 as a mask to remove the unmasked second material layer 115 in the future.
  • the first mask layer 112 , the second mask layer 122 and part of the first material layer 104 are reserved for the purpose of using the reserved second material layer 115 as a mask to remove the unmasked second material layer 115 in the future.
  • the remaining second material layer 115 as a mask, remove the remaining first mask layer 112 , the second mask layer 122 , the first material layer 104 and the second mask layer 104 on the remaining first mask layer 112
  • the first material layer 104 on the mask layer 122 forms the capacitor lower electrode 114 .
  • a dry etching process may also be used to remove the remaining first mask layer 112 , the second mask layer 122 and part of the first material layer 104 .
  • the remaining second material layer 115 is removed.
  • the remaining second material layer 115 is removed by a third etching process, and the third etching process is the same as the etching process for the initial second material layer 125 in the aforementioned etching part.
  • a first material layer 104 is formed at least on the surface of the mask layer 102 located in the array region II and the surface of the contact hole 103 .
  • the capacitor bottom electrode 114 in the semiconductor structure is subsequently formed; then a second material layer 115 is formed on the first material layer 104, and a partial thickness of the mask layer 102 is etched with the second material layer 115 as a mask to reduce the peripheral area.
  • the thickness difference between the mask layer 102 of I and the mask layer 102 of the array region II is favorable for forming the semiconductor structure as shown in FIG. 14 .
  • the top of the insulating layer 101 in the peripheral region I is flush with the top of the insulating layer 101 in the array region II, and the top of the capacitor lower electrode 114 on the sidewall of the contact hole 103 is flush with the top of the insulating layer 101 Therefore, when other structures are formed on the top of the capacitor lower electrode 114 and the top of the insulating layer 101 by the photolithography process, the unevenness on the top of the insulating layer 101 itself or the height between the top of the insulating layer 101 and the top of the capacitor lower electrode 114 is avoided. poor, resulting in defocusing of the lithography pattern, which is beneficial to improve the etching accuracy of the subsequent photolithography process and the dimensional accuracy of other structures formed subsequently, thereby helping to improve the yield of the semiconductor structure.
  • the capacitor lower electrodes 114 located on the sidewalls of the adjacent through holes 103 are parallel to each other, so the distance between the adjacent capacitor lower electrodes 114 is constant, which is beneficial to reduce the probability of a short circuit between adjacent capacitor lower electrodes 114, and Part of the insulating layer 101 is subsequently removed, and when a gap is formed between adjacent capacitor lower electrodes 114 , the size of the top opening of the gap and the size of the bottom opening of the gap can be kept the same, which is conducive to subsequent filling of the gap with material.

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Abstract

本申请实施例提供一种半导体结构的制作方法，制作方法包括：提供衬底，衬底具有***区和阵列区；在衬底上堆叠形成绝缘层和具有掩膜图形的掩膜层；以掩膜层为掩膜刻蚀绝缘层，以在阵列区形成贯穿绝缘层的接触孔，接触孔形成之后，保留掩膜层，在垂直于衬底表面的方向上，***区的掩膜层与阵列区的掩膜层存在厚度差；形成第一材料层，第一材料层至少覆盖阵列区的掩膜层表面和接触孔表面；形成第二材料层，第二材料层位于第一材料层上；以第二材料层为掩膜，刻蚀部分掩膜层，以降低***区的掩膜层与阵列区的掩膜层的厚度差；去除剩余的第二材料层、剩余的掩膜层和剩余的掩膜层上的第一材料层。

Description

半导体结构的制作方法
交叉引用
本申请基于申请号为202110126271.1、申请日为2021年01月29日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体领域，尤其涉及一种半导体结构的制作方法。
背景技术
半导体结构中的存储器是用来存储程序和各种数据信息的记忆部件，按存储器的使用类型可分为只读存储器和随机存取存储器。存储器通常包括电容以及与电容连接的晶体管，电容用来存储代表存储信息的电荷，晶体管是控制电容的电荷流入和释放的开关。
随着存储器工艺节点的不断缩小，相邻电容之间的距离逐渐缩短，为避免相邻电容之间的信号干扰的问题，对电容和半导体结构的尺寸精度提出了更高的要求，如何解决这个问题已成为存储器工艺优化的重要方向。
发明内容
本申请实施例解决的技术问题为提供一种半导体结构的制作方法，有利于提高半导体结构的尺寸精度，从而有利于提高半导体结构的良率。
为解决上述问题，本申请实施例提供一种半导体结构的制作方法，包括：提供衬底，所述衬底具有***区和阵列区；在所述衬底上 堆叠形成绝缘层和具有掩膜图形的掩膜层；以所述掩膜层为掩膜刻蚀所述绝缘层，以在所述阵列区形成贯穿所述绝缘层的接触孔，所述接触孔形成之后，保留所述掩膜层，在垂直于所述衬底表面的方向上，所述***区的所述掩膜层与所述阵列区的所述掩膜层存在厚度差；形成第一材料层，所述第一材料层至少覆盖所述阵列区的所述掩膜层表面和所述接触孔表面；形成第二材料层，所述第二材料层位于所述第一材料层上；以所述第二材料层为掩膜，刻蚀部分所述掩膜层，以降低所述***区的所述掩膜层与所述阵列区的所述掩膜层的厚度差；去除剩余的所述第二材料层、剩余的所述掩膜层和剩余的所述掩膜层上的所述第一材料层。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申明，附图中的图不构成比例限制。
图1至图5为一种半导体结构的制作方法各步骤对应的剖面结构示意图；
图6至图14为本申请第一实施例提供的一种半导体结构的制作方法各步骤对应的剖面结构示意图。
具体实施方式
由背景技术可知，现有技术中半导体结构的尺寸精度有待提高，半导体结构的良率有待提高。
图1至图5为一种半导体结构的制作方法各步骤对应的剖面结构示意图。
形成接触孔15的工艺步骤通常如图1至图2所示。
参考图1，提供衬底10，衬底10上具有***区I和阵列区II。在衬底10上依次堆叠形成绝缘层11和具有掩膜图形的掩膜层14，此时在垂直于衬底10表面的方向上，位于***区I的掩膜层12和位于阵列区II的掩膜层13的厚度相同。具体地，衬底10中具有位线、字线和电容接触窗等结构，在衬底10和部分绝缘层11之间还具有电连接层19，电连接层19位于绝缘层11和***区I的衬底10之间，电连接层19还位于后续形成的电容下电极和阵列区II的衬底10之间。绝缘层11包括依次堆叠的第一稳定层1、第一隔离层2、第二稳定层3、第二隔离层4和支撑层5。
进一步地，形成具有掩膜图形的掩膜层14的工艺步骤包括：在绝缘层11上形成初始掩膜层，对初始掩膜层进行图案-干法刻蚀，从而形成具有掩膜图形的掩膜层14。
参考图2，采用第一刻蚀工艺，以掩膜层14作为掩膜刻蚀绝缘层11以形成接触孔15时，掩膜层14也会受到刻蚀损伤。由于具有许多接触孔15的阵列区II的掩膜层13上的图案的图形尺寸比***区I的掩膜层12上的图案的图形尺寸小得多，即***区I与阵列区II的掩膜层14上的图案的图形尺寸存在差异，则第一刻蚀工艺对位于阵列区II的掩膜层13的刻蚀速率较大，对位于***区I的掩膜层12的刻蚀速率较小，则当形成接触孔15之后，阵列区II的掩膜层13被刻蚀的量大于***区I的掩膜层12被刻蚀的量，使得***区I的掩膜层12厚度大于阵列区II的膜层13的厚度。
形成电容下电极的工艺步骤通常如图3至图5所示。
参考图3，刻蚀去除位于绝缘层11上的掩膜层14(参考图2)。
由于***区I的掩膜层12的厚度大于阵列区II的掩膜层13的厚度，因而在相同的刻蚀时间内，位于***区I的绝缘层11上会有掩膜层12(参考图1)残留，形成凸点缺陷16，而且位于阵列区II的部分绝缘层11也会被刻蚀，使得在衬底10指向绝缘层11的方向III上，绝缘层11的宽度逐渐变窄，不利于保证绝缘层11的尺寸精度，因而影响后续形成的电容下电极的尺寸精度。
参考图4，形成保形覆盖的第一材料层17，第一材料层17位于接触孔15(参考图2)底部和侧壁，且还覆盖绝缘层11表面。由于凸点缺陷16的存在，使得位于***区I的第一材料层17在凸点缺陷16处会凸起。
参考图5，在去除位于绝缘层11顶部的第一材料层17以形成电容下电极时，为去除***区I的凸点缺陷16(参考图3)，会去除部分***区I的绝缘层11，使得***区I剩余的绝缘层11在与凸点缺陷16相对应的位置具有凸起。后续利用光刻工艺去去除部分绝缘层11以形成电容介质层和电容下电极等结构时，该凸起会导致光刻图案散焦，从而影响光刻工艺的刻蚀精度。
此外，位于阵列区II的绝缘层11包括多个被接触孔15间隔开的长条状绝缘层19，由于在衬底10指向绝缘层11的方向III上，长条状绝缘层19的宽度逐渐变窄，则方向III上，位于同一条状绝缘层19的两个侧壁的电容下电极18之间的距离逐渐变小，容易引起 相邻电容下电极18之间的短路现象。后续去除部分绝缘层11，在相邻电容下电极18之间形成间隙时，由于在衬底10指向绝缘层11的方向III上，位于同一条状绝缘层19的两个侧壁的电容下电极18之间的距离逐渐变小，则该间隙的顶部开口尺寸小于该间隙的底部开口尺寸，不便于后续向该间隙中填充材料。
为解决上述问题，本申请实施例提供一种半导体结构的制作方法，在去除位于绝缘层上的掩膜层之前，先在阵列区的掩膜层表面和接触孔表面形成第一材料层，然后在第一材料层上形成第二材料层，并以第二材料层为掩膜，刻蚀部分厚度***区的掩膜层，使得剩余***区的掩膜层顶部不高于阵列区的掩膜层上的第一材料层顶部，以降低剩余***区的掩膜层和阵列区的掩膜层之间的厚度差，从而在后续去除掩膜层和部分第一材料层以形成电容下电极的工艺中，能在完全去除位于绝缘层顶部的掩膜层的前提下，避免对阵列区的绝缘层的刻蚀，避免绝缘层的尺寸精度降低导致后续形成的电容下电极的尺寸精度降低和相邻电容下电极之间的短路现象，从而有利于提高电容下电极的尺寸精度，以降低相邻电容下电极之间的信号干扰问题，并有利于提高半导体结构的良率。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。
但是，即使没有这些技术细节和基于以下各实施例的种种变化和 修改，也可以实现本申请所要求保护的技术方案。
图6至图14为本申请第一实施例提供的一种半导体结构的制作方法各步骤对应的剖面结构示意图。
参考图6，提供衬底100，衬底100具有***区I和阵列区II；在衬底100上堆叠形成有绝缘层101和具有掩膜图形的掩膜层102，且位于***区I的掩膜层102为第一掩膜层112，位于阵列区II的掩膜层102为第二掩膜层122，第一掩膜层112的顶部与第二掩膜层122的顶部齐平。
本实施例中，半导体结构可以为存储器，衬底100中具有位线、字线和电容接触窗等结构，***区I位于阵列区II的周围，***区I用于实现存储器的输入输出电路与其他电学元件的电性连接，阵列区II用于实现存储器中不同导电结构之间的电性连接。
具体地，形成绝缘层101的工艺步骤包括：在衬底100上形成介质层161，在介质层161上形成支撑层151。介质层161的材料包括氧化硅或者氮化硅，支撑层151的材料可以为氮化硅或碳氮化硅。
本实施例中，形成介质层161的工艺步骤包括：在衬底100上依次堆叠形成第一稳定层111、第一隔离层121、第二稳定层131和第二隔离层141，有利于后续形成深宽比较大的接触孔。在其他实施例中，介质层161也可以为单层结构。
具体地，第一稳定层111和第二稳定层131的材料包括氮化硅或碳氮化硅，后续形成的电容下电极位于第二稳定层131和支撑层151的侧壁，第二稳定层131和支撑层151均可以对电容下电极起到支撑 作用，以避免电容下电极发生倾斜或坍塌。本实施例中，第一稳定层111、第二稳定层131和支撑层151的材料相同，均为氮化硅。在其他实施例中，第一稳定层111、第二稳定层131和支撑层151的材料可以不同。此外，由于后续需要去除部分区域的支撑层151，因此，为保证支撑层151能够起到对电容下电极的加固作用，支撑层151的厚度可以大于第一稳定层111的厚度和第二稳定层131的厚度。
后续为形成电容上电极、电容介质层等结构的过程中，第一隔离层121以和第二隔离层141会被去除，因此，可以采用易于被去除的材料作为第一隔离层121以及第二隔离层141的材料。第一隔离层121及第二隔离层141的材料可以为氧化硅。本实施例中，第一隔离层121及第二隔离层141的材料相同，在其他实施例中，第一隔离层121及第二隔离层141的材料可以不同。
本实施例中，第一隔离层121和第二隔离层141的材料相同，可以均为氧化硅。在其他实施例中，第一隔离层121及第二隔离层141的材料也可以不同。
本实施例中，在衬底100和部分绝缘层101之间还具有电连接层109，电连接层109位于绝缘层101和***区I的衬底100之间，电连接层109还位于后续形成的电容下电极和阵列区II的衬底100之间。电连接层109的材料可以为多晶硅或者金属材料。
参考图7，以掩膜层102为掩膜刻蚀绝缘层101，以在阵列区II形成贯穿绝缘层101的接触孔103，接触孔103形成之后，保留掩膜层102，由于第一掩膜层112和第二掩膜层122上的图案的图形尺寸 存在差异，则在垂直于衬底100表面的方向III上，第一掩膜层112和第二掩膜层122之间存在厚度差。具体地，第一掩膜层112顶部高于第二掩膜层122顶部。
本实施例中，掩膜层102的材料包括多晶硅，且在垂直于衬底100表面的方向上，第一掩膜层112和第二掩膜层122之间的厚度差可以为100～500nm。第一掩膜层112和第二掩膜层122之间的厚度差与形成的接触孔103的深宽比有关，在一个例子中，第一掩膜层112和第二掩膜层122之间的厚度差为300nm。在其他实施例中，掩膜层102的材料还可以是其他与绝缘层101之间具有较高刻蚀选择比的材料。
参考图8，形成第一材料层104，第一材料层104至少覆盖第二掩膜层122表面和接触孔103(参考图7)表面，后续去除第一掩膜层112和第二掩膜层122时，也会将高于绝缘层101顶部的第一材料层104去除，则剩余的第一材料层104可以作为电容下电极，在保证第一掩膜层112和第二掩膜层122均被完全去除，且不损伤绝缘层101的前提下，有利于提高形成的电容下电极的尺寸精度，从而提高半导体结构的良率。
本实施例中，第一材料层104还覆盖第一掩膜层112表面，在其他实施例中，第一材料层104可以只位于第二掩膜层122表面和接触孔103表面。
具体地，第一材料层104可以通过沉积工艺形成，其中沉积工艺包括化学气相沉积或者原子层沉积。第一材料层104为电容电极材 料，其中，电容电极材料包括氮化钛、钛、多晶硅或者钨等导电材料。
本实施例中，通过沉积工艺在第一掩膜层112和第二掩膜层122的表面均沉积第一材料层104，后续去除掩膜层102时，会将部分第一材料层104也同时去除以形成电容下电极，有利于在保证后续形成的电容下电极的尺寸精度满足要求的情况下，通过同步去除掩膜层102和部分第一材料层104来简化制备半导体结构的工艺步骤。
参考图10，形成第二材料层115，第二材料层115位于阵列区II的第一材料层104上，且阵列区II的第一材料层104围成多个通孔，第二材料层115填充满该多个通孔，第二材料层115的顶面低于***区I的第一材料层104的顶面。在其他实施例中，第二材料层115的顶面也可以与***区I的第一材料层104的顶面齐平。
由于第二材料层115覆盖在阵列区II的第一材料层104表面，且填充满第一材料层104围成的多个通孔，在后续以第二材料层115掩膜刻蚀第一掩膜层112和***区I的第一材料层104时，第二材料层115能对阵列区II的第一材料层104起到良好的保护作用，以保证后续形成的电容下电极的尺寸精度。
本实施例中，形成第二材料层115的工艺步骤包括：参考图9，形成初始第二材料层125，初始第二材料层125覆盖第一材料层104表面，且初始第二材料层125顶表面高于第一材料层104最高表面；参考图10，去除部分初始第二材料层125，以露出第一材料层104最高表面，形成第二材料层115。
本实施例中，第二材料层115为可流动式介质，由于可流动式介 质具有较好的流动性和填充性，有利于第二材料层115均匀且没有间隙的覆盖第一材料层104表面，且填充满接触孔103，在后续去除掩膜层102和部分第一材料层104，以形成电容下电极时，填充满接触孔103的第二材料层115可以保护接触孔103底部的衬底100，使得衬底100不会与去除掩膜层102和部分第一材料层104时产生的残渣接触，从而提高了半导体结构的良率。
进一步地，可流动式介质包括光刻胶或者包含Si-H键、Si-N键及N-H键的电介质，形成第二材料层115的方法包括化学气相沉积工艺或者旋转涂覆工艺。
具体地，以第二材料层115为光刻胶进行举例说明。参考图9，形成初始第二材料层125的方法为：采用旋转涂覆工艺，在第一材料层104上涂覆光刻胶层，且光刻胶层的顶部高于第一材料层104最高表面。由于半导体结构的制备工艺中，半导体结构整体的尺寸较小，在***区I的第一材料层104和阵列区II的第一材料层104的表面均涂覆光刻胶层，不用区分***区I和阵列区II，同时由于工艺上操作更简便，有利于简化制备半导体结构的工艺步骤。
在其他实施例中，参考图10，也可以仅在阵列区II的第一材料层104的表面形成第二材料层115。具体地，可以仅在阵列区II的第一材料层104上涂覆光刻胶层，且光刻胶层的顶部低于阵列区II的第一材料层104顶部。
在其他实施例中，当第一掩膜层112的表面没有形成第一材料层104时，形成第二材料层115的工艺步骤可以包括：在第一掩膜层112 表面和第一材料层104表面均形成初始第二材料层125；去除部分初始第二材料层125至露出第一掩膜层112，剩余的初始第二材料层125为第二材料层115。
本实施例中，去除部分初始第二材料层125，以露出第一材料层104最高表面的方法为刻蚀。具体地，可采用干法刻蚀工艺对部分初始第二材料层125进行刻蚀至露出第一材料层104最高表面，刻蚀气体包括氧气、氮气或者氢气。
在一个实施例中，以第一材料层104最高表面为刻蚀停止层，采用含氧的等离子体去除部分初始第二材料层125。因为初始第二材料层125的材料为光刻胶，含氧的等离子体可以与光刻胶快速反应，生成二氧化碳、一氧化碳和水，则采用含氧的等离子体与初始第二材料层125的反应迅速，可以较快地去除部分初始第二材料层125，提高了制备半导体结构的效率。
在其他实施例中，去除部分初始第二材料层125以露出第一材料层104最高表面的方法也可以为化学机械研磨。
参考图11，以第二材料层115为掩膜，刻蚀部分第一掩膜层112，以降低第一掩膜层112与第二掩膜层122的厚度差。具体地，使得剩余的第一掩膜层112的顶部a不高于位于第二掩膜层122上的第一材料层104的顶部b。
本实施例中，由于第一掩膜层112的顶部和侧壁也形成有第一材料层104，因而在以第二材料层115为掩膜刻蚀部分厚度的第一掩膜层112的工艺步骤中，还包括刻蚀位于第一掩膜层112上的第一材料 层104。
本实施例中，刻蚀部分第一掩膜层112和位于第一掩膜层112上的第一材料层104的方法为干法刻蚀工艺。在一个例子中，第一掩膜层112的材料为多晶硅，第一材料层104的材料为氮化钛或者钛，同一干法刻蚀工艺对多晶硅的刻蚀速率和对氮化钛或者钛的刻蚀速率的差异较小，且不会损伤第一掩膜层112，则可以通过同一刻蚀工艺同时将部分第一掩膜层112和部分第一材料层104去除，有利于简化制备半导体结构的工艺步骤。具体地，可以采用含氯和/或含氟的等离子体刻蚀部分第一掩膜层112和部分第一材料层104。因为第一掩膜层112的材料为多晶硅，第一材料层104的材料为氮化钛或者钛，则第一掩膜层112和第一材料层104均易与含氯和/或含氟的等离子体发生反应，可以较快地去除部分第一掩膜层112和部分第一材料层104，有利于提高半导体结构的制备效率。在其他实施例中，刻蚀第一掩膜层112和位于第一掩膜层112上的第一材料层104的方法也可以为湿法刻蚀工艺。
在其他实施例中，也可以以第二材料层115为掩膜先刻蚀掉位于第一掩膜层112上的第一材料层104，然后再以第二材料层115和剩余的第一材料层104为掩膜刻蚀部分厚度的第一掩膜层112，使得剩余的第一掩膜层112的顶部不高于第二掩膜层122上的第一材料层104的顶部。
本实施例中，剩余的第一掩膜层112的顶部a不高于位于第二掩膜层122上的第一材料层104的顶部b。在一个例子中，剩余的第一 掩膜层112的顶部与第二掩膜层122的顶部齐平，有利于消除剩余的第一掩膜层112和第二掩膜层122之间的厚度差异，从而在后续去除掩膜层102和部分第一材料层104的工艺步骤中，使得第一掩膜层112、第二掩膜层122和高于绝缘层101顶部的第一材料层104能够同时被完全去除，避免部分第一掩膜层112残留在***区I的绝缘层101上，以及避免位于阵列区II的部分绝缘层101被去除，则在衬底10指向绝缘层101的方向III上，避免绝缘层101的宽度逐渐变窄，有利于保证绝缘层101的尺寸精度，从而有利于保证位于绝缘层101侧壁的电容下电极的尺寸精度，避免相邻电容下电极之间的距离较近，从而降低相邻电容下电极之间发生短路现象的概率，降低相邻电容下电极之间的信号干扰问题，以提高半导体结构的良率。
需要说明的是，第一材料层104为薄层结构，则在后续去除第一掩膜层112、第二掩膜层122和高于绝缘层101顶部的第一材料层104的工艺步骤中，第一材料层104对刻蚀时间的影响很小，可以认为，在相同的刻蚀时间内，第一掩膜层112和第二掩膜层122被完全去除时，高于绝缘层101顶部的第一材料层104也被完全去除。
此外，由于后续形成的电容下电极的尺寸精度得到了提高，则后续去除第一隔离层121以及第二隔离层141以形成电容介质层和电容上电极等结构时，电容上电极和电容介质层依据尺寸精度较高的电容下电极成型，有利于提高形成的电容上电极和电容介质层的尺寸精度。
结合参考图11和图14，去除剩余的第二材料层115、剩余的掩 膜层102和剩余的掩膜层102上的第一材料层104，以形成电容下电极114。
具体地，形成电容下电极114的工艺步骤包括：
参考图12，刻蚀剩余的部分第二材料层115，以露出位于第二掩膜层122顶部的第一材料层104。本实施例中，刻蚀该部分第二材料层115的刻蚀工艺与前述刻蚀部分初始第二材料层125的刻蚀工艺相同，位于第二掩膜层122顶部的第一材料层104为刻蚀停止层，采用含氧的等离子体去除剩余的部分第二材料层115。
需要说明的是，保留位于接触孔103(参考图7)中的第二材料层115，目的是便于后续以保留的第二材料层115为掩膜，去除保留的第二材料层115未遮蔽的第一掩膜层112、第二掩膜层122以及部分第一材料层104。
参考图13，以剩余的第二材料层115为掩膜，去除剩余的第一掩膜层112第二掩膜层122、剩余的第一掩膜层112上的第一材料层104和第二掩膜层122上的第一材料层104，以形成电容下电极114。本实施例中，也可采用干法刻蚀工艺去除剩余的第一掩膜层112、第二掩膜层122和部分第一材料层104。
参考图14，去除剩余的第二材料层115。本实施例中，采用第三刻蚀工艺去除剩余的第二材料层115，第三刻蚀工艺与前述刻蚀部分初始第二材料层125的刻蚀工艺相同。
本实施例中，在去除位于绝缘层101上的掩膜层102(参考图7)之前，至少在位于阵列区II的掩膜层102表面和接触孔103表面都 形成第一材料层104，用于后续做半导体结构中的电容下电极114；然后在第一材料层104上形成第二材料层115，以第二材料层115为掩膜刻蚀部分厚度的掩膜层102，以降低***区I的掩膜层102与阵列区II的掩膜层102之间的厚度差，从而有利于形成如图14所示的半导体结构。
参考图14，由于位于***区I的绝缘层101的顶部与位于阵列区II的绝缘层101的顶部齐平，且位于接触孔103侧壁的电容下电极114的顶部与绝缘层101的顶部齐平，因而后续利用光刻工艺在电容下电极114的顶部与绝缘层101的顶部形成其他结构时，避免由于绝缘层101自身顶部的不平或者绝缘层101顶部与电容下电极114顶部之间的高度差，导致光刻图案散焦，因而有利于提高后续光刻工艺的刻蚀精度和提高后续形成的其他结构的尺寸精度，从而有利于提高半导体结构的良率。
此外，位于相邻通孔103侧壁的电容下电极114之间相互平行，因而相邻电容下电极114之间的距离恒定，有利于降低相邻电容下电极114之间发生短路的概率，且后续去除部分绝缘层101，在相邻电容下电极114之间形成间隙时，间隙的顶部开口尺寸与间隙的底部开口尺寸可以保持一致，有利于后续向间隙中填充材料。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精神和范围内，均可作各自更动与修改，因此本申请的保 护范围应当以权利要求限定的范围为准。

Claims (13)

  1. 一种半导体结构的制作方法，其中，包括：
    提供衬底，所述衬底具有***区和阵列区；
    在所述衬底上堆叠形成绝缘层和具有掩膜图形的掩膜层；
    以所述掩膜层为掩膜刻蚀所述绝缘层，以在所述阵列区形成贯穿所述绝缘层的接触孔，所述接触孔形成之后，保留所述掩膜层，在垂直于所述衬底表面的方向上，所述***区的所述掩膜层与所述阵列区的所述掩膜层存在厚度差；
    形成第一材料层，所述第一材料层至少覆盖所述阵列区的所述掩膜层表面和所述接触孔表面；
    形成第二材料层，所述第二材料层位于所述第一材料层上；
    以所述第二材料层为掩膜，刻蚀部分所述掩膜层，以降低所述***区的所述掩膜层与所述阵列区的所述掩膜层的厚度差；
    去除剩余的所述第二材料层、剩余的所述掩膜层和剩余的所述掩膜层上的所述第一材料层。
  2. 根据权利要求1所述的半导体结构的制作方法，其中,所述第一材料层还覆盖所述***区的所述掩膜层表面；以所述第二材料层为掩膜，刻蚀部分所述掩膜层的工艺步骤中，还包括刻蚀位于所述***区的所述掩膜层上的所述第一材料层。
  3. 根据权利要求2所述的半导体结构的制作方法，其中，形成所述第二材料层的工艺步骤包括：
    形成初始第二材料层，所述初始第二材料层覆盖所述第一材料层 表面，且所述初始第二材料层顶表面高于所述第一材料层最高表面；
    去除部分所述初始第二材料层，以露出所述第一材料层最高表面，形成所述第二材料层。
  4. 根据权利要求2所述的半导体结构的制作方法，其中,所述第二材料层仅覆盖所述阵列区的所述第一材料层。
  5. 根据权利要求3或4所述的半导体结构的制作方法，其中,所述第二材料层为可流动式介质。
  6. 根据权利要求5所述的半导体结构的制作方法，其中,所述可流动式介质包括光刻胶或者包含Si-H键、Si-N键及N-H键的电介质。
  7. 根据权利要求6所述的半导体结构的制作方法，其中,形成所述第二材料层的方法包括化学气相沉积工艺或者旋转涂覆工艺。
  8. 根据权利要求1所述的半导体结构的制作方法，其中,所述掩膜层的材料包括多晶硅。
  9. 根据权利要求1所述的半导体结构的制作方法，其中,所述第一材料层为电容电极材料。
  10. 根据权利要求1所述的半导体结构的制作方法，其中,去除剩余的所述第二材料层、剩余的所述掩膜层和剩余的所述掩膜层上的所述第一材料层的工艺步骤包括：
    刻蚀剩余的部分所述第二材料层，以露出剩余的所述掩膜层上的所述第一材料层；
    以剩余的所述第二材料层为掩膜，去除剩余的所述掩膜层和剩余的所述掩膜层上的所述第一材料层；去除剩余的所述第二材料层。
  11. 根据权利要求1所述的半导体结构的制作方法，其中,去除部分所述第二材料层，以露出所述第一材料层最高表面的方法包括刻蚀或者化学机械研磨。
  12. 根据权利要求1所述的半导体结构的制作方法，其中，形成所述绝缘层的工艺步骤包括：在所述衬底上形成介质层，在所述介质层上形成支撑层。
  13. 根据权利要求12所述的半导体结构的制作方法，其中，形成所述介质层的工艺步骤包括：在所述衬底上依次堆叠形成第一稳定层、第一隔离层、第二稳定层和第二隔离层。
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