WO2022151572A1 - 一种降低塑封晶圆翘曲的封装结构及其制造方法 - Google Patents

一种降低塑封晶圆翘曲的封装结构及其制造方法 Download PDF

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WO2022151572A1
WO2022151572A1 PCT/CN2021/079256 CN2021079256W WO2022151572A1 WO 2022151572 A1 WO2022151572 A1 WO 2022151572A1 CN 2021079256 W CN2021079256 W CN 2021079256W WO 2022151572 A1 WO2022151572 A1 WO 2022151572A1
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chip
manufacturing
board
initial
plastic
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PCT/CN2021/079256
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English (en)
French (fr)
Inventor
曹立强
徐成
孙鹏
耿菲
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华进半导体封装先导技术研发中心有限公司
上海先方半导体有限公司
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Priority to US18/270,840 priority Critical patent/US20240071873A1/en
Publication of WO2022151572A1 publication Critical patent/WO2022151572A1/zh

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Definitions

  • the invention relates to the technical field of semiconductors, and in particular, to a package structure and a manufacturing method thereof for reducing the warpage of a plastic packaged wafer.
  • Warpage brings risks such as chipping, scratching, etc. to chip manufacturing, and may even lead to parameter drift.
  • one aspect of the present invention provides a package structure for reducing the warpage of a plastic-packaged wafer, including:
  • an adapter board the first surface of which is arranged with a first redistribution layer, and the second surface of which is arranged with external solder balls;
  • a plastic encapsulation layer which covers the chip but exposes the first surface of the chip.
  • the chip includes a plurality of identical, similar or different chips.
  • an underfill material is provided between the chip and the first redistribution layer.
  • Another aspect of the present invention provides a method for manufacturing the package structure, comprising:
  • the chip is mounted on the first surface of the initial transfer board, and the pad of the chip is electrically connected to the first redistribution layer;
  • the first surface of the first slide includes a lithography pattern, and the lithography pattern matches the non-patch area on the initial transition board.
  • thermal expansion coefficient of the material of the first carrier sheet is the same as or close to that of silicon.
  • the surface of the photolithography pattern is coated with a bonding material.
  • the bonding material is coated on the surface of the photolithography pattern by a rolling process.
  • the removal of the first slide comprises:
  • the manufacturing method also includes:
  • a second carrier is bonded to the first surface of the chip prior to the TSV exposure operation, and the second carrier is removed before the first carrier is removed.
  • the invention provides a packaging structure and a manufacturing method for reducing the warpage of a plastic-sealed wafer.
  • a material with a thermal expansion coefficient close to that of silicon such as silicon wafer or glass, is mounted in the non-chip area, so as to reduce the plastic sealing during plastic sealing.
  • the proportion of plastic sealing material in the process reduces warpage.
  • the plastic sealing area is smaller than the wafer size, it is also beneficial to reduce the amount of plastic packaging material used; after the plastic packaging is thinned, the plastic packaging material mainly fills the gap between the chips and the gap with the edge protection area, and due to the use of silicon and other materials As an edge filling material, its edge can be used for wafer alignment after plastic sealing, which is convenient for subsequent processes.
  • FIG. 1 shows a schematic structural diagram of a package structure for reducing warpage of a plastic encapsulated wafer according to an embodiment of the present invention
  • FIG. 2 shows a schematic flowchart of a method for manufacturing a packaging structure for reducing warpage of a plastic-encapsulated wafer according to an embodiment of the present invention
  • 3a-3m are schematic cross-sectional views illustrating a process of forming a package structure for reducing warpage of a plastic encapsulated wafer according to an embodiment of the present invention.
  • the present invention mounts a material with a thermal expansion coefficient close to that of silicon, such as silicon wafer or glass, in the non-chip area before plastic sealing of the wafer, so as to reduce the warpage and reduce the warpage. Reduce the use of molding compound.
  • a manufacturing method of a package structure includes:
  • an initial interposer board is formed.
  • the formation of the initial adapter board 101 includes:
  • TSVs 111 are formed on the first surface of the silicon wafer, the TSVs 111 do not penetrate the silicon wafer, and keep a certain distance from the second surface of the silicon wafer 101, and the TSVs 111 can pass through Photolithography and etching process formation;
  • a passivation layer or direct thermal oxidation is deposited on the surface of the TSV 111.
  • the material of the passivation layer is silicon oxide or silicon nitride, etc.;
  • a seed layer is made above the passivation layer, and the seed layer can be made of metals such as titanium, copper, aluminum, silver, gold, palladium, thallium, tin, nickel;
  • Electroplating fill metal in the TSV the metal may be copper metal;
  • a first redistribution layer 112 may also be formed on the first surface of the silicon wafer to be electrically connected to the through silicon via 111;
  • a first slide is fabricated.
  • a photolithography pattern 011 is formed on the first surface of the first carrier 001 by a photolithography process, so as to avoid bonding the first carrier 001 to the When the initial adapter plate 101 is on, the patch area is blocked.
  • the material of the first carrier is selected from a material with a thermal expansion coefficient close to or the same as that of silicon, such as glass, silicon, etc. .
  • a bonding material is applied on the surface of the lithography pattern by a process such as rolling glue;
  • step 203 as shown in FIG. 3c, the first slide is bonded.
  • the first slide 001 is bonded to the non-patch area of the initial transfer board 101. Due to the presence of the lithography image 011 and the bonding material, the first slide 001 and the initial transfer There is a certain gap between the patch areas of the connecting board 101;
  • the first slide is cut. Cut the first slide 001 to expose the patch area of the initial adapter board 101.
  • the first slide 001 can be cut by laser, and laser cutting can be set to cut Since there is a certain gap between the first carrier 001 and the patch area of the initial adapter board 101, as long as an appropriate cutting depth is set, damage to the patch area can be avoided;
  • the chip is mounted.
  • the chip 102 is mounted on the patch area on the first surface of the initial interposer 101, so that the pads of the chip 102 are electrically connected to the first redistribution layer 112 or the through silicon via 111; in one implementation of the present invention
  • an underfill 121 is filled in the gap between the chip 102 and the initial adapter board 101;
  • the chip may be a CPU, DSP, GPU, or FPGA. It can also be a memory chip such as DRAM, Flash, etc., or other types of chips or sensors such as SOC (such as MEMS sensors, etc.), and a package structure can contain one or more identical, similar or different chips;
  • a plastic encapsulation layer is formed.
  • the plastic sealing layer 103 covers the chip 102; in an embodiment of the present invention, the material of the plastic sealing layer 103 may be a resin material or the like;
  • step 207 as shown in FIG. 3g, the plastic sealing layer is thinned.
  • the plastic sealing layer 103 is thinned by grinding, so that the first surface of the chip 102 is exposed;
  • step 208 as shown in Figure 3h, circumscribed solder balls are formed.
  • the second surface of the initial interposer 101 is thinned so that the TSVs 111 are exposed, and then an electroplating seed layer is formed on the second surface of the initial interposer 101.
  • the specific formation method may be chemical plating, PVD
  • a layer of 200-1000 angstroms of chromium and a layer of 500-3000 angstroms of copper can be deposited by PVD to form the electroplating seed layer, and then patterned electroplating on the electroplating seed layer
  • the second redistribution layer 113 is formed so as to be electrically connected to the TSV.
  • the specific patterned electroplating method further includes steps of gluing, drying, photolithography, developing, electroplating, and degumming.
  • external solder balls 114 may also be formed on the external pads of the second redistribution layer 113 by ball-planting, electroplating and other processes;
  • step 209 as shown in Figure 3i, the first slide is removed. cutting along the edge of the plastic encapsulation layer 103 to cut off the first carrier sheet 001 and the non-patch area of the interposer board;
  • step 210 a single package structure is formed by dicing.
  • FIG. 3j to FIG. 3m illustrate another process for forming the external solder balls.
  • a bonding solution can be selected to complete the related processes, including:
  • a second slide is bonded.
  • a second carrier 002 is bonded on the first surface of the chip 102, wherein the second carrier 002 may be a carrier material such as wafer or glass, and is bonded to the first surface of the chip through an adhesive material, so The size of the second carrier board is not smaller than the initial adapter board, and the bonding material is a detachable bonding bonding material such as heating and lighting;
  • solder balls are formed.
  • the second surface of the initial interposer 101 is thinned so that the TSVs 111 are exposed, and then an electroplating seed layer is formed on the second surface of the initial interposer 101.
  • the specific formation method may be chemical plating, PVD
  • a layer of 200-1000 angstroms of chromium and a layer of 500-3000 angstroms of copper can be deposited by PVD to form the electroplating seed layer, and then patterned electroplating on the electroplating seed layer
  • the second redistribution layer 113 is formed so as to be electrically connected to the TSV.
  • the specific patterned electroplating method further includes steps of gluing, drying, photolithography, developing, electroplating, and degumming.
  • external solder balls 114 may also be formed on the external pads of the second redistribution layer 113 by ball-planting, electroplating and other processes;
  • the second slide is removed.
  • the specific removal method can be realized by heating debonding, laser irradiation debonding, etc., according to the characteristics of the bonding material, and further cleaning processes can be used to completely remove the bonding material;
  • the first slide is removed. Cut along the edge of the plastic sealing layer 103 to cut off the first carrier 001 and the non-patch area of the interposer.
  • the finally formed package structure is shown in FIG. 1 , including: an adapter board 101 , a chip 102 and a plastic sealing layer 103 .
  • the chip 102 is mounted on the first surface of the adapter board 101 and is electrically connected to the through silicon vias 111 on the adapter board 101.
  • the chip 102 is connected to An underfill material 121 is also filled between the transfer boards 101.
  • the chip 102 is electrically connected to the through silicon vias 111 through a first redistribution layer, and the transfer board
  • the second surface includes external solder balls so that the package can be mounted on the substrate, wherein the external solder balls 114 are arranged on the external pads of the second redistribution layer 113 formed on the
  • the second surface of the interposer 101 is electrically connected to the TSVs 111 , and the bumps are formed by thinning the interposer so that the TSVs are exposed.
  • the plastic packaging layer 103 covers the chip 102 but exposes the first surface of the chip 102 .
  • the invention provides a packaging structure for reducing the warpage of a plastic-sealed wafer and a manufacturing method thereof.
  • a material with a thermal expansion coefficient close to that of silicon such as silicon wafer or glass, is mounted in the non-chip area, so as to reduce the plastic sealing during plastic sealing.
  • the proportion of plastic sealing material in the process reduces warpage.
  • the plastic sealing area is smaller than the wafer size, it is also beneficial to reduce the amount of plastic packaging material used; after the plastic packaging is thinned, the plastic packaging material mainly fills the gap between the chips and the gap with the edge protection area, and due to the use of silicon and other materials As an edge filling material, its edge can be used for wafer alignment after plastic sealing, which is convenient for subsequent processes.

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Abstract

一种降低塑封晶圆翘曲的封装结构，包括转接板（101），贴装于转接板上的芯片（102），以及包覆芯片的第一塑封层（103），转接板上设置有硅通孔（111），其第一表面及第二表面分别设置有与硅通孔电连接的外接焊球（114）和/或外接焊盘。该封装结构的制作过程包括：在转接板第一表面工艺完成后，在其第一表面键合第一载片（001），然后切割所述第一载片，露出贴片区域，然后进行贴片等后续工艺，最后将第一载片切割去除，完成封装。

Description

一种降低塑封晶圆翘曲的封装结构及其制造方法 技术领域
本发明涉及半导体技术领域，特别涉及一种降低塑封晶圆翘曲的封装结构及其制造方法。
背景技术
随着半导体技术的发展，集成电路尺寸持续减小，人们对于集成电路的封装要求越来越高。
随着芯片的厚度的减小，在封装过程中，对于晶圆的研磨量则越来越大，这就使得晶圆自身硬度降低的同时，应力却更大，使得晶圆的翘曲越来越严重。翘曲会给芯片制造带来碎片、划伤等风险，甚至可能导致参数漂移。
因此，有效地控制晶圆翘曲有助于提高封装的可靠性。
发明内容
针对现有技术中的部分或全部问题，本发明一方面提供一种降低塑封晶圆翘曲的封装结构，包括：
转接板，其第一表面布置有第一重布线层，第二表面布置有外接焊球；
芯片，其第二表面包括焊盘，所述焊盘电连接至所述第一重布线层；以及
塑封层，其包覆所述芯片，但露出所述芯片的第一表面。
进一步地，所述芯片包括多个相同、同类或不同的芯片。
进一步地，所述芯片与所述第一重布线层之间设置有底层填充料。
本发明另一方面提供所述封装结构的制造方法，包括：
在硅片的第一表面形成硅通孔以及第一重布线层，得到初始转接板；
将第一载片键合至所述初始转接板上；
切割所述第一载片，露出所述初始转接板的贴片区域；
将芯片贴片至初始转接板的第一表面，所述芯片的焊盘与第一重布线层电连接；
形成塑封层；
减薄所述塑封层，露出所述芯片的第一表面；
减薄所述初始转接板的第二表面，使得所述硅通孔露头；
在所述初始转接板的第二表面上形成第二重布线层以及外接焊球，电连接至所述硅通孔；
去除第一载片；以及
切割形成单颗封装结构。
进一步地，所述第一载片的第一表面包括光刻图形，所述光刻图形与所述初始转接板上的非贴片区域吻合。
进一步地，所述第一载片的材料的热膨胀系数与硅相同或接近。
进一步地，所述光刻图形表面涂覆有键合材料。
进一步地，所述键合材料通过滚胶工艺，涂覆于所述光刻图形表面。
进一步地，所述第一载片的去除包括：
沿所述塑封层的边沿切割，切除所述第一载片以及转接板的非贴片区。
进一步地，所述制造方法还包括：
在硅通孔露头操作前，在所述芯片的第一表面键合第二载片，并在去除所述第一载片前，去除所述第二载片。
本发明提供的一种降低塑封晶圆翘曲的封装结构及其制造方法，在晶圆塑封前，在非贴片区域贴装硅片或者玻璃等热膨胀系数与硅接近的材料，降低塑封时塑封工艺中塑封料占比，降低翘曲。此外，由于塑封区域小于晶圆尺寸，还有利于减小塑封料使用的量；塑封减薄后，塑封料填充的主要是芯片间的间隙以及与边缘保护区域的间隙，且由于采用硅等材料作为边缘填充材料，其边缘可以在塑封后需工艺后用于晶圆对位，便于后续工艺的进行。
附图说明
为进一步阐明本发明的各实施例的以上和其它优点和特征，将参考附图来呈现本发明的各实施例的更具体的描述。可以理解，这些附图只描绘本发明的典型实施例，因此将不被认为是对其范围的限制。在附图 中，为了清楚明了，相同或相应的部件将用相同或类似的标记表示。
图1示出本发明一个实施例的一种降低塑封晶圆翘曲的封装结构的结构示意图；
图2示出本发明一个实施例的一种降低塑封晶圆翘曲的封装结构的制造方法的流程示意图；以及
图3a-3m示出根据本发明一个实施例形成一种降低塑封晶圆翘曲的封装结构的过程剖面示意图。
具体实施方式
以下的描述中，参考各实施例对本发明进行描述。然而，本领域的技术人员将认识到可在没有一个或多个特定细节的情况下或者与其它替换和/或附加方法、材料或组件一起实施各实施例。在其它情形中，未示出或未详细描述公知的结构、材料或操作以免模糊本发明的发明点。类似地，为了解释的目的，阐述了特定数量、材料和配置，以便提供对本发明的实施例的全面理解。然而，本发明并不限于这些特定细节。此外，应理解附图中示出的各实施例是说明性表示且不一定按正确比例绘制。
在本说明书中，对“一个实施例”或“该实施例”的引用意味着结合该实施例描述的特定特征、结构或特性被包括在本发明的至少一个实施例中。在本说明书各处中出现的短语“在一个实施例中”并不一定全部指代同一实施例。
需要说明的是，本发明的实施例以特定顺序对工艺步骤进行描述，然而这只是为了阐述该具体实施例，而不是限定各步骤的先后顺序。相反，在本发明的不同实施例中，可根据工艺的调节来调整各步骤的先后顺序。
针对现有的封装技术存在工艺过程翘曲较大的问题，本发明在晶圆塑封前，在非贴片区域贴装硅片或者玻璃等热膨胀系数与硅接近的材料，以降低翘曲，并减小塑封料的使用。下面结合实施例附图，对本发明的具体方案做进一步描述。
图2及图3a-3i分别示出根据本发明一个实施例形成一种封装结构的流程图以及过程剖面示意图。如图所示，一种封装结构的制造方法，包括：
首先，在步骤201，如图3a所示，形成初始转接板。所述初始转接板101的形成包括：
在硅片的第一表面形成硅通孔111，所述硅通孔111不穿透所述硅片，与所述硅片101的第二表面保持一定的距离，所述硅通孔111可通过光刻和刻蚀工艺形成；
在所述硅通孔111的表面沉积钝化层或直接热氧化，在本发明的一个实施例中，所述钝化层的材料为氧化硅或氮化硅等；
通过物理溅射、磁控溅射或蒸镀工艺，在所述钝化层上方制作种子层，种子层可采用钛、铜、铝、银、金、钯、铊、锡、镍等金属制作；
在所述硅通孔内电镀填充金属，所述金属可以为铜金属；以及
采用干法刻蚀或湿法腐蚀工艺，去除硅片表面绝缘层，使得填充的金属露头，形成初始转接板；
在本发明的一个实施例中，也可以在所述硅片的第一表面形成第一重布线层112，使其电连接至所述硅通孔111；
接下来，在步骤202，如图3b所述，制作第一载片。根据所述初始转接板101的第一表面的非贴片区域，在第一载片001的第一表面，通过光刻工艺形成光刻图形011，以避免将第一载片001键合至所述初始转接板101上时，遮挡住贴片区域，在本发明的一个实施例中，所述第一载片的材料选用与硅的热膨胀系数接近或相同的材料，例如玻璃、硅等。为了将所述第一载片001键合至所述初始转接板上，通过滚胶等工艺在所述光刻图形表面涂覆键合材料；
接下来，在步骤203，如图3c所示，键合第一载片。将所述第一载片001键合至所述初始转接板101的非贴片区域，由于所述光刻图像011以及键合材料的存在，所述第一载片001与所述初始转接板101的贴片区域之间有一定间隙；
接下来，在步骤204，如图3d所示，切割第一载片。切割所述第一载片001，露出所述初始转接板101的贴片区域，在本发明的一个实施例中，可通过激光对所述第一载片001进行切割，激光切割可以设置切割深度，由于所述第一载片001与所述初始转接板101的贴片区域之间有一定间隙，因此，只要设置了合适的切割深度，就可避免对贴片区域造成损坏；
接下来，在步骤205，如图3e所示，芯片贴片。将芯片102贴片至初始转接板101的第一表面上的贴片区域，使得所述芯片102的焊盘与第一重布线层112或硅通孔111电连接；在本发明的一个实施例中，贴片完成后，在所述芯片102与初始转接板101的间隙内填充底部填充料121；在本发明的一个实施例中，所述芯片可以为为CPU、DSP、GPU、FPGA等逻辑芯片，也可以为DRAM、Flash等存储芯片，还可以为SOC等其他类型芯片或传感器(如MEMS传感器等)，一个封装结构上可以包含一个或多个相同、同类或不同的芯片；
接下来，在步骤206，如图3f所示，形成塑封层。所述塑封层103包覆所述芯片102；在本发明的一个实施例中，所述塑封层103的材料可以为树脂材料等；
接下来，在步骤207，如图3g所示，减薄塑封层。通过研磨减薄所述塑封层103，使得芯片102的第一表面露出；
接下来，在步骤208，如图3h所示，形成外接焊球。减薄所述初始转接板101的第二表面，使得所述硅通孔111露头，然后在所述初始转接板101的第二表面形成电镀种子层，具体形成方法可以通过化学镀、PVD等工艺形成，在本发明的一个具体实施例中，可以通过PVD沉积一层200-1000埃的铬和一层500-3000埃的铜形成该电镀种子层，然后在电镀种子层上图形化电镀形成第二重布线层113，使得其与所述硅通孔电连接，具体的图形化电镀方法进一步包括，涂胶、烘干、光刻、显影、电镀、去胶等步骤。在本发明的一个实施例中，还可在所述第二重布线层113的外接焊盘上，通过植球、电镀等工艺形成外接焊球114；
接下来，在步骤209，如图3i所示，去除第一载片。沿所述塑封层103的边沿切割，切除所述第一载片001以及转接板的非贴片区；以及
最后，在步骤210，切割形成单颗封装结构。
图3j至图3m示出了另一种外接焊球的形成工艺过程。当所述塑封层减薄后，若正反面应力不平衡，或整体刚度过大，可选择键合方案完成相关工艺，包括：
首先，如图3j所示，键合第二载片。在所述芯片102的第一表面上键合第二载板002，其中，第二载板002可以为晶圆、玻璃等载板材料，通过粘接材料键合至芯片的第一表面，所述第二载板的尺寸不小于所述初始转接板，所述粘接材料为加热、光照等可拆键合粘接材料；
接下来，如图3k所示，形成外接焊球。减薄所述初始转接板101的第二表面，使得所述硅通孔111露头，然后在所述初始转接板101的第二表面形成电镀种子层，具体形成方法可以通过化学镀、PVD等工艺形成，在本发明的一个具体实施例中，可以通过PVD沉积一层200-1000埃的铬和一层500-3000埃的铜形成该电镀种子层，然后在电镀种子层上图形化电镀形成第二重布线层113，使得其与所述硅通孔电连接，具体的图形化电镀方法进一步包括，涂胶、烘干、光刻、显影、电镀、去胶等步骤。在本发明的一个实施例中，还可在所述第二重布线层113的外接焊盘上，通过植球、电镀等工艺形成外接焊球114；
接下来，如图3l所示，去除第二载片。具体去除方法可以依据粘接材料的特性，采用加热拆键合、激光照射拆键合等方式实现，并可采用进一步的清洗工艺来彻底清除掉粘接材料；以及
最后，如图3m所示，去除第一载片。沿所述塑封层103的边沿者切割，切除所述第一载片001以及转接板的非贴片区。
最终形成的封装结构如图1所示，包括：转接板101，芯片102以及塑封层103。其中，所述芯片102贴装于所述转接板101的第一表面，与所述转接板101上的硅通孔111电连接，在本发明的一个实施例中，所述芯片102与所述转接板101之间还填充有底层填充料121，在本发明的一个实施例中，所述芯片102通过第一重布线层与所述硅通孔111电连接，所述转接板的第二表面包括外接焊球，使得所述封装可以贴装至基板上，其中，外接焊球114布置于第二重布线层113的外接焊盘上，所述第二重布线113形成于所述转接板101的第二表面，与所述硅通孔111电连接，以及所述凸点通过减薄所述转接板，使得硅通孔露头形成。所述塑封层103包覆所述芯片102，但露出所述芯片102的第一表面。
本发明提供的一种降低塑封晶圆翘曲的封装结构及其制造方法，在晶圆塑封前，在非贴片区域贴装硅片或者玻璃等热膨胀系数与硅接近的材料，降低塑封时塑封工艺中塑封料占比，降低翘曲。此外，由于塑封区域小于晶圆尺寸，还有利于减小塑封料使用的量；塑封减薄后，塑封料填充的主要是芯片间的间隙以及与边缘保护区域的间隙，且由于采用硅等材料作为边缘填充材料，其边缘可以在塑封后需工艺后用于晶圆对位，便于后续工艺的进行。
尽管上文描述了本发明的各实施例，但是，应该理解，它们只是作 为示例来呈现的，而不作为限制。对于相关领域的技术人员显而易见的是，可以对其做出各种组合、变型和改变而不背离本发明的精神和范围。因此，此处所公开的本发明的宽度和范围不应被上述所公开的示例性实施例所限制，而应当仅根据所附权利要求书及其等同替换来定义。

Claims (8)

  1. 一种降低塑封晶圆翘曲的封装结构，其特征在于，包括：
    转接板，其包括硅通孔，所述转接板的第一表面及第二表面分别设置有与所述硅通孔电连接的外接焊球和/或外接焊盘，且所述转接板的侧面包括第二塑封层；
    芯片，贴装至所述转接板的第一表面；以及
    塑封层，其包覆所述芯片，但露出所述芯片的第一表面。
  2. 一种降低塑封晶圆翘曲的封装结构的制作方法，其特征在于，包括步骤：
    在硅片的第一表面形成硅通孔以及第一重布线层，得到初始转接板；
    将第一载片键合至所述初始转接板上；
    切割所述第一载片，露出所述初始转接板的贴片区域；
    将芯片贴片至初始转接板的第一表面，所述芯片的焊盘与第一重布线层电连接；
    形成塑封层；
    减薄所述塑封层，露出所述芯片的第一表面；
    减薄所述初始转接板的第二表面，使得所述硅通孔露头；
    在所述初始转接板的第二表面上形成第二重布线层及外接焊球，电连接至所述硅通孔；
    去除第一载片；以及
    切割形成单颗封装结构。
  3. 如权利要求2所述的制作方法，其特征在于，所述第一载片的第一表面包括光刻图形，所述光刻图形与所述初始转接板上的非贴片区域吻合。
  4. 如权利要求2所述的制作方法，其特征在于，所述第一载片的材料的热膨胀系数与硅相同或接近。
  5. 如权利要求3所述的制作方法，其特征在于，所述光刻图形表面涂覆有键合材料。
  6. 如权利要求5所述的制作方法，其特征在于，所述键合材料通过滚胶工艺，涂覆于所述光刻图形表面。
  7. 如权利要求2所述的制作方法，其特征在于，所述第一载片的去除包括：
    沿所述塑封层的边沿切割，切除所述第一载片以及转接板的非贴片区。
  8. 如权利要求2所述的制作方法，其特征在于，所述制作方法还包括：
    在硅通孔露头操作前，在所述芯片的第一表面键合第二载片，并在去除所述第一载片前，去除所述第二载片。
PCT/CN2021/079256 2021-01-18 2021-03-05 一种降低塑封晶圆翘曲的封装结构及其制造方法 WO2022151572A1 (zh)

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