WO2022143085A1 - 输入阻抗匹配网络和射频前端模组 - Google Patents

输入阻抗匹配网络和射频前端模组 Download PDF

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Publication number
WO2022143085A1
WO2022143085A1 PCT/CN2021/136814 CN2021136814W WO2022143085A1 WO 2022143085 A1 WO2022143085 A1 WO 2022143085A1 CN 2021136814 W CN2021136814 W CN 2021136814W WO 2022143085 A1 WO2022143085 A1 WO 2022143085A1
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Prior art keywords
pad
ground
impedance matching
compensation
parasitic capacitance
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PCT/CN2021/136814
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English (en)
French (fr)
Inventor
丁团结
倪建兴
Original Assignee
锐石创芯(深圳)科技股份有限公司
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Publication of WO2022143085A1 publication Critical patent/WO2022143085A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/18—Input circuits, e.g. for coupling to an antenna or a transmission line
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0278—Arrangements for impedance matching

Definitions

  • the present application relates to the technical field of radio frequency communication, and in particular, to an input impedance matching network and a radio frequency front-end module.
  • the performance of the LNA plays a crucial role in the performance of the whole receiver system, because the signal-to-noise ratio (SNR) of the whole receiver system is largely determined by the performance of the LNA.
  • SNR signal-to-noise ratio
  • NF Noise figure
  • NF gain
  • designing a low-noise amplifier with good performance becomes an important goal of RF front-end design.
  • the input impedance matching network of the LNA has a great influence on the noise figure of the LNA, and also affects the gain of the LNA.
  • the input matching of the LNA is realized by a series inductor.
  • some inevitable parasitic capacitances are often generated, which leads to the mismatch of the input impedance and affects the performance of the LNA.
  • Embodiments of the present application provide an input impedance matching network and a radio frequency front-end module, so as to solve the problem of impedance matching caused by parasitic capacitance introduced by a pad in an actual circuit.
  • An embodiment of the present application provides an input impedance matching network, including a first pad, a second pad, and a first inductor having one end connected to the first pad and the other end connected to the second pad, the The output end of the second pad is used as the output end of the input impedance matching network, and is configured to be connected to the input end of the low noise amplifier;
  • the input impedance matching network further includes a connection with the first pad and/or the A compensation adjustment circuit connected to the second pad, the compensation adjustment circuit being configured to adjust the parasitic capacitance from the first pad to the ground and/or the parasitic capacitance from the second pad to the ground, so that all The parasitic capacitance from the first pad to the ground is greater than the parasitic capacitance from the second pad to the ground.
  • the compensation adjustment circuit includes a capacitance compensation circuit disposed between the first pad and the ground terminal, for increasing the parasitic capacitance from the first pad to the ground.
  • the capacitance compensation circuit includes at least two compensation metal plates arranged in parallel and opposite to each other, the projections of the at least two compensation metal plates in the longitudinal direction at least partially overlap, and the compensation metal plates include a first compensation metal plate and a second compensation metal plate.
  • Two compensating metal plates, the first compensating metal plate and the second compensating metal plate are arranged crosswise, the first compensating metal plate is connected to the ground terminal, and the second compensating metal plate is connected to the first welding discs are connected.
  • the compensation metal plate and the first pad are disposed on different layers of the substrate.
  • the capacitance compensation circuit includes a third pad, a second inductor and a fourth pad connected in series, the third pad is connected to the first pad, and the fourth pad is connected to the ground end connected.
  • the third pad, the second inductor, the fourth pad and the first pad are arranged on the same layer of the substrate.
  • the compensation adjustment circuit includes a capacitance adjustment circuit disposed between the second pad and the ground terminal, for reducing the parasitic capacitance from the second pad to the ground.
  • the first pad, the first inductor and the second pad are arranged on the same layer of the substrate.
  • An embodiment of the present application provides a radio frequency front-end module, including an input impedance matching network and a low noise amplifier connected to the input impedance matching network;
  • the input impedance matching network includes a first pad, a second pad, and a first inductor having one end connected to the first pad and the other end connected to the second pad, and the second pad has a
  • the output terminal is used as the output terminal of the input impedance matching network, and is configured to be connected to the input terminal of the low noise amplifier; the input impedance matching network also includes connecting to the first pad and/or the second pad
  • the compensation adjustment circuit is configured to adjust the parasitic capacitance from the first pad to the ground and/or the parasitic capacitance from the second pad to the ground, so that the first pad The parasitic capacitance to ground is greater than the parasitic capacitance of the second pad to ground.
  • the compensation adjustment circuit includes a capacitance compensation circuit disposed between the first pad and the ground terminal, for increasing the parasitic capacitance from the first pad to the ground.
  • the capacitance compensation circuit includes at least two compensation metal plates arranged in parallel and opposite to each other, the projections of the at least two compensation metal plates in the longitudinal direction at least partially overlap, and the compensation metal plates include a first compensation metal plate and a second compensation metal plate.
  • Two compensating metal plates, the first compensating metal plate and the second compensating metal plate are arranged crosswise, the first compensating metal plate is connected to the ground terminal, and the second compensating metal plate is connected to the first welding discs are connected.
  • the compensation metal plate and the first pad are disposed on different layers of the substrate.
  • the capacitance compensation circuit includes a third pad, a second inductor and a fourth pad connected in series, the third pad is connected to the first pad, and the fourth pad is connected to the ground end connected.
  • the third pad, the second inductor, the fourth pad and the first pad are arranged on the same layer of the substrate.
  • the compensation adjustment circuit includes a capacitance adjustment circuit disposed between the second pad and the ground terminal, for reducing the parasitic capacitance from the second pad to the ground.
  • the first pad, the first inductor and the second pad are arranged on the same layer of the substrate.
  • the low noise amplifier includes a radio frequency amplifier circuit, a first capacitive element, a second capacitive element and an impedance matching circuit; one end of the radio frequency amplifier circuit is connected to the second pad, and the other end passes through the first The capacitive element is connected to the signal output terminal; one end of the second capacitive element is connected to the connection node between the radio frequency amplifier circuit and the first capacitive element, and the other end is connected to the ground terminal; one end of the impedance matching circuit is connected to the power supply The other end is connected to the connection node between the radio frequency amplifier circuit and the first capacitive element.
  • the input end of the network, and the second pad is used as the output end of the input impedance matching network, and is configured to be connected to the input end of the low noise amplifier, and the compensation adjustment circuit connected to the first pad or the second pad is used.
  • the parasitic capacitance from one pad to ground and/or the parasitic capacitance from the second pad to ground is adjusted so that the parasitic capacitance from the first pad to ground is greater than the parasitic capacitance from the second pad to ground, thereby slowing down the first pad to ground.
  • the impedance mismatch problem caused by the parasitic capacitance from the pad to the ground and the parasitic capacitance from the second pad to the ground is equal to realize the impedance matching of the input end of the low noise amplifier.
  • 1 is a schematic circuit diagram of an input impedance matching network in the prior art
  • Fig. 2 is a Smith chart of the input impedance matching network shown in Fig. 1;
  • FIG. 3 is a schematic circuit diagram of an input impedance matching network in an embodiment of the present application.
  • Fig. 4 is a Smith chart of the input impedance matching network shown in Fig. 3;
  • Fig. 5 is another Smith chart of the input impedance matching network shown in Fig. 3;
  • FIG. 6 is a schematic circuit diagram of an input impedance matching network in an embodiment of the present application.
  • FIG. 7 is another schematic circuit diagram of an input impedance matching network in an embodiment of the present application.
  • FIG 8 is another schematic circuit diagram of an input impedance matching network in an embodiment of the present application.
  • FIG. 9 is another schematic circuit diagram of an input impedance matching network in an embodiment of the present application.
  • FIG. 10 is a schematic circuit diagram of a radio frequency front-end module in an embodiment of the present application.
  • Spatial relational terms such as “under”, “below”, “below”, “under”, “above”, “above”, etc., may be used herein for convenience of description This describes the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as “below” or “beneath” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
  • the input impedance matching network 10 includes a first pad 11, a second pad 12, one end connected to the first pad 11, and the other end connected to the first pad 11.
  • the first inductor L1 connected to the two bonding pads 12, the output end of the second bonding pad 12 is used as the output end of the input impedance matching network 10, and is configured to be connected to the input end of the low noise amplifier 20;
  • the input impedance matching network 10 also includes and A compensation adjustment circuit 13 connected to the first pad 11 and/or the second pad 12, the compensation adjustment circuit 13 is configured to adjust the parasitic capacitance from the first pad 11 to the ground and/or the parasitic capacitance from the second pad 12 to the ground The capacitance is adjusted so that the parasitic capacitance from the first pad 11 to the ground is larger than the parasitic capacitance from the second pad 12 to the ground.
  • the input impedance matching network 10 includes a first pad 11 , a second pad 12 , and a first inductor L1 whose one end is connected to the first pad 11 and the other end is connected to the second pad 12 .
  • 11 is used as the input end of the input impedance matching network 10
  • the second pad 12 is used as the output end of the input impedance matching network 10, and is configured to be connected to the input end of the low noise amplifier 20 for filtering the input interference of the low noise amplifier 20.
  • each pad and the GND metal plane (referred to as the ground terminal) form a parallel-plate capacitor
  • the first pad 11 will generate a parasitic capacitance Cgnd1 to the ground and the second pad 12 will generate a parasitic capacitance Cgnd1 to the ground during the actual operation.
  • the parasitic capacitance Cgnd2 generally speaking, the first pad 11 and the second pad 12 are pads of the same type, so that the first pad 11 will generate the parasitic capacitance Cgnd1 and the second pad 12 to the ground.
  • the parasitic capacitance Cgnd1 generated by the first pad 11 to the ground and the parasitic capacitance Cgnd2 generated by the second pad 12 to the ground are both 200fF, and the inductance value of the first inductor L1 is 3.3nH, then
  • the Smith chart of the input impedance matching network 10 shown in FIG. 1 is shown in FIG. 2 .
  • Point A is the input impedance conjugate point. In an ideal state, if the parasitic capacitance Cgnd1 and the parasitic capacitance Cgnd2 do not exist, the The impedance value should be directly moved from point O to the conjugate point A of the input impedance under the influence of the first inductance L1, so as to realize the impedance matching of the circuit.
  • the impedance value of the low noise amplifier 20 moves from point O to point B1; Under the influence, the impedance value of the low noise amplifier 20 moves from point B1 to point C1; finally, under the influence of the parasitic capacitance Cgnd2 formed by the second pad 12, the impedance value of the low noise amplifier 20 moves from point C1 to point D1 , so that the input impedance mismatch phenomenon occurs in the low noise amplifier 20 , which affects the performance of the low noise amplifier 20 .
  • the input impedance matching network 10 is further provided with a The compensation adjustment circuit 13 connected to the pad 11 or the second pad 12 uses the compensation adjustment circuit 13 to increase the parasitic capacitance from the first pad 11 to the ground, or to reduce the parasitic capacitance Cgnd2 generated by the second pad 12 to the ground.
  • the impedance mismatch problem caused by the equal capacitance Cgnd2 achieves the impedance matching of the input end of the low noise amplifier 20 .
  • the compensation adjustment circuit 13 connected to the first pad 11 or the second pad 12 is used for adjustment to increase the parasitic capacitance from the first pad 11 to the ground, so that the parasitic capacitance from the first pad 11 to the ground is greater than
  • the second pad 12 generates a parasitic capacitance Cgnd2 to the ground.
  • the parasitic capacitances from the first pad 11 and the second pad 12 to the ground are both 200fF. After the first pad 11 is connected to the first compensation adjustment circuit 13, the parasitic capacitance from the first pad 11 to the ground is generated.
  • the capacitance Cgnd1 is increased from 200fF to 640fF, and the parasitic capacitance generated by the second pad 12 to the ground does not change to 200fF, then the Smith chart of the input impedance matching network 10 shown in FIG. 3 is shown in FIG. 4, point A is The input impedance conjugate point, in an ideal state, if there is no parasitic capacitance Cgnd1 and parasitic capacitance Cgnd2, the impedance value of the low noise amplifier 20 should be directly moved from the O point to the input impedance conjugate point under the influence of the first inductance L1 A, so as to achieve the impedance matching of the circuit.
  • the impedance is at the conjugate point A. Therefore, the parasitic capacitance from the first pad 11 to the ground can be increased, thereby reducing the input impedance mismatch caused by the equal parasitic capacitance from the first pad 11 and the second pad 12 to the ground. phenomenon, improving the performance of the low noise amplifier 20.
  • the compensation adjustment circuit 13 connected to the first pad 11 or the second pad 12 is used for adjustment, and the parasitic capacitance Cgnd2 generated by the second pad 12 to the ground can also be reduced, so that the first pad 11 can be adjusted.
  • the parasitic capacitance to ground is greater than the parasitic capacitance Cgnd2 generated by the second pad 12 to ground.
  • originally the parasitic capacitances from the first pad 11 and the second pad 12 to ground are both 200fF.
  • the parasitic capacitance Cgnd2 from the pad 12 to the ground is reduced from 200fF to 100fF, and the parasitic capacitance Cgnd1 from the first pad 11 to the ground does not change to 200fF, then the Smith chart of the input impedance matching network 10 shown in FIG.
  • point A is the conjugate point of the input impedance.
  • the impedance value of the low noise amplifier 20 should be affected by the first inductance L1 , from point O Move directly to the input impedance conjugate point A to achieve impedance matching of the circuit.
  • the impedance is at the conjugate point A. Therefore, the parasitic capacitance from the second pad 12 to the ground can be reduced, thereby reducing the input impedance mismatch caused by the equal parasitic capacitance from the first pad 11 and the second pad 12 to the ground. phenomenon, improving the performance of the low noise amplifier 20.
  • the first pad 11 , the second pad 12 and the first inductor L1 whose one end is connected to the first pad 11 and the other end is connected to the second pad 12
  • the first A pad 11 is used as the input terminal of the input impedance matching network 10
  • the second pad 12 is used as the output terminal of the input impedance matching network 10 , and is configured to be connected to the input terminal of the low noise amplifier 20 .
  • the compensation adjustment circuit 13 connected to the second pad 12 adjusts the parasitic capacitance from the first pad 11 to the ground and/or the parasitic capacitance from the second pad 12 to the ground, so that the first pad 11 to the ground has a
  • the parasitic capacitance is greater than the parasitic capacitance Cgnd2 generated from the second pad 12 to the ground, thereby reducing the impedance mismatch problem caused by the parasitic capacitance Cgnd1 from the first pad 11 to the ground and the parasitic capacitance Cgnd2 from the second pad 12 to the ground being equal. Impedance matching at the input end of the low noise amplifier 20 is achieved.
  • the compensation adjustment circuit 13 includes a capacitance compensation circuit 131 disposed between the first pad 11 and the ground terminal for increasing the parasitic capacitance from the first pad 11 to the ground.
  • the parasitic capacitance Cgnd1 from the first pad 11 to the ground and the second pad 12
  • a capacitance compensation circuit 131 is provided between the first pad 11 and the ground terminal, and the capacitance compensation circuit 131 can increase the parasitic capacitance from the first pad 11 to the ground.
  • the capacitance compensation circuit 131 disposed between the first pad 11 and the ground terminal forms a parasitic capacitance Cgnd3 during operation
  • the parasitic capacitance from the first pad 11 and the second pad 12 to the ground are equal, in order to make the parasitic capacitance from the first pad 11 to the ground greater than the parasitic capacitance from the second pad 12 to the ground, the parasitic capacitance from the first pad 11 to the ground can be A capacitance compensation circuit 131 is arranged between a pad 11 and the ground terminal to increase the parasitic capacitance from the first pad 11 to the ground and reduce the parasitic capacitance caused by the equal parasitic capacitance from the first pad 11 and the second pad 12 to the ground.
  • the impedance mismatch problem of the low noise amplifier 20 is ensured to match the impedance of the input end of the low noise amplifier.
  • the capacitance compensation circuit 131 includes at least two compensation metal plates 1311/1312/1313 arranged in parallel and opposite to each other, and the projections of the at least two compensation metal plates 1311/1312/1313 in the longitudinal direction are at least partially Overlapping, the compensation metal plate includes a first compensation metal plate and a second compensation metal plate, the first compensation metal plate and the second compensation metal plate are crossed, and the first compensation metal plate 1313 is connected to the ground terminal connected, the second compensation metal plate 1311 is connected to the first pad.
  • the capacitance compensation circuit 131 includes at least two compensation metal plates 1311/1312/1313 arranged in parallel and opposite to each other, and the first compensation metal plate 1313 is connected to the ground terminal, that is, the first compensation metal plate 1313 is connected to the ground terminal
  • the connected compensation metal plate, the second compensation metal plate 1311 is connected to the first pad, that is, the second compensation metal plate 1311 is a compensation metal plate connected to the first pad 11, so that the first pad 11 passes through
  • At least two compensating metal plates 1311/1312/1313 are connected to the ground terminal, since the projections of at least two compensating metal plates 1311/1312/1313 in the longitudinal direction at least partially overlap, so that at least two compensating metal plates 1311/1312/1313 are matched
  • the compensation metal plate 1311/1312/1313 and the first pad 11 are disposed on different layers of the substrate.
  • At least two compensating metal plates 1311/1312/1313 are arranged in parallel and opposite to each other. Therefore, at least two compensating metal plates 1311/1312/1313 are arranged on different layers of the substrate, which helps to reduce the size of the input impedance matching network 10.
  • the area of the amplifying branch where the low noise amplifier 20 is located is further reduced;
  • the metal plates 1311/1312/1313 and the first pads 11 are arranged in different layers of the substrate, so that the first pads 11 and the at least two compensation metal plates 1311/1312/1313 are arranged on different layers of the substrate.
  • the capacitance compensation circuit 131 includes a third pad 1314 , a second inductor L2 and a fourth pad 1315 connected in series, the third pad 1314 is connected to the first pad 11 , and the The four pads 1315 are connected to the ground terminal.
  • the third pad 1314, the second inductor L2 and the fourth pad 1315 are arranged in series between the first pad 11 and the ground terminal, wherein the third pad 1314 is connected to the first pad 11, and the third pad 1314 is connected to the first pad 11.
  • the four pads 1315 are connected to the ground terminal, so that the capacitance compensation circuit 131 formed by the third pad 1314, the second inductor L2 and the fourth pad 1315 in series can increase the effect of the parasitic capacitance from the first pad 11 to the ground,
  • the problem of impedance mismatch caused by equal parasitic capacitances from the first pad 11 and the second pad 12 to the ground is alleviated, and the impedance matching of the input end of the low noise amplifier 20 is ensured.
  • the third pad 1314 , the second inductor L2 , the fourth pad 1315 and the first pad 11 are disposed on the same layer of the substrate.
  • the capacitance compensation circuit 131 formed by the third pad 1314, the second inductor L2, and the fourth pad 1315 in series is arranged on the same layer of the substrate as the first pad 11, and the second The parasitic capacitance to the ground formed by the pad 11 and the second pad 12 is canceled, so as to achieve impedance matching at the input end of the low noise amplifier.
  • the compensation adjustment circuit 13 includes a capacitance adjustment circuit 132 disposed between the second pad 12 and the ground terminal for reducing the parasitic capacitance from the second pad 12 to the ground.
  • the capacitance adjustment circuit 132 may be a circuit for adjusting the size of the second pad 12 . In this embodiment, by reducing the size of the second pad 12 , the parasitic capacitance from the second pad 12 to the ground is reduced.
  • the parasitic capacitance Cgnd1 from the first pad 11 to the ground and the second pad 12
  • a capacitance adjustment circuit 132 is provided between the second pad 12 and the ground terminal, and the capacitance adjustment circuit 132 can reduce the parasitic capacitance from the second pad 12 to the ground.
  • the parasitic capacitance from the second pad 12 to the ground can reduce the phenomenon that the input impedance conjugate point mismatch is caused by the equal parasitic capacitance from the first pad 11 and the second pad 12 to the ground, and improve the low noise amplifier 20 performance.
  • the first pad 11 , the first inductor L1 and the second pad 12 are disposed on the same layer of the substrate.
  • the first pad 11 , the first inductor L1 and the second pad 12 are arranged on the same layer of the substrate, so that the first pad 11 , the first inductor L1 and the second pad 12 are connected in series to form an input impedance
  • the matching network 10 is provided on the same layer of the substrate.
  • the impedance matching effect of the input impedance matching network 10 formed by the first pad 11 , the first inductor L1 and the second pad 12 arranged on the same layer of the substrate helps to ensure the first pad 11 , the first pad 11 and the second pad 12 .
  • the impedance matching effect of the input impedance matching network 10 formed by an inductor L1 and the second pad 12 is performed.
  • the first pad 11 , the first inductor L1 and the second pad 12 are disposed on the top layer of the substrate.
  • the first pad 11 , the first inductor L1 and the second pad 12 are arranged on the same layer of the substrate, specifically on the top layer of the substrate. On the one hand, the first pad 11 and the first inductor can be guaranteed.
  • the impedance matching effect of the input impedance matching network 10 formed by the L1 and the second pad 12 in series can facilitate the welding operation of the first pad 11 and the second pad 12 on the other hand.
  • the embodiment of the present application also provides a radio frequency front-end module, the radio frequency front-end module includes the input impedance matching network 10 provided in the above embodiment and the low noise amplifier 20 connected to the input impedance matching network 10. Since in the input impedance matching network 10, the first pad 11, the second pad 12 and the first inductor L1 whose one end is connected to the first pad 11 and the other end is connected to the second pad 12, the first pad 11 is used as the first inductance L1.
  • the input end of the input impedance matching network 10, and the second pad 12, as the output end of the input impedance matching network 10, is configured to be connected to the input end of the low noise amplifier 20, and is connected to the first pad 11 or the second pad by using
  • the compensation adjustment circuit 13 connected to 12 adjusts the parasitic capacitance from the first pad 11 to the ground and/or the parasitic capacitance from the second pad 12 to the ground, so that the parasitic capacitance from the first pad 11 to the ground is greater than that from the second pad 11 to the ground.
  • the pad 12 generates a parasitic capacitance Cgnd2 to the ground, thereby reducing the impedance mismatch problem caused by the parasitic capacitance Cgnd1 from the first pad 11 to the ground and the parasitic capacitance Cgnd2 from the second pad 12 to the ground being equal, and realizing the low noise amplifier 20 Impedance matching at the input.
  • the low noise amplifier 20 includes a radio frequency amplifier circuit 21 , a first capacitive element 22 , a second capacitive element 23 and an impedance matching circuit 24 ; one end of the radio frequency amplifier circuit 21 is connected to the second pad. 12 is connected, and the other end is connected to the signal output terminal through the first capacitive element 22; one end of the second capacitive element 23 is connected to the connection node between the radio frequency amplifier circuit 21 and the first capacitive element 22, and the other end is connected to the ground terminal; impedance matching One end of the circuit 24 is connected to the power supply end, and the other end is connected to the connection node between the radio frequency amplifier circuit 21 and the first capacitive element 22 .
  • the radio frequency amplifier circuit 21 is a circuit for implementing amplifying processing of the radio frequency signal.
  • the first capacitance element 22 is an element whose capacitance value can be adjusted. By adjusting the capacitance value of the first capacitance element 22 , impedance matching between the radio frequency amplifier circuit 22 and other circuits connected after the signal output terminal is realized.
  • a second capacitive element 23 and an impedance matching circuit 24 are arranged in parallel, and impedance matching is achieved through the interaction between the second capacitive element 23 and the impedance matching circuit 24. .
  • the radio frequency amplifying circuit 21 includes a first amplifying transistor M21, a second amplifying transistor M22, an input DC blocking capacitor C21, a radio frequency grounding capacitor C22 and a gain adjusting inductor L21; the signal of the first amplifying transistor M21
  • the control terminal is connected to the second pad 12 through the input DC blocking capacitor C21, the first connection terminal of the first amplifier transistor M21 is connected to the second connection terminal of the second amplifier transistor M22, and the second connection terminal of the first amplifier transistor M21 is connected through
  • the gain adjustment inductor L21 is connected to the ground terminal, the signal control terminal of the second amplifier transistor M22 is connected to the impedance matching circuit 24, and is connected to the ground terminal through the radio frequency ground capacitor C22, and the first connection terminal of the second amplifier transistor M22 is connected to the first capacitor Elements 22 are connected.
  • the RF signal output from the second pad 12 of the input impedance matching network 10 is sent to the first amplifier transistor M21 through the input DC blocking capacitor C21, and the RF signal is coupled to the first amplifier transistor M21 by using the DC blocking characteristic of the input DC blocking capacitor C21
  • the gain adjustment inductor L21 is connected to the second connection terminal of the first amplifying transistor M21 and the ground terminal to achieve the effect of gain adjustment, thereby ensuring the quality of the amplified radio frequency signal.
  • the first connection end of the second amplifying transistor M22 is connected to the first capacitive element 22 , and can output the amplified radio frequency signal to the first capacitive element 22 , and
  • the impedance matching circuit 24 includes a matching inductor L22 , a first resistor R21 and a second resistor R22 arranged in parallel; one end of the first resistor R21 is connected to the power supply end, and the other end is connected to the second amplifying transistor
  • the signal control end of M22 is connected to the connection node between the radio frequency ground capacitor C22; one end of the matching inductor L22 is connected to the power supply end, and the other end is connected to the first connection end of the second amplifying transistor M22 and the connection node between the first capacitive element 22
  • One end of the second resistor R22 is connected to the power supply end, and the other end is connected to the connection node between the first connection end of the second amplifying transistor M22 and the first capacitive element 22 .

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Abstract

本申请公开一种输入阻抗匹配网络和射频前端模组。输入阻抗匹配网络包括第一焊盘、第二焊盘以及一端与第一焊盘连接，另一端与第二焊盘连接的第一电感，第二焊盘的输出端作为输入阻抗匹配网络的输出端，被配置为与低噪声放大器的输入端相连；输入阻抗匹配网络还包括与第一焊盘和/或第二焊盘相连的补偿调整电路，补偿调整电路被配置为对第一焊盘到地的寄生电容和/或第二焊盘到地的寄生电容进行调整，以使第一焊盘到地的寄生电容大于第二焊盘到地的寄生电容。补偿调整电路可使第一焊盘到地的寄生电容大于第二焊盘产生到地的寄生电容，减缓寄生电容相等所导致的阻抗失配问题，实现低噪声放大器输入端的阻抗匹配。

Description

输入阻抗匹配网络和射频前端模组
本申请要求以2020年12月31日提交的申请号为202011637066.3，名称为“输入阻抗匹配网络和射频前端模组”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及射频通信技术领域，尤其涉及一种输入阻抗匹配网络和射频前端模组。
背景技术
作为接收机的第一级，低噪声放大器的性能对整个接收机***的性能起到至关重要的作用，因为整个接收机***的信噪比(SNR)很大程度上取决于低噪声放大器的噪声系数(NF)和增益，因此，设计性能良好的低噪声放大器成为射频前端设计的重要目标。根据噪声级联公式可知，低噪声放大器的输入阻抗匹配网络对低噪声放大器的噪声系数影响非常大，同时也会影响低噪声放大器的增益。一般低噪声放大器的输入匹配由一个串联电感实现，然而由于SMD焊盘的存在，往往会产生一些不可避免的寄生电容，导致输入阻抗失配，对低噪声放大器的性能造成影响。
发明内容
本申请实施例提供一种输入阻抗匹配网络和射频前端模组，以解决在实际电路中因焊盘引入的寄生电容导致阻抗匹配的问题。
本申请实施例提供一种输入阻抗匹配网络，包括第一焊盘、第二焊盘以及一端与所述第一焊盘连接，另一端与所述第二焊盘连接的第一电感，所述第二焊盘的输出端作为所述输入阻抗匹配网络的输出端，被配置为与低噪声放大器的输入端相连；所述输入阻抗匹配网络还包括与所述第一焊盘和/或所述第二焊盘相连的补偿调整电路，所述补偿调整电路被配置为对所述第一焊盘到地的寄生电容和/或所述第二焊盘到地的寄生电容进行调整，以使所述第一焊盘到地的寄生电容大于所述第二焊盘到地的寄生电容。
优选地，所述补偿调整电路包括设置在所述第一焊盘和所述接地端之间的电容补偿电路，用于增大所述第一焊盘到地的寄生电容。
优选地，所述电容补偿电路包括平行相对设置的至少两个补偿金属板，至少两个所述补偿金属板在纵向的投影至少部分交叠，所述补偿金属板包括第一补偿金属板和第二补偿金属板，所述第一补偿金属板和所述第二补偿金属板交叉设置，所述第一补偿金属板与所述接地端相连，所述第二补偿金属板与所述第一焊盘相连。
优选地，所述补偿金属板与所述第一焊盘设置在基板的不同层。
优选地，所述电容补偿电路包括串联的第三焊盘、第二电感和第四焊盘，所述第三焊盘与所述第一焊盘相连，所述第四焊盘与所述接地端相连。
优选地，所述第三焊盘、所述第二电感、所述第四焊盘和所述第一焊盘设置在基板的同一层上。
优选地，所述补偿调整电路包括设置在所述第二焊盘和所述接地端之间的电容调整电路，用于减小所述第二焊盘到地的寄生电容。
优选地，所述第一焊盘、所述第一电感和所述第二焊盘设置在基板的同一层上。
本申请实施例提供一种射频前端模组，包括输入阻抗匹配网络和与所述输入阻抗匹配网络相连的低噪声放大器；
所述输入阻抗匹配网络，包括第一焊盘、第二焊盘以及一端与所述第一焊盘连接，另一端与所述第二焊盘连接的第一电感，所述第二焊盘的输出端作为所述输入阻抗匹配网络的输出端，被配置为与低噪声放大器的输入端相连；所述输入阻抗匹配网络还包括与所述第一焊盘和/或所述第二焊盘相连的补偿调整电路，所述补偿调整电路被配置为对所述第一焊盘到地的寄生电容和/或所述第二焊盘到地的寄生电容进行调整，以使所述第一焊盘到地的寄生电容大于所述第二焊盘到地的寄生电容。
优选地，所述补偿调整电路包括设置在所述第一焊盘和所述接地端之间的电容补偿电路，用于增大所述第一焊盘到地的寄生电容。
优选地，所述电容补偿电路包括平行相对设置的至少两个补偿金属板，至少两个所述补偿金属板在纵向的投影至少部分交叠，所述补偿金属板包括第一补偿金属板和第二补偿金属板，所述第一补偿金属板和所述第二补偿金属板交叉设置，所述第一补偿金属板与所述接地端相连，所述第二补偿金属板与所述第一焊盘相连。
优选地，所述补偿金属板与所述第一焊盘设置在基板的不同层。
优选地，所述电容补偿电路包括串联的第三焊盘、第二电感和第四焊盘，所述第三焊盘与所述第一焊盘相连，所述第四焊盘与所述接地端相连。
优选地，所述第三焊盘、所述第二电感、所述第四焊盘和所述第一焊盘设置在基板的 同一层上。
优选地，所述补偿调整电路包括设置在所述第二焊盘和所述接地端之间的电容调整电路，用于减小所述第二焊盘到地的寄生电容。
优选地，所述第一焊盘、所述第一电感和所述第二焊盘设置在基板的同一层上。
优选地，所述低噪声放大器包括射频放大电路、第一电容元件、第二电容元件和阻抗匹配电路；所述射频放大电路的一端与所述第二焊盘相连，另一端通过所述第一电容元件与信号输出端相连；所述第二电容元件一端与所述射频放大电路和所述第一电容元件之间的连接节点相连，另一端与接地端相连；所述阻抗匹配电路一端与供电端相连，另一端与所述射频放大电路和所述第一电容元件之间的连接节点相连。
上述输入阻抗匹配网络和射频前端模组，第一焊盘、第二焊盘以及一端与第一焊盘相连，另一端与第二焊盘相连的第一电感，第一焊盘作为输入阻抗匹配网络的输入端，而第二焊盘作为输入阻抗匹配网络的输出端，被配置为与低噪声放大器的输入端相连，利用与第一焊盘或者第二焊盘相连的补偿调整电路，对第一焊盘到地的寄生电容和/或第二焊盘到地的寄生电容进行调整，以使第一焊盘到地的寄生电容大于第二焊盘产生到地的寄生电容，从而减缓第一焊盘到地的寄生电容和第二焊盘到地的寄生电容相等所导致的阻抗失配问题，实现低噪声放大器输入端的阻抗匹配。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对本申请实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中输入阻抗匹配网络的一电路示意图；
图2是图1所示的输入阻抗匹配网络的一Smith圆图；
图3是本申请一实施例中输入阻抗匹配网络的一电路示意图；
图4是图3所示的输入阻抗匹配网络的一Smith圆图；
图5是图3所示的输入阻抗匹配网络的另一Smith圆图；
图6是本申请一实施例中输入阻抗匹配网络的一电路示意图；
图7是本申请一实施例中输入阻抗匹配网络的另一电路示意图；
图8是本申请一实施例中输入阻抗匹配网络的另一电路示意图；
图9是本申请一实施例中输入阻抗匹配网络的另一电路示意图；
图10是本申请一实施例中射频前端模组的一电路示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解的是，本申请能够以不同形式实施，而不应当解释为局限于这里提出的实施例。相反地，提供这些实施例将使公开彻底和完全，并且将本申请的范围完全地传递给本领域技术人员。在附图中，为了清楚，层和区的尺寸以及相对尺寸可能被夸大自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在…上”、“与…相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在…上”、“与…直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本申请教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。
空间关系术语例如“在…下”、“在…下面”、“下面的”、“在…之下”、“在…之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在…下面”和“在…下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本申请的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚 指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本申请，将在下列的描述中提出详细的结构及步骤，以便阐释本申请提出的技术方案。本申请的较佳实施例详细描述如下，然而除了这些详细描述外，本申请还可以具有其他实施方式。
本申请实施例提供一种输入阻抗匹配网络10，如图3所示，输入阻抗匹配网络10包括第一焊盘11、第二焊盘12以及一端与第一焊盘11相连，另一端与第二焊盘12相连的第一电感L1，第二焊盘12的输出端作为输入阻抗匹配网络10的输出端，被配置为与低噪声放大器20的输入端相连；输入阻抗匹配网络10还包括与第一焊盘11和/或第二焊盘12相连的补偿调整电路13，补偿调整电路13被配置为对第一焊盘11到地的寄生电容和/或第二焊盘12到地的寄生电容进行调整，以使将第一焊盘11到地的寄生电容大于第二焊盘12到地的寄生电容。
作为一示例，输入阻抗匹配网络10包括第一焊盘11、第二焊盘12以及一端与第一焊盘11相连，另一端与第二焊盘12相连的第一电感L1，第一焊盘11作为输入阻抗匹配网络10的输入端，第二焊盘12作为输入阻抗匹配网络10的输出端，被配置为与低噪声放大器20的输入端相连，用于滤除低噪声放大器20的输入干扰。由于每个焊盘与GND金属平面(简称接地端)形成一个平行板电容器，从而使得实际工作过程中，第一焊盘11会产生到地的寄生电容Cgnd1和第二焊盘12会产生到地的寄生电容Cgnd2，一般来说，第一焊盘11和第二焊盘12为同种型号的焊盘，使得第一焊盘11会产生到地的寄生电容Cgnd1和第二焊盘12会产生到地的寄生电容Cgnd2相等，即Cgnd1＝Cgnd2，会存在阻抗失配的问题。
如图1所示，在第一焊盘11会产生到地的寄生电容Cgnd1和第二焊盘12会产生到地的寄生电容Cgnd2均为200fF，第一电感L1的电感值为3.3nH，则图1所示的输入阻抗匹配网络10的Smith圆图如图2所示，A点为输入阻抗共轭点，在理想状态下，若不存在寄生电容Cgnd1和寄生电容Cgnd2，低噪声放大器20的阻抗值应在第一电感L1的影响下，由O点直接移动到输入阻抗共轭点A，从而实现电路的阻抗匹配。但在输入阻抗匹配网络10实际工作时，在第一焊盘11到地的寄生电容Cgnd1的影响下，低噪声放大器20的阻抗值从O点移动到B1点；接着，在第一电感L1的影响下，低噪声放大器20的阻抗值由B1 点移动到C1点；最后，在第二焊盘12所形成的寄生电容Cgnd2的影响下，低噪声放大器20的阻抗值由C1点移动到D1点，使得低噪声放大器20产生输入阻抗失配现象，给低噪声放大器20的性能造成影响。
为了减缓第一焊盘11会产生到地的寄生电容Cgnd1和第二焊盘12会产生到地的寄生电容Cgnd2相等而导致的阻抗失配的问题，输入阻抗匹配网络10还设置有与第一焊盘11或者第二焊盘12相连的补偿调整电路13，利用补偿调整电路13增大第一焊盘11到地的寄生电容，或者减小第二焊盘12会产生到地的寄生电容Cgnd2，使得第一焊盘11到地的寄生电容，大于第二焊盘12产生到地的寄生电容Cgnd2，从而减缓第一焊盘11到地的寄生电容Cgnd1和第二焊盘12到地的寄生电容Cgnd2相等所导致的阻抗失配问题，实现低噪声放大器20输入端的阻抗匹配。
例如，采用与第一焊盘11或者第二焊盘12相连的补偿调整电路13进行调整，增大第一焊盘11到地的寄生电容，使得第一焊盘11到地的寄生电容，大于第二焊盘12产生到地的寄生电容Cgnd2。例如，原本第一焊盘11和第二焊盘12产生到地的寄生电容均为200fF，在第一焊盘11接入第一补偿调整电路13之后，第一焊盘11产生到地的寄生电容Cgnd1由200fF增大为640fF，而第二焊盘12产生到地的寄生电容不变为200fF，则图3所示的输入阻抗匹配网络10的Smith圆图如图4所示，A点为输入阻抗共轭点，在理想状态下，若不存在寄生电容Cgnd1和寄生电容Cgnd2，低噪声放大器20的阻抗值应在第一电感L1的影响下，由O点直接移动到输入阻抗共轭点A，从而实现电路的阻抗匹配。但在输入阻抗匹配网络10实际工作时，在第一焊盘11到地的寄生电容Cgnd1的影响下，低噪声放大器20的阻抗值从O点移动到B2点；接着，在第一电感L1的影响下，低噪声放大器20的阻抗值由B2点移动到C2点；最后，在第二焊盘12所形成的寄生电容Cgnd2的影响下，低噪声放大器20的阻抗值由C2点移动到D2点。由图2和图4的Smith圆图可知，在第一焊盘11到地的寄生电容Cgnd1由200fF增大至640fF时，图4所示的D2点比图2所示的D1点更接近输入阻抗共轭点A，因此，可通过增大第一焊盘11到地的寄生电容，从而减少因第一焊盘11和第二焊盘12产生到地寄生电容相等而导致输入阻抗失配的现象，提高低噪声放大器20的性能。
又例如，采用与第一焊盘11或者第二焊盘12相连的补偿调整电路13进行调整，还可以通过减小第二焊盘12产生的到地的寄生电容Cgnd2，使得第一焊盘11到地的寄生电容，大于第二焊盘12产生到地的寄生电容Cgnd2。例如，原本第一焊盘11和第二焊盘12产生到地的寄生电容均为200fF，在接入补偿调整电路13对第二焊盘12产生的到地寄生 电容Cgnd2进行调整之后，第二焊盘12产生到地的寄生电容Cgnd2由200fF减小为100fF，第一焊盘11产生到地的寄生电容Cgnd1不变为200fF，则图3所示的输入阻抗匹配网络10的Smith圆图如图5所示，A点为输入阻抗共轭点，在理想状态下，若不存在寄生电容Cgnd1和寄生电容Cgnd2，低噪声放大器20的阻抗值应在第一电感L1的影响下，由O点直接移动到输入阻抗共轭点A，从而实现电路的阻抗匹配。但在输入阻抗匹配网络10实际工作时，在第一焊盘11到地的寄生电容Cgnd1的影响下，低噪声放大器20的阻抗值从O点移动到B2点；接着，在第一电感L1的影响下，低噪声放大器20的阻抗值由B2点移动到C2点；最后，在第二焊盘12所形成的寄生电容Cgnd2的影响下，低噪声放大器20的阻抗值由C2点移动到D2点。由图2和图5的Smith圆图可知，在第二焊盘12到地的寄生电容Cgnd1由200fF减小至100fF时，图5所示的D2点比图2所示的D1点更接近输入阻抗共轭点A，因此，可通过减小第二焊盘12到地的寄生电容，从而减少因第一焊盘11和第二焊盘12产生到地寄生电容相等而导致输入阻抗失配的现象，提高低噪声放大器20的性能。
本实施例所提供的输入阻抗匹配网络10中，第一焊盘11、第二焊盘12以及一端与第一焊盘11相连，另一端与第二焊盘12相连的第一电感L1，第一焊盘11作为输入阻抗匹配网络10的输入端，而第二焊盘12作为输入阻抗匹配网络10的输出端，被配置为与低噪声放大器20的输入端相连，利用与第一焊盘11或者第二焊盘12相连的补偿调整电路13，对第一焊盘11到地的寄生电容和/或第二焊盘12到地的寄生电容进行调整，以使第一焊盘11到地的寄生电容大于第二焊盘12产生到地的寄生电容Cgnd2，从而减缓第一焊盘11到地的寄生电容Cgnd1和第二焊盘12到地的寄生电容Cgnd2相等所导致的阻抗失配问题，实现低噪声放大器20输入端的阻抗匹配。
在一实施例中，如图6所示，补偿调整电路13包括设置在第一焊盘11和接地端之间的电容补偿电路131，用于增大第一焊盘11到地的寄生电容。
一般来说，在第一焊盘11、第一电感L1和第二焊盘12串联形成的输入阻抗匹配网络10工作过程中，第一焊盘11到地的寄生电容Cgnd1和第二焊盘12到地的寄生电容Cgnd2相同，即Cgnd1＝Cgnd2。本示例中，在第一焊盘11和接地端之间设置电容补偿电路131，电容补偿电路131可以增大第一焊盘11到地的寄生电容。例如，若设置在第一焊盘11和接地端之间的电容补偿电路131在工作过程中形成寄生电容为Cgnd3，则在将电容补偿电路131接入第一焊盘11和接地端之后，第一焊盘11到地的寄生电容更新为Cgnd1’＝Cgnd1+Cgnd3>Cgnd2。可理解地，由于第一焊盘11和第二焊盘12到地的寄生电容相等， 为了使第一焊盘11到地的寄生电容大于第二焊盘12到地的寄生电容，可在第一焊盘11与接地端之间设置电容补偿电路131，以增大第一焊盘11到地的寄生电容，减缓因第一焊盘11和第二焊盘12到地的寄生电容相等所导致的阻抗失配的问题，保证低噪声放大器20输入端的阻抗匹配。
在一实施例中，如图7所示，电容补偿电路131包括平行相对设置的至少两个补偿金属板1311/1312/1313，至少两个补偿金属板1311/1312/1313在纵向的投影至少部分交叠，补偿金属板包括第一补偿金属板和第二补偿金属板，所述第一补偿金属板和所述第二补偿金属板交叉设置，所述第一补偿金属板1313与所述接地端相连，所述第二补偿金属板1311与所述第一焊盘相连。
本示例中，电容补偿电路131包括至少两个补偿金属板1311/1312/1313平行相对设置，第一个补偿金属板1313与所述接地端相连，即第一个补偿金属板1313为与接地端相连的补偿金属板，所述第二补偿金属板1311与所述第一焊盘相连，即第二补偿金属板1311为与第一焊盘11相连的补偿金属板，使得第一焊盘11通过至少两个补偿金属板1311/1312/1313与接地端相连，由于至少两个补偿金属板1311/1312/1313在纵向的投影至少部分交叠，使得至少两个补偿金属板1311/1312/1313配合形成平行板电容器，从而达到增大第一焊盘11到地的寄生电容的效果，减缓因第一焊盘11和第二焊盘12到地的寄生电容相等所导致的阻抗失配的问题，保证低噪声放大器20输入端的阻抗匹配。
在一实施例中，补偿金属板1311/1312/1313与第一焊盘11设置在基板的不同层。
本示例中，至少两个补偿金属板1311/1312/1313平行相对设置，因此，至少两个补偿金属板1311/1312/1313设置在基板的不同层上，有助于缩小输入阻抗匹配网络10的面积，进而缩小低噪声放大器20所在的放大支路的面积；补偿金属板1311/1312/1313中的第一个补偿金属板1311/1312/1313与第一焊盘11相连，将第一个补偿金属板1311/1312/1313与第一焊盘11设置在基板的不同层中，使得第一焊盘11和至少两个补偿金属板1311/1312/1313设置在基板的不同层上。
在一实施例中，如图8所示，电容补偿电路131包括串联的第三焊盘1314、第二电感L2和第四焊盘1315，第三焊盘1314与第一焊盘11相连，第四焊盘1315与接地端相连。
本示例中，第三焊盘1314、第二电感L2和第四焊盘1315串联设置在第一焊盘11与接地端之间，其中，第三焊盘1314与第一焊盘11相连，第四焊盘1315与接地端相连，使得第三焊盘1314、第二电感L2和第四焊盘1315串联所形成的电容补偿电路131可以增大第一焊盘11到地的寄生电容的效果，减缓因第一焊盘11和第二焊盘12到地的寄生电 容相等所导致的阻抗失配的问题，保证低噪声放大器20输入端的阻抗匹配。
在一实施例中，第三焊盘1314、第二电感L2、第四焊盘1315和第一焊盘11设置在基板的同一层上。
本示例中，第三焊盘1314、第二电感L2、第四焊盘1315串联形成的电容补偿电路131，与第一焊盘11设置在基板的同一层上，通过第二电感L2对第一焊盘11和第二焊盘12形成的到地的寄生电容进行抵消，从而实现低噪声放大器输入端的阻抗匹配。
在一实施例中，如图8，补偿调整电路13包括设置在第二焊盘12和接地端之间的电容调整电路132，用于减小第二焊盘12到地的寄生电容。
其中，电容调整电路132可以为对第二焊盘12的尺寸大小进行调节的电路。本实施例中，通过减小第二焊盘12的尺寸大小，从而实现减小第二焊盘12到地的寄生电容。
一般来说，在第一焊盘11、第一电感L1和第二焊盘12串联形成的输入阻抗匹配网络10工作过程中，第一焊盘11到地的寄生电容Cgnd1和第二焊盘12到地的寄生电容Cgnd2相同，即Cgnd1＝Cgnd2。本示例中，在第二焊盘12和接地端之间设置电容调整电路132，电容调整电路132可以减小第二焊盘12到地的寄生电容。例如，若设置在第二焊盘12和接地端之间的电容调整电路132，将第二焊盘12到地的寄生电容Cgnd2减小到Cgnd2’，Cgnd2’<Cgnd2＝Cgnd1，即通过减小第二焊盘12到地的寄生电容，从而减小减少因第一焊盘11和第二焊盘12产生到地寄生电容相等而导致输入阻抗共轭点失配的现象，提高低噪声放大器20的性能。
在一实施例中，第一焊盘11、第一电感L1和第二焊盘12设置在基板的同一层上。
本示例中，第一焊盘11、第一电感L1和第二焊盘12设置在基板的同一层上，使得第一焊盘11、第一电感L1和第二焊盘12串联形成的输入阻抗匹配网络10设置在基板的同一层上。一般来说，设置在基板同一层的第一焊盘11、第一电感L1和第二焊盘12形成的输入阻抗匹配网络10进行阻抗匹配的效果，有助于保障第一焊盘11、第一电感L1和第二焊盘12形成的输入阻抗匹配网络10进行阻抗匹配的效果。
在一实施例中，第一焊盘11、第一电感L1和第二焊盘12设置在基板的顶层上。
本示例中，第一焊盘11、第一电感L1和第二焊盘12设置在基板的同一层上，具体为设置在基板的顶层上，一方面可以保障第一焊盘11、第一电感L1和第二焊盘12串联形成的输入阻抗匹配网络10进行阻抗匹配的效果，另一方面可以方便第一焊盘11和第二焊盘12进行焊接操作。
本申请实施例还提供一种射频前端模组，射频前端模组包括上述实施例所提供的输入 阻抗匹配网络10和与输入阻抗匹配网络10相连的低噪声放大器20。由于输入阻抗匹配网络10中，第一焊盘11、第二焊盘12以及一端与第一焊盘11相连，另一端与第二焊盘12相连的第一电感L1，第一焊盘11作为输入阻抗匹配网络10的输入端，而第二焊盘12作为输入阻抗匹配网络10的输出端，被配置为与低噪声放大器20的输入端相连，利用与第一焊盘11或者第二焊盘12相连的补偿调整电路13，对第一焊盘11到地的寄生电容和/或第二焊盘12到地的寄生电容进行调整，以使第一焊盘11到地的寄生电容大于第二焊盘12产生到地的寄生电容Cgnd2，从而减缓第一焊盘11到地的寄生电容Cgnd1和第二焊盘12到地的寄生电容Cgnd2相等所导致的阻抗失配问题，实现低噪声放大器20输入端的阻抗匹配。
在一实施例中，如图10所示，低噪声放大器20包括射频放大电路21、第一电容元件22、第二电容元件23和阻抗匹配电路24；射频放大电路21的一端与第二焊盘12相连，另一端通过第一电容元件22与信号输出端相连；第二电容元件23一端与射频放大电路21和第一电容元件22之间的连接节点相连，另一端与接地端相连；阻抗匹配电路24一端与供电端相连，另一端与射频放大电路21和第一电容元件22之间的连接节点相连。
其中，射频放大电路21是用于实现对射频信号进行放大处理的电路。第一电容元件22是电容值可调整的元件，通过调整第一电容元件22的电容值，实现射频放大电路22与信号输出端之后相连的其他电路的阻抗匹配。在射频放大电路21和第一电容元件22之间的连接节点上，并联设置有第二电容元件23和阻抗匹配电路24，通过第二电容元件23和阻抗匹配电路24的相互作用，实现阻抗匹配。
作为一示例，如图10所示，射频放大电路21包括第一放大晶体管M21、第二放大晶体管M22、输入隔直电容C21、射频地电容C22和增益调节电感L21；第一放大晶体管M21的信号控制端通过输入隔直电容C21与第二焊盘12相连，第一放大晶体管M21的第一连接端与第二放大晶体管M22的第二连接端相连，第一放大晶体管M21的第二连接端通过增益调节电感L21与接地端相连，第二放大晶体管M22的信号控制端与阻抗匹配电路24相连，并通过射频地电容C22与接地端相连，第二放大晶体管M22的第一连接端与第一电容元件22相连。
本示例中，输入阻抗匹配网络10的第二焊盘12输出的射频信号，经过输入隔直电容C21发送给第一放大晶体管M21，利用输入隔直电容C21的隔直特性，将射频信号耦合至第一放大晶体管M21；射频信号经过第一放大晶体管M21和第二放大晶体管M22进行放大处理，且在放大处理过程中，采用射频地电容C22与第二放大晶体管M22的信号控制端和 接地端相连，可实现射频到地的效果；采用增益调节电感L21与第一放大晶体管M21的第二连接端和接地端相连，以实现增益调节的效果，从而保证放大后的射频信号的质量。第二放大晶体管M22的第一连接端与第一电容元件22相连，可将放大后的射频信号输出至第一电容元件22，利用第一电容元件22实现阻抗匹配。
作为一示例，如图10所示，阻抗匹配电路24包括并联设置的匹配电感L22、第一电阻R21和第二电阻R22；第一电阻R21的一端与供电端相连，另一端与第二放大晶体管M22的信号控制端和射频地电容C22之间的连接节点相连；匹配电感L22一端与供电端相连，另一端与第二放大晶体管M22的第一连接端和第一电容元件22之间的连接节点相连；第二电阻R22一端与供电端相连，另一端与第二放大晶体管M22的第一连接端和第一电容元件22之间的连接节点相连。
以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围，均应包含在本申请的保护范围之内。

Claims (17)

  1. 一种输入阻抗匹配网络，其特征在于，包括第一焊盘、第二焊盘以及一端与所述第一焊盘连接，另一端与所述第二焊盘连接的第一电感，所述第二焊盘的输出端作为所述输入阻抗匹配网络的输出端，被配置为与低噪声放大器的输入端相连；所述输入阻抗匹配网络还包括与所述第一焊盘和/或所述第二焊盘相连的补偿调整电路，所述补偿调整电路被配置为对所述第一焊盘到地的寄生电容和/或所述第二焊盘到地的寄生电容进行调整，以使所述第一焊盘到地的寄生电容大于所述第二焊盘到地的寄生电容。
  2. 如权利要求1所述的输入阻抗匹配网络，其特征在于，所述补偿调整电路包括设置在所述第一焊盘和所述接地端之间的电容补偿电路，用于增大所述第一焊盘到地的寄生电容。
  3. 如权利要求2所述的输入阻抗匹配网络，其特征在于，所述电容补偿电路包括平行相对设置的至少两个补偿金属板，至少两个所述补偿金属板在纵向的投影至少部分交叠，所述补偿金属板包括第一补偿金属板和第二补偿金属板，所述第一补偿金属板和所述第二补偿金属板交叉设置，所述第一补偿金属板与所述接地端相连，所述第二补偿金属板与所述第一焊盘相连。
  4. 如权利要求3所述的输入阻抗匹配网络，其特征在于，所述补偿金属板与所述第一焊盘设置在基板的不同层。
  5. 如权利要求2所述的输入阻抗匹配网络，其特征在于，所述电容补偿电路包括串联的第三焊盘、第二电感和第四焊盘，所述第三焊盘与所述第一焊盘相连，所述第四焊盘与所述接地端相连。
  6. 如权利要求5所述的输入阻抗匹配网络，其特征在于，所述第三焊盘、所述第二电感、所述第四焊盘和所述第一焊盘设置在基板的同一层上。
  7. 如权利要求1-6任一项所述的输入阻抗匹配网络，其特征在于，所述补偿调整电路包括设置在所述第二焊盘和所述接地端之间的电容调整电路，用于减小所述第二焊盘到地的寄生电容。
  8. 如权利要求1所述的输入阻抗匹配网络，其特征在于，所述第一焊盘、所述第一电感和所述第二焊盘设置在基板的同一层上。
  9. 一种射频前端模组，其特征在于，包括输入阻抗匹配网络和与所述输入阻抗匹配网络相连的低噪声放大器；
    所述输入阻抗匹配网络，包括第一焊盘、第二焊盘以及一端与所述第一焊盘连接，另一端与所述第二焊盘连接的第一电感，所述第二焊盘的输出端作为所述输入阻抗匹配网络的输出端，被配置为与低噪声放大器的输入端相连；所述输入阻抗匹配网络还包括与所述第一焊盘和/或所述第二焊盘相连的补偿调整电路，所述补偿调整电路被配置为对所述第一焊盘到地的寄生电容和/或所述第二焊盘到地的寄生电容进行调整，以使所述第一焊盘到地的寄生电容大于所述第二焊盘到地的寄生电容。
  10. 如权利要求9所述的射频前端模组，其特征在于，所述补偿调整电路包括设置在所述第一焊盘和所述接地端之间的电容补偿电路，用于增大所述第一焊盘到地的寄生电容。
  11. 如权利要求10所述的射频前端模组，其特征在于，所述电容补偿电路包括平行相对设置的至少两个补偿金属板，至少两个所述补偿金属板在纵向的投影至少部分交叠，所述补偿金属板包括第一补偿金属板和第二补偿金属板，所述第一补偿金属板和所述第二补偿金属板交叉设置，所述第一补偿金属板与所述接地端相连，所述第二补偿金属板与所述第一焊盘相连。
  12. 如权利要求11所述的射频前端模组，其特征在于，所述补偿金属板与所述第一焊盘设置在基板的不同层。
  13. 如权利要求10所述的射频前端模组，其特征在于，所述电容补偿电路包括串联的第三焊盘、第二电感和第四焊盘，所述第三焊盘与所述第一焊盘相连，所述第四焊盘与所述接地端相连。
  14. 如权利要求13所述的射频前端模组，其特征在于，所述第三焊盘、所述第二电感、所述第四焊盘和所述第一焊盘设置在基板的同一层上。
  15. 如权利要求9-14任一项所述的射频前端模组，其特征在于，所述补偿调整电路包括设置在所述第二焊盘和所述接地端之间的电容调整电路，用于减小所述第二焊盘到地的寄生电容。
  16. 如权利要求9所述的射频前端模组，其特征在于，所述第一焊盘、所述第一电感和所述第二焊盘设置在基板的同一层上。
  17. 如权利要求9所述的射频前端模组，其特征在于，所述低噪声放大器包括射频放大电路、第一电容元件、第二电容元件和阻抗匹配电路；所述射频放大电路的一端与所述第二焊盘相连，另一端通过所述第一电容元件与信号输出端相连；所述第二电容元件一端与所述射频放大电路和所述第一电容元件之间的连接节点相连，另一端与接地端相连；所 述阻抗匹配电路一端与供电端相连，另一端与所述射频放大电路和所述第一电容元件之间的连接节点相连。
PCT/CN2021/136814 2020-12-31 2021-12-09 输入阻抗匹配网络和射频前端模组 WO2022143085A1 (zh)

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