WO2022141403A1 - 像素驱动电路及显示装置 - Google Patents

像素驱动电路及显示装置 Download PDF

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Publication number
WO2022141403A1
WO2022141403A1 PCT/CN2020/142159 CN2020142159W WO2022141403A1 WO 2022141403 A1 WO2022141403 A1 WO 2022141403A1 CN 2020142159 W CN2020142159 W CN 2020142159W WO 2022141403 A1 WO2022141403 A1 WO 2022141403A1
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WIPO (PCT)
Prior art keywords
electrically connected
gate
transistor
data writing
writing module
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PCT/CN2020/142159
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English (en)
French (fr)
Inventor
高磊
王振岭
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US17/267,804 priority Critical patent/US20240005857A1/en
Publication of WO2022141403A1 publication Critical patent/WO2022141403A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present application relates to the field of display technology, and in particular, to a pixel driving circuit and a display device.
  • OLED Organic Light Emitting Diode
  • LCD Liquid Crystal Display, liquid crystal display
  • OLED Organic Light Emitting Diode
  • OLEDs are current-driven devices and are sensitive to changes in electrical characteristics of thin-film transistors.
  • changes in threshold voltage and mobility of driving transistors will directly affect the display effect of OLED devices.
  • the magnitude of the current flowing through the driving transistor is regulated by the voltage applied to the control terminal of the driving transistor, but the electric field generated by the voltage at the control terminal of the driving transistor will directly act on the electrons in the channel region, resulting in the threshold voltage and mobility of the driving transistor.
  • the change is mainly manifested in that the greater the voltage of the control terminal, the greater the electrical stress generated, the greater the threshold voltage of the driving transistor, and the lower the electron mobility.
  • the larger the threshold voltage of the driving transistor and the smaller the mobility the higher the requirements for the compensation circuit of the compensation circuit, and ultimately lead to an increase in the cost of the OLED.
  • the present application provides a pixel driving circuit and a display device, which are used for alleviating the problem that the control terminal voltage of the driving transistor causes the threshold voltage of the driving transistor to increase and the mobility to decrease.
  • the present application provides a pixel driving circuit, which includes:
  • the driving transistor includes a channel in a channel layer, a first gate in a first gate layer, and a second gate in a second gate layer, the first gate and the first gate Two gates are respectively located on opposite sides of the channel, and the output end of the driving transistor is electrically connected to the light-emitting unit;
  • a first data writing module the output end of the first data writing module is electrically connected to the first gate
  • a second data writing module the output end of the second data writing module is electrically connected with the second gate.
  • the pixel driving circuit further includes a compensation module, and the output end of the compensation module is electrically connected to the output end of the driving transistor.
  • the pixel driving circuit further includes a first storage capacitor, a first end of the first storage capacitor is electrically connected to the first gate, and a second end of the first storage capacitor is electrically connected to the first gate.
  • the terminal is electrically connected to the output terminal of the driving transistor.
  • the pixel driving circuit further includes a second storage capacitor, the first end of the second storage capacitor is electrically connected to the second gate, and the second storage capacitor is electrically connected to the second gate.
  • the terminal is electrically connected to the output terminal of the driving transistor.
  • an input end of the first data writing module is electrically connected to a first data line, and the first data line is used for inputting a first data signal to the first data writing module .
  • a control terminal of the first data writing module is electrically connected to a first scan line, and the first scan line is used to input a first scan signal to the first data writing module .
  • the first data writing module includes a first transistor, the gate of the first transistor is electrically connected to the first scan line, and the source of the first transistor is electrically connected The first data line is connected, and the drain of the first transistor is electrically connected to the first gate.
  • an input end of the second data writing module is electrically connected to a second data line, and the second data line is used to input a second data signal to the second data writing module .
  • control terminal of the second data writing module is electrically connected to the second scan line, and the second scan line is used for inputting the second scan signal to the second data writing module .
  • the second data writing module includes a second transistor, the gate of the second transistor is electrically connected to the second scan line, and the source of the second transistor is electrically connected The second data line is connected, and the drain of the second transistor is electrically connected to the second gate.
  • the compensation module includes a third transistor, the gate of the third transistor is electrically connected to the detection signal line, and the source of the third transistor is electrically connected to the reference signal line, so The drain of the third transistor is electrically connected to the output end of the driving transistor.
  • the driving transistor is an n-type transistor or a p-type transistor.
  • the input end of the driving transistor is electrically connected to a first power supply line, and the first power supply line is used for providing a first power supply signal.
  • the output end of the driving transistor is electrically connected to a second power supply line through the light emitting unit, and the second power supply line is used for providing a second power supply signal.
  • the input terminal of the first data writing module and the input terminal of the second data writing module are electrically connected to the same data line.
  • control terminal of the first data writing module and the control terminal of the second data writing module are electrically connected to the same scan line.
  • the present application also provides a display device including the above pixel driving circuit.
  • the present application also provides a display device, which includes a pixel driving circuit, and the pixel driving circuit includes:
  • the driving transistor includes a channel in a channel layer, a first gate in a first gate layer, and a second gate in a second gate layer, the first gate and the first gate Two gates are respectively located on opposite sides of the channel, and the output end of the driving transistor is electrically connected to the light-emitting unit;
  • a first data writing module the output end of the first data writing module is electrically connected to the first gate
  • the output end of the second data writing module is electrically connected to the second gate
  • a compensation module the output end of the compensation module is electrically connected with the output end of the driving transistor.
  • the pixel driving circuit further includes a first storage capacitor and a second storage capacitor; a first end of the first storage capacitor is electrically connected to the first gate, and the first storage capacitor is electrically connected to the first gate.
  • the second end of the capacitor is electrically connected to the output end of the driving transistor; the first end of the second storage capacitor is electrically connected to the second gate, and the second end of the second storage capacitor is electrically connected to the second gate. the output of the drive transistor.
  • the display device further includes the light-emitting unit, the light-emitting unit includes an anode, a light-emitting functional layer disposed on the anode, and a cathode disposed on the light-emitting functional layer, the The anode is electrically connected to the output terminal of the driving transistor.
  • the pixel driving circuit provided by the present application includes a driving transistor, a first data writing module and a second data writing module connected to the driving transistor, and the driving transistor includes a channel and a first gate located on opposite sides of the channel. and a second gate, the first data writing module is electrically connected to the first gate, the second data writing module is electrically connected to the second gate, and the output of the driving transistor The terminal is electrically connected to the light emitting unit.
  • the driving transistor is set to a double gate structure, and data signals are written to the two gates of the driving transistor through two data writing modules, thereby reducing the amount of voltage shared by the single-side gate, effectively controlling The threshold voltage and mobility of the driving transistor are drifted; and the threshold voltage of the driving transistor is kept at a low level, which reduces the requirement for the output capability of the driving voltage output circuit and is beneficial to reducing costs.
  • FIG. 1 is a first structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application
  • FIG. 2 is a schematic diagram of a second structure of a pixel driving circuit provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a wiring structure of the pixel driving circuit shown in FIG. 2 in a display device;
  • FIG. 4 is a timing diagram of the pixel drive circuit described in FIG. 2 in a threshold voltage detection stage
  • FIG. 5 is a schematic cross-sectional structure diagram of a display device provided by an embodiment of the present application.
  • Embodiments of the present application provide a pixel driving circuit and a display device, wherein the pixel driving circuit includes a driving transistor, a first data writing module and a second data writing module connected to the driving transistor, and the driving transistor includes a channel and a first gate and a second gate located on opposite sides of the channel, the first data writing module is electrically connected to the first gate, and the second data writing module is electrically connected to the second The gate is electrically connected, and the output end of the driving transistor is electrically connected to the light-emitting unit.
  • the driving transistor in a double-gate structure, and writing data signals to the two gates of the driving transistor through two data writing modules respectively, it is ensured that the single-sided gate has a smaller voltage.
  • the current flowing through the driving transistor can meet the display requirements, and the drift of the threshold voltage and mobility of the driving transistor can be effectively controlled, which is beneficial to reduce the cost of the display device.
  • FIG. 1 is a first structural schematic diagram of a pixel driving circuit provided by an embodiment of the present application.
  • the pixel driving circuit includes a driving transistor T0, a first data writing module 10 and a second data writing module 20.
  • the driving transistor T0 includes a channel CH located in the channel layer, a first gate layer located in the first gate layer.
  • the gate G1 and the second gate G2 located in the second gate layer are located on opposite sides of the channel CH, respectively.
  • the first data writing module 10 is electrically connected to the first gate G1
  • the second data writing module 20 is electrically connected to the second gate G2.
  • the first data writing module 10 is used for transmitting a first data signal to the first gate G1
  • the second data writing module 20 is used for transmitting a second data signal to the second gate G2
  • the driving transistor T0 is turned on or off under the combined action of the first data signal and the second data signal.
  • the output end of the driving transistor T0 is electrically connected to the light-emitting unit LED; when the driving transistor T0 is turned on, current flows to the light-emitting unit LED through the driving transistor T0, and the light-emitting unit LED emits light; when the driving transistor T0 is driven When the transistor T0 is turned off, the current flowing to the light-emitting unit LED is cut off, and the light-emitting unit LED does not emit light.
  • the first data signal and the second data signal are both voltage signals
  • the driving transistor T0 may be an n-type transistor or a p-type transistor.
  • the driving transistor T0 When the driving transistor T0 is an n-type transistor, and the sum of the first data signal and the second data signal is a positive voltage signal and is greater than the threshold voltage of the driving transistor T0, the driving transistor T0 conducts turn on; when the driving transistor T0 is a p-type transistor, and the sum of the first data signal and the second data signal is a negative voltage signal and is greater than the threshold voltage of the driving transistor T0, the driving transistor T0 is turned on.
  • the embodiments of the present application describe the pixel driving circuit by taking the driving transistor T0 as an n-type transistor as an example.
  • the driving transistor T0 when the driving transistor T0 is an n-type transistor, the pixel driving circuit It is easy to obtain the working principle of the pixel driving circuit when the driving transistor T0 is a p-type transistor.
  • the driving transistor is set to a double-gate structure, and the data signals are respectively transmitted to the two gates of the driving transistor through the two data writing modules, and the sum of the voltages on the two gates only needs to be greater than
  • the threshold voltage of the drive transistor can realize the turn-on of the drive transistor, which is equivalent to dividing the voltage that originally needs to be loaded on a single gate into two parts, and each gate only needs to load a part of the voltage, so as to ensure that the single-sided gate has
  • the drive transistor can be turned on at a lower voltage, effectively controlling the large electrical stress caused by the excessive gate voltage on one side, and the threshold voltage and mobility of the driving transistor caused by the large electrical stress. Drift problem.
  • the output capability of the voltage output circuit puts forward higher requirements, resulting in increased cost.
  • the pixel driving circuit provided in this embodiment can effectively control the increase of the threshold voltage of the driving transistor, and reduce the requirement on the output capability of the driving voltage output circuit, thereby reducing the cost.
  • the threshold voltage of the driving transistor T0 is 1V
  • the ideal driving voltage required to realize the normal light emission of the light-emitting unit LED is 4V
  • the actual load on the first gate G1 and the The sum of the voltages on the two gates G2 needs to reach 5V; if the voltages loaded on the first gate G1 and the second gate G2 are set to be equal, the voltage loaded on each gate only needs to be 2.5V, so compared to
  • this implementation can effectively control the electrical stress generated by the gate voltage, and further control the drift of the threshold voltage and mobility.
  • the input end of the first data writing module 10 is electrically connected to the first data line D1, and the first data line D1 is used for inputting the first data signal to the first data writing module 10;
  • the control terminal of the first data writing module 10 is electrically connected to a first scan line S1, and the first scan line S1 is used to input a first scan signal to the first data writing module 10; the first data Under the control of the first scan signal, the writing module 10 outputs the first data signal to the first gate G1, so as to realize the writing of the driving voltage of the first gate G1.
  • the input end of the second data writing module 20 is electrically connected to the second data line D2, and the second data line D2 is used for inputting the second data signal to the second data writing module 20;
  • the control terminal of the second data writing module 20 is electrically connected to the second scan line S2, and the second scan line S2 is used to input a second scan signal to the second data writing module 20; the second data Under the control of the second scan signal, the writing module 20 outputs the second data signal to the second gate G2, so as to realize the writing of the driving voltage of the second gate G2.
  • the first data line D1 and the second data line D2 may be the same data line; correspondingly, the first data signal and the second data signal may be the same.
  • the first scan line S1 and the second scan line S2 may be the same scan line; correspondingly, the first scan signal and the second scan signal may be the same. It should be understood that the first data line D1 is the same as the second data line D2, and the first scan line S1 is the same as the second scan line S2, this design can simplify the structure of the pixel driving circuit , reducing the wiring space of the pixel driving circuit in the display device.
  • the output end of the driving transistor T0 is electrically connected to the first node S.
  • the pixel driving circuit further includes a compensation module 30, the output end of the compensation module 30 is electrically connected to the first node S; the input end of the compensation module 30 is electrically connected to the reference signal line RE, the reference The signal line RE is used for inputting a reference signal to the compensation module 30 ; the control end of the compensation module 30 is electrically connected with the detection signal line SE, and the detection signal line SE is used for inputting the detection signal to the compensation module 30 . measurement signal.
  • the compensation module 30 is configured to output the reference signal to the first node S under the control of the detection signal, and to detect the threshold voltage of the driving transistor T0.
  • the process of detecting the threshold voltage of the driving transistor T0 by the compensation module 30 includes: the first data writing module 10 and the second data writing module 20 respectively write to the first gate The pole G1 and the second gate G2 transmit a voltage signal to form a gate voltage; the compensation module 30 transmits a voltage signal to the first node S, and the potential of the first node S rises;
  • the driving transistor T0 changes from the on state to the off state; the gate voltage of the driving transistor T0 and the off potential of the first node S are obtained, and the difference between the two is obtained, that is, the Threshold voltage of drive transistor T0.
  • the process of compensating the threshold voltage of the driving transistor T0 includes: obtaining the ideal driving voltage required by the light-emitting unit LED to achieve normal light emission; adding the ideal driving voltage to the threshold voltage of the driving transistor T0 to obtain the threshold voltage that needs to be loaded into the LED.
  • the actual driving voltage on the gate of the driving transistor T0; the actual driving voltage is loaded through the first gate G1 and the second gate G2 respectively.
  • the pixel driving circuit further includes a first storage capacitor C1, a first end of the first storage capacitor C1 is electrically connected to the first gate G1, and a second end of the first storage capacitor C1 is electrically connected is electrically connected to the first node S.
  • the first storage capacitor C1 is used to store the potentials of the first gate G1 and the first node S.
  • the pixel driving circuit further includes a second storage capacitor C2, a first end of the second storage capacitor C2 is electrically connected to the second gate G2, and a second end of the second storage capacitor C2 is electrically connected is electrically connected to the first node S.
  • the second storage capacitor C2 is used to store the potentials of the second gate G2 and the first node S.
  • the input terminal of the driving transistor T0 is electrically connected to a first power supply line VDD, and the first power supply line VDD is used for providing a first power supply signal;
  • the output terminal of the driving transistor T0 is electrically connected to the light-emitting unit LED through the light-emitting unit LED.
  • both the first power supply signal and the second power supply signal are voltage signals, and the first power supply signal is greater than the second power supply signal; for example, the first power supply signal is 5V, the first power supply signal is The second power supply signal is 0V.
  • FIG. 2 is a schematic diagram of a second structure of a pixel driving circuit provided by an embodiment of the present application.
  • the pixel driving circuit includes a driving transistor T0, a first data writing module 10, a second data writing module 20, a compensation module 30, a first storage capacitor C1 and a second storage capacitor C2.
  • the driving transistor T0 includes a channel CH located in the channel layer, a first gate G1 located in the first gate layer, and a second gate G2 located in the second gate layer.
  • the second gates G2 are located on opposite sides of the channel CH, respectively.
  • the first data writing module 10 is electrically connected to the first gate G1
  • the second data writing module 20 is electrically connected to the second gate G2.
  • the first data writing module 10 is used for transmitting a first data signal to the first gate G1
  • the second data writing module 20 is used for transmitting a second data signal to the second gate G2
  • the driving transistor T0 is turned on or off under the combined action of the first data signal and the second data signal.
  • the input terminal of the driving transistor T0 is electrically connected to the first power supply line VDD, and the first power supply line VDD is used for providing a first power supply signal; the output terminal of the driving transistor T0 is electrically connected to the light-emitting unit through the first node S LED, the other end of the light-emitting unit LED is electrically connected to the second power line VSS.
  • the driving transistor T0 When the driving transistor T0 is turned on, the current flows to the light-emitting unit LED through the driving transistor T0, and the light-emitting unit LED emits light; when the driving transistor T0 is turned off, the current flowing to the light-emitting unit LED is cut off , the light-emitting unit LED does not emit light.
  • the input end of the first data writing module 10 is electrically connected to a first data line D1, and the first data line D1 is used to input a first data signal to the first data writing module 10; the first data line D1 is used for inputting a first data signal to the first data writing module 10;
  • the control terminal of the data writing module 10 is electrically connected to the first scan line S1, and the first scan line S1 is used for inputting a first scan signal to the first data writing module 10; the first data writing module 10. Under the control of the first scan signal, output the first data signal to the first gate G1, so as to realize writing of the driving voltage of the first gate G1.
  • the first data writing module 10 includes a first transistor T1, the gate of the first transistor T1 is electrically connected to the first scan line S1, and the source of the first transistor T1 is electrically connected to the first scan line S1.
  • a data line D1 the drain of the first transistor T1 is electrically connected to the first gate G1.
  • the first transistor T1 may be an n-type transistor or a p-type transistor.
  • the input end of the second data writing module 20 is electrically connected to a second data line D2, and the second data line D2 is used to input a second data signal to the second data writing module 20; the second data line D2 is used for inputting a second data signal to the second data writing module 20;
  • the control terminal of the data writing module 20 is electrically connected to the second scan line S2, and the second scan line S2 is used for inputting a second scan signal to the second data writing module 20; the second data writing module 20. Under the control of the second scan signal, output the second data signal to the second gate G2, so as to realize the writing of the driving voltage of the second gate G2.
  • the second data writing module 20 includes a second transistor T2, the gate of the second transistor T2 is electrically connected to the second scan line S1, and the source of the second transistor T2 is electrically connected to the first scan line S1.
  • Two data lines D2, the drain of the second transistor T2 is electrically connected to the second gate G2.
  • the second transistor T2 may be an n-type transistor or a p-type transistor.
  • the output end of the compensation module 30 is electrically connected to the first node S; the input end of the compensation module 30 is electrically connected to the reference signal line RE, and the reference signal line RE is used for sending the compensation module 30 to the compensation module 30 .
  • a reference signal is input; the control terminal of the compensation module 30 is electrically connected to the detection signal line SE, and the detection signal line SE is used for inputting the detection signal to the compensation module 30 .
  • the compensation module 30 is configured to output the reference signal to the first node S under the control of the detection signal, and to detect the threshold voltage of the driving transistor T0.
  • the compensation module 30 includes a third transistor T3, the gate of the third transistor T3 is electrically connected to the detection signal line SE, and the source of the third transistor T3 is electrically connected to the reference signal line RE, The drain of the third transistor T3 is electrically connected to the first node S.
  • the third transistor T3 may be an n-type transistor or a p-type transistor.
  • the first end of the first storage capacitor C1 is electrically connected to the first gate G1 , and the second end of the first storage capacitor C1 is electrically connected to the first node S.
  • the first storage capacitor C1 is used to store the potentials of the first gate G1 and the first node S.
  • the first end of the second storage capacitor C2 is electrically connected to the second gate G2, and the second end of the second storage capacitor C2 is electrically connected to the first node S.
  • the second storage capacitor C2 is used to store the potentials of the second gate G2 and the first node S.
  • the driving transistor T0 is a double-gate structure, and the data signals are respectively transmitted to the two gates of the driving transistor through the two data writing modules, and only the voltages on the two gates are required.
  • the turn-on of the drive transistor can be realized if the sum is greater than the threshold voltage of the drive transistor.
  • the drive transistor can be turned on with a relatively small voltage, and the electrical stress generated by the gate voltage can be effectively controlled, thereby solving the drift problem of the threshold voltage and mobility of the drive transistor caused by excessive electrical stress.
  • the larger the one-side gate voltage of the drive transistor the greater the electrical stress generated, the greater the threshold voltage of the drive transistor, and the greater the drive voltage that needs to be loaded to the gate of the drive transistor, which will affect the drive transistor.
  • the output capability of the voltage output circuit puts forward higher requirements, resulting in increased cost.
  • the pixel driving circuit provided in this embodiment can effectively control the increase of the threshold voltage of the driving transistor, and reduce the requirement on the output capability of the driving voltage output circuit, thereby reducing the cost.
  • the first data line D1 and the second data line D2 may be the same data line; correspondingly, the first data signal and the second data signal may be the same.
  • the first scan line S1 and the second scan line S2 may be the same scan line; correspondingly, the first scan signal and the second scan signal may be the same. It should be understood that the first data line D1 is the same as the second data line D2, and the first scan line S1 is the same as the second scan line S2, this design can simplify the structure of the pixel driving circuit , reducing the wiring space of the pixel driving circuit in the display device.
  • FIG. 3 is a schematic diagram of a wiring structure of the pixel driving circuit shown in FIG. 2 in a display device.
  • the display device includes a plurality of pixel driving circuits, and each pixel driving circuit corresponds to one display unit or pixel unit of the display device;
  • FIG. 3 only shows the wiring of four adjacent pixel driving circuits in the display device Structure, those skilled in the art can easily obtain the wiring structures of other pixel driving circuits in the display device according to the technical features disclosed in the present application.
  • the input terminal of the first data writing module 10 and the input terminal of the second data writing module 20 of the pixel driving circuit are both electrically connected to the same data line Data, and the first data writing module 10 is electrically connected to the same data line Data.
  • the control end of the input module 10 and the control end of the second data writing module 20 are both electrically connected to the same scan line Scan.
  • the arrangement and connection relationship of the plurality of pixel driving circuits have the following characteristics: the plurality of pixel driving circuits are arranged along a matrix of N rows and M columns, where N and M are both integers greater than 0;
  • the first data writing module 10 and the second data writing module 20 of the pixel driving circuit in the same row transmit scan signals to it through the same scan line Scan;
  • Both the data writing module 20 and the second data writing module 20 transmit data signals to it through the same data line Data.
  • this embodiment Compared with the prior art, although this embodiment increases the number of gates of driving transistors and the number of data writing modules, it does not increase the number of scan lines and the number of data lines; therefore, this embodiment effectively controls On the premise that the threshold voltage and mobility of the driving transistor are shifted, the wiring of the pixel driving circuit in the display device will not be complicated.
  • FIG. 4 is a timing diagram of the pixel driving circuit described in FIG. 2 in the threshold voltage detection stage.
  • the input end of the first data writing module 10 and the input end of the second data writing module 20 of the pixel driving circuit are both electrically connected to the same data line Data, and the data line Data is connected to the first data line Data.
  • the data writing module 10 and the second data writing module 20 transmit the data signal D'.
  • the control terminal of the first data writing module 10 and the control terminal of the second data writing module 20 are both electrically connected to the same scan line Scan, and the scan line Scan sends the first data writing module 10 and the The second data writing module 20 transmits the scan signal G'.
  • the input end of the compensation module 30 is electrically connected to the reference signal line RE, and the reference signal line RE is used for inputting the reference signal Vref to the compensation module 30 .
  • the control end of the compensation module 30 is electrically connected to the detection signal line SE, and the detection signal line SE is used for inputting the detection signal Sense to the compensation module 30 .
  • the output end of the compensation module 30 is electrically connected to the first node S, and the potential of the first node S is marked as the node potential Vs.
  • the timing chart shown in FIG. 4 corresponds to the voltage changes of each signal in the threshold voltage detection stage of the pixel driving circuit.
  • the scan signal G' and the data signal D' are both at high level
  • the first transistor T1 and the second transistor T2 are turned on
  • the first gate G1 and the second gate G2 of the driving transistor T0 Receive a high-level data signal D'
  • both the first end of the first storage capacitor C1 and the first end of the second storage capacitor C2 are at a high level
  • the detection signal Sense is at a high level
  • the third transistor T3 conducts
  • the reference signal Vref resets the node potential Vs of the first node S and keeps the low level.
  • the method for compensating the driving transistor T0 is: obtaining the ideal driving voltage required by the light-emitting unit LED to achieve normal light emission; Adding the threshold voltage of the driving transistor T0, the actual driving voltage that needs to be loaded on the gate of the driving transistor T0 is obtained; the actual driving voltage is loaded through the first gate G1 and the second gate G2 respectively.
  • the pixel driving circuit includes a driving transistor, a first data writing module and a second data writing module connected to the driving transistor, and the driving transistor includes a first gate and a second data writing module. Two gates, the first data writing module is electrically connected to the first gate, the second data writing module is electrically connected to the second gate, and the output terminal of the driving transistor is electrically connected connected to the light-emitting unit.
  • the driving transistor is set to a double-gate structure, and data signals are written to the two gates of the driving transistor through two data writing modules, thereby reducing the amount of voltage shared by the single-side gate, effectively
  • the threshold voltage and mobility drift of the driving transistor are controlled; and the threshold voltage of the driving transistor is kept at a low level, which reduces the requirement on the output capability of the driving voltage output circuit and is beneficial to reducing the cost.
  • Embodiments of the present application further provide a display device, where the display device includes the pixel driving circuit provided by the above-mentioned embodiments.
  • FIG. 5 is a schematic cross-sectional structure diagram of a display device provided by an embodiment of the present application.
  • the display device may be an OLED display device or a Mini LED display device.
  • the display device includes a base substrate 101, a second gate G2 disposed on the base substrate 101, a second gate insulating layer 102 covering the second gate G2, and a second gate G2 disposed on the second gate
  • the source electrode 106 and the drain electrode 107 are respectively connected to opposite ends of the active layer 103 through vias on the interlayer insulating layer 105; the channel layer 103 includes a channel CH, the The first gate G1 and the second gate G2 are respectively located on opposite sides of the channel CH, the second gate G2, the channel layer 103, the first gate G1, the The source electrode 106 and the drain electrode 107 together constitute a dual-gate driving transistor, and the dual-gate driving transistor is equivalent to the driving transistor T0 shown in any one of FIG. 1 to FIG. 3 .
  • the anode 109 is connected to the drain 107 through a via hole on the flat layer 108, the light-emitting functional layer 111 is connected to the anode 109, and the cathode 112 is connected to the light-emitting functional layer 111; the The anode 109 , the light-emitting functional layer 111 and the cathode 112 together constitute a light-emitting element, and the light-emitting element corresponds to the light-emitting unit LED shown in any one of FIGS. 1 to 3 .
  • the display device provided by this embodiment includes the pixel driving circuit provided by the embodiment of the present application, and thus has the following beneficial effects:
  • the driving transistor of the display device is a double-gate structure, and two data writing modules are used to write to the driving transistor respectively.
  • the two gates of the two gates write data signals, reducing the amount of voltage shared by the single-side gate, effectively controlling the threshold voltage and mobility drift of the driving transistor; and this design keeps the threshold voltage of the driving transistor at a low level , reducing the requirement on the output capability of the driving voltage output circuit, which is beneficial to reducing the cost of the display device.

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Abstract

本申请提供一种像素驱动电路及显示装置，所述像素驱动电路包括驱动晶体管和连接所述驱动晶体管的第一数据写入模块和第二数据写入模块，所述驱动晶体管包括沟道和位于沟道相对两侧的第一栅极和第二栅极，所述第一数据写入模块与所述第一栅极电性连接，所述第二数据写入模块与所述第二栅极电性连接，所述驱动晶体管的输出端电性连接至发光单元。

Description

像素驱动电路及显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种像素驱动电路及显示装置。
 背景技术
相较于传统的LCD（Liquid Crystal Display，液晶显示器）技术，OLED（Organic Light Emitting Diode，有机发光二极管）具有更高的对比度、更快的反应速度和广视角等优势，逐渐取代LCD成为主流显示技术。
OLED属于电流驱动型器件，对薄膜晶体管的电特性变化比较敏感，尤其是驱动晶体管的阈值电压和迁移率的变化将会直接影响OLED器件的显示效果。流经驱动晶体管的电流大小是通过施加在该驱动晶体管控制端的电压来调控的，但是驱动晶体管控制端的电压产生的电场会直接作用在沟道区的电子上，导致驱动晶体管的阈值电压和迁移率发生变化，主要表现为，控制端的电压越大，产生的电应力越大，则驱动晶体管的阈值电压越大，电子迁移率越小。而驱动晶体管的阈值电压越大、迁移率越小，对补偿电路的补偿能力要求就越高，并最终导致OLED的成本升高。
所以，目前的电流驱动型显示器件中存在驱动晶体管的控制端电压过大导致该驱动晶体管的阈值电压增大、迁移率减小的问题。
 技术问题
目前的电流驱动型显示器件中，存在驱动晶体管的控制端电压过大导致该驱动晶体管的阈值电压增大、迁移率减小的问题。
 技术解决方案
本申请提供一种像素驱动电路及显示装置，用于缓解驱动晶体管的控制端电压导致该驱动晶体管的阈值电压增大、迁移率减小的问题。
本申请提供一种像素驱动电路，其包括：
驱动晶体管，所述驱动晶体管包括位于沟道层的沟道、位于第一栅极层的第一栅极和位于第二栅极层的第二栅极，所述第一栅极和所述第二栅极分别位于所述沟道的相对两侧，所述驱动晶体管的输出端与发光单元电性连接；
第一数据写入模块，所述第一数据写入模块的输出端与所述第一栅极电性连接；
第二数据写入模块，所述第二数据写入模块的输出端与所述第二栅极电性连接。
在本申请的像素驱动电路中，所述像素驱动电路还包括补偿模块，所述补偿模块的输出端与所述驱动晶体管的输出端电性连接。
在本申请的像素驱动电路中，所述像素驱动电路还包括第一存储电容，所述第一存储电容的第一端电性连接所述第一栅极，所述第一存储电容的第二端电性连接所述驱动晶体管的输出端。
在本申请的像素驱动电路中，所述像素驱动电路还包括第二存储电容，所述第二存储电容的第一端电性连接所述第二栅极，所述第二存储电容的第二端电性连接所述驱动晶体管的输出端。
在本申请的像素驱动电路中，所述第一数据写入模块的输入端电性连接第一数据线，所述第一数据线用于向所述第一数据写入模块输入第一数据信号。
在本申请的像素驱动电路中，所述第一数据写入模块的控制端电性连接第一扫描线，所述第一扫描线用于向所述第一数据写入模块输入第一扫描信号。
在本申请的像素驱动电路中，所述第一数据写入模块包括第一晶体管，所述第一晶体管的栅极电性连接所述第一扫描线，所述第一晶体管的源极电性连接所述第一数据线，所述第一晶体管的漏极电性连接所述第一栅极。
在本申请的像素驱动电路中，所述第二数据写入模块的输入端电性连接第二数据线，所述第二数据线用于向所述第二数据写入模块输入第二数据信号。
在本申请的像素驱动电路中，所述第二数据写入模块的控制端电性连接第二扫描线，所述第二扫描线用于向所述第二数据写入模块输入第二扫描信号。
在本申请的像素驱动电路中，所述第二数据写入模块包括第二晶体管，所述第二晶体管的栅极电性连接所述第二扫描线，所述第二晶体管的源极电性连接所述第二数据线，所述第二晶体管的漏极电性连接所述第二栅极。
在本申请的像素驱动电路中，所述补偿模块包括第三晶体管，所述第三晶体管的栅极电性连接侦测信号线，所述第三晶体管的源极电性连接参考信号线，所述第三晶体管的漏极电性连接所述驱动晶体管的输出端。
在本申请的像素驱动电路中，所述驱动晶体管为n型晶体管或p型晶体管。
在本申请的像素驱动电路中，所述驱动晶体管的输入端电性连接第一电源线，所述第一电源线用于提供第一电源信号。
在本申请的像素驱动电路中，所述驱动晶体管的输出端通过所述发光单元电性连接至第二电源线，所述第二电源线用于提供第二电源信号。
在本申请的像素驱动电路中，所述第一数据写入模块的输入端与所述第二数据写入模块的输入端电性连接同一条数据线。
在本申请的像素驱动电路中，所述第一数据写入模块的控制端与所述第二数据写入模块的控制端电性连接同一条扫描线。
本申请还提供一种显示装置，其包括如上所述的像素驱动电路。
本申请还提供一种显示装置，其包括像素驱动电路，所述像素驱动电路包括：
驱动晶体管，所述驱动晶体管包括位于沟道层的沟道、位于第一栅极层的第一栅极和位于第二栅极层的第二栅极，所述第一栅极和所述第二栅极分别位于所述沟道的相对两侧，所述驱动晶体管的输出端与发光单元电性连接；
第一数据写入模块，所述第一数据写入模块的输出端与所述第一栅极电性连接；
第二数据写入模块，所述第二数据写入模块的输出端与所述第二栅极电性连接；
补偿模块，所述补偿模块的输出端与所述驱动晶体管的输出端电性连接。
在本申请的显示装置中，所述像素驱动电路还包括第一存储电容和第二存储电容；所述第一存储电容的第一端电性连接所述第一栅极，所述第一存储电容的第二端电性连接所述驱动晶体管的输出端；所述第二存储电容的第一端电性连接所述第二栅极，所述第二存储电容的第二端电性连接所述驱动晶体管的输出端。
在本申请的显示装置中，所述显示装置还包括所述发光单元，所述发光单元包括阳极、设置于所述阳极上的发光功能层和设置于所述发光功能层上的阴极，所述阳极与所述驱动晶体管的输出端电性连接。
 有益效果
本申请提供的像素驱动电路包括驱动晶体管和连接所述驱动晶体管的第一数据写入模块和第二数据写入模块，所述驱动晶体管包括沟道和位于沟道相对两侧的第一栅极和第二栅极，所述第一数据写入模块与所述第一栅极电性连接，所述第二数据写入模块与所述第二栅极电性连接，所述驱动晶体管的输出端电性连接至发光单元。本申请通过将驱动晶体管设置为双栅结构，并通过两个数据写入模块分别向驱动晶体管的两个栅极写入数据信号，从而减小了单侧栅极所分担的电压量，有效控制驱动晶体管的阈值电压和迁移率的漂移；并且使驱动晶体管的阈值电压保持在较低水平，降低对驱动电压输出电路的输出能力的要求，有利于降低成本。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的像素驱动电路的第一种结构示意图；
图2是本申请实施例提供的像素驱动电路的第二种结构示意图；
图3是图2所示的像素驱动电路在显示装置中的一种布线结构示意图；
图4是图2所述的像素驱动电路在阈值电压侦测阶段的时序图；
图5是本申请实施例提供的显示装置的一种截面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
本申请实施例提供一种像素驱动电路及显示装置，所述像素驱动电路包括驱动晶体管和连接所述驱动晶体管的第一数据写入模块和第二数据写入模块，所述驱动晶体管包括沟道和位于沟道相对两侧的第一栅极和第二栅极，所述第一数据写入模块与所述第一栅极电性连接，所述第二数据写入模块与所述第二栅极电性连接，所述驱动晶体管的输出端电性连接至发光单元。本申请实施例通过将驱动晶体管设置为双栅结构，并通过两个数据写入模块分别向驱动晶体管的两个栅极写入数据信号，保证单侧栅极在具有较小电压的情况下即可使流经驱动晶体管的电流满足显示需求，有效控制驱动晶体管的阈值电压和迁移率的漂移，有利于降低显示装置的成本。
请参阅图1，图1是本申请实施例提供的像素驱动电路的第一种结构示意图。所述像素驱动电路包括驱动晶体管T0、第一数据写入模块10和第二数据写入模块20，所述驱动晶体管T0包括位于沟道层的沟道CH、位于第一栅极层的第一栅极G1和位于第二栅极层的第二栅极G2，所述第一栅极G1和所述第二栅极G2分别位于所述沟道CH的相对两侧。所述第一数据写入模块10与所述第一栅极G1电性连接，所述第二数据写入模块20与所述第二栅极G2电性连接。所述第一数据写入模块10用于向所述第一栅极G1传输第一数据信号，所述第二数据写入模块20用于向所述第二栅极G2传输第二数据信号，所述驱动晶体管T0在所述第一数据信号和所述第二数据信号的共同作用下实现导通或关闭。所述驱动晶体管T0的输出端电性连接发光单元LED；当所述驱动晶体管T0导通时，电流通过所述驱动晶体管T0流向所述发光单元LED，所述发光单元LED发光；当所述驱动晶体管T0关闭时，流向所述发光单元LED的电流被截止，所述发光单元LED不发光。
具体地，所述第一数据信号和所述第二数据信号均为电压信号，所述驱动晶体管T0可以是n型晶体管或p型晶体管。当所述驱动晶体管T0为n型晶体管时，所述第一数据信号与所述第二数据信号之和为正电压信号，且大于所述驱动晶体管T0的阈值电压时，所述驱动晶体管T0导通；当所述驱动晶体管T0为p型晶体管时，所述第一数据信号与所述第二数据信号之和为负电压信号，且大于所述驱动晶体管T0的阈值电压时，所述驱动晶体管T0导通。本申请实施例以所述驱动晶体管T0为n型晶体管为例对所述像素驱动电路进行说明，应当理解的是，基于本申请实施例以驱动晶体管T0为n型晶体管时对所述像素驱动电路的描述，容易得出驱动晶体管T0为p型晶体管时所述像素驱动电路的工作原理。
需要说明的是，本实施例将驱动晶体管设置为双栅结构，并通过两个数据写入模块分别向驱动晶体管的两个栅极传输数据信号，只需两个栅极上的电压之和大于驱动晶体管的阈值电压即可实现驱动晶体管的导通，相当于将原来需要加载在的单个栅极上的电压分成两部分，每个栅极只需加载一部分电压，从而保证单侧栅极在具有较小电压的情况下即可实现驱动晶体管的导通，有效控制因单侧栅极电压过大而产生的较大电应力，并因较大电应力而导致的驱动晶体管阈值电压和迁移率的漂移问题。
此外，驱动晶体管的单侧栅极电压越大，产生的电应力越大，该驱动晶体管的阈值电压也越大，进而需要加载到驱动晶体管栅极的驱动电压也会越大，这就对驱动电压输出电路的输出能力提出了更高的要求，造成成本增加。本实施例提供的像素驱动电路可以有效控制驱动晶体管阈值电压的增加，降低对驱动电压输出电路的输出能力的要求，从而降低成本。
例如，针对本申请实施例提供的像素驱动电路，所述驱动晶体管T0的阈值电压为1V，实现发光单元LED正常发光所需要的理想驱动电压为4V，那么实际加载在第一栅极G1和第二栅极G2上的电压的总和需要达到5V；若设置第一栅极G1和第二栅极G2加载的电压相等，则每个栅极上加载的电压只需2.5V，因此，相比于单栅极结构的驱动晶体管需要加载5V的驱动电压的情况，本实施可以有效控制栅极电压产生的电应力，进而控制阈值电压和迁移率的漂移。
进一步地，所述第一数据写入模块10的输入端电性连接第一数据线D1，所述第一数据线D1用于向所述第一数据写入模块10输入第一数据信号；所述第一数据写入模块10的控制端电性连接第一扫描线S1，所述第一扫描线S1用于向所述第一数据写入模块10输入第一扫描信号；所述第一数据写入模块10在所述第一扫描信号的控制下，将所述第一数据信号输出至所述第一栅极G1，从而实现对所述第一栅极G1的驱动电压的写入。
进一步地，所述第二数据写入模块20的输入端电性连接第二数据线D2，所述第二数据线D2用于向所述第二数据写入模块20输入第二数据信号；所述第二数据写入模块20的控制端电性连接第二扫描线S2，所述第二扫描线S2用于向所述第二数据写入模块20输入第二扫描信号；所述第二数据写入模块20在所述第二扫描信号的控制下，将所述第二数据信号输出至所述第二栅极G2，从而实现对所述第二栅极G2的驱动电压的写入。
可选地，所述第一数据线D1和所述第二数据线D2可以是相同的数据线；与之对应地，所述第一数据信号与所述第二数据信号可以相同。所述第一扫描线S1和所述第二扫描线S2可以是相同的扫描线；与之对应地，所述第一扫描信号与所述第二扫描信号可以相同。应当理解的是，所述第一数据线D1与所述第二数据线D2相同，以及述第一扫描线S1与所述第二扫描线S2相同，该设计可以简化所述像素驱动电路的结构，缩减所述像素驱动电路在显示装置中布线空间。
进一步地，所述驱动晶体管T0的输出端电性连接第一节点S。所述像素驱动电路还包括补偿模块30，所述补偿模块30的输出端与所述第一节点S电性连接；所述补偿模块30的输入端与参考信号线RE电性连接，所述参考信号线RE用于向所述补偿模块30输入参考信号；所述补偿模块30的控制端与侦测信号线SE电性连接，所述侦测信号线SE用于向所述补偿模块30输入侦测信号。所述补偿模块30用于在所述侦测信号的控制下，将所述参考信号输出至所述第一节点S，并实现对所述驱动晶体管T0的阈值电压的侦测。
具体地，所述补偿模块30对所述驱动晶体管T0的阈值电压进行侦测的过程包括：所述第一数据写入模块10和所述第二数据写入模块20分别向所述第一栅极G1和所述第二栅极G2传输电压信号，形成栅极电压；所述补偿模块30向所述第一节点S传输电压信号，所述第一节点S的电位抬升；当所述第一节点S的电位抬升到截止电位时，驱动晶体管T0由导通状态变为截止状态；获取驱动晶体管T0的栅极电压以及第一节点S的截止电位，并将二者作差，即得到所述驱动晶体管T0的阈值电压。
对所述驱动晶体管T0的阈值电压进行补偿的过程包括：获取发光单元LED实现正常发光所需的理想驱动电压；将所述理想驱动电压加上所述驱动晶体管T0的阈值电压，得到需要加载到所述驱动晶体管T0栅极上的实际驱动电压；将该实际驱动电压分别通过第一栅极G1和第二栅极G2进行加载。
进一步地，所述像素驱动电路还包括第一存储电容C1，所述第一存储电容C1的第一端与所述第一栅极G1电性连接，所述第一存储电容C1的第二端与所述第一节点S电性连接。所述第一存储电容C1用于存储所述第一栅极G1和所述第一节点S的电位。
进一步地，所述像素驱动电路还包括第二存储电容C2，所述第二存储电容C2的第一端与所述第二栅极G2电性连接，所述第二存储电容C2的第二端与所述第一节点S电性连接。所述第二存储电容C2用于存储所述第二栅极G2和所述第一节点S的电位。
进一步地，所述驱动晶体管T0的输入端电性连接第一电源线VDD，所述第一电源线VDD用于提供第一电源信号；所述驱动晶体管T0的输出端通过所述发光单元LED电性连接至第二电源线VSS，所述第二电源线VSS用于提供第二电源信号。可选地，所述第一电源信号和所述第二电源信号均为电压信号，所述第一电源信号大于所述第二电源信号；比如，所述第一电源信号为5V，所述第二电源信号为0V，当所述驱动晶体管T0导通时，所述发光单元LED的两端会存在5V的电压差，进而产生流经所述发光单元LED的电流，所述发光单元LED实现发光。
在一种实施例中，请参阅图2，图2是本申请实施例提供的像素驱动电路的第二种结构示意图。所述像素驱动电路包括驱动晶体管T0、第一数据写入模块10、第二数据写入模块20、补偿模块30、第一存储电容C1和第二存储电容C2。
所述驱动晶体管T0包括位于沟道层的沟道CH、位于第一栅极层的第一栅极G1和位于第二栅极层的第二栅极G2，所述第一栅极G1和所述第二栅极G2分别位于所述沟道CH的相对两侧。所述第一数据写入模块10与所述第一栅极G1电性连接，所述第二数据写入模块20与所述第二栅极G2电性连接。所述第一数据写入模块10用于向所述第一栅极G1传输第一数据信号，所述第二数据写入模块20用于向所述第二栅极G2传输第二数据信号，所述驱动晶体管T0在所述第一数据信号和所述第二数据信号的共同作用下实现导通或关闭。
所述驱动晶体管T0的输入端电性连接第一电源线VDD，所述第一电源线VDD用于提供第一电源信号；所述驱动晶体管T0的输出端通过第一节点S电性连接发光单元LED，所述发光单元LED的另一端电性连接第二电源线VSS。当所述驱动晶体管T0导通时，电流通过所述驱动晶体管T0流向所述发光单元LED，所述发光单元LED发光；当所述驱动晶体管T0关闭时，流向所述发光单元LED的电流被截止，所述发光单元LED不发光。
所述第一数据写入模块10的输入端电性连接第一数据线D1，所述第一数据线D1用于向所述第一数据写入模块10输入第一数据信号；所述第一数据写入模块10的控制端电性连接第一扫描线S1，所述第一扫描线S1用于向所述第一数据写入模块10输入第一扫描信号；所述第一数据写入模块10在所述第一扫描信号的控制下，将所述第一数据信号输出至所述第一栅极G1，从而实现对所述第一栅极G1的驱动电压的写入。
所述第一数据写入模块10包括第一晶体管T1，所述第一晶体管T1的栅极电性连接所述第一扫描线S1，所述第一晶体管T1的源极电性连接所述第一数据线D1，所述第一晶体管T1的漏极电性连接所述第一栅极G1。可选地，所述第一晶体管T1可以是n型晶体管或p型晶体管。
所述第二数据写入模块20的输入端电性连接第二数据线D2，所述第二数据线D2用于向所述第二数据写入模块20输入第二数据信号；所述第二数据写入模块20的控制端电性连接第二扫描线S2，所述第二扫描线S2用于向所述第二数据写入模块20输入第二扫描信号；所述第二数据写入模块20在所述第二扫描信号的控制下，将所述第二数据信号输出至所述第二栅极G2，从而实现对所述第二栅极G2的驱动电压的写入。
所述第二数据写入模块20包括第二晶体管T2，所述第二晶体管T2的栅极电性连接所述第二扫描线S1，所述第二晶体管T2的源极电性连接所述第二数据线D2，所述第二晶体管T2的漏极电性连接所述第二栅极G2。可选地，所述第二晶体管T2可以是n型晶体管或p型晶体管。
所述补偿模块30的输出端与所述第一节点S电性连接；所述补偿模块30的输入端与参考信号线RE电性连接，所述参考信号线RE用于向所述补偿模块30输入参考信号；所述补偿模块30的控制端与侦测信号线SE电性连接，所述侦测信号线SE用于向所述补偿模块30输入侦测信号。所述补偿模块30用于在所述侦测信号的控制下，将所述参考信号输出至所述第一节点S，并实现对所述驱动晶体管T0的阈值电压的侦测。
所述补偿模块30包括第三晶体管T3，所述第三晶体管T3的栅极电性连接所述侦测信号线SE，所述第三晶体管T3的源极电性连接所述参考信号线RE，所述第三晶体管T3的漏极电性连接所述第一节点S。可选地，所述第三晶体管T3可以是n型晶体管或p型晶体管。
所述第一存储电容C1的第一端与所述第一栅极G1电性连接，所述第一存储电容C1的第二端与所述第一节点S电性连接。所述第一存储电容C1用于存储所述第一栅极G1和所述第一节点S的电位。
所述第二存储电容C2的第一端与所述第二栅极G2电性连接，所述第二存储电容C2的第二端与所述第一节点S电性连接。所述第二存储电容C2用于存储所述第二栅极G2和所述第一节点S的电位。
需要说明的是，在本实施例中，所述驱动晶体管T0为双栅结构，通过两个数据写入模块分别向驱动晶体管的两个栅极传输数据信号，只需两个栅极上的电压之和大于驱动晶体管的阈值电压即可实现驱动晶体管的导通，相当于将原来需要加载在的单个栅极上的电压分成两部分，每个栅极只需加载一部分电压，从而保证单侧栅极在具有较小电压的情况下即可实现驱动晶体管的导通，有效控制栅极电压产生的电应力，从而解决因电应力过大而导致的驱动晶体管阈值电压和迁移率的漂移问题。此外，驱动晶体管的单侧栅极电压越大，产生的电应力越大，该驱动晶体管的阈值电压也越大，进而需要加载到驱动晶体管栅极的驱动电压也会越大，这就对驱动电压输出电路的输出能力提出了更高的要求，造成成本增加。本实施例提供的像素驱动电路可以有效控制驱动晶体管阈值电压的增加，降低对驱动电压输出电路的输出能力的要求，从而降低成本。
可选地，所述第一数据线D1和所述第二数据线D2可以是相同的数据线；与之对应地，所述第一数据信号与所述第二数据信号可以相同。所述第一扫描线S1和所述第二扫描线S2可以是相同的扫描线；与之对应地，所述第一扫描信号与所述第二扫描信号可以相同。应当理解的是，所述第一数据线D1与所述第二数据线D2相同，以及述第一扫描线S1与所述第二扫描线S2相同，该设计可以简化所述像素驱动电路的结构，缩减所述像素驱动电路在显示装置中布线空间。
请参阅图2及图3，其中，图3是图2所示的像素驱动电路在显示装置中的一种布线结构示意图。需要说明的是，显示装置包括多个像素驱动电路，每一个像素驱动电路对应显示装置的一个显示单元或像素单元；图3中仅示出了显示装置中的相邻四个像素驱动电路的布线结构，本领域的技术人员，容易根据本申请公开的技术特征得到显示装置中的其它像素驱动电路的布线结构。
在图3所示的实施例中，像素驱动电路的第一数据写入模块10的输入端和第二数据写入模块20的输入端均与同一条数据线Data电性连接，第一数据写入模块10的控制端和第二数据写入模块20的控制端均与同一条扫描线Scan电性连接。其中，关于单个像素驱动电路的结构特征的描述请参考上面实施例，此处不再赘述。
在本实施例中，多个像素驱动电路的排布和连接关系具有以下特征：多个像素驱动电路沿N行、M列的矩阵进行排布，其中N、M均为大于0的整数；位于同一行的像素驱动电路的第一数据写入模块10和第二数据写入模块20均通过同一条扫描线Scan向其传输扫描信号；位于同一列的像素驱动电路的第一数据写入模块10和第二数据写入模块20均通过同一条数据线Data向其传输数据信号。
本实施例相较于现有技术，虽然增加了驱动晶体管的栅极数量以及数据写入模块的数量，但是并不会增加扫描线的数量和数据线的数量；因此，本实施例在有效控制驱动晶体管的阈值电压和迁移率漂移的前提下，并不会导致像素驱动电路在显示装置中布线的复杂化。
请参阅图2至图4，图4是图2所述的像素驱动电路在阈值电压侦测阶段的时序图。其中，所述像素驱动电路的第一数据写入模块10的输入端和第二数据写入模块20的输入端均与同一条数据线Data电性连接，所述数据线Data向所述第一数据写入模块10和所述第二数据写入模块20传输数据信号D’。第一数据写入模块10的控制端和第二数据写入模块20的控制端均与同一条扫描线Scan电性连接，所述扫描线Scan向所述第一数据写入模块10和所述第二数据写入模块20传输扫描信号G’。所述补偿模块30的输入端与所述参考信号线RE电性连接，所述参考信号线RE用于向所述补偿模块30输入参考信号Vref。所述补偿模块30的控制端与所述侦测信号线SE电性连接，所述侦测信号线SE用于向所述补偿模块30输入侦测信号Sense。所述补偿模块30的输出端电性连接所述第一节点S，所述第一节点S的电位标记为节点电位Vs。
图4所示的时序图对应所述像素驱动电路在阈值电压侦测阶段的各个信号的电压变化。
在第一时间段t1，扫描信号G’和数据信号D’均为为高电平，第一晶体管T1和第二晶体管T2导通，驱动晶体管T0的第一栅极G1和第二栅极G2接收高电平的数据信号D’，且第一存储电容C1的第一端和第二存储电容C2的第一端均为高电平；侦测信号Sense为高电平，第三晶体管T3导通，参考信号Vref使第一节点S的节点电位Vs复位，并保持低电平。
在第二时间段t2，驱动晶体管T0导通；第一电源线VDD和第二电源线VSS之间的电压差，使所述第一节点S的节点电位Vs逐渐抬升，并最终达到截止电位并稳定；在所述节点电位Vs达到截止电位后，由于第一存储电容C1和所述第二存储电容C2的存在，所述驱动晶体管T0的栅极电位Vg（栅极电位Vg是第一栅极的电位与第二栅极的电位之和）与所述节点电位Vs的差值刚好等于驱动晶体管T0的阈值电压Vth，驱动晶体管T0截止；根据栅极电位Vg、节点电位Vs和阈值电压Vth之间的关系式：Vth = Vg – Vs，计算得到驱动晶体管T0的阈值电压。需要说明的是，所述节点电位Vs可以通过将第三晶体管T3的源极连接模数转换器（ADC）进行测量得到。
根据阈值电压侦测阶段侦测到的驱动晶体管T0的阈值电压后，对所述驱动晶体管T0进行补偿的方法是：获取发光单元LED实现正常发光所需的理想驱动电压；将所述理想驱动电压加上驱动晶体管T0的阈值电压，得到需要加载到所述驱动晶体管T0栅极上的实际驱动电压；将该实际驱动电压分别通过第一栅极G1和第二栅极G2进行加载。
综上所述，本申请实施例提供的像素驱动电路，包括驱动晶体管和连接所述驱动晶体管的第一数据写入模块和第二数据写入模块，所述驱动晶体管包括第一栅极和第二栅极，所述第一数据写入模块与所述第一栅极电性连接，所述第二数据写入模块与所述第二栅极电性连接，所述驱动晶体管的输出端电性连接至发光单元。本申请实施例通过将驱动晶体管设置为双栅结构，并通过两个数据写入模块分别向驱动晶体管的两个栅极写入数据信号，从而减小单侧栅极所分担的电压量，有效控制驱动晶体管的阈值电压和迁移率的漂移；并且使驱动晶体管的阈值电压保持在较低水平，降低对驱动电压输出电路的输出能力的要求，有利于降低成本。
本申请实施例还提供一种显示装置，所述显示装置包括上述实施例所提供的像素驱动电路。
具体地，请参阅图5，图5是本申请实施例提供的显示装置的一种截面结构示意图。所述显示装置可以是OLED显示装置或Mini LED显示装置。所述显示装置包括衬底基板101、设置于所述衬底基板101上的第二栅极G2、覆盖所述第二栅极G2的第二栅极绝缘层102、设置于所述第二栅极绝缘层102上的沟道层103、设置于所述沟道层103上的第一栅极绝缘层104、设置于所述第一栅极绝缘层104上的第一栅极G1、覆盖所述沟道层103、所述第一栅极绝缘层104和所述第一栅极G1的层间绝缘层105、设置于所述层间绝缘层105上的源极106和漏极107、设置于所述层间绝缘层105上的平坦层108、设置于所述平坦层108上的阳极109和像素定义层110、设置于所述像素定义层110的开孔中的发光功能层111、设置于所述像素定义层110上的阴极112、以及覆盖所述阴极112的封装层113。
所述源极106和所述漏极107分别通过所述层间绝缘层105上的过孔连接至所述有源层103的相对两端；所述沟道层103包括沟道CH，所述第一栅极G1和所述第二栅极G2分别位于所述沟道CH的相对两侧，所述第二栅极G2、所述沟道层103、所述第一栅极G1、所述源极106和所述漏极107共同构成双栅极驱动晶体管，所述双栅极驱动晶体管相当于图1至图3中任一所示的驱动晶体管T0。
所述阳极109通过所述平坦层108上的过孔连接至所述漏极107，所述发光功能层111与所述阳极109连接，所述阴极112与所述发光功能层111连接；所述阳极109、所述发光功能层111和所述阴极112共同构成发光元件，所述发光元件相当于图1至图3中任一所示的发光单元LED。
本实施例提供的显示装置，包括了本申请实施例提供的像素驱动电路，因而具有以下有益效果：所述显示装置的驱动晶体管为双栅结构，分别通过两个数据写入模块分别向驱动晶体管的两个栅极写入数据信号，减小了单侧栅极所分担的电压量，有效控制驱动晶体管的阈值电压和迁移率的漂移；并且该设计使驱动晶体管的阈值电压保持在较低水平，降低对驱动电压输出电路的输出能力的要求，有利于降低显示装置的成本。
需要说明的是，虽然本申请以具体实施例揭露如上，但上述实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种像素驱动电路，其包括：
    驱动晶体管，所述驱动晶体管包括位于沟道层的沟道、位于第一栅极层的第一栅极和位于第二栅极层的第二栅极，所述第一栅极和所述第二栅极分别位于所述沟道的相对两侧，所述驱动晶体管的输出端与发光单元电性连接；
    第一数据写入模块，所述第一数据写入模块的输出端与所述第一栅极电性连接；
    第二数据写入模块，所述第二数据写入模块的输出端与所述第二栅极电性连接。
  2. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括补偿模块，所述补偿模块的输出端与所述驱动晶体管的输出端电性连接。
  3. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括第一存储电容，所述第一存储电容的第一端电性连接所述第一栅极，所述第一存储电容的第二端电性连接所述驱动晶体管的输出端。
  4. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路还包括第二存储电容，所述第二存储电容的第一端电性连接所述第二栅极，所述第二存储电容的第二端电性连接所述驱动晶体管的输出端。
  5. 根据权利要求1所述的像素驱动电路，其中，所述第一数据写入模块的输入端电性连接第一数据线，所述第一数据线用于向所述第一数据写入模块输入第一数据信号。
  6. 根据权利要求5所述的像素驱动电路，其中，所述第一数据写入模块的控制端电性连接第一扫描线，所述第一扫描线用于向所述第一数据写入模块输入第一扫描信号。
  7. 根据权利要求6所述的像素驱动电路，其中，所述第一数据写入模块包括第一晶体管，所述第一晶体管的栅极电性连接所述第一扫描线，所述第一晶体管的源极电性连接所述第一数据线，所述第一晶体管的漏极电性连接所述第一栅极。
  8. 根据权利要求1所述的像素驱动电路，其中，所述第二数据写入模块的输入端电性连接第二数据线，所述第二数据线用于向所述第二数据写入模块输入第二数据信号。
  9. 根据权利要求8所述的像素驱动电路，其中，所述第二数据写入模块的控制端电性连接第二扫描线，所述第二扫描线用于向所述第二数据写入模块输入第二扫描信号。
  10. 根据权利要求9所述的像素驱动电路，其中，所述第二数据写入模块包括第二晶体管，所述第二晶体管的栅极电性连接所述第二扫描线，所述第二晶体管的源极电性连接所述第二数据线，所述第二晶体管的漏极电性连接所述第二栅极。
  11. 根据权利要求2所述的像素驱动电路，其中，所述补偿模块包括第三晶体管，所述第三晶体管的栅极电性连接侦测信号线，所述第三晶体管的源极电性连接参考信号线，所述第三晶体管的漏极电性连接所述驱动晶体管的输出端。
  12. 根据权利要求1所述的像素驱动电路，其中，所述驱动晶体管为n型晶体管或p型晶体管。
  13. 根据权利要求1所述的像素驱动电路，其中，所述驱动晶体管的输入端电性连接第一电源线，所述第一电源线用于提供第一电源信号。
  14. 根据权利要求1所述的像素驱动电路，其中，所述驱动晶体管的输出端通过所述发光单元电性连接至第二电源线，所述第二电源线用于提供第二电源信号。
  15. 根据权利要求1所述的像素驱动电路，其中，所述第一数据写入模块的输入端与所述第二数据写入模块的输入端电性连接同一条数据线。
  16. 根据权利要求1所述的像素驱动电路，其中，所述第一数据写入模块的控制端与所述第二数据写入模块的控制端电性连接同一条扫描线。
  17. 一种显示装置，其包括权利要求1所述的像素驱动电路。
  18. 一种显示装置，其包括像素驱动电路，所述像素驱动电路包括：
    驱动晶体管，所述驱动晶体管包括位于沟道层的沟道、位于第一栅极层的第一栅极和位于第二栅极层的第二栅极，所述第一栅极和所述第二栅极分别位于所述沟道的相对两侧，所述驱动晶体管的输出端与发光单元电性连接；
    第一数据写入模块，所述第一数据写入模块的输出端与所述第一栅极电性连接；
    第二数据写入模块，所述第二数据写入模块的输出端与所述第二栅极电性连接；
    补偿模块，所述补偿模块的输出端与所述驱动晶体管的输出端电性连接。
  19. 根据权利要求18所述的显示装置，其中，所述像素驱动电路还包括第一存储电容和第二存储电容；所述第一存储电容的第一端电性连接所述第一栅极，所述第一存储电容的第二端电性连接所述驱动晶体管的输出端；所述第二存储电容的第一端电性连接所述第二栅极，所述第二存储电容的第二端电性连接所述驱动晶体管的输出端。
  20. 根据权利要求18所述的显示装置，其中，所述显示装置还包括所述发光单元，所述发光单元包括阳极、设置于所述阳极上的发光功能层和设置于所述发光功能层上的阴极，所述阳极与所述驱动晶体管的输出端电性连接。
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