WO2022134113A1 - 阵列基板及其制作方法、显示面板和显示装置 - Google Patents
阵列基板及其制作方法、显示面板和显示装置 Download PDFInfo
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- 239000000758 substrate Substances 0.000 title claims abstract description 129
- 238000000034 method Methods 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title description 9
- 230000005540 biological transmission Effects 0.000 claims abstract description 363
- 230000001934 delay Effects 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 3
- 238000012546 transfer Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 15
- 230000002159 abnormal effect Effects 0.000 description 8
- 230000009286 beneficial effect Effects 0.000 description 6
- 238000005401 electroluminescence Methods 0.000 description 6
- 230000005856 abnormality Effects 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 4
- 239000002096 quantum dot Substances 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
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-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
- G11C19/287—Organisation of a multiplicity of shift registers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
Definitions
- the present disclosure relates to the field of display technology, and in particular, to an array substrate and a manufacturing method thereof, a display panel and a display device.
- the array substrate in the display panel mainly includes a substrate and a circuit structure located on the substrate.
- the circuit structure includes, for example, at least one gate driving circuit, and the gate driving circuit includes a plurality of shift registers corresponding to a plurality of rows of sub-pixels. , multiple shift registers can sequentially drive multiple rows of sub-pixels to emit light under the control of the clock voltage signal.
- an array substrate in one aspect, includes a substrate, at least one gate driving circuit and at least one clock signal line.
- the substrate includes a display area and a non-display area on at least one side of the display area.
- the at least one gate driving circuit is located on one side of the substrate; the gate driving circuit includes a plurality of shift registers in cascade, the shift registers are respectively located in different rows, and the plurality of shift registers are located in different rows.
- the shift registers are divided into at least two groups of shift registers, each group of shift registers includes at least one shift register, and all shift registers in each group of shift registers are located in the same column; the clock signal line and the gate
- the drive circuit is located on the same side of the substrate, one gate drive circuit corresponds to at least one of the clock signal lines, and the clock signal line includes: a main transmission section, the main transmission section is on the substrate
- the orthographic projection is located in the non-display area, and the main transmission section is configured to transmit a clock signal; at least two branch transmission sections are connected with the main transmission section, and the at least two branch transmission sections are located on the substrate
- the orthographic projection above is located in the display area, and each branch transmission segment is connected to a clock signal input terminal of each shift register in a group of shift registers.
- the display area includes a one-to-one correspondence of multiple rows of pixel areas and multiple rows of shift register areas, and a corresponding row of pixel areas and a row of shift register areas are arranged adjacently;
- the orthographic projections of the plurality of shift registers on the substrate are located in the shift register regions of the plurality of rows in a one-to-one correspondence.
- the shift register regions of each row are located on the same side of the pixel regions corresponding to them; or, One row of the shift register areas is located on the first side of the pixel area corresponding thereto, and the shift register area in the other row is located on the second side of the pixel area corresponding thereto.
- the at least two groups of shift registers are sequentially from a first group of shift registers to an M-th group of shift registers along a direction away from the main transmission segment; wherein, from the first group of shift registers To the Mth group of shift registers, the number of shift registers in each group of shift registers is gradually reduced; and/or, from the first group of shift registers to the Mth group of shift registers, any phase The adjacent two sets of shift registers are not in the same column.
- M is greater than or equal to 3; for any one of the clock signal lines, among all the branch transmission segments connected with the second group of the shift registers to the M-th group of the shift registers, at least The two branch transmission segments include a common part.
- the common portion is located close to the main body of at least two groups of the shift registers connected to the at least two branch transmission segments that are closest to the main transmission segment. side of the transmission segment.
- the branch transmission segment includes a first portion connected to the main transmission segment and a second portion connected to the first portion; the second portion is along a corresponding set of the shift registers. extending in the column direction of the second part, and a group of the shift registers corresponding to the second part are connected in parallel on the second part.
- the first portion of the branch transmission segment spans no more than 100 pixels in the row direction.
- all of the branch transmission segments have equal or approximately equal resistance-capacitance delays on ends remote from the main transmission segment.
- the at least two groups of shift registers include a first group of shift registers and a second group of shift registers that are sequentially away from the main transmission segment;
- the clock signal line includes a first branch transmission segment and a second group of shift registers.
- the first branch transmission segment includes at least a second portion extending along the column direction of the first group of shift registers, and each shift register in the first group of shift registers is connected in parallel to the on the second part of the first branch transmission section;
- the second branch transmission section includes a first part and a second part connected to each other, and the first part of the second branch transmission section is also connected with the main transmission section, so The second part of the second branch transmission segment extends along the column direction of the second group of shift registers, and each shift register in the second group of shift registers is connected in parallel to the first part of the second branch transmission segment. On the second part.
- the orthographic projections of the plurality of shift registers on the substrate are respectively located in N rows of shift register regions, and the orthographic projections of the first group of shift registers on the substrate are located in In the shift register area of row X, the orthographic projection of the second group of shift registers on the substrate is located in the shift register area of row N-X; the second part of the first branch transmission section passes through X rows of the shift register area; the first part of the second branch transmission section passes through the X row of the shift register area; the second part of the second branch transmission section passes through the N-X rows of the shift Register area, where X, N satisfy:
- X ⁇ C1 (N-X) ⁇ C1+X ⁇ C2;
- X and N are both positive integers, and X is less than N;
- C1 is the resistance and capacitance generated on the branch transmission section when it passes through one row of the pixel area and one row of the shift register area and is connected to the shift register Delay;
- C2 is the resistance-capacitance delay generated by the branch transmission segment when passing through a row of pixel regions and a row of shift register regions.
- the at least two groups of shift registers include a first group of shift registers, a second group of shift registers, and a third group of shift registers that are located in sequence away from the body transfer segment;
- the clock signal lines include a first branch transfer section, a second branch transfer section and a third branch transfer section;
- the first branch transfer section includes at least a second portion extending in the column direction of the first group of shift registers, the first group of shift registers each of the shift registers is connected in parallel on a second part of the first branch transmission segment;
- the second branch transmission segment includes a first part and a second part connected to each other, the second branch transmission segment
- the first part of the second set of shift registers is also connected to the main transmission segment, and the second part of the second branch transmission segment extends along the column direction of the second set of shift registers, each shift register of the second set of shift registers.
- the bit register is connected in parallel on the second part of the second branch transmission segment;
- the third branch transmission segment includes a first part and a second part connected to each other, and the first part of the third branch transmission segment is also connected to the main body
- the transmission segments are connected, and the second part of the third branch transmission segment extends along the column direction of the third group of shift registers, and each shift register in the third group of shift registers is connected in parallel with the second group of shift registers. part.
- the orthographic projections of the plurality of shift registers on the substrate are located within N rows of shift register regions, and the orthographic projections of the first group of shift registers on the substrate are located at X In the shift register area of row Y, the orthographic projection of the second group of shift registers on the substrate is located in the shift register area of row Y, and the third group of shift registers is in the substrate
- the orthographic projection on is located within the shift register area of rows N-X-Y; the second part of the first branch transmission segment passes through the shift register area of row X; the first part of the second branch transmission segment passes through X row of the shift register area, the second portion of the second branch transfer segment passes through the Y row of the shift register area, and the first portion of the third branch transfer segment passes through the X+Y row of the shift In the register area, the second part of the third branch transmission segment passes through the N-X-Y row of the shift register area, and X, Y, and N satisfy:
- X ⁇ C1 Y ⁇ C1+X ⁇ C2;
- X ⁇ C1 (N-X-Y) ⁇ C1+(X+Y) ⁇ C2;
- X, Y, and N are all positive integers, and both X and Y are less than N;
- C1 is the branch transmission segment that passes through the pixel area of one row and the shift register area of one row and is connected to the shift register.
- C2 is the resistance-capacitance delay generated by the branch transmission section when passing through a row of pixel regions and a row of shift register regions.
- the at least two sets of shift registers include a first set of shift registers, a second set of shift registers, a third set of shift registers, and a fourth set of shift registers that are sequentially remote from the body transfer segment ;
- the clock signal line includes a first branch transmission section, a second branch transmission section, a third branch transmission section and a fourth branch transmission section;
- the first branch transmission section at least includes A second portion extending in the column direction, each shift register in the first group of shift registers is connected in parallel on the second portion of the first branch transmission segment;
- the second branch transmission segment includes a part and a second part, the first part of the second branch transmission segment is further connected to the main transmission segment, and the second part of the second branch transmission segment extends along the column direction of the second group of shift registers,
- Each shift register in the second set of shift registers is connected in parallel on a second portion of the second branch transmission segment;
- the third branch transmission segment includes a first portion and a second portion connected to each other, the The first part
- the orthographic projections of the plurality of shift registers on the substrate fall within N rows of shift register regions, and the orthographic projections of the first set of shift registers on the substrate fall within the region of N rows of shift registers.
- the orthographic projection of the second group of shift registers on the substrate falls into the shift register area of row Y
- the third group of shift registers is in the The orthographic projection on the substrate falls within the shift register area of row Z
- the orthographic projection of the fourth group of shift registers on the substrate falls within the shift register area of row N-X-Y-Z;
- the second part of the first branch transmission section passes through the shift register area of X rows;
- the first part of the second branch transmission section passes through the shift register area of X rows, and the first part of the second branch transmission section
- Two parts pass through the shift register area of row Y
- the first part of the third branch transmission section passes through the shift register area of row X+Y
- the second part of the third branch transmission section passes through Z row
- X ⁇ C1 Y ⁇ C1+X ⁇ C2;
- X ⁇ C1 Z ⁇ C1+(X+Y) ⁇ C2;
- X ⁇ C1 (N-X-Y-Z) ⁇ C1+(X+Y+Z) ⁇ C2;
- X, Y, Z, N are all positive integers, and X, Y, Z are all less than N;
- C1 is when passing through a row of the pixel area and a row of the shift register area and connected to the shift register, so The resistance-capacitance delay generated on the branch transmission section;
- C2 is the resistance-capacitance delay generated by the branch transmission section when passing through a row of pixel regions and a row of shift register regions.
- the first branch transmission segment further includes a first portion, the first portion of the first branch transmission segment connecting the second portion of the first branch transmission segment and the main transmission segment; each of the The first portion of the branch transport segment includes a lateral portion extending in the row direction; wherein the lateral portions of each of the branch transport segments are approximately equal in length.
- a display panel in another aspect, includes the array substrate according to any one of the above embodiments.
- a display device includes: the display panel according to any one of the above embodiments.
- a method for fabricating an array substrate includes: providing a substrate; and forming at least one gate driving circuit and at least one clock signal line on the same side of the substrate.
- the gate driving circuit includes multiple shift registers in cascade, the multiple shift registers are respectively located in different rows, and the multiple shift registers are divided into at least two groups of shift registers, each group shift registers
- the bit register includes at least one shift register, and all shift registers in each group of shift registers are located in the same column; one of the gate driving circuits corresponds to at least one of the clock signal lines, and the clock signal lines include a main transmission section and at least two branch transmission sections connected with the main transmission section; the main transmission section is configured to transmit a clock signal, and each branch transmission section is connected to a clock signal input end of each shift register in a group of shift registers .
- FIG. 1 is a structural diagram of an array substrate according to some embodiments
- FIG. 2 is a circuit structure diagram of a shift register according to some embodiments.
- FIG. 3 is a structural diagram of another array substrate according to some embodiments.
- FIG. 4 is a structural diagram of yet another array substrate according to some embodiments.
- FIG. 5 is a structural diagram of yet another array substrate according to some embodiments.
- FIG. 6 is a structural diagram of yet another array substrate according to some embodiments.
- FIG. 7 is a structural diagram of yet another array substrate according to some embodiments.
- FIG. 8 is a structural diagram of yet another array substrate according to some embodiments.
- FIG. 9 is a waveform diagram of a clock signal according to some embodiments.
- FIG. 10 is a waveform diagram of another clock signal according to some embodiments.
- FIG. 11 is a circuit structure diagram of a pixel driving circuit according to some embodiments.
- 12A is a structural diagram of a display panel according to some embodiments.
- 12B is a structural diagram of another display panel according to some embodiments.
- FIG. 13 is a flow diagram of a method of fabrication according to some embodiments.
- first and second are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as “first” or “second” may expressly or implicitly include one or more of that feature.
- plural means two or more.
- the expressions “coupled” and “connected” and their derivatives may be used.
- the term “connected” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
- the term “coupled” may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact.
- the terms “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, yet still co-operate or interact with each other.
- the embodiments disclosed herein are not necessarily limited by the content herein.
- Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings.
- the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated.
- example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features.
- the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.
- the array substrate 100 includes a substrate 1 , at least one gate driving circuit 2 and at least one clock signal line 3 .
- the at least one gate driving circuit 2 is located on one side of the substrate 1 .
- the clock signal line 3 and the gate driving circuit 2 are located on the same side of the substrate 1 , and one gate driving circuit 2 corresponds to at least one clock signal line 3 . That is, one gate driving circuit 2 may be connected to one clock signal line 3 (as shown in FIG. 1 ), or, one gate driving circuit 2 may be connected to two or more clock signal lines 3 .
- the gate driving circuit 2 includes a plurality of shift registers 21 in cascade, the plurality of shift registers 21 are located in different rows, and the plurality of shift registers 21 are divided into at least two groups of shift registers 21 , each group of shift registers 21 It includes at least one shift register 21, and all shift registers 21 in each group of shift registers 21 are located in the same column.
- the clock signal line 3 includes a main transmission section 31 and at least two branch transmission sections 32 connected to the main transmission section 31 .
- the main transmission section 31 is configured to transmit a clock signal.
- Each branch transmission segment 32 is connected to one clock signal input terminal of each shift register 21 in a group of shift registers 21 .
- each shift register 21 in the gate driving circuit 2 has a clock signal input terminal; while one gate driving circuit 2 corresponds to one clock signal line 3 In the case of two clock signal lines 3, each shift register 21 in the gate drive circuit 2 has two clock signal input terminals. Therefore, the number of clock signal lines 3 corresponding to one gate driving circuit 2 is equal to the number of clock signal input terminals of each shift register 21 in the gate driving circuit 2 .
- a plurality of shift registers in a gate driving circuit are arranged in a column, and all of them are connected in parallel to a segment of clock signal lines (eg, a branch transmission segment). Due to the unidirectional transmission of the electrical signal in the clock signal line, there will be a certain resistance-capacitance delay each time it passes through a shift register. Therefore, the shift register close to the end of the clock signal line is prone to excessive resistance-capacitance delay due to excessive resistance and capacitance delay. There is a problem of abnormal output.
- each clock signal line 3 includes at least two branch transmission segments 32 , and each branch transmission segment 32 is connected to each group of shift registers 21 of the gate driving circuit 2 in a one-to-one correspondence, thereby So that each branch transmission segment 32 can respectively provide a clock signal for each shift register 21 in the corresponding group of shift registers 21, and control the shift register 21 to output a gate control signal.
- the number of shift registers 21 connected to each branch transmission segment 32 is reduced, and each The total resistance-capacitance delay on the branch transmission segment 32 is small, that is, the resistance-capacitance delay on the end of each branch transmission segment 32 away from the main transmission segment 31 is small, which can help to improve the ease of the shift register near the end of the clock signal line.
- the problem of abnormal output occurs due to excessive delay of resistance and capacitance.
- the present disclosure does not limit the circuit structure of the shift register 21 .
- the circuit structure of the shift register 21 may be as shown in FIG. 2 .
- the shift register 21 includes two clock signal input terminals, ie, CLK and CLKB.
- the gate drive circuit 2 composed of the plurality of shift registers 21 shown in FIG. 2 can correspond to two clock signal lines 3 .
- the plurality of shift registers 21 in the gate driving circuit 2 are divided into at least two groups of shift registers 21, all the shift registers 21 in one gate driving circuit 2 are still The cascade relationship is maintained, that is, the two shift registers 21 located in two adjacent rows and in different groups are still cascaded through signal lines.
- the substrate 1 includes a display area A and a non-display area B on at least one side of the display area A.
- the display area A includes a one-to-one correspondence of multiple rows of pixel areas A1 and multiple rows of shift register areas A2, and a corresponding row of pixel areas A1 and a row of shift register areas A2 are arranged adjacent to each other.
- the orthographic projections of the plurality of shift registers 21 in the gate driving circuit 2 on the substrate 1 are located in the multi-row shift register area A2 in a one-to-one correspondence.
- the orthographic projection of the main transmission section 31 on the substrate 1 is located in the non-display area B, and the orthographic projection of the branch transmission section 32 on the substrate 1 is located in the display area A.
- the orthographic projections of the plurality of shift registers 21 in the gate driving circuit 2 on the substrate 1 are located in the multi-row shift register area A2 in a one-to-one correspondence, that is, the gate driving circuit 2 is on the substrate 1
- the orthographic projection is located in the display area A, so that the gate driving circuit 2 does not need to occupy the non-display area B of the substrate 1, thereby reducing the area of the non-display area B in the substrate 1, thereby helping to reduce the use of the array substrate 100.
- the width of the frame of the display device is limited, and the narrow frame design of the display device is realized.
- each row of shift register areas A2 may be located on the same side of the corresponding pixel areas A1.
- one row of shift register areas A2 is located in the area of the corresponding pixel area A1 On the first side, the shift register area A2 of another row is located on the second side of the pixel area A1 corresponding thereto.
- two rows of shift register areas A2 can be continuously set for every two rows of pixel areas A1 (that is, no pixel area A1 is set between the two rows of shift register areas A2).
- the distance between the bit register areas A2 is relatively short, so that the distance between the two shift registers 21 corresponding to the two shift register areas A2 is also relatively short, so it can be used between the two shift registers 21.
- Common signal lines ie, signal lines extending along the row direction L1 ) are arranged between them, which is beneficial to reduce the number of signal lines to be arranged, thereby facilitating the simplification of the structure of the array substrate 100 .
- a pixel driving circuit 4 may also be provided on the side of the substrate 1 where the gate driving circuit 2 and the clock signal line 3 are arranged.
- the orthographic projections of the pixel driving circuit 4 , the gate line 5 and the data line 6 on the substrate 1 are all located in the display area A.
- the gate lines 5 may extend in the row direction L1
- the data lines 6 may extend in the column direction L2.
- the row direction L1 and the column direction L2 are both parallel to the plane where the substrate 1 is located. Exemplarily, as shown in FIG. 1 and FIG. 3 , the row direction L1 and the column direction L2 are perpendicular to each other. Of course, the present disclosure is not limited to this. In other examples, the row direction L1 and the column direction L2 only need to intersect. For example, there may be an included angle between the row direction L1 and the column direction L2, and the included angle may be 60 degrees. or 80 degrees.
- the branch transmission segment 32 further includes a portion extending along the row direction L1 , the orthographic projection of the portion of the branch transmission segment 32 extending along the row direction L1 on the substrate 1 and the positive projection of the data line 6 on the substrate 1
- a resistance-capacitance delay is also likely to occur between the part of the branch transmission section 32 extending in the row direction L1 and the data line 6, so that the clock transmitted on the branch transmission section 32 is prone to be delayed.
- the signal generated an exception.
- the capacitance-resistance delay on the branch transmission segment 32 also gradually increases.
- the main body transmission section 31 is located on either side of the display area A along the column direction L2 (for example, FIG. 3 illustrates that the main body transmission section 31 is located at the lower side of the display area A along the column direction L2 ).
- the at least two groups of shift registers 21 are sequentially formed from the first group of shift registers 211 to the M-th group of shift registers 21M along the direction away from the main transmission section 31 . where M is greater than or equal to 2.
- at least two groups of shift registers 21 in FIG. 1 are divided into a first group of shift registers 211 and a second group of shift registers 212 .
- the branches corresponding to the first group of shift registers 211 to the M-th group of shift registers 21M branch out for transmission.
- the number of rows of the pixel area A1 spanned by the segment 32 gradually increases, and the number of gate lines 5 spanned by the branch transmission segment 32 also increases gradually, so the resistance-capacitance delay generated by the gate line 5 on the branch transmission segment 32 increases gradually.
- the number of shift registers 21 in each group of shift registers is gradually reduced, and a group of shift registers far away from the main transmission section 31 can also be shifted.
- the resistance and capacitance at the end of the branch transmission section 32 connected to the register 21 is small, thereby further improving the problem that the output abnormality of the shift register connected to the end of the clock signal line is prone to occur due to the large resistance and capacitance delay at the end of the clock signal line.
- any adjacent two groups of shift registers 21 are in the same column.
- the first group of shift registers 211 and the second group of shift registers 212 are located in the same column. That is, each group of shift registers 21 may all be located in the same column on the substrate 1, and at this time, it is convenient to cascade multiple shift registers 21 in one gate driving circuit 2 together.
- any adjacent two groups of shift registers 21 are not in the same column.
- the first group of shift registers 211 and the second group of shift registers 212 are located in different columns.
- the branch transmission section 32 does not need to extend to the far end of the M-th group of shift registers 21M, and extends from the far end of the M-th group of shift registers 21M to the proximal end of the M-th group of shift registers 21M. Therefore, the number of gate lines spanned by each branch transmission segment 32 is reduced, and the resistance-capacitance delay at the end of each branch transmission segment 32 is reduced.
- the far end of each group of shift registers 21 is the end of each group of shift registers 21 away from the main transmission section 31
- the near end of each group of shift registers 21 is the end of each group of shift registers 21 close to the main transmission section 31 .
- any adjacent two groups of shift registers 21 in different columns, it is also convenient to arrange the branch transmission section 32 between the adjacent two groups of shift registers 21 (see FIG. 6 ), thereby reducing the number of The length of the portion of the branch transmission segment 32 extending along the row direction L1 reduces the number of data lines 6 spanned by the portion of the branch transmission segment 32 extending along the row direction L1, thereby reducing the length of each branch transmission segment 32 extending along the row direction L1.
- the resistance-capacitor delay on the part reduces the total resistance-capacitance delay on each branch transmission section 32, and improves the problem that the output abnormality of the shift register connected to the end of the clock signal line is prone to occur due to the large resistance-capacitance delay on the clock signal line. .
- the gate driving circuit 2 includes at least three sets of shift registers 21
- the gate driving circuit 2 includes at least three sets of shift registers 21
- the second set of shift registers 212 Of all the branch transfer sections 32 connected to the M-th group of shift registers 21M, at least two branch transfer sections 32 include a common portion 321 .
- the other branch transmission segments 32 can include a shared portion 321, thereby simplifying the branches other than those connected to the first group of shift registers 211.
- the wiring structure of the remaining branch transmission sections 32 other than the transmission section 32 reduces the cost.
- the common part 321 is located in at least two groups of shift registers 21 connected to the at least two branch transmission sections 32 , and the group of shift registers 21 closest to the main transmission section 31 is close to the main transmission section 31 . side.
- each branch transmission segment 32 includes a first portion 322 connected to the main transmission segment 31 and a second portion 323 connected to the first portion 322 .
- Each second portion 323 extends along the column direction L2 of a group of shift registers 21 corresponding thereto, and a group of shift registers 21 corresponding to each second portion 323 is connected to the second portion 323 in parallel.
- each row of pixel areas A1 includes a plurality of sub-pixels A12 (eg, R, G, B), and the plurality of sub-pixels A12 are sequentially arranged along the row direction L1 .
- the adjacent three sub-pixels A12 in the pixel area A1 of each row can be used as a pixel unit, and the three sub-pixels A12 in the pixel unit can be used to generate three primary color lights (for example, red light, green light , Blu-ray).
- one pixel A11 refers to the above-mentioned one sub-pixel A12. In other examples, one pixel A11 refers to the above-mentioned one pixel unit (as shown in FIG. 3 , one pixel A11 includes three sub-pixels A12 ).
- the portion of the first portion 322 of all branch transmission segments 32 extending along the row direction L1 spans fewer pixels, and the portion of the first portion 322 of the branch transmission segment 32 extending along the row direction L1 spans the number of data lines 6 It is also less, so that the resistance-capacitance delay on the part of the first part 322 of the branch transmission section 32 extending along the row direction L1 is smaller, which is beneficial to reduce the total resistance-capacitance delay on the branch transmission section 32 and improve the delay caused by the clock signal line 3
- the delay of the terminal resistance and capacitance is relatively large, which leads to the problem of abnormal output of the shift register 21 connected to the terminal of the clock signal line 3 easily.
- the resistance-capacitance delays of all branch transmission segments 32 on the ends remote from the main transmission segment 31 are equal or approximately equal.
- the waveforms of the clock signals received by the shift registers 21 connected to the ends of each branch transmission section 32 are the same or approximately the same, that is, the clock signals transmitted at the ends of each branch transmission section 32 are the same or approximately the same, that is, the clock signals transmitted at the ends of the branch transmission sections 32 are the same or approximately the same.
- the signals received on the connected shift registers are the same or approximately the same, and the shift registers output the gate control signals at the same or approximately the same time, which improves the reliability of the gate control signals output by each group of shift registers 21 of the gate drive circuit 2 sex.
- the at least two sets of shift registers 21 include a first set of shift registers 211 and a second set of shift registers 212 that are in turn remote from the main transfer section 31 .
- the clock signal line 3 includes a first branch transmission section 33 and a second branch transmission section 34 .
- the first branch transmission section 33 includes at least a second portion 332 extending along the column direction L2 of the first group of shift registers 211 , and each shift register 21 in the first group of shift registers 211 is connected in parallel to the first branch transmission section 33 on the second part 332.
- the second branch transmission section 34 includes a first part 341 and a second part 342 connected to each other, the first part 341 of the second branch transmission section 34 is also connected to the main transmission section 31, and the second part 342 of the second branch transmission section 34
- the two groups of shift registers 212 extend in the column direction L2 , and each shift register 21 in the second group of shift registers 212 is connected in parallel on the second portion 342 of the second branch transmission section 34 .
- the second part 332 of the first branch transmission section 33 may be directly connected to the main transmission section 31; or, as shown in FIG. 1, the first branch transmission section 33 may further include a first part 331, which is used to connect the The second part 332 and the main transmission section 31 .
- the plurality of shift registers 21 in the gate driving circuit 2 are divided into two groups, and the two branch transmission sections 32 are used to provide clock signals for the two groups of shift registers 21 respectively.
- the branch transmission sections 32 can be connected to each other.
- the number of the shift registers 21 is small, which reduces the resistance-capacitance delay on the branch transmission section 32 and improves the output abnormality of the shift register connected to the end of the clock signal line due to the large resistance-capacitance delay on the clock signal line. question.
- the grouping of the shift register 21 is simple, the wiring structure can be simplified, and the cost can be reduced.
- the orthographic projections of the plurality of shift registers 21 on the substrate 1 may be located in the shift register areas A2 of N rows, respectively, and the orthographic projections of the first group of shift registers 211 on the substrate 1 may be located in X rows
- the orthographic projection of the second group of shift registers 212 on the substrate 1 may be located in the N-X row shift register area A2; the second portion 332 of the first branch transmission section 33 may move through the X rows
- the bit register area A2; the first portion 341 of the second branch transfer section 34 may pass through the X row shift register area A2; the second section 342 of the second branch transfer section 34 may pass through the N-X row shift register area A2.
- X and N satisfy:
- X ⁇ C1 (N-X) ⁇ C1+X ⁇ C2.
- C1 is the resistance-capacitance delay generated on the branch transmission section 32 when it passes through one row of pixel area A1 and one row of shift register area A2 and is connected to the shift register 21;
- C2 is the resistance and capacitance delay generated on one row of pixel area A1 and one row of shift register area A2 , the resistance-capacitance generated by the branch transmission section 32 is delayed.
- C1 and C2 may have different values, for example, C1 may be 60fF, and C2 may be 30fF.
- the number N of the shift register areas A2 may also be different. The present disclosure does not limit the number of shift register areas A2.
- the at least two groups of shift registers 21 include a first group of shift registers 211 , a second group of shift registers 212 and a third group of shift registers 211 , which are sequentially away from the main transmission section 31 .
- the clock signal line 3 includes a first branch transmission section 33 , a second branch transmission section 34 and a third branch transmission section 35 .
- the first branch transmission section 33 includes at least a second portion 332 extending along the column direction L2 of the first group of shift registers 211 , and each shift register 21 in the first group of shift registers 211 is connected in parallel to the first branch transmission section 33 on the second part 332.
- the second branch transmission section 34 includes a first part 341 and a second part 342 connected to each other, the first part 341 of the second branch transmission section 34 is also connected to the main transmission section 31, and the second part 342 of the second branch transmission section 34
- the two groups of shift registers 212 extend in the column direction L2, and each shift register 21 in the second group of shift registers 212 is connected in parallel on the second part 342 of the second branch transmission section 34;
- the third branch transmission section 35 includes each other The first part 351 and the second part 352 are connected, the first part 351 of the third branch transmission section 35 is also connected with the main transmission section 31, the second part 352 extends along the column direction L2 of the third group of shift registers 213, the third group Each of the shift registers 21 of the shift registers 213 is connected in parallel on the second part 352 of the third set of shift registers 213 .
- the second part 332 of the first branch transmission section 33 may be directly connected to the main transmission section 31; or, as shown in FIG. 6, the first branch transmission section 33 may further include a first part 331, which is used to connect the first part 331 The second part 332 and the main transmission section 31 .
- the first branch transmission section 33 may further include a first part 331 , and the first part 331 is used for connecting the second part 332 and the main transmission section 31 .
- the number of shift registers 21 connected to each branch transmission section 32 of the clock signal line 3 is smaller, and the delay of the resistance and capacitance of each branch transmission section 32 is smaller, which is more conducive to improving the problems caused by the clock signal line.
- the resistor-capacitor delay is relatively large, and the shift register connected to the end of the clock signal line is prone to the problem of abnormal output.
- the orthographic projections of the plurality of shift registers 21 on the substrate 1 may be located in the shift register area A2 of N rows, and the orthographic projections of the first group of shift registers 211 on the substrate 1 may be located in the X rows of shift registers In the area A2, the orthographic projection of the second group of shift registers 212 on the substrate 1 may be located in the Y row shift register area A2, and the orthographic projection of the third group of shift registers 213 on the substrate 1 may be located in the N-X-Y row shift. in the bit register area A2.
- the second portion 332 of the first branch transmission segment 33 may pass through the X-row shift register area A2; the first portion 341 of the second branch transmission segment 34 may pass through the X-row shift register area A2.
- the second part 342 may pass through the Y row shift register area A2, the first part 351 of the third branch transmission section 35 may pass through the X+Y row shift register area A2, and the second part of the third branch transmission section 35 may pass through the X+Y row shift register area A2 Through N-X-Y row shift register area A2, X, Y, N satisfy:
- X ⁇ C1 Y ⁇ C1+X ⁇ C2;
- X ⁇ C1 (N-X-Y) ⁇ C1+(X+Y) ⁇ C2.
- C1 is the resistance-capacitance delay generated on the branch transmission section 32 when it passes through one row of pixel area A1 and one row of shift register area A2 and is connected to the shift register 21;
- C2 is the resistance and capacitance delay generated on one row of pixel area A1 and one row of shift register area A2 , the resistance-capacitance generated by the branch transmission section 32 is delayed.
- the at least two groups of shift registers 21 include a first group of shift registers 211 , a second group of shift registers 212 , and a third group of shift registers 211 , which are sequentially away from the main transmission section 31 .
- the register 213 and the fourth group of shift registers 214 , and the clock signal line 3 includes a first branch transmission section 33 , a second branch transmission section 34 , a third branch transmission section 35 and a fourth branch transmission section 36 .
- the first branch transmission section 33 includes at least a second portion 332 extending along the column direction L2 of the first group of shift registers 211 , and each shift register 21 in the first group of shift registers 211 is connected in parallel to the first branch transmission section 33 on the second part 332.
- the second branch transmission section 34 includes a first part 341 and a second part 342 connected to each other, the first part 341 of the second branch transmission section 34 is also connected to the main transmission section 31, and the second part 342 of the second branch transmission section 34
- the two groups of shift registers 212 extend in the column direction L2 , and each shift register 21 in the second group of shift registers 212 is connected in parallel on the second portion 342 of the second branch transmission section 34 .
- the third branch transmission section 35 includes a first part 351 and a second part 352 connected to each other, the first part 351 of the third branch transmission section 35 is also connected with the main transmission section 31, and the second part 352 of the third branch transmission section 35
- the three groups of shift registers 213 extend in the column direction L2 , and each shift register 21 in the third group of shift registers 213 is connected in parallel on the second portion 352 of the third branch transmission section 35 .
- the fourth branch transmission section 36 includes a first part 361 and a second part 362 connected to each other, the first part 361 of the fourth branch transmission section 36 is also connected to the main transmission section 31, and the second part 362 of the fourth branch transmission section 36 is along the
- the four groups of shift registers 214 extend in the column direction L2 , and each shift register 21 in the fourth group of shift registers 214 is connected in parallel on the second portion 362 of the fourth branch transmission section 36 .
- the second part 332 of the first branch transmission section 33 may be directly connected to the main transmission section 31; or, as shown in FIG. 7, the first branch transmission section 33 may further include a first part 331, which is used to connect the first part 331 The second part 332 and the main transmission section 31 .
- the plurality of shift registers 21 in the gate driving circuit 2 are divided into four groups, each group of shift registers 21 is connected to one branch transmission section 32, and the number of the connected shift registers 21 on each branch transmission section 32 is increased.
- the total resistance-capacitance delay on the branch transmission segment is smaller, and the shift register 21 connected to the end of the branch transmission segment 32 is less prone to the problem of abnormal output.
- the orthographic projections of the plurality of shift registers 21 on the substrate 1 may fall within the shift register area A2 of N rows, and the orthographic projections of the first group of shift registers 211 on the substrate 1 may fall within the X row shift register area A2.
- the orthographic projection of the second group of shift registers 212 on the substrate 1 may fall within the Y row shift register area A2
- the orthographic projection of the third group of shift registers 213 on the substrate 1 may fall within the bit register area A2.
- the orthographic projection of the fourth group of shift registers 214 on the substrate 1 may fall into the N-X-Y-Z row shift register area A2.
- the second portion 332 of the first branch transmission segment 33 may pass through the X-row shift register area A2; the first portion 341 of the second branch transmission segment 34 may pass through the X-row shift register area A2.
- the second portion 342 may pass through the Y row shift register area A2, the first portion 351 of the third branch transmission segment 35 may pass through the X+Y row shift register area A2, and the second portion 352 of the third branch transmission segment 35 may Passing through the Z-row shift register area A2, the first portion 361 of the fourth branch transmission segment 36 may pass through the X+Y+Z row shift register area, and the second portion 362 of the fourth branch transmission segment 36 may pass through the N-X-Y-Z rows Shift register area; X, Y, Z, N satisfy:
- X ⁇ C1 Y ⁇ C1+X ⁇ C2;
- X ⁇ C1 Z ⁇ C1+(X+Y) ⁇ C2;
- X ⁇ C1 (N-X-Y-Z) ⁇ C1+(X+Y+Z) ⁇ C2.
- C1 is the resistance-capacitance delay generated on the branch transmission section 32 when it passes through one row of pixel area A1 and one row of shift register area A2 and is connected to the shift register 21;
- C2 is the resistance and capacitance delay generated on one row of pixel area A1 and one row of shift register area A2 , the resistance-capacitance generated by the branch transmission section 32 is delayed.
- the first branch transmission segment 33 may further include a first portion 331 , and the first portion 331 of the first branch transmission segment 33 connects the second portion 332 of the first branch transmission segment 33 and the main transmission segment 31 .
- the first portion 322 of each branch transport segment 32 includes a lateral portion extending in the row direction L1; wherein the lateral portions of each branch transport segment 32 are approximately equal in length. In this way, the value calculated by the above equation can be more accurate.
- FIG. 1 , FIG. 6 , and FIG. 7 only show that the plurality of shift registers 21 in the gate driving circuit 2 are divided into 2 groups of shift registers, 3 groups of shift registers, and 4 groups of shift registers.
- the connection method of the gate driving circuit 2 and the clock signal line 3 when the signal line includes two branch transmission sections 32 , three branch transmission sections 32 , and four branch transmission sections 32 .
- the shift register 21 in the gate driving circuit 2 can also be divided into 5 groups of shift registers or more groups of shift registers, so that each branch transmits
- the resistor-capacitor delay on the segment 32 is small, so as to improve the problem that the resistor-capacitor delay on the clock signal line is too large, resulting in abnormal output of the shift register connected to the end of the clock signal line.
- the clock signal line CLK is directly connected to all shift registers in one gate driving line, and the resistance-capacitance delay at the end of the clock signal line CLK is relatively large.
- the maximum value of the clock signal voltage Vm output from the end of the clock signal line CLK can only reach 10.6V, and the falling edge time of the clock signal is 3 ⁇ s.
- the clock signal line 3 includes a main transmission segment 31 and three branch transmission segments 32 connected to the main transmission segment 31 , and one branch transmission segment 32 is respectively connected to a set of shift registers. 21 is connected.
- the resistance-capacitance delays at the ends of the branch transmission sections 32 are both small.
- the maximum value of the clock signal voltage Vm output from the end of the branch transmission section 32 can reach 12V, and the falling edge time of the clock signal is only 1.65 ⁇ s.
- the clock signal transmitted by the branch transmission section 32 is sufficient to turn on the transistor, thereby improving the shifting performance.
- the problem of abnormal output of bit register 21 since the falling edge time of the clock signal is small, the turn-on time of the transistor can be controlled more accurately by using the clock signal, thereby ensuring that the shift register 21 normally outputs the gate control signal.
- the gate driving circuit 2 provides gate driving signals for the plurality of pixel driving circuits 4 on the array substrate 100 .
- the array substrate 100 may further include multiple gate driving circuits.
- the pixel driving circuit includes the circuit structure shown in FIG. 11 (that is, the pixel driving circuit is provided with four gate signal terminals, namely G1, G2, G3 and EM)
- the array substrate 1 may be provided with The four gate driving circuits 2 respectively provide gate driving signals for the pixel driving circuits.
- the display panel 300 includes the array substrate 100 described in any of the above embodiments.
- the display panel 300 may be a liquid crystal display panel (Liquid Crystal Display, LCD for short), an organic electroluminescence display panel (Organic Light-Emitting Diode, OLED for short) or a quantum dot electroluminescence display panel (Quantum Dot Light Emitting Diodes, referred to as QLED) and so on.
- LCD Liquid Crystal Display
- OLED Organic Light-Emitting Diode
- QLED Quantum Dot Light Emitting Diodes
- the liquid crystal display panel may include an array substrate 100 , a cell assembling substrate 210 , and a liquid crystal layer 220 disposed between the array substrate 100 and the cell assembling substrate 210 .
- the organic electroluminescence display panel (or quantum dot electroluminescence display panel) may include an array substrate 100 and a light-emitting device 200.
- the light emitting device 200 may include an anode, a cathode, and a light emitting functional layer between the cathode and the anode.
- the beneficial effects that can be achieved by the display panel provided by the present disclosure include at least the same beneficial effects as the array substrate provided by the above-mentioned technical solutions, and are not described in detail here.
- Some embodiments of the present disclosure also provide a display device including the display panel provided by the above embodiments.
- the above-mentioned display device may be any component with a display function, such as a TV, a digital camera, a mobile phone, a watch, a tablet computer, a notebook computer, a navigator, and the like.
- the beneficial effects that can be achieved by the display device provided by the present disclosure are the same as the beneficial effects that can be achieved by the array substrate and the display panel provided by the above technical solutions, and will not be repeated here.
- Some embodiments of the present disclosure also provide a fabrication method for fabricating the array substrate described in any of the foregoing embodiments. As shown in Figure 13, the manufacturing method includes:
- At least one gate driving circuit 2 and at least one clock signal line 3 are formed on the same side of the substrate 1 .
- the gate driving circuit 2 includes a plurality of shift registers 21 connected in cascade, and the plurality of shift registers 21 are respectively located in different rows, and the plurality of shift registers 21 are divided into at least two groups of shift registers 21 , and each group of shift registers 21 shifts
- the register 21 includes at least one shift register 21, and all the shift registers 21 in each group of shift registers 21 are located in the same column.
- One gate drive circuit 2 corresponds to at least one clock signal line 3, and the clock signal line 3 includes a main transmission section 31 and at least two branch transmission sections 32 connected to the main transmission section 31; the main transmission section 31 is configured to transmit a clock signal, Each branch transfer segment 32 is connected to the clock signal input terminal of each shift register 21 in a group of shift registers.
- each clock signal line 3 includes at least two branch transmission segments 32 , and each branch transmission segment 32 is connected to each group of shifters of the gate driving circuit 2 in a one-to-one correspondence. register 21, so that each branch transmission segment 32 can respectively provide a clock signal for each shift register 21 in a corresponding group of shift registers 21, and control the shift register 21 to output a gate control signal.
- the total resistance-capacitance delay on each branch transmission segment 32 is small, that is, the resistance on the end of each branch transmission segment 32 away from the main transmission segment 31
- the capacitance delay is small, which can help to improve the problem that the shift register near the end of the clock signal line is prone to output abnormality due to excessive resistance and capacitance delay.
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Abstract
一种阵列基板(100),包括:衬底(1);至少一个栅极驱动电路(2),位于衬底(1)的一侧;栅极驱动电路(2)包括级联的多个移位寄存器(21),多个移位寄存器(21)分别位于不同行,且多个移位寄存器(21)分为至少两组移位寄存器(21),每组移位寄存器(21)中包括至少一个移位寄存器(21),每组移位寄存器(21)中的所有移位寄存器(21)位于同一列;至少一条时钟信号线(3),时钟信号线(3)与栅极驱动电路(2)位于衬底(1)的同一侧,一个栅极驱动电路(2)对应至少一条时钟信号线(3),时钟信号线(3)包括:主体传输段(31),被配置为传输时钟信号(3);与主体传输段(31)连接的至少两个分支传输段(32),每个分支传输段(32)连接一组移位寄存器(21)中每个移位寄存器(21)的一个时钟信号输入端。
Description
本公开涉及显示技术领域,尤其涉及一种阵列基板及其制作方法、显示面板和显示装置。
显示面板中的阵列基板主要包括衬底和位于衬底上的电路结构,该电路结构例如包括至少一个栅极驱动电路,栅极驱动电路包括与多行子像素一一对应地多个移位寄存器,多个移位寄存器可以在时钟电压信号的控制下依次驱动多行子像素发光。
发明内容
一方面,提供一种阵列基板。所述阵列基板包括衬底、至少一个栅极驱动电路和至少一条时钟信号线。所述衬底包括显示区域和位于所述显示区域至少一侧的非显示区域。所述至少一个栅极驱动电路位于所述衬底的一侧;所述栅极驱动电路包括级联的多个移位寄存器,所述多个移位寄存器分别位于不同行,且所述多个移位寄存器分为至少两组移位寄存器,每组移位寄存器中包括至少一个移位寄存器,每组移位寄存器中的所有移位寄存器位于同一列;所述时钟信号线与所述栅极驱动电路位于所述衬底的同一侧,一个所述栅极驱动电路对应至少一条所述时钟信号线,所述时钟信号线包括:主体传输段,所述主体传输段在所述衬底上的正投影位于所述非显示区域内,所述主体传输段被配置为传输时钟信号;与所述主体传输段连接的至少两个分支传输段,所述至少两个分支传输段在所述衬底上的正投影位于所述显示区域内,每个分支传输段连接一组移位寄存器中每个移位寄存器的一个时钟信号输入端。
在一些实施例中,所述显示区域包括一一对应的多行像素区域和多行移位寄存器区域,对应的一行像素区域和一行移位寄存器区域相邻设置;所述栅极驱动电路中的多个移位寄存器在所述衬底上的正投影一一对应地位于多行移位寄存器区域内。
在一些实施例中,在与相邻的两行所述像素区域对应的两行所述移位寄存器区域中:各行所述移位寄存器区域位于与其对应的所述像素区域的同一侧;或者,一行所述移位寄存器区域位于与其对应的所述像素区域的第一侧,另一行所述移位寄存器区域位于与其对应的所述像素区域的第二侧。
在一些实施例中,所述至少两组移位寄存器沿远离所述主体传输段的方向依次为第一组移位寄存器到第M组移位寄存器;其中,自所述第一组移位 寄存器至所述第M组移位寄存器,各组移位寄存器中的移位寄存器的数量逐渐减少;和/或,自所述第一组移位寄存器至所述第M组移位寄存器,任意相邻的两组移位寄存器不处于同一列。
在一些实施例中,M大于或等于3;对于任一所述时钟信号线,与第二组所述移位寄存器到第M组所述移位寄存器连接的所有所述分支传输段中,至少两个分支传输段包括共用部分。
在一些实施例中,所述共用部分位于与所述至少两个分支传输段连接的至少两组所述移位寄存器中距离所述主体传输段最近的一组所述移位寄存器靠近所述主体传输段的一侧。
在一些实施例中,所述分支传输段包括与所述主体传输段连接的第一部分和与所述第一部分连接的第二部分;所述第二部分沿与其对应的一组所述移位寄存器的列方向延伸,与所述第二部分对应的一组所述移位寄存器并联在所述第二部分上。
在一些实施例中,所述分支传输段的第一部分沿行方向跨过不超过100个像素。
在一些实施例中,所有所述分支传输段在远离所述主体传输段的端部上的电阻电容延迟相等或近似相等。
在一些实施例中,所述至少两组移位寄存器包括依次远离所述主体传输段的第一组移位寄存器和第二组移位寄存器;所述时钟信号线包括第一分支传输段和第二分支传输段;所述第一分支传输段至少包括沿所述第一组移位寄存器的列方向延伸的第二部分,所述第一组移位寄存器中的每个移位寄存器并联在所述第一分支传输段的第二部分上;所述第二分支传输段包括彼此连接的第一部分和第二部分,所述第二分支传输段的第一部分还与所述主体传输段相连,所述第二分支传输段的第二部分沿所述第二组移位寄存器的列方向延伸,所述第二组移位寄存器中的每个移位寄存器并联在所述第二分支传输段的第二部分上。
在一些实施例中,所述多个移位寄存器在所述衬底上的正投影分别位于N行移位寄存器区域内,所述第一组移位寄存器在所述衬底上的正投影位于X行所述移位寄存器区域内,所述第二组移位寄存器在所述衬底上的正投影位于N-X行所述移位寄存器区域内;所述第一分支传输段的第二部分穿过X行所述移位寄存器区域;所述第二分支传输段的第一部分穿过X行所述移位寄存器区域;所述第二分支传输段的第二部分穿过N-X行所述移位寄存器区域,其中,X、N满足:
X·C1=(N-X)·C1+X·C2;
其中,X、N均为正整数,且X小于N;C1为穿过一行所述像素区域和一行移位寄存器区域且与所述移位寄存器相连时,所述分支传输段上产生的电阻电容延迟;C2为穿过一行像素区域和一行移位寄存器区域时,所述分支传输段产生的电阻电容延迟。
在一些实施例中,所述至少两组移位寄存器包括依次远离所述主体传输段的第一组移位寄存器、第二组移位寄存器和第三组移位寄存器;所述时钟信号线包括第一分支传输段、第二分支传输段和第三分支传输段;所述第一分支传输段至少包括沿所述第一组移位寄存器的列方向延伸的第二部分,所述第一组移位寄存器中的每个移位寄存器并联在所述第一分支传输段的第二部分上;所述第二分支传输段包括彼此连接的第一部分和第二部分,所述第二分支传输段的第一部分还与所述主体传输段相连,所述第二分支传输段的第二部分沿所述第二组移位寄存器的列方向延伸,所述第二组移位寄存器中的每个移位寄存器并联在所述第二分支传输段的第二部分上;所述第三分支传输段包括彼此连接的第一部分和第二部分,所述第三分支传输段的第一部分还与所述主体传输段相连,所述第三分支传输段的第二部分沿所述第三组移位寄存器的列方向延伸,所述第三组移位寄存器中的每个移位寄存器并联在所述第二部分上。
在一些实施例中,所述多个移位寄存器在所述衬底上的正投影位于N行移位寄存器区域内,所述第一组移位寄存器在所述衬底上的正投影位于X行所述移位寄存器区域内,所述第二组移位寄存器在所述衬底上的正投影位于Y行所述移位寄存器区域内,所述第三组移位寄存器在所述衬底上的正投影位于N-X-Y行所述移位寄存器区域内;所述第一分支传输段的第二部分穿过X行所述移位寄存器区域;所述第二分支传输段的第一部分穿过X行所述移位寄存器区域,所述第二分支传输段的第二部分穿过Y行所述移位寄存器区域,所述第三分支传输段的第一部分穿过X+Y行所述移位寄存器区域,所述第三分支传输段的第二部分穿过N-X-Y行所述移位寄存器区域,X、Y、N满足:
X·C1=Y·C1+X·C2;
X·C1=(N-X-Y)·C1+(X+Y)·C2;
其中,X、Y、N均为正整数,且X、Y均小于N;C1为穿过一行所述像素区域和一行移位寄存器区域且与所述移位寄存器相连时,所述分支传输段上产生的电阻电容延迟;C2为穿过一行像素区域和一行移位寄存器区域时, 所述分支传输段产生的电阻电容延迟。
在一些实施例中,所述至少两组移位寄存器包括依次远离所述主体传输段的第一组移位寄存器、第二组移位寄存器、第三组移位寄存器和第四组移位寄存器;所述时钟信号线包括第一分支传输段、第二分支传输段、第三分支传输段和第四分支传输段;所述第一分支传输段至少包括沿所述第一组移位寄存器的列方向延伸的第二部分,所述第一组移位寄存器中的每个移位寄存器并联在所述第一分支传输段的第二部分上;所述第二分支传输段包括彼此连接的第一部分和第二部分,所述第二分支传输段的第一部分还与所述主体传输段相连,所述第二分支传输段的第二部分沿所述第二组移位寄存器的列方向延伸,所述第二组移位寄存器中的每个移位寄存器并联在所述第二分支传输段的第二部分上;所述第三分支传输段包括彼此连接的第一部分和第二部分,所述第三分支传输段的第一部分还与所述主体传输段相连,所述第三分支传输段的第二部分沿所述第三组移位寄存器的列方向延伸,所述第三组移位寄存器中的每个移位寄存器并联在所述第三分支传输段的第二部分上;所述第四分支传输段包括彼此连接的第一部分和第二部分,所述第四分支传输段的第一部分还与所述主体传输段相连,所述第四分支传输段的第二部分沿所述第四组移位寄存器的列方向延伸,所述第四组移位寄存器中的每个移位寄存器并联在所述第四分支传输段的第二部分上。
在一些实施例中,所述多个移位寄存器在所述衬底上的正投落入N行移位寄存器区域内,所述第一组移位寄存器在所述衬底上的正投影落入X行所述移位寄存器区域内,所述第二组移位寄存器在所述衬底上的正投影落入Y行所述移位寄存器区域内,所述第三组移位寄存器在所述衬底上的正投影落入Z行所述移位寄存器区域内,所述第四组移位寄存器在所述衬底上的正投影落入N-X-Y-Z行所述移位寄存器区域内;所述第一分支传输段的第二部分穿过X行所述移位寄存器区域;所述第二分支传输段的第一部分穿过X行所述移位寄存器区域,所述第二分支传输段的第二部分穿过Y行所述移位寄存器区域,所述第三分支传输段的第一部分穿过X+Y行所述移位寄存器区域,所述第三分支传输段的第二部分穿过Z行所述移位寄存器区域,所述第四分支传输段的第一部分穿过X+Y+Z行所述移位寄存器区域,所述第四分支传输段的第二部分穿过N-X-Y-Z行所述移位寄存器区域;X、Y、Z、N满足:
X·C1=Y·C1+X·C2;
X·C1=Z·C1+(X+Y)·C2;
X·C1=(N-X-Y-Z)·C1+(X+Y+Z)·C2;
其中,X、Y、Z、N均为正整数,且X、Y、Z均小于N;C1为穿过一行所述像素区域和一行移位寄存器区域且与所述移位寄存器相连时,所述分支传输段上产生的电阻电容延迟;C2为穿过一行像素区域和一行移位寄存器区域时,所述分支传输段产生的电阻电容延迟。
在一些实施例中,所述第一分支传输段还包括第一部分,所述第一分支传输段的第一部分连接所述第一分支传输段的第二部分和所述主体传输段;每个所述分支传输段的第一部分包括沿行方向延伸的横向部分;其中,各个所述分支传输段的横向部分的长度大致相等。
另一方面,提供一种显示面板。所述显示面板包括如上述任一实施例所述的阵列基板。
又一方面,提供一种显示装置。所述显示装置包括:如上述任一实施例所述的显示面板。
又一方面,提供一种阵列基板的制作方法。所述制作方法包括:提供衬底;在所述衬底的同一侧形成至少一个栅极驱动电路和至少一条时钟信号线。其中,所述栅极驱动电路包括级联的多个移位寄存器,所述多个移位寄存器分别位于不同行,且所述多个移位寄存器分为至少两组移位寄存器,每组移位寄存器中包括至少一个移位寄存器,每组移位寄存器中的所有移位寄存器位于同一列;一个所述栅极驱动电路对应至少一条所述时钟信号线,所述时钟信号线包括主体传输段和与所述主体传输段连接的至少两个分支传输段;所述主体传输段被配置为传输时钟信号,每个分支传输段连接一组移位寄存器中每个移位寄存器的时钟信号输入端。
为了更清楚地说明本公开中的技术方案,下面将对本公开一些实施例中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本公开的一些实施例的附图,对于本领域普通技术人员来讲,还可以根据这些附图获得其他的附图。此外,以下描述中的附图可以视作示意图,并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的一种阵列基板的结构图;
图2为根据一些实施例的一种移位寄存器的电路结构图;
图3为根据一些实施例的另一种阵列基板的结构图;
图4为根据一些实施例的再一种阵列基板的结构图;
图5为根据一些实施例的又一种阵列基板的结构图;
图6为根据一些实施例的又一种阵列基板的结构图;
图7为根据一些实施例的又一种阵列基板的结构图;
图8为根据一些实施例的又一种阵列基板的结构图;
图9为根据一些实施例的一种时钟信号的波形图;
图10为根据一些实施例的另一种时钟信号的波形图;
图11为根据一些实施例的一种像素驱动电路的电路结构图;
图12A为根据一些实施例的一种显示面板的结构图;
图12B为根据一些实施例的另一种显示面板的结构图;
图13为根据一些实施例的一种制作方法的流程图。
下面将结合附图,对本公开一些实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本公开一部分实施例,而不是全部的实施例。基于本公开所提供的实施例,本领域普通技术人员所获得的所有其他实施例,都属于本公开保护的范围。
除非上下文另有要求,否则,在整个说明书和权利要求书中,术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思,即为“包含,但不限于”。在说明书的描述中,术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外,所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中,除非另有说明,“多个”的含义是两个或两个以上。
在描述一些实施例时,可能使用了“耦接”和“连接”及其衍伸的表达。例如,描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如,描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而,术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼 此间并无直接接触,但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言,其不排除适用于或被配置为执行额外任务或步骤的设备。
另外,“基于”的使用意味着开放和包容性,因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样,“约”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值,其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即,测量***的局限性)所确定。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中,为了清楚,放大了层和区域的厚度。因此,可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此,示例性实施方式不应解释为局限于本文示出的区域的形状,而是包括因例如制造而引起的形状偏差。例如,示为矩形的蚀刻区域通常将具有弯曲的特征。因此,附图中所示的区域本质上是示意性的,且它们的形状并非旨在示出设备的区域的实际形状,并且并非旨在限制示例性实施方式的范围。
本公开的一些实施例提供了一种阵列基板100。如图1所示,该阵列基板100包括衬底1、至少一个栅极驱动电路2和至少一条时钟信号线3。其中,所述至少一个栅极驱动电路2位于衬底1的一侧。时钟信号线3与栅极驱动电路2位于衬底1的同一侧,一个栅极驱动电路2对应至少一条时钟信号线3。也即,一个栅极驱动电路2可以连接一条时钟信号线3(如图1所示),或者,一个栅极驱动电路2可以连接两条或两条以上的时钟信号线3。
栅极驱动电路2包括级联的多个移位寄存器21,多个移位寄存器21分别位于不同行,且多个移位寄存器21分为至少两组移位寄存器21,每组移位寄存器21中包括至少一个移位寄存器21,每组移位寄存器21中的所有移位寄存器21位于同一列。
时钟信号线3包括主体传输段31和与主体传输段31连接的至少两个分支传输段32。主体传输段31被配置为传输时钟信号。每个分支传输段32连接一组移位寄存器21中每个移位寄存器21的一个时钟信号输入端。
可以理解,在一个栅极驱动电路2对应一条时钟信号线3的情况下,该栅极驱动电路2中的每个移位寄存器21具有一个时钟信号输入端;而在一个 栅极驱动电路2对应两条时钟信号线3的情况下,该栅极驱动电路2中的每个移位寄存器21具有两个时钟信号输入端。因此,与一个栅极驱动电路2对应的时钟信号线3的条数和该栅极驱动电路2中的每个移位寄存器21的时钟信号输入端的数量相等。
需要说明的是,相关技术中,栅极驱动电路中的多个移位寄存器排列成一列,且全部并联在一段时钟信号线(例如一个分支传输段)上。由于时钟信号线中的电信号在单向传输的过程中,每经过一个移位寄存器会产生一定的电阻电容延迟,因此靠近时钟信号线末端的移位寄存器容易因电阻电容延迟过大,而导致出现输出异常的问题。
而在本公开的一些实施例中,每条时钟信号线3包括至少两个分支传输段32,且各个分支传输段32一一对应地连接栅极驱动电路2的各组移位寄存器21,从而使得各个分支传输段32可以分别为对应的一组移位寄存器21中的每个移位寄存器21提供时钟信号,控制移位寄存器21输出栅极控制信号。因此,与相关技术中栅极驱动电路的全部移位寄存器同时并联在一段时钟信号线相比,本公开的一些实施例中,各分支传输段32上连接的移位寄存器21的数量减少,各分支传输段32上总的电阻电容延迟较小,即各分支传输段32远离主体传输段31的一端上的电阻电容延迟较小,从而可以有助于改善靠近时钟信号线末端的移位寄存器容易因电阻电容延迟过大出现输出异常的问题。
需要说明的是,本公开不对移位寄存器21的电路结构进行限制。示例性的,移位寄存器21的电路结构可以如图2所示。此时,移位寄存器21包括两个时钟信号输入端,即CLK和CLKB。这样,由多个图2所示的移位寄存器21构成的栅极驱动电路2可以对应两条时钟信号线3。
另外,在本公开一些实施例中,虽然将栅极驱动电路2中的多个移位寄存器21划分成至少两组移位寄存器21,但是一个栅极驱动电路2中所有的移位寄存器21仍然保持着级联关系,即位于相邻两行、位于不同组的两个移位寄存器21仍通过信号线实现级联。
在一些实施例中,如图3所示,衬底1包括显示区域A和位于显示区域A至少一侧的非显示区域B。显示区域A包括一一对应的多行像素区域A1和多行移位寄存器区域A2,对应的一行像素区域A1和一行移位寄存器区域A2相邻设置。栅极驱动电路2中的多个移位寄存器21在衬底1上的正投影一一对应地位于多行移位寄存器区域A2内。主体传输段31在衬底1上的正投影位于非显示区域B内,分支传输段32在衬底1上的正投影位于显示区域A内。
这样设置,使得栅极驱动电路2中的多个移位寄存器21在衬底1上的正投影一一对应地位于多行移位寄存器区域A2内,即栅极驱动电路2在衬底1上的正投影位于显示区域A内,使得栅极驱动电路2无需占用衬底1的非显示区域B,减小了衬底1中非显示区域B的面积,从而有利于减小采用该阵列基板100的显示装置的边框宽度,实现显示装置的窄边框设计。
在一些实施例中,在与相邻的两行像素区域A1对应的两行移位寄存器区域A2中,各行移位寄存器区域A2可以位于与其对应的像素区域A1的同一侧。
或者,在另一些实施例中,如图3所示,在与相邻的两行像素区域A1对应的两行移位寄存器区域A2中,一行移位寄存器区域A2位于与其对应的像素区域A1的第一侧,另一行移位寄存器区域A2位于与其对应的像素区域A1的第二侧。通过这样设置,使得每隔两行像素区域A1,可以连续设置两行移位寄存器区域A2(也即这两行移位寄存器区域A2之间不设置像素区域A1),此时,这两行移位寄存器区域A2之间的距离较近,从而使得与这两个移位寄存器区域A2相对应的两个移位寄存器21之间的距离也较近,因此可以在这两个移位寄存器21之间设置共用的信号线(即沿行方向L1延伸的信号线),这样有利于减少信号线的布置数量,从而有利于简化阵列基板100的结构。
值得注意的是,如图4所示,衬底1上设置栅极驱动电路2和时钟信号线3的一侧上还可以设置有像素驱动电路4、栅线5和数据线6。其中,像素驱动电路4、栅线5和数据线6在衬底1上的正投影均位于显示区域A内。栅线5可以沿行方向L1延伸,数据线6可以沿列方向L2延伸。
其中,行方向L1和列方向L2均平行于衬底1所在的平面。示例性的,如图1和图3所示,行方向L1和列方向L2相互垂直。当然,本公开并不仅局限于此,在另一些示例中,行方向L1和列方向L2只要相交即可,例如行方向L1和列方向L2之间可以存在夹角,该夹角可以为60度或80度。
这样,参见图4,分支传输段32沿移位寄存器21的列方向L2延伸的部分在衬底1上的正投影与栅线5在衬底1上的正投影之间存在交叠区域。此时,本公开发明人经研究发现,即使分支传输段32沿列方向L2延伸的部分不与移位寄存器21相连,分支传输段32沿列方向L2延伸的部分与栅线5之间也容易产生电阻电容延迟,从而使分支传输段32上传输的时钟信号产生异常(例如电压降低,下降沿时间增大)。随着分支传输段32沿列方向L2延伸的部分的长度增加,分支传输段32上的电容电阻延迟也逐渐增大。
同时,参见图4,分支传输段32还包括沿行方向L1延伸的部分,分支传 输段32沿行方向L1延伸的部分在衬底1上的正投影与数据线6在衬底1上的正投影之间存在交叠区域,本公开发明人经研究发现:分支传输段32沿行方向L1延伸的部分与数据线6之间也容易产生电阻电容延迟,从而使分支传输段32上传输的时钟信号产生异常。随着分支传输段32沿行方向L1延伸的部分的长度增加,分支传输段32上的电容电阻延迟也逐渐增大。
基于此,在一些实施例中,主体传输段31位于显示区域A沿列方向L2的任一侧(例如图3以主体传输段31位于显示区域A沿列方向L2的下侧进行示意)。至少两组移位寄存器21沿远离主体传输段31的方向依次为第一组移位寄存器211到第M组移位寄存器21M。其中,M大于或等于2。例如,图1中至少两组移位寄存器21分为第一组移位寄存器211和第二组移位寄存器212。
在此基础上,示例性的,如图1所示,自第一组移位寄存器211至第M组移位寄存器21M,各组移位寄存器21中的移位寄存器21的数量逐渐减少。通过这样设置,各分支传输段32上的电阻电容延迟较小,从而改善了因时钟信号线末端电阻电容延迟较大,导致与时钟信号线末端连接的移位寄存器容易出现输出异常的问题。
其中,由于第一组移位寄存器211到第M组移位寄存器21M逐渐远离主体传输段31,因此与该第一组移位寄存器211到第M组移位寄存器21M相对应的各个分支出传输段32跨过的像素区域A1的行数逐渐增多,分支传输段32跨过的栅线5的数目也逐渐增多,因而分支传输段32上因栅线5产生的电阻电容延迟逐渐增大。基于此,自第一组移位寄存器211至第M组移位寄存器21M,各组移位寄存器中的移位寄存器21的数量逐渐减少,还能够使与远离主体传输段31的一组移位寄存器21相连的分支传输段32末端的电阻电容较小,从而进一步改善因时钟信号线末端电阻电容延迟较大,导致与时钟信号线末端连接的移位寄存器容易出现输出异常的问题。
示例性的,自第一组移位寄存器211至第M组移位寄存器21M,任意相邻的两组移位寄存器21处于同一列。参见图5,第一组移位寄存器211与第二组移位寄存器212位于同一列。即,各组移位寄存器21在衬底1上可以均位于同一列,此时便于将一个栅极驱动电路2中的多个移位寄存器21级联在一起。
又示例性的,自第一组移位寄存器211至第M组移位寄存器21M,任意相邻的两组移位寄存器21不处于同一列。参见图6,第一组移位寄存器211与第二组移位寄存器212位于不同列。通过这样设置,一方面能够方便各分 支传输段32与移位寄存器21相连,即,各分支传输段32均能够由其所对应的各组移位寄存器的近端向各组移位寄存器的远端延伸,分支传输段32无需如图5所示延伸至第M组移位寄存器21M远端,由第M组移位寄存器21M的远端向第M组移位寄存器21M的近端延伸。从而减少了各分支传输段32跨越的栅线的数目,减小各分支传输段32末端的电阻电容延迟。其中,各组移位寄存器21的远端为各组移位寄存器21远离主体传输段31的一端,各组移位寄存器21的近端为各组移位寄存器21靠近主体传输段31的一端。
另一方面,将任意相邻的两组移位寄存器21设置在不同列,还能够方便将分支传输段32设置在相邻两组移位寄存器21之间(参见图6),从而减小各分支传输段32沿行方向L1延伸的部分的长度,减小分支传输段32沿行方向L1延伸的部分跨过的数据线6的数量,进而减小各分支传输段32沿行方向L1延伸的部分上的电阻电容延迟,减小各分支传输段32上总的电阻电容延迟,改善因时钟信号线上的电阻电容延迟较大,与时钟信号线末端连接的移位寄存器容易出现输出异常的问题。
在一些实施例中,当M大于或等于3(即栅极驱动电路2包括至少三组移位寄存器21)时,参见图6,对于任一时钟信号线3,与第二组移位寄存器212到第M组移位寄存器21M连接的所有分支传输段32中,至少两个分支传输段32包括共用部分321。通过这样设置,使得除与第一组移位寄存器21相连的分支传输段32外,其余各分支传输段32之间可以包括共用部分321,从而简化除与第一组移位寄存器211相连的分支传输段32外的其余分支传输段32的布线结构,降低成本。
示例性的,如图6所示,共用部分321位于与至少两个分支传输段32连接的至少两组移位寄存器21中距离主体传输段31最近的一组移位寄存器21靠近主体传输段31的一侧。
在一些实施例中,如图1所示,每个分支传输段32包括与主体传输段31连接的第一部分322和与第一部分322连接的第二部分323。每个第二部分323沿与其对应的一组移位寄存器21的列方向L2延伸,与每个第二部分323对应的一组移位寄存器21并联在第二部分323上。
在一些实施例中,参见图3,每行像素区域A1中包括多个亚像素A12(例如R、G、B),多个亚像素A12沿行方向L1依次排列。其中,示例性的,可以将每行像素区域A1中相邻的三个亚像素A12作为一个像素单元,像素单元中的三个亚像素A12可以用于产生三基色光(例如红光、绿光、蓝光)。
结合图3和图4,任一时钟信号线3中,所有分支传输段32的第一部分 322沿行方向L1跨过不超过100个像素A11。在一些示例中,一个像素A11是指上述一个亚像素A12。在另一些示例中,一个像素A11是指上述一个像素单元(如图3所示,一个像素A11包括三个亚像素A12)。
通过这样设置,所有分支传输段32的第一部分322沿行方向L1延伸的部分跨过的像素较少,分支传输段32的第一部分322沿行方向L1延伸的部分跨过的数据线6的数量也较少,从而使得分支传输段32第一部分322沿行方向L1延伸的部分上的电阻电容延迟较小,进而有利于减小分支传输段32上总的电阻电容延迟,改善因时钟信号线3末端电阻电容延迟较大,导致与时钟信号线3末端相连的移位寄存器21容易出现输出异常的问题。
在一些实施例中,所有分支传输段32在远离主体传输段31的端部上的电阻电容延迟相等或近似相等。这样,各分支传输段32末端连接的移位寄存器21所接收的时钟信号的波形相同或大致相同,即各分支传输段32末端传输的时钟信号相同或大致相同,也即与分支传输段32末端相连的移位寄存器上接收的信号相同或大致相同,移位寄存器输出栅极控制信号的时间相同或大致相同,提高了栅极驱动电路2各组移位寄存器21输出的栅极控制信号的可靠性。
在一些实施例中,如图1所示,至少两组移位寄存器21包括依次远离主体传输段31的第一组移位寄存器211和第二组移位寄存器212。时钟信号线3包括第一分支传输段33和第二分支传输段34。第一分支传输段33至少包括沿第一组移位寄存器211的列方向L2延伸的第二部分332,第一组移位寄存器211中的每个移位寄存器21并联在第一分支传输段33的第二部分332上。第二分支传输段34包括彼此连接的第一部分341和第二部分342,第二分支传输段34的第一部分341还与主体传输段31相连,第二分支传输段34的第二部分342沿第二组移位寄存器212的列方向L2延伸,第二组移位寄存器212中的每个移位寄存器21并联在第二分支传输段34的第二部分342上。
其中,第一分支传输段33的第二部分332可以直接连接至主体传输段31;或者,如图1所示,第一分支传输段33还可以包括第一部分331,第一部分331用于连接第二部分332和主体传输段31。
这样,将栅极驱动电路2中的多个移位寄存器21分成两组,利用两条分支传输段32分别为两组移位寄存器21提供时钟信号,一方面能够使各分支传输段32上连接的移位寄存器21的数量较少,减小分支传输段32上的电阻电容延迟,改善因时钟信号线上的电阻电容延迟较大,与时钟信号线末端相连的移位寄存器容易出现输出异常的问题。另一方面,移位寄存器21的分组简 单,可以简化布线结构,降低成本。
在此基础上,多个移位寄存器21在衬底1上的正投影可以分别位于N行移位寄存器区域A2内,第一组移位寄存器211在衬底1上的正投影可以位于X行移位寄存器区域A2内,第二组移位寄存器212在衬底1上的正投影可以位于N-X行移位寄存器区域A2内;第一分支传输段33的第二部分332可以穿过X行移位寄存器区域A2;第二分支传输段34的第一部分341可以穿过X行移位寄存器区域A2;第二分支传输段34的第二部分342可以穿过N-X行移位寄存器区域A2。其中,X、N满足:
X·C1=(N-X)·C1+X·C2。
其中,X、N均为正整数,且X小于N。C1为穿过一行像素区域A1和一行移位寄存器区域A2且与移位寄存器21相连时,分支传输段32上产生的电阻电容延迟;C2为穿过一行像素区域A1和一行移位寄存器区域A2时,分支传输段32产生的电阻电容延迟。
通过上述等式可以推导出:
在C1、C2、N的值已知的情况下,X的值可以通过计算得到。其中,根据产品结构的不同,C1和C2可以具有不同的值,示例性的,C1可以为60fF,C2可以是30fF。同样的,根据产品的像素结构的不同,其移位寄存器区域A2数量N也可以不同。本公开并不对移位寄存器区域A2的数量进行限制。
在另一些实施例中,如图6所示,所述至少两组移位寄存器21包括依次远离主体传输段31的第一组移位寄存器211、第二组移位寄存器212和第三组移位寄存器213。时钟信号线3包括第一分支传输段33、第二分支传输段34和第三分支传输段35。
第一分支传输段33至少包括沿第一组移位寄存器211的列方向L2延伸的第二部分332,第一组移位寄存器211中的每个移位寄存器21并联在第一分支传输段33的第二部分332上。第二分支传输段34包括彼此连接的第一部分341和第二部分342,第二分支传输段34的第一部分341还与主体传输段31相连,第二分支传输段34的第二部分342沿第二组移位寄存器212的列方向L2延伸,第二组移位寄存器212中的每个移位寄存器21并联在第二分支传输段34的第二部分342上;第三分支传输段35包括彼此连接的第一部分351和第二部分352,第三分支传输段35的第一部分351还与主体传输段31相连,第二部分352沿第三组移位寄存器213的列方向L2延伸,第三 组移位寄存器213中的每个移位寄存器21并联在第三组移位寄存器213的第二部分352上。
其中,第一分支传输段33的第二部分332可以直接连接至主体传输段31;或者,如图6所示,第一分支传输段33还可以包括第一部分331,第一部分331用于连接第二部分332和主体传输段31。
其中,第一分支传输段33还可以包括第一部分331,第一部分331用于连接第二部分332和主体传输段31。
通过这样设置,使得时钟信号线3的各分支传输段32上连接的移位寄存器21的数目更小,各分支传输段32上的电阻电容延迟更小,从而能够更加有利于改善因时钟信号线上的电阻电容延迟较大,与时钟信号线末端连接的移位寄存器容易出现输出异常的问题。
基于此,多个移位寄存器21在衬底1上的正投影可以位于N行移位寄存器区域A2内,第一组移位寄存器211在衬底1上的正投影可以位于X行移位寄存器区域A2内,第二组移位寄存器212在衬底1上的正投影可以位于Y行移位寄存器区域A2内,第三组移位寄存器213在衬底1上的正投影可以位于N-X-Y行移位寄存器区域A2内。
第一分支传输段33的第二部分332可以穿过X行移位寄存器区域A2;第二分支传输段34的第一部分341可以穿过X行移位寄存器区域A2,第二分支传输段34的第二部分342可以穿过Y行移位寄存器区域A2,第三分支传输段35的第一部分351可以穿过X+Y行移位寄存器区域A2,第三分支传输段35的第二部分可以穿过N-X-Y行移位寄存器区域A2,X、Y、N满足:
X·C1=Y·C1+X·C2;
X·C1=(N-X-Y)·C1+(X+Y)·C2。
其中,X、Y、N均为正整数,且X、Y均小于N。C1为穿过一行像素区域A1和一行移位寄存器区域A2且与移位寄存器21相连时,分支传输段32上产生的电阻电容延迟;C2为穿过一行像素区域A1和一行移位寄存器区域A2时,分支传输段32产生的电阻电容延迟。
通过上述等式,可以推导出:
在一些实施例中,如图7所示,所述至少两组移位寄存器21包括依次远离主体传输段31的第一组移位寄存器211、第二组移位寄存器212、第三组 移位寄存器213和第四组移位寄存器214,时钟信号线3包括第一分支传输段33、第二分支传输段34、第三分支传输段35和第四分支传输段36。
第一分支传输段33至少包括沿第一组移位寄存器211的列方向L2延伸的第二部分332,第一组移位寄存器211中的每个移位寄存器21并联在第一分支传输段33的第二部分332上。第二分支传输段34包括彼此连接的第一部分341和第二部分342,第二分支传输段34的第一部分341还与主体传输段31相连,第二分支传输段34的第二部分342沿第二组移位寄存器212的列方向L2延伸,第二组移位寄存器212中的每个移位寄存器21并联在第二分支传输段34的第二部分342上。第三分支传输段35包括彼此连接的第一部分351和第二部分352,第三分支传输段35的第一部分351还与主体传输段31相连,第三分支传输段35的第二部分352沿第三组移位寄存器213的列方向L2延伸,第三组移位寄存器213中的每个移位寄存器21并联在第三分支传输段35的第二部分352上。第四分支传输段36包括彼此连接的第一部分361和第二部分362,第四分支传输段36的第一部分361还与主体传输段31相连,第四分支传输段36的第二部分362沿第四组移位寄存器214的列方向L2延伸,第四组移位寄存器214中的每个移位寄存器21并联在第四分支传输段36的第二部分362上。
其中,第一分支传输段33的第二部分332可以直接连接至主体传输段31;或者,如图7所示,第一分支传输段33还可以包括第一部分331,第一部分331用于连接第二部分332和主体传输段31。
这样,将栅极驱动电路2中的多个移位寄存器21分成四组,各组移位寄存器21与一条分支传输段32相连,各分支传输段32上的连接的移位寄存器21的数目更少,分支传输段上总的电阻电容延迟更小,与分支传输段32末端相连的移位寄存器21更不容易出现输出异常的问题。
基于此,多个移位寄存器21在衬底1上的正投影可以落入N行移位寄存器区域A2内,第一组移位寄存器211在衬底1上的正投影可以落入X行移位寄存器区域A2内,第二组移位寄存器212在衬底1上的正投影可以落入Y行移位寄存器区域A2内,第三组移位寄存器213在衬底1上的正投影可以落入Z行移位寄存器区域A2内,第四组移位寄存器214在衬底1上的正投影可以落入N-X-Y-Z行移位寄存器区域A2内。
第一分支传输段33的第二部分332可以穿过X行移位寄存器区域A2;第二分支传输段34的第一部分341可以穿过X行移位寄存器区域A2,第二分支传输段34的第二部分342可以穿过Y行移位寄存器区域A2,第三分支 传输段35的第一部分351可以穿过X+Y行移位寄存器区域A2,第三分支传输段35的第二部分352可以穿过Z行移位寄存器区域A2,第四分支传输段36的第一部分361可以穿过X+Y+Z行移位寄存器区域,第四分支传输段36的第二部分362可以穿过N-X-Y-Z行移位寄存器区域;X、Y、Z、N满足:
X·C1=Y·C1+X·C2;
X·C1=Z·C1+(X+Y)·C2;
X·C1=(N-X-Y-Z)·C1+(X+Y+Z)·C2。
其中,X、Y、Z、N均为正整数,且X、Y、Z均小于N。C1为穿过一行像素区域A1和一行移位寄存器区域A2且与移位寄存器21相连时,分支传输段32上产生的电阻电容延迟;C2为穿过一行像素区域A1和一行移位寄存器区域A2时,分支传输段32产生的电阻电容延迟。
通过上述等式可以推导出:
在一些实施例中,第一分支传输段33还可以包括第一部分331,第一分支传输段33的第一部分331连接第一分支传输段33的第二部分332和主体传输段31。每个分支传输段32的第一部分322包括沿行方向L1延伸的横向部分;其中,各个分支传输段32的横向部分的长度大致相等。这样,通过上述等式所计算出的值能够更加准确。
需要说明的是,图1、图6、图7仅示出了栅极驱动电路2中的多个移位寄存器21分成2组移位寄存器、3组移位寄存器、4组移位寄存器,时钟信号线包括2个分支传输段32、3个分支传输段32、4个分支传输段32时的栅极驱动电路2与时钟信号线3的连接方式。可以理解,本公开所提供的技术方案并不仅限制于此,即栅极驱动电路2中的移位寄存器21还可以划分成5组移位寄存器或者更多组移位寄存器,从而使各分支传输段32上的电阻电容延迟较小,以改善时钟信号线上电阻电容延迟过大,导致与时钟信号线末端相连的移位寄存器输出异常的问题。
在一些实施例中,参见图8和图9,时钟信号线CLK直接与一个栅极驱动线路中的所有移位寄存器相连,时钟信号线CLK末端的电阻电容延迟较大。在此情况下,当向时钟信号线CLK输入12V电压信号时,时钟信号线CLK 的末端输出的时钟信号电压Vm的最大值仅能够达到10.6V,且该时钟信号的下降沿时间为3μs。这样,在与时钟信号线CLK末端相连的移位寄存器中的晶体管需要12V的时钟信号才能够被开启的情况下,时钟信号线CLK末端输出的时钟信号不足以将该晶体管打开,从而容易使得移位寄存器出现输出异常的问题。
而在一些实施例中,参见图6和图10,时钟信号线3包括主体传输段31和与主体传输段31相连的三个分支传输段32,一个分支传输段32分别与一组移位寄存器21相连接。这样,分支传输段32末端的电阻电容延迟均较小。在此情况下,在向时钟信号线3输入12V电压信号时,分支传输段32的末端输出的时钟信号电压Vm的最大值能够达到12V,且该时钟信号的下降沿时间仅为1.65μs。这样,在与分支传输段32的末端相连的移位寄存器21中的晶体管需要12V的电信号才能被开启的情况下,分支传输段32传输的时钟信号足够可以将该晶体管打开,从而改善了移位寄存器21输出异常的问题。同时由于时钟信号的下降沿时间较小,利用该时钟信号还能够更加准确的控制晶体管的打开时间,从而保证该移位寄存器21正常输出栅极控制信号。
上述实施例均以一个栅极驱动电路21为例进行说明,可以理解,栅极驱动电路2为阵列基板100上的多个像素驱动电路4提供栅极驱动信号。当像素驱动电路需要利用多个栅极驱动信号时,阵列基板100还可以包括多个栅极驱动电路。示例性的,当像素驱动电路包括如图11所示的电路结构(即,像素驱动电路设置有四个栅极信号端,即G1、G2、G3和EM)时,阵列基板1上可以设置有四个栅极驱动电路2,分别为该像素驱动电路提供栅极驱动信号。
本公开的一些实施例还提供了一种显示面板300,参见图12A和图12B,该显示面板300包括上述任一实施例所述的阵列基板100。其中,显示面板300可以是液晶显示面板(Liquid Crystal Display,简称LCD),有机电致发光显示面板(Organic Light-Emitting Diode,简称OLED)或量子点电致发光显示面板(Quantum Dot Light Emitting Diodes,简称QLED)等。
当显示面板300为液晶显示面板时,参见图12A,液晶显示面板可以包括阵列基板100、对盒基板210以及设置在阵列基板100和对盒基板210之间的液晶层220。
当显示面板300为有机电致发光显示面板(或量子点电致发光显示面板)时,参见图12B,有机电致发光显示面板(或量子点电致发光显示面板)可以包括阵列基板100和发光器件200。发光器件200可以包括阳极,阴极以及位 于阴极与阳极之间的发光功能层。
本公开提供的显示面板所能实现的有益效果,至少包括与上述技术方案提供的阵列基板相同的有益效果,在此不做赘述。
本公开的一些实施例还提供了一种显示装置,该显示装置包括上述实施例所提供的显示面板。上述显示装置可以是电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的部件。本公开提供的显示装置所能实现的有益效果,与上述技术方案提供的阵列基板、显示面板所能达到的有益效果相同,在此不做赘述。
本公开的一些实施例还提供了一种制作方法,用于制作上述任一实施例所述的阵列基板。如图13所示,该制作方法包括:
S1、提供衬底1。
S2、在衬底1的同一侧形成至少一个栅极驱动电路2和至少一条时钟信号线3。
其中,栅极驱动电路2包括级联的多个移位寄存器21,多个移位寄存器21分别位于不同行,且多个移位寄存器21分为至少两组移位寄存器21,每组移位寄存器21中包括至少一个移位寄存器21,每组移位寄存器21中的所有移位寄存器21位于同一列。
一个栅极驱动电路2对应至少一条时钟信号线3,时钟信号线3包括主体传输段31和与主体传输段31连接的至少两个分支传输段32;主体传输段31被配置为传输时钟信号,每个分支传输段32连接一组移位寄存器中每个移位寄存器21的时钟信号输入端。
这样,利用上述制作方法制作而成的阵列基板中,每条时钟信号线3包括至少两个分支传输段32,且各个分支传输段32一一对应地连接栅极驱动电路2的各组移位寄存器21,从而使得各个分支传输段32可以分别为对应的一组移位寄存器21中的每个移位寄存器21提供时钟信号,控制移位寄存器21输出栅极控制信号。其中,由于各分支传输段32上连接的移位寄存器21的数量较少,各分支传输段32上总的电阻电容延迟较小,即各分支传输段32远离主体传输段31的一端上的电阻电容延迟较小,因而可以有助于改善靠近时钟信号线末端的移位寄存器容易因电阻电容延迟过大出现输出异常的问题。
以上所述,仅为本公开的具体实施方式,但本公开的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本公开揭露的技术范围内,想到变化或替换,都应涵盖在本公开的保护范围之内。因此,本公开的保护范围应以所述权利要求的保护范围为准。
Claims (19)
- 一种阵列基板,包括:衬底,包括显示区域和位于所述显示区域至少一侧的非显示区域;至少一个栅极驱动电路,位于所述衬底的一侧;所述栅极驱动电路包括级联的多个移位寄存器,所述多个移位寄存器分别位于不同行,且所述多个移位寄存器分为至少两组移位寄存器,每组移位寄存器中包括至少一个移位寄存器,每组移位寄存器中的所有移位寄存器位于同一列;至少一条时钟信号线,所述时钟信号线与所述栅极驱动电路位于所述衬底的同一侧,一个所述栅极驱动电路对应至少一条所述时钟信号线,所述时钟信号线包括:主体传输段,所述主体传输段在所述衬底上的正投影位于所述非显示区域内,所述主体传输段被配置为传输时钟信号;与所述主体传输段连接的至少两个分支传输段,所述至少两个分支传输段在所述衬底上的正投影位于所述显示区域内,每个分支传输段连接一组移位寄存器中每个移位寄存器的一个时钟信号输入端。
- 根据权利要求1所述的阵列基板,其中,所述显示区域包括一一对应的多行像素区域和多行移位寄存器区域,对应的一行像素区域和一行移位寄存器区域相邻设置;所述栅极驱动电路中的多个移位寄存器在所述衬底上的正投影一一对应地位于多行移位寄存器区域内。
- 根据权利要求2所述的阵列基板,其中,在与相邻的两行所述像素区域对应的两行所述移位寄存器区域中:各行所述移位寄存器区域位于与其对应的所述像素区域的同一侧;或者,一行所述移位寄存器区域位于与其对应的所述像素区域的第一侧,另一行所述移位寄存器区域位于与其对应的所述像素区域的第二侧。
- 根据权利要求2或3所述的阵列基板,其中,所述至少两组移位寄存器沿远离所述主体传输段的方向依次为第一组移位寄存器到第M组移位寄存器;其中,自所述第一组移位寄存器至所述第M组移位寄存器,各组移位寄存器中的移位寄存器的数量逐渐减少;和/或,自所述第一组移位寄存器至所述第M组移位寄存器,任意相邻的两组移位寄存器不处于同一列。
- 根据权利要求4所述的阵列基板,其中,M大于或等于3;对于任一所述时钟信号线,与第二组所述移位寄存器到第M组所述移位寄存器连接的所有所述分支传输段中,至少两个分支传输段包括共用部分。
- 根据权利要求5所述的阵列基板,其中,所述共用部分位于与所述至少两个分支传输段连接的至少两组所述移位寄存器中距离所述主体传输段最近的一组所述移位寄存器靠近所述主体传输段的一侧。
- 根据权利要求1~6任一项中所述的阵列基板,其中,所述分支传输段包括与所述主体传输段连接的第一部分和与所述第一部分连接的第二部分;所述第二部分沿与其对应的一组所述移位寄存器的列方向延伸,与所述第二部分对应的一组所述移位寄存器并联在所述第二部分上。
- 根据权利要求7所述的阵列基板,其中,所述分支传输段的第一部分沿行方向跨过不超过100个像素。
- 根据权利要求1~8任一项中所述的阵列基板,其中,所有所述分支传输段在远离所述主体传输段的端部上的电阻电容延迟相等或近似相等。
- 根据权利要求1~9任一项中所述的阵列基板,其中,所述至少两组移位寄存器包括依次远离所述主体传输段的第一组移位寄存器和第二组移位寄存器;所述时钟信号线包括第一分支传输段和第二分支传输段;所述第一分支传输段至少包括沿所述第一组移位寄存器的列方向延伸的第二部分,所述第一组移位寄存器中的每个移位寄存器并联在所述第一分支传输段的第二部分上;所述第二分支传输段包括彼此连接的第一部分和第二部分,所述第二分支传输段的第一部分还与所述主体传输段相连,所述第二分支传输段的第二部分沿所述第二组移位寄存器的列方向延伸,所述第二组移位寄存器中的每个移位寄存器并联在所述第二分支传输段的第二部分上。
- 根据权利要求10所述的阵列基板,其中,所述多个移位寄存器在所述衬底上的正投影分别位于N行移位寄存器区域内,所述第一组移位寄存器在所述衬底上的正投影位于X行所述移位寄存器区域内,所述第二组移位寄存器在所述衬底上的正投影位于N-X行所述移位寄存器区域内;所述第一分支传输段的第二部分穿过X行所述移位寄存器区域;所述第二分支传输段的第一部分穿过X行所述移位寄存器区域;所述 第二分支传输段的第二部分穿过N-X行所述移位寄存器区域,其中,X、N满足:X·C1=(N-X)·C1+X·C2;其中,X、N均为正整数,且X小于N;C1为穿过一行所述像素区域和一行移位寄存器区域且与所述移位寄存器相连时,所述分支传输段上产生的电阻电容延迟;C2为穿过一行像素区域和一行移位寄存器区域时,所述分支传输段产生的电阻电容延迟。
- 根据权利要求1~9任一项中所述的阵列基板,其中,所述至少两组移位寄存器包括依次远离所述主体传输段的第一组移位寄存器、第二组移位寄存器和第三组移位寄存器;所述时钟信号线包括第一分支传输段、第二分支传输段和第三分支传输段;所述第一分支传输段至少包括沿所述第一组移位寄存器的列方向延伸的第二部分,所述第一组移位寄存器中的每个移位寄存器并联在所述第一分支传输段的第二部分上;所述第二分支传输段包括彼此连接的第一部分和第二部分,所述第二分支传输段的第一部分还与所述主体传输段相连,所述第二分支传输段的第二部分沿所述第二组移位寄存器的列方向延伸,所述第二组移位寄存器中的每个移位寄存器并联在所述第二分支传输段的第二部分上;所述第三分支传输段包括彼此连接的第一部分和第二部分,所述第三分支传输段的第一部分还与所述主体传输段相连,所述第三分支传输段的第二部分沿所述第三组移位寄存器的列方向延伸,所述第三组移位寄存器中的每个移位寄存器并联在所述第二部分上。
- 根据权利要求12所述的阵列基板,其中,所述多个移位寄存器在所述衬底上的正投影位于N行移位寄存器区域内,所述第一组移位寄存器在所述衬底上的正投影位于X行所述移位寄存器区域内,所述第二组移位寄存器在所述衬底上的正投影位于Y行所述移位寄存器区域内,所述第三组移位寄存器在所述衬底上的正投影位于N-X-Y行所述移位寄存器区域内;所述第一分支传输段的第二部分穿过X行所述移位寄存器区域;所述第二分支传输段的第一部分穿过X行所述移位寄存器区域,所述第二分支传输段的第二部分穿过Y行所述移位寄存器区域,所述第三分支传输段的第一部分穿过X+Y行所述移位寄存器区域,所述第三分支传输段的第二部分穿过N-X-Y行所述移位寄存器区域,X、Y、N满足:X·C1=Y·C1+X·C2;X·C1=(N-X-Y)·C1+(X+Y)·C2;其中,X、Y、N均为正整数,且X、Y均小于N;C1为穿过一行所述像素区域和一行移位寄存器区域且与所述移位寄存器相连时,所述分支传输段上产生的电阻电容延迟;C2为穿过一行像素区域和一行移位寄存器区域时,所述分支传输段产生的电阻电容延迟。
- 根据权利要求1~9任一项中所述的阵列基板,其中,所述至少两组移位寄存器包括依次远离所述主体传输段的第一组移位寄存器、第二组移位寄存器、第三组移位寄存器和第四组移位寄存器;所述时钟信号线包括第一分支传输段、第二分支传输段、第三分支传输段和第四分支传输段;所述第一分支传输段至少包括沿所述第一组移位寄存器的列方向延伸的第二部分,所述第一组移位寄存器中的每个移位寄存器并联在所述第一分支传输段的第二部分上;所述第二分支传输段包括彼此连接的第一部分和第二部分,所述第二分支传输段的第一部分还与所述主体传输段相连,所述第二分支传输段的第二部分沿所述第二组移位寄存器的列方向延伸,所述第二组移位寄存器中的每个移位寄存器并联在所述第二分支传输段的第二部分上;所述第三分支传输段包括彼此连接的第一部分和第二部分,所述第三分支传输段的第一部分还与所述主体传输段相连,所述第三分支传输段的第二部分沿所述第三组移位寄存器的列方向延伸,所述第三组移位寄存器中的每个移位寄存器并联在所述第三分支传输段的第二部分上;所述第四分支传输段包括彼此连接的第一部分和第二部分,所述第四分支传输段的第一部分还与所述主体传输段相连,所述第四分支传输段的第二部分沿所述第四组移位寄存器的列方向延伸,所述第四组移位寄存器中的每个移位寄存器并联在所述第四分支传输段的第二部分上。
- 根据权利要求14所述的阵列基板,其中,所述多个移位寄存器在所述衬底上的正投落入N行移位寄存器区域内,所述第一组移位寄存器在所述衬底上的正投影落入X行所述移位寄存器区域内,所述第二组移位寄存器在所述衬底上的正投影落入Y行所述移位寄存器区域内,所述第三组移位寄存器在所述衬底上的正投影落入Z行所述移位寄存器区域内,所述第四组移位寄存器在所述衬底上的正投影落入N-X-Y-Z行所述移位寄存器区域内;所述第一分支传输段的第二部分穿过X行所述移位寄存器区域;所述第二分支传输段的第一部分穿过X行所述移位寄存器区域,所述第二分支传输段的第二部分穿过Y行所述移位寄存器区域,所述第三分支传输段的第一部分穿过X+Y行所述移位寄存器区域,所述第三分支传输段的第二部分穿过Z行所述移位寄存器区域,所述第四分支传输段的第一部分穿过X+Y+Z行所述移位寄存器区域,所述第四分支传输段的第二部分穿过N-X-Y-Z行所述移位寄存器区域;X、Y、Z、N满足:X·C1=Y·C1+X·C2;X·C1=Z·C1+(X+Y)·C2;X·C1=(N-X-Y-Z)·C1+(X+Y+Z)·C2;其中,X、Y、Z、N均为正整数,且X、Y、Z均小于N;C1为穿过一行所述像素区域和一行移位寄存器区域且与所述移位寄存器相连时,所述分支传输段上产生的电阻电容延迟;C2为穿过一行像素区域和一行移位寄存器区域时,所述分支传输段产生的电阻电容延迟。
- 根据权利要求10~15任一项中所述的阵列基板,其中,所述第一分支传输段还包括第一部分,所述第一分支传输段的第一部分连接所述第一分支传输段的第二部分和所述主体传输段;每个所述分支传输段的第一部分包括沿行方向延伸的横向部分;其中,各个所述分支传输段的横向部分的长度大致相等。
- 一种显示面板,包括:如权利要求1~16任一项中所述的阵列基板。
- 一种显示装置,包括:如权利要求17所述的显示面板。
- 一种阵列基板的制作方法,包括:提供衬底;在所述衬底的同一侧形成至少一个栅极驱动电路和至少一条时钟信号线;其中,所述栅极驱动电路包括级联的多个移位寄存器,所述多个移位寄存器分别位于不同行,且所述多个移位寄存器分为至少两组移位寄存器,每组移位寄存器中包括至少一个移位寄存器,每组移位寄存器中的所有移位寄存器位于同一列;一个所述栅极驱动电路对应至少一条所述时钟信号线,所述时钟信号线包括主体传输段和与所述主体传输段连接的至少两个分支传输段;所述主体传输段被配置为传输时钟信号,每个分支传输段连接一组移位寄存器中每个 移位寄存器的时钟信号输入端。
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