WO2022127077A1 - 激光雷达的发射端电路及检测其驱动电流的方法 - Google Patents

激光雷达的发射端电路及检测其驱动电流的方法 Download PDF

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WO2022127077A1
WO2022127077A1 PCT/CN2021/104001 CN2021104001W WO2022127077A1 WO 2022127077 A1 WO2022127077 A1 WO 2022127077A1 CN 2021104001 W CN2021104001 W CN 2021104001W WO 2022127077 A1 WO2022127077 A1 WO 2022127077A1
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clock signal
voltage
unit
output
sampling
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PCT/CN2021/104001
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English (en)
French (fr)
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历洪宇
刘建峰
向少卿
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上海禾赛科技有限公司
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Publication of WO2022127077A1 publication Critical patent/WO2022127077A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
    • G01S7/483—Details of pulse systems
    • G01S7/484—Transmitters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/14—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
    • G01R15/22—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using light-emitting devices, e.g. LED, optocouplers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S3/00—Lasers, i.e. devices using stimulated emission of electromagnetic radiation in the infrared, visible or ultraviolet wave range
    • H01S3/09—Processes or apparatus for excitation, e.g. pumping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor

Definitions

  • the present invention generally relates to the technical field of laser radar, and in particular, to a transmitter circuit of a laser radar.
  • the transmitting end relies on the high-voltage driving tube to provide current for the laser, so that the laser emits light.
  • characteristics such as threshold voltage and mobility of high-voltage drive transistors will vary with factors such as temperature and process angle, so the output current will have problems of temperature drift and inconsistency between chips.
  • the direct detection requires that all the devices inside the detection circuit work in the high-voltage domain, and there are many functional components in the detection circuit. At the same time, due to the parasitic effect caused by the large area, the circuit works slower.
  • the driving current in the current scenario is a current signal in the form of a narrow pulse
  • ADC analog-to-digital converter
  • the rate of change of the current value is fast.
  • the sampling clock is biased, the measurement error will be particularly large; the second is to convert the The pulse peak is broadened and quantified by a low-speed analog-to-digital converter, but the peak hold circuit in the high-voltage domain is difficult to achieve.
  • the present invention provides a transmitter circuit for lidar, comprising:
  • a driving circuit for applying a driving voltage to at least one laser to make the at least one laser emit light
  • a detection circuit including a voltage dividing part and a sampling unit, is used to detect the driving current when the at least one laser emits light, wherein:
  • the voltage dividing part is configured to divide the driving voltage to output a voltage dividing signal to the sampling unit;
  • the sampling unit is configured to sample the voltage-divided signal output from the voltage-dividing part according to the system clock signal of the transmitter circuit to obtain a corresponding sampling value.
  • the driving circuit includes a voltage source and a switching device, one end of the at least one laser is connected to the voltage source, and the other end is connected to the switching device to form a light-emitting current loop, the switch The device controls the turn-on and turn-off of the light-emitting current loop according to the system clock signal, and the voltage source is grounded through a first capacitor;
  • the partial pressure part includes:
  • a first voltage dividing capacitor the first end of the first voltage dividing capacitor is coupled to the voltage source
  • a second voltage dividing capacitor the first end of the second voltage dividing capacitor is coupled to the second end of the first capacitor, and the second end of the second voltage dividing capacitor is grounded.
  • the detection circuit further comprises:
  • the signal processing unit coupled to the output end of the sampling unit, is configured to determine the driving current when the at least one laser emits light according to the sampling value output by the sampling unit.
  • the detection circuit further includes a low-pass filtering unit, coupled between the voltage dividing part and the input end of the sampling unit, for slowing down the voltage dividing part output from the voltage dividing part the rate of change of the pressure signal.
  • the low-pass filtering unit comprises:
  • the first end of the first resistor is coupled to the second end of the first voltage dividing capacitor, and the second end of the first resistor is coupled to the input end of the sampling unit;
  • the first end of the second resistor is coupled to the second end of the first resistor
  • the first end of the second capacitor is coupled to the input end of the sampling unit, and the second end of the second capacitor is grounded;
  • the direct current source is coupled to the second end of the second resistor.
  • the detection circuit further includes a gain unit, coupled between the low-pass filtering unit and the input end of the sampling unit, for restoring the divided voltage output by the voltage dividing unit The voltage amplitude of the signal.
  • the detection circuit further comprises:
  • a clock adjustment part configured to adjust the pulse period and/or pulse width of the system clock signal, so as to output a sampling clock signal to the sampling unit;
  • the sampling unit samples the voltage-divided signal output by the voltage-dividing unit according to a sampling clock signal corresponding to the system clock signal.
  • the clock adjustment section includes a period expansion unit configured to receive the system clock signal and expand a signal period of the system clock signal to output an expanded intermediate clock signal.
  • the period expansion unit is formed by a monostable circuit
  • the monostable circuit includes:
  • the first D flip-flop is triggered by the system clock signal, the input terminal is connected to a high level, and the reverse output terminal outputs an intermediate clock signal;
  • a first inverter the input end of which is coupled to the inverted output end of the first D flip-flop
  • a third capacitor the first end of which is coupled to the output end of the first inverter, and the second end is grounded;
  • the input terminal is coupled to the first terminal of the third capacitor, and the output terminal is coupled to the reset terminal of the first D flip-flop.
  • the period extension length of the period extension unit for the system clock signal is determined by a parameter of the third capacitor in the monostable circuit.
  • the clock adjustment part further includes a pulse width expansion unit, configured to generate a sampling clock signal according to the system clock signal and the intermediate clock signal; wherein, the sampling clock signal has a The pulse width is greater than the pulse width of the system clock signal, and the period of the sampling clock signal is the same as the period of the intermediate clock signal.
  • the pulse width expansion unit comprises:
  • the second D flip-flop is triggered by the reverse signal of the system clock signal, the input terminal is connected to a high level, and the reset terminal is coupled to the reverse output terminal of the first D flip-flop;
  • NOR gate two input ends are respectively coupled with the forward output end of the second D flip-flop and the reverse signal of the system clock signal;
  • the input terminal is coupled to the output terminal of the NOR gate
  • a fourth capacitor the first end of which is coupled to the output end of the third inverter, and the second end is grounded;
  • the fourth inverter the input terminal is coupled to the first terminal of the fourth capacitor, and the second terminal is used as the output terminal of the pulse width expansion unit to output the sampling clock signal.
  • the pulse width extension length of the pulse width extension unit for the system clock signal is determined by a parameter of the fourth capacitor.
  • the sampling unit includes an analog-to-digital converter.
  • the driving circuit is a high-side transistor driver.
  • the driving voltage of the driving circuit is in the range of 30-60v.
  • the present invention also provides a method for detecting the driving current of the laser radar transmitter circuit, including:
  • S101 Apply a drive voltage to at least one laser through a drive circuit, so that the at least one laser emits light;
  • S102 Divide the driving voltage through a voltage dividing unit to output a voltage-divided signal
  • S103 Using the sampling unit, according to the system clock signal of the transmitter circuit, sample the voltage division signal output by the voltage dividing unit to obtain a corresponding sampling value.
  • the detection method further includes:
  • the sampling value output by the sampling unit is received by the signal processing unit, and the driving current on the at least one laser is determined.
  • the detection method further includes:
  • the change speed of the voltage dividing signal output from the voltage dividing part is slowed down.
  • the detection method further includes:
  • the gain unit coupled between the low-pass filtering unit and the input end of the sampling unit, the voltage amplitude of the voltage division signal output from the voltage dividing unit is restored.
  • the detection method further includes:
  • the pulse period and/or the pulse width of the system clock signal are adjusted by the clock adjustment part, so as to output the sampling clock signal to the sampling unit.
  • the clock adjustment section comprises a period expansion unit
  • the detection method also includes:
  • the system clock signal is received by the period extension unit, and the pulse period of the system clock signal is extended to output an extended intermediate clock signal.
  • the clock adjustment unit further includes a pulse width expansion unit
  • the detection method further includes:
  • the system clock signal and the intermediate clock signal are received by the pulse width expansion unit, and the pulse width of the intermediate clock signal is expanded to generate the sampling clock signal.
  • the preferred embodiment of the present invention provides a transmitter circuit of a laser radar, the transmitter circuit can detect the driving current of the high voltage side at the low voltage side, the circuit implementation cost is low, no circuit elements in the high voltage domain are required, and the cost is saved.
  • the circuit area is improved, the working speed of the circuit is improved, and the high-speed detection of current pulses can be realized through the medium and low-speed analog-to-digital converter, which solves the problems that the current pulses are difficult to maintain and difficult to measure synchronously.
  • the present invention also provides a detection laser radar emission The method of driving current of the terminal circuit.
  • Fig. 1 schematically shows a transmitter circuit according to a preferred embodiment of the present invention
  • FIG. 2 schematically shows a transmitter circuit according to a preferred embodiment of the present invention
  • FIG. 3 schematically shows a transmitter circuit according to a preferred embodiment of the present invention
  • Fig. 4 shows the output waveform timing diagram of each node of the transmitter circuit shown in Fig. 3;
  • FIG. 5 schematically shows a transmitter circuit according to a preferred embodiment of the present invention
  • FIG. 6 schematically shows a period expansion unit in a transmitter circuit according to a preferred embodiment of the present invention
  • FIG. 7 schematically shows a pulse width expansion unit in a transmitter circuit according to a preferred embodiment of the present invention
  • Fig. 8 shows the output waveform timing diagram of each node in the cycle expansion unit and the pulse width expansion unit in the transmitter circuit according to a preferred embodiment of the present invention
  • Fig. 9 shows the output waveform timing diagram of each node of the transmitter circuit shown in Fig. 6;
  • FIG. 10 shows a method for detecting the output drive current of the transmitter circuit according to a preferred embodiment of the present invention.
  • the terms “installed”, “connected” and “connected” should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection: it can be a mechanical connection or an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • installed should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection Connection, or integral connection: it can be a mechanical connection or an electrical connection or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two elements or the interaction of two elements relation.
  • a first feature "on” or “under” a second feature may include the first and second features in direct contact, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and diagonally above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature “below”, “below” and “beneath” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature has a lower level than the second feature.
  • the present invention provides a circuit suitable for automatic detection of high-voltage output current inside a chip of a laser radar transmitting system.
  • the principle of the circuit structure is based on the following formula:
  • the output current can be equivalently measured by measuring ⁇ V under the premise of controlling ⁇ t unchanged (determined according to the system clock signal). Based on the above detection principle, the present invention provides a circuit structure and a measurement method for determining a high-voltage output current based on the detection of a voltage change on a high-voltage capacitor.
  • the present invention provides a transmitter circuit 10 of a laser radar, including: a drive circuit 11 and a detection circuit 12 .
  • the driving circuit 11 is used to drive at least one laser (a laser 13 is schematically shown in the figure, in practical applications, the driving circuit 11 may be connected with multiple lasers, and the multiple lasers include vertical cavity surface emitting lasers (VCSELs). ), one or more of an edge-emitting laser (EEL), but not limited to the case shown in FIG. 1 ) to apply a driving voltage V HVDD to cause at least one laser 13 to emit light.
  • VCSELs vertical cavity surface emitting lasers
  • EEL edge-emitting laser
  • the detection circuit 12 includes a voltage divider 121 and a sampling unit 122 for detecting the driving current when at least one laser 13 emits light.
  • the voltage dividing unit 121 is configured to divide the driving voltage V HVDD to output the divided voltage signal to the sampling unit 122 .
  • the sampling unit 122 is configured to sample the voltage-divided signal output from the voltage-dividing part 121 according to the system clock signal CLK of the transmitter circuit 10 to obtain a corresponding sampling value.
  • the driving circuit 11 in the transmitter circuit 10 includes a voltage source 111 and a switching device 112 , one end of at least one laser 13 is connected to the voltage source 111 , and the other end is connected to the switch
  • the device 112 forms a light-emitting current loop
  • the switching device 112 controls the on and off of the light-emitting current loop according to the system clock signal CLK
  • the voltage source 111 is grounded through the first capacitor 113 .
  • the magnitude of the driving current output by the driving circuit terminal can be calculated according to the change value of the voltage on the first capacitor 113 .
  • the voltage dividing part 121 in the detection circuit 12 includes: a first voltage dividing capacitor 1211 and a second voltage dividing capacitor 1212 connected in series with the voltage source 111 .
  • the first end of the first voltage dividing capacitor 1211 is coupled to the voltage source 111
  • the second end of the first voltage dividing capacitor 1211 is coupled to the first end of the second voltage dividing capacitor 1212 .
  • the first end of the second voltage dividing capacitor 1212 is coupled to the second end of the first voltage dividing capacitor 1211 , and the second end of the second voltage dividing capacitor 1212 is grounded.
  • the switching device 112 When the system clock signal CLK is used as a trigger signal, the switching device 112 is turned on, that is, the driving transistor is turned on. At this time, the voltage source 111 applies the driving voltage V HVDD to at least one laser 13 to generate a voltage drop.
  • the first voltage dividing capacitor 1211 and the second voltage dividing capacitor 1212 are used to divide the voltage, and the change of V HVDD is coupled to the detection circuit 12 .
  • the sampling unit 122 includes an analog-to-digital converter.
  • ⁇ t is determined based on the system clock signal CLK, and the output voltage between the first voltage dividing capacitor 1211 and the second voltage dividing capacitor 1212 is read out. divide the voltage signal, and then determine the output current I of the drive circuit terminal.
  • the pulse width of the system clock signal CLK is very narrow, the driving voltage V HVDD on at least one laser 13 changes rapidly, and direct detection of this signal will impose strict requirements on the analog-to-digital converter.
  • the detection circuit 12 in the transmitter circuit 10 further includes a signal processing unit 123 .
  • the signal processing unit 123 is coupled to the output end of the sampling unit 122, and is used for determining the driving current of the at least one laser 13 when emitting light according to the sampling value output by the sampling unit 122.
  • the preferred embodiment of the present invention realizes the function of automatically detecting the output current of the drive circuit terminal, and the information of the chip output current value can be obtained by reading the output code value of the sampling unit 122 .
  • the full scale of the detection circuit 12 is 20A, and a 10-bit analog-to-digital converter is used as the sampling unit 122, when the current is 0, the output code value is 0; when the current is 20A, the output code value is 1023; when the current is 10A, the output code value is 0.
  • the output code value is 511; when the current is 5A, the output code value is 255; quantizing the current from 0 to 20A linearly, a total of 1024 quantization values are obtained.
  • the detection circuit 12 further includes a low-pass filter unit 124 , which is coupled between the voltage dividing unit 121 and the input end of the sampling unit 122 to slow down the voltage dividing unit 121 The speed of change of the voltage divider signal output on.
  • the low-pass filtering unit 124 includes: a first resistor 1241 , a second resistor 1242 , a second capacitor 1243 and a DC source 1244 .
  • the first end of the first resistor 1241 is coupled to the second end of the first voltage dividing capacitor 1211
  • the second end of the first resistor 1241 is coupled to the input end of the sampling unit 122 .
  • the first end of the second resistor 1242 is coupled to the second end of the first resistor 1241 , and the second end of the second resistor 1242 is coupled to the DC source 1244 .
  • the first end of the second capacitor 1243 is coupled to the input end of the sampling unit 122, and the second end of the second capacitor 1243 is grounded.
  • the low-pass filtering unit 124 is added after the voltage dividing part 121 performs voltage dividing coupling, so as to slow down the signal change speed and facilitate the sampling by the sampling unit 122 .
  • the low-pass filter unit 124 is realized by a first resistor 1241, a second resistor 1242, a second voltage dividing capacitor 1212, and a second capacitor 1243.
  • the second end of the second resistor 1242 is connected to a DC source 1244, and the DC source 1244 provides a fixed voltage , which is usually the upper limit of the reference voltage of the sampling unit 122 . Its function is to fix the DC point of the sampling voltage Vo corresponding to the sampling unit 122 , and Vo usually varies between the upper and lower limits of the reference voltage of the sampling unit 122 .
  • the variation range of Vo is from 3.2V to 1.6V
  • the quantization range of the sampling unit 122 is 1.6V V to 3.2V
  • the second resistor 1242 is used to fix the DC point of the sampling network as the upper limit of the reference voltage of the sampling unit, so as to effectively utilize the quantization range of the sampling unit.
  • the detection circuit 12 further includes a gain unit 125 , which is coupled between the low-pass filter unit 124 and the input end of the sampling unit 122 and is used to restore the voltage divider 121 The voltage amplitude of the output voltage divider signal. Low-pass filtering will cause the attenuation of signal peaks. After low-pass filtering, a gain stage is introduced to restore the signal amplitude, and the output of the gain stage is sent to the analog-to-digital converter to be quantized.
  • the current of 20A corresponds to a maximum change of 2.5V in V HVDD , and then by adjusting the values of the first voltage dividing capacitor 1211 , the second voltage dividing capacitor 1212 , the second capacitor 1243 , the first resistor 1241 and the second resistor 1242 As well as the gain of the gain unit 125, it is ensured that the gain of V HVDD to the input end of the sampling unit 122 is (1.6-3.2)/(37.5-40), which can satisfy the sampling unit corresponding to the full scale of 20A.
  • the sampling unit 122 when the chip itself has a suitable system clock (eg, the pulse width is 100ns and the period is 1 ⁇ s), the sampling unit 122 can be triggered to directly perform sampling according to the system clock signal CLK .
  • the sampling unit 122 based on the high-speed analog-to-digital converter uses the system clock signal CLK as the sampling clock signal CLK_ADC to directly sample the voltage-divided signal output from the voltage-dividing part 121.
  • the embodiment shown in FIG. 3 saves the work of adjusting the period and pulse width of the system clock signal, which is more conducive to the alignment of the sampling clock signal and the system clock signal, and the internal components of the circuit are simple and easy to integrate.
  • the output waveform of each node of the preferred embodiment shown in FIG. 3 is shown in FIG. 4 , at the moment when the switching device 112 is turned on, the voltage V HVDD on at least one laser 13 drops, and then the first capacitor 113 is charged to rise again, and the pulse Vo For the sampling voltage corresponding to the sampling unit 122, the relationship between Vo and V HVDD is determined by the above formula (3).
  • the low-pass filtering unit 124 slows down the speed of change of Vo relative to the voltage on the at least one laser 13 .
  • the sampling clock signal CLK_ADC in this embodiment is the system clock signal CLK. As shown in FIG.
  • the system clock signal CLK has an appropriate pulse width (100 ns) and period (1 ⁇ s), and the sampling unit 122 can be triggered to directly perform sampling according to the system clock signal CLK.
  • DOUT is the waveform obtained by sampling the peak voltage of the sampling voltage Vo by the sampling unit 122 according to the triggering of the system clock signal CLK.
  • the variation value of the voltage V HVDD on at least one laser 13 can be inversely deduced from the peak variation value of Vo, and according to the above Formulas (1) and (2) calculate the driving current output by the transmitter circuit 10 .
  • the detection circuit 12 in the transmitter circuit 10 further includes a clock adjustment part 126 .
  • the clock adjustment section 126 is configured to adjust the pulse period and/or the pulse width of the system clock signal CLK to output the sampling clock signal CLK_ADC to the sampling unit 122 .
  • the sampling unit 122 samples the voltage-divided signal output by the voltage-dividing unit 121 according to the sampling clock signal CLK_ADC corresponding to the system clock signal CLK.
  • the clock adjustment part 126 includes a period expansion unit 127 configured to receive the system clock signal CLK and expand the signal period of the system clock signal CLK to output the expanded Intermediate clock signal CLK1.
  • the period expansion unit 127 is composed of a monostable circuit.
  • the monostable circuit includes: a first D flip-flop 1271, which is triggered by the system clock signal CLK, the input terminal is connected to a high level, and the output terminal outputs a middle clock signal CLK1.
  • the input terminal of the first inverter 1272 is coupled to the inverting output terminal of the first D flip-flop 1271 .
  • the first terminal of the third capacitor 1273 is coupled to the output terminal of the first inverter 1272, and the second terminal is grounded.
  • the input terminal of the second inverter 1274 is coupled to the first terminal of the third capacitor 1273 , and the output terminal is coupled to the reset terminal of the first D flip-flop 1271 .
  • the input terminal (D) of the first D flip-flop 1271 is connected to a high level (1), triggered by the system clock signal CLK, and the reverse output terminal (QN) is shifted and output low
  • the level (0) after passing through two inverters (the first inverter 1272 and the second inverter 1274), outputs a low level (0) to the reset terminal (RST).
  • the reset terminal (RST) triggers a higher priority than the input terminal (D)
  • the D flip-flop is an RST/N trigger, that is, when a low level (0) is output to the reset terminal (RST) , the reverse output terminal (QN) outputs a high level (1).
  • the reverse output terminal (QN) When the second inverter 1274 outputs a low level (0) to the reset terminal (RST) once, the reverse output terminal (QN) outputs a high level (1), and keeps it for a period of time until the next clock cycle comes ( The next time the system clock signal CLK is triggered), the inverted output terminal (QN) shifts to output a low level (0).
  • the two inverters (the first inverter 1272 and the second inverter 1274)
  • the inverter 1274 outputs a low level (0), that is, outputs a low level (0) to the reset terminal (RST), and the reverse output terminal (QN) outputs a high level (1) at this time, and the above process is repeated.
  • the monostable circuit not only lengthens the period of the system clock signal CLK to obtain an intermediate clock signal CLK1 whose period is longer than that of the system clock signal CLK, but also aligns each change of the intermediate clock signal CLK1 with the change of the system clock signal CLK , so as to obtain a clock signal with an extended period corresponding to the system clock signal CLK.
  • the corresponding timing diagram is shown in FIG. 8. It can be seen that the reverse output terminal (QN) of the first D flip-flop 1271 outputs the intermediate clock signal CLK1, and the QN output high level (1) is determined by the output of the first D flip-flop 1271.
  • the reset terminal (RST/N) is triggered, the QN output low level (0) is triggered by the next system clock signal CLK, and the cycle length of the intermediate clock signal CLK1 output by QN is determined by the charging time at point A, that is, the cycle extension
  • the cycle extension length of the unit 127 for the system clock signal CLK is determined by the parameters of the third capacitor 1273 in the monostable circuit.
  • the clock adjustment part 126 further includes a pulse width expansion unit 128 .
  • the pulse width expansion unit 128 is configured to generate the sampling clock signal CLK_ADC according to the system clock signal CLK and the intermediate clock signal CLK1.
  • the pulse width of the sampling clock signal CLK_ADC is greater than the pulse width of the system clock signal CLK, and the period of the sampling clock signal CLK_ADC is the same as the period of the intermediate clock signal CLK1.
  • the pulse width expansion unit 127 includes: a second D flip-flop 1281 , which is triggered by the inverse signal of the system clock signal CLK, the input terminal is connected to a high level, and the reset terminal is connected to the inverse of the first D flip-flop 1271 . coupled to the output.
  • the two input terminals of the NOR gate 1282 are respectively coupled to the forward output terminal of the second D flip-flop 1281 and the reverse signal of the system clock signal CLK.
  • the input terminal of the third inverter 1283 is coupled to the output terminal of the NOR gate 1282 .
  • the first end of the fourth capacitor 1284 is coupled to the output end of the third inverter 1283, and the second end is grounded.
  • the input terminal of the fourth inverter 1285 is coupled to the first terminal of the fourth capacitor 1284 , and the second terminal is used as the output terminal of the pulse width expansion unit 128 to output the sampling clock signal CLK_ADC.
  • the inverse signal of the system clock signal CLK and the output (Q) of the second D flip-flop 1281 are respectively input to the two input terminals of the NOR gate 1282. Since the input terminal of the second D flip-flop 1281 ( D) Connect to a high level, in the case that the trigger signal is not output to the reset terminal (RST) of the second D flip-flop 1281 (the D flip-flop is RST triggered, that is, triggered when a high level is output to the reset terminal), the second The output terminal (Q) of the D flip-flop 1281 continues to output a high level (1), and the NOR gate 1282 continues to output a low level (0).
  • the reset terminal (RST) of the second D flip-flop 1281 is coupled to the output terminal (QN) of the first D flip-flop 1271 in the monostable circuit.
  • the output of the NOR gate 1282 is inverted, that is, the NOR gate 1282 outputs a high level (1), and passes through two inverters (the third The inverter 1283 and the fourth inverter 1285) output the high level (1) as the system clock signal CLK_ADC, and keep it for a period of time.
  • the output of the NOR gate 1282 becomes a low level (0) again.
  • the two inverters (the third inverter The node between 1283 and the fourth inverter 1285), as shown in point B in Figure 7, changes from low level (0) to high level (1) and needs to be recharged, when point B is charged to high level
  • the fourth inverter 1285 outputs a low level (0), that is, the output sampling clock signal CLK_ADC becomes a low level (0).
  • the pulse width expansion unit 128 outputs the sampling clock signal CLK_ADC, the sampling clock signal CLK_ADC is expanded compared with the pulse width of the system clock signal CLK, and the period of the sampling clock signal CLK_ADC is the same as the period of the intermediate clock signal CLK1, even if the system obtains A sampling clock signal CLK_ADC with an elongated period and a widened pulse width is obtained, and each change of the sampling clock signal CLK_ADC is aligned with the change of the system clock signal CLK.
  • the corresponding timing diagram is shown in Figure 8. It can be seen that the rising edge of the sampling clock signal CLK_ADC is triggered by the intermediate clock signal CLK1 and the system clock signal CLK aligned with it, and the pulse width of the sampling clock signal CLK_ADC is determined by the charging time at point B. It is determined, that is, the pulse width extension length of the pulse width extension unit 128 for the system clock signal CLK is determined by the parameters of the fourth capacitor 1274 .
  • the time of the clock cycle is limited by the conversion speed of the sampling unit (preferably an analog-to-digital converter), and is limited by technology, power consumption, and area, taking a 10-bit analog-to-digital converter as an example, its conversion speed is around 1M, so It is necessary to control the input clock period of the analog-to-digital converter to be no less than 1 ⁇ s. Extending the pulse width is also to reduce the burden of the analog-to-digital converter. If the pulse width is too narrow, the sampling network bandwidth of the analog-to-digital converter is required to be large, which is difficult to achieve.
  • the sampling unit preferably an analog-to-digital converter, requires a sampling clock to operate, and requires that the sampling moment be aligned with the peak value of the sampled signal.
  • the ADC sampling moment is triggered by the falling edge of the sampling clock signal CLK_ADC, that is, in this embodiment, the falling edge of the sampling clock signal CLK_ADC needs to be aligned with the peak value of Vo.
  • the pulse width of the sampling clock signal CLK_ADC is determined by the charging time at point B. Therefore, by adjusting the performance parameters of the fourth capacitor 1274 used at point B, the falling edge of the sampling clock signal CLK_ADC can be adjusted to the sampling voltage Vo. corresponds to the peak point of . In order to obtain as accurate sampling information as possible.
  • the preferred embodiment of the present invention utilizes a period expansion unit (including a monostable circuit) and a pulse width expansion unit (including a shaping circuit) to convert the input system clock signal into an analog signal.
  • the clock signal required by the digital converter.
  • the monostable circuit converts a signal with a repetition period of 200ns (or shorter) into a signal with a repetition period of 1 ⁇ s, which can also be regarded as eliminating repetitive pulses within 1 ⁇ s.
  • a shaping circuit is used to convert the pulse width from 5ns to 100ns. In this way, a clock signal with a period of 1 ⁇ s and a duty cycle of 10% is fed into the analog-to-digital converter.
  • the output of the analog-to-digital converter is latched by the register, so it will not change in one cycle.
  • the waveform DOUT obtained by sampling the peak voltage of the sampling voltage Vo will be refreshed. value. Assuming the same change of V HVDD in the previous cycle, the sampling waveform DOUT always outputs the same value, that is, its waveform is a straight line as shown in FIG. 9 .
  • the period of the system clock is elongated and the pulse width is widened by adopting a period expansion unit including a monostable circuit and a pulse width expansion unit including a shaping circuit, so as to improve the performance of high-speed analog-to-digital converters using medium and low-speed analog-to-digital converters. It is possible to sample the changing driving voltage, thereby solving the technical problems that the pulse of the driving current is difficult to maintain and synchronously measure.
  • the drive circuit 11 in the transmitter circuit 10 is driven by a high-side transistor, and the drive voltage of the drive circuit 11 is in the range of 30-60v.
  • the present invention further provides a method 100 for detecting the driving current of a lidar transmitter circuit, including:
  • step S101 a drive voltage is applied to at least one laser through a drive circuit, so that the at least one laser emits light;
  • step S102 the driving voltage is divided by the voltage dividing unit to output a divided voltage signal
  • step S103 the sampling unit samples the voltage-divided signal output by the voltage-dividing part according to the system clock signal of the transmitting-end circuit to obtain a corresponding sampling value.
  • the detection method 100 further includes:
  • the sampling value output by the sampling unit is received by the signal processing unit, and the driving current on the at least one laser is determined.
  • the detection method 100 further includes:
  • the change speed of the voltage dividing signal output from the voltage dividing part is slowed down.
  • the detection method 100 further includes:
  • the gain unit coupled between the low-pass filtering unit and the input end of the sampling unit, the voltage amplitude of the voltage division signal output from the voltage dividing unit is restored.
  • the detection method 100 further includes:
  • the pulse period and/or the pulse width of the system clock signal are adjusted by the clock adjustment part, so as to output the sampling clock signal to the sampling unit.
  • the clock adjustment unit includes a period extension unit
  • the detection method 100 further includes:
  • the system clock signal is received by the period extension unit, and the pulse period of the system clock signal is extended to output an extended intermediate clock signal.
  • the clock adjustment unit further includes a pulse width expansion unit
  • the detection method 100 further includes:
  • the system clock signal and the intermediate clock signal are received by the pulse width expansion unit, and the pulse width of the intermediate clock signal is expanded to generate the sampling clock signal.
  • the preferred embodiment of the present invention provides a transmitter circuit of a laser radar, the transmitter circuit can detect the driving current of the high voltage side at the low voltage side, the circuit implementation cost is low, no circuit elements in the high voltage domain are required, and the cost is saved.
  • the circuit area is increased, the working speed of the circuit is improved, and the high-speed detection of current pulses can be realized through the medium and low-speed analog-to-digital converter, which solves the problems that the current pulses are difficult to maintain and synchronously measure.
  • the present invention also provides a detection laser radar emission The method of driving current of the terminal circuit.

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Abstract

一种用于激光雷达的发射端电路及检测发射端电路驱动电流的方法，发射端电路包括：驱动电路（11），用于向至少一个激光器（13）施加驱动电压，以使至少一个激光器（13）发光；检测电路（12），包括分压部（121）和采样单元（122），用于检测至少一个激光器（13）发光时的驱动电流，其中：分压部（121）配置成对驱动电压进行分压，以向采样单元（122）输出分压信号；采样单元（122）配置成可根据发射端电路的***时钟信号，对分压部（121）上输出的分压信号进行采样，以获得相应的采样值。检测发射端电路驱动电流的方法与发射端电路相对应。

Description

激光雷达的发射端电路及检测其驱动电流的方法 技术领域
本发明大致涉及激光雷达技术领域，尤其涉及一种激光雷达的发射端电路。
背景技术
在激光雷达发射***中，发射端依靠高压驱动管为激光器提供电流，使激光器发光。而高压驱动管的阈值电压、迁移率等特性会随着温度、工艺角等因素变化，因此输出电流会存在温漂以及芯片间的不一致的问题。
目前行业内没有有效解决上述输出电流不准问题的办法，一个主要原因是无法直接读取电流，而读取电流比较困难的原因有两点：
一方面，由于动电流是从高压(通常为40V左右)端流出，直接检测的话要求检测电路内部的器件都工作在高压域，检测电路里面的功能元件较多，用高压管实现会浪费较大的面积，同时由于面积大带来的寄生影响使得电路工作速度较慢。
另一方面，由于当前场景下驱动电流是窄脉冲形式的电流信号，而量化窄脉冲信号的峰值有两种办法。第一种是依靠高速模数转换器(ADC)，但高速模数转换器难以实现，此外电流值的变化速率较快，一旦采样时钟有偏差，测量误差将会特别大；第二种是将脉冲峰值展宽，用低速模数转换器来量化，但高压域的峰值保持电路较难实现。
背景技术部分的内容仅仅是公开人所知晓的技术，并不当然代表本领域的现有技术。
发明内容
有鉴于现有技术的至少一个缺陷，本发明提供一种用于激光雷达的发射端电路，包括：
驱动电路，用于向至少一个激光器施加驱动电压，以使所述至少一个激光器发光；
检测电路，包括分压部和采样单元，用于检测所述至少一个激光器发光时的驱动电流，其中：
所述分压部配置成对所述驱动电压进行分压，以向所述采样单元输出分压信号；
所述采样单元配置成可根据所述发射端电路的***时钟信号，对所述分压部上输出的分压信号进行采样，以获得相应的采样值。
根据本发明的一个方面，其中所述驱动电路包括电压源和开关器件，所述至少一个激光器的一端连接到所述电压源，另一端连接到所述开关器件以形成发光电流回路，所述开关器件根据所述***时钟信号控制所述发光电流 回路的导通和断开，所述电压源通过第一电容接地；
其中所述分压部包括：
第一分压电容，所述第一分压电容的第一端与所述电压源耦接；
第二分压电容，所述第二分压电容的第一端与所述第一电容的第二端耦接，所述第二分压电容的第二端接地。
根据本发明的一个方面，其中所述检测电路还包括：
信号处理单元，与所述采样单元的输出端耦接，用于根据所述采样单元输出的采样值，确定所述至少一个激光器发光时的驱动电流。
根据本发明的一个方面，其中所述检测电路还包括低通滤波单元，耦接在所述分压部与所述采样单元的输入端之间，用以减缓所述分压部上输出的分压信号的变化速度。
根据本发明的一个方面，其中所述低通滤波单元包括：
第一电阻，所述第一电阻的第一端与所述第一分压电容的第二端耦接，所述第一电阻的第二端与所述采样单元的输入端耦接；
第二电阻，所述第二电阻的第一端与所述第一电阻的第二端耦接；
第二电容，所述第二电容的第一端与所述采样单元的输入端耦接，所述第二电容的第二端接地；
直流源，所述直流源与所述第二电阻的第二端耦接。
根据本发明的一个方面，其中所述检测电路还包括增益单元，耦接在所述低通滤波单元与所述采样单元的输入端之间，用以还原所述分压部上输出的分压信号的电压幅度。
根据本发明的一个方面，其中所述检测电路还包括：
时钟调节部，配置成可调节所述***时钟信号的脉冲周期和/或脉冲宽度，以向所述采样单元输出采样时钟信号；
其中，所述采样单元根据与所述***时钟信号对应的采样时钟信号，对所述分压部上输出的分压信号进行采样。
根据本发明的一个方面，其中所述时钟调节部包括周期扩展单元，配置成可接收所述***时钟信号，并扩展所述***时钟信号的信号周期，以输出扩展后的中间时钟信号。
根据本发明的一个方面，其中所述周期扩展单元采用单稳态电路构成，所述单稳态电路包括：
第一D触发器，由所述***时钟信号触发，输入端接高电平，反向输出端输出中间时钟信号；
第一反相器，输入端与所述第一D触发器的反向输出端耦接；
第三电容，第一端与所述第一反相器的输出端耦接，第二端接地；
第二反相器，输入端与所述第三电容的第一端耦接，输出端与所述第一D触发器的复位端耦接。
根据本发明的一个方面，其中所述周期扩展单元对于所述***时钟信号 的周期扩展长度由所述单稳态电路中的第三电容的参数来决定。
根据本发明的一个方面，其中所述时钟调节部还包括脉宽扩展单元，配置成可根据所述***时钟信号以及所述中间时钟信号，来生成采样时钟信号；其中，所述采样时钟信号的脉宽大于所述***时钟信号的脉宽，并且，所述采样时钟信号的周期与所述中间时钟信号的周期相同。
根据本发明的一个方面，其中所述脉宽扩展单元包括：
第二D触发器，由所述***时钟信号的反向信号触发，输入端接高电平，复位端与所述第一D触发器的反向输出端耦接；
或非门，两个输入端分别与所述第二D触发器的正向输出端和所述***时钟信号的反向信号耦接；
第三反相器，输入端与所述或非门的输出端耦接；
第四电容，第一端与所述第三反相器的输出端耦接，第二端接地；
第四反相器，输入端与所述第四电容的第一端耦接，第二端作为所述脉宽扩展单元的输出端输出所述采样时钟信号。
根据本发明的一个方面，其中所述脉宽扩展单元对于所述***时钟信号的脉宽扩展长度由所述第四电容的参数来决定。
根据本发明的一个方面，其中所述采样单元包括模数转换器。
根据本发明的一个方面，其中所述驱动电路为高边管驱动。
根据本发明的一个方面，其中所述驱动电路的驱动电压范围为30-60v。
本发明还提供一种检测激光雷达发射端电路的驱动电流的方法，包括：
S101：通过驱动电路，向至少一个激光器施加驱动电压，以使所述至少一个激光器发光；
S102：通过分压部对所述驱动电压进行分压，以输出分压信号；
S103：通过采样单元，根据所述发射端电路的***时钟信号，对所述分压部上输出的分压信号进行采样，以获得相应的采样值。
根据本发明的一个方面，所述检测方法还包括：
通过信号处理单元接收所述采样单元输出的采样值，并确定所述至少一个激光器上的驱动电流。
根据本发明的一个方面，所述检测方法还包括：
通过耦接在所述分压部与所述采样单元的输入端之间的低通滤波单元，减缓所述分压部上输出的分压信号的变化速度。
根据本发明的一个方面，所述检测方法还包括：
通过耦接在所述低通滤波单元与所述采样单元的输入端之间的增益单元，还原所述分压部上输出的分压信号的电压幅度。
根据本发明的一个方面，所述检测方法还包括：
通过时钟调节部调节所述***时钟信号的脉冲周期和/或脉冲宽度，以向所述采样单元输出采样时钟信号。
根据本发明的一个方面，其中所述时钟调节部包括周期扩展单元，所述 检测方法还包括：
通过所述周期扩展单元接收所述***时钟信号，并扩展所述***时钟信号的脉冲周期，以输出扩展后的中间时钟信号。
根据本发明的一个方面，其中所述时钟调节部还包括脉宽扩展单元，所述检测方法还包括：
通过所述脉宽扩展单元接收所述***时钟信号以及所述中间时钟信号，并扩展所述中间时钟信号的脉冲宽度，以生成所述采样时钟信号。
本发明的优选实施例提供了一种激光雷达的发射端电路，该发射端电路能够实现在低压侧检测高压侧的驱动电流，该电路实现的代价较低，无需高压域的电路元件，节省了电路面积，提高了电路的工作速度，且通过中低速模数转换器即可实现高速检测电流脉冲，解决了电流脉冲难以保持、难以同步测量的问题，本发明还提供了一种检测激光雷达发射端电路的驱动电流的方法。
附图说明
附图用来提供对本发明的进一步理解，并且构成说明书的一部分，与本发明的实施例一起用于解释本发明，并不构成对本发明的限制。在附图中：
图1示意性地示出了根据本发明的一个优选实施例的发射端电路；
图2示意性地示出了根据本发明的一个优选实施例的发射端电路；
图3示意性地示出了根据本发明的一个优选实施例的发射端电路；
图4示出了图3所示的发射端电路各个节点的输出波形时序图；
图5示意性地示出了根据本发明的一个优选实施例的发射端电路；
图6示意性地示出了根据本发明的一个优选实施例的发射端电路中的周期扩展单元；
图7示意性地示出了根据本发明的一个优选实施例的发射端电路中的脉宽扩展单元；
图8示出了根据本发明的一个优选实施例的发射端电路中周期扩展单元、脉宽扩展单元中各个节点的输出波形时序图；
图9示出了图6所示的发射端电路各个节点的输出波形时序图；
图10示出了根据本发明的一个优选实施例的发射端电路输出驱动电流的检测方法。
具体实施方式
在下文中，仅简单地描述了某些示例性实施例。正如本领域技术人员可认识到的那样，在不脱离本发明的精神或范围的情况下，可通过各种不同方式修改所描述的实施例。因此，附图和描述被认为本质上是示例性的而非限制性的。
在本发明的描述中，需要理解的是，术语"中心"、"纵向"、"横向"、"长度"、"宽度"、"厚度"、"上"、"下"、"前"、"后"、"左"、"右"、"竖直"、"水平"、"顶"、"底"、"内"、"外"、"顺时针"、"逆时针"等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。此外，术语"第一"、"第二"仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有"第一"、"第二"的特征可以明示或者隐含地包括一个或者更多个所述特征。在本发明的描述中，"多个"的含义是两个或两个以上，除非另有明确具体的限定。
在本发明的描述中，需要说明的是，除非另有明确的规定和限定，术语"安装"、"相连"、"连接"应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接:可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本发明中的具体含义。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之"上"或之"下"可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征"之上"、"上方"和"上面"包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征"之下"、"下方"和"下面"包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
以下结合附图对本发明的实施例进行说明，应当理解，此处所描述的实施例仅用于说明和解释本发明，并不用于限定本发明。
本发明提供一种适用于激光雷达发射***的芯片内部自动检测高压输出电流的电路，该电路结构的原理基于以下公式：
Q＝C·ΔV＝I·Δt  (1)
则：I＝(C·ΔV)/Δt  (2)
考虑到高压电容是固定的，因此在控制Δt不变的前提下(根据***时钟 信号确定)，测量ΔV即可等效测量输出电流。基于上述检测原理，本发明提供一种基于对高压电容上电压变化的检测来确定高压输出电流的电路结构与测量方法。
如图1所示，根据本发明一个优选实施例，本发明提供一种激光雷达的发射端电路10，包括：驱动电路11和检测电路12。驱动电路11用于向至少一个激光器(图中示意性地示出了一个激光器13，实际应用中，驱动电路11可能与多个激光器相连接，该多个激光器包括垂直腔面发射型激光器(VCSEL)、边发射型激光器(EEL)中的一种或多种，而不仅限于图1中所示的情形)施加驱动电压V HVDD，以使至少一个激光器13发光。检测电路12包括分压部121和采样单元122，用于检测至少一个激光器13发光时的驱动电流。其中，分压部121配置成对驱动电压V HVDD进行分压，以向采样单元122输出分压信号。采样单元122配置成可根据发射端电路10的***时钟信号CLK，对分压部121上输出的分压信号进行采样，以获得相应的采样值。
根据本发明的一个优选实施例，如图1所示，发射端电路10中的驱动电路11包括电压源111和开关器件112，至少一个激光器13的一端连接到电压源111，另一端连接到开关器件112以形成发光电流回路，开关器件112根据***时钟信号CLK控制所述发光电流回路的导通和断开，电压源111通过第一电容113接地。可以根据第一电容113上电压的变化值，计算驱动电路端输出的驱动电流的大小。优选地，检测电路12中的分压部121包括：串联在电压源111上的第一分压电容1211和第二分压电容1212。其中第一分压电容1211的第一端与电压源111耦接，第一分压电容1211的第二端与第二分压电容1212的第一端耦接。第二分压电容1212的第一端与第一分压电容1211的第二端耦接，第二分压电容1212的第二端接地。
***时钟信号CLK作为触发信号(trigger)来临后，开关器件112导通，即驱动管开启，此时电压源111会向至少一个激光器13施加驱动电压V HVDD，从而产生压降。利用第一分压电容1211和第二分压电容1212进行分压，将V HVDD的变化耦合到检测电路12中。
优选地，采样单元122包括模数转换器，根据上文所述的检测原理，基于***时钟信号CLK来确定Δt，并读出第一分压电容1211和第二分压电容1212之间输出的分压信号，进而确定驱动电路端的输出电流I。但由于***时钟信号CLK的脉宽很窄，至少一个激光器13上的驱动电压V HVDD的变化速度很快，直接检测该信号会对模数转换器的要求十分苛刻。
根据本发明的一个优选实施例，发射端电路10中的检测电路12还包括信号处理单元123。信号处理单元123与采样单元122的输出端耦接，用于根据采样单元122输出的采样值，确定至少一个激光器13发光时的驱动电流。
本发明的优选实施例实现了自动检测驱动电路端输出电流的功能，可通过读取采样单元122的输出码值得到芯片输出电流值的信息。假设检测电路12的满量程为20A，采用10bit的模数转换器作为采样单元122，则电流为0 时，输出码值为0；电流为20A时，输出码值为1023；电流为10A时，输出码值为511；电流为5A时，输出码值为255；将0至20A的电流线性的量化，共得到1024个量化值。
根据本发明的一个优选实施例，如图2所示，检测电路12还包括低通滤波单元124，耦接在分压部121与采样单元122的输入端之间，用以减缓分压部121上输出的分压信号的变化速度。低通滤波单元124包括：第一电阻1241、第二电阻1242、第二电容1243和直流源1244。第一电阻1241的第一端与第一分压电容1211的第二端耦接，第一电阻1241的第二端与采样单元122的输入端耦接。第二电阻1242的第一端与第一电阻1241的第二端耦接，第二电阻1242的第二端与直流源1244耦接。第二电容1243的第一端与采样单元122的输入端耦接，第二电容1243的第二端接地。
在分压部121进行分压耦合后加入低通滤波单元124，减缓信号变化速度，便于采样单元122采样。低通滤波单元124由第一电阻1241、第二电阻1242、第二分压电容1212、第二电容1243共同作用实现，第二电阻1242的第二端接直流源1244，直流源1244提供固定电压，通常也是采样单元122的参考电压的上限。其作用在于固定采样单元122对应的采样电压Vo的直流点，Vo通常在采样单元122的参考电压的上下限之间变化。
例如，采样单元122(优选为模数转换器)参考电压的上限为3.2V，下限为1.6V，则Vo的变化范围为从3.2V向下变化至1.6V，采样单元122的量化范围是1.6V至3.2V，而V HVDD的变化可基于公式(1)确定。假定第一电容113的容值C＝40nF，最大测量电流I＝20A，时间t＝5ns，则变化的范围V＝20A*5ns/40nF＝2.5V。这种情况下V HVDD变化区间为40V至37.5V。
因此考虑输入电压只能朝下降方向变化，利用第二电阻1242固定采样网络的直流点为采样单元参考电压的上限，有效利用采样单元的量化范围。可
Figure PCTCN2021104001-appb-000001
根据本发明的一个优选实施例，如图2所示，检测电路12还包括增益单元125，耦接在低通滤波单元124与采样单元122的输入端之间，用以还原分压部121上输出的分压信号的电压幅度。低通滤波会造成信号峰值的衰减，在低通滤波后面引入增益级还原信号幅度，增益级的输出送入模数转换器被量化。
继续基于前述实施例，20A的电流对应V HVDD最大变化2.5V，然后通过调节第一分压电容1211、第二分压电容1212、第二电容1243、第一电阻1241、第二电阻1242的值以及增益单元125的增益，保证V HVDD到采样单元122的输入端的增益是(1.6-3.2)/(37.5-40)，即可以满足采样单元对应到满量程20A。
如图3所示，根据本发明的一个优选实施例，在芯片本身具有合适的***时钟(如脉宽100ns，周期为1μs)的情况下，可以根据***时钟信号CLK触发采样单元122直接进行采样。基于高速模数转换器的采样单元122，利用 ***时钟信号CLK作为采样时钟信号CLK_ADC，对分压部121上输出的分压信号直接进行采样。
图3所示的实施例省去了对***时钟信号的周期和脉宽进行调整的工作，更有利于采样时钟信号与***时钟信号的对齐，电路内部的部件简单，易于集成。
图3所示的优选实施例各个节点的输出波形如图4所示，在开关器件112导通的瞬间，至少一个激光器13上的电压V HVDD下降，再通过第一电容113充电回升，脉冲Vo为采样单元122对应的采样电压，Vo与V HVDD的关系由上述公式(3)确定。通过低通滤波单元124，减缓了Vo相对于至少一个激光器13上电压的变化速度，本实施例中的采样时钟信号CLK_ADC即为***时钟信号CLK。如图4中所示，该***时钟信号CLK具有合适的脉宽(100ns)和周期(1μs)，可以根据***时钟信号CLK触发采样单元122直接进行采样。DOUT为采样单元122根据***时钟信号CLK的触发对采样电压Vo的峰值电压进行采样得到的波形，可以通过Vo的峰值变化值反推出至少一个激光器13上的电压V HVDD的变化值，并根据上述公式(1)、(2)计算发射端电路10输出的驱动电流。
然而，通常情况下，激光雷达发射***的芯片不会提供刚好满足要求的时钟，因此需要在分压部121进行分压耦合、低通滤波单元124进行低通滤波后，加入时钟调节部。如图5所示，根据本发明的一个优选实施例，发射端电路10中的检测电路12还包括时钟调节部126。时钟调节部126配置成可调节***时钟信号CLK的脉冲周期和/或脉冲宽度，以向采样单元122输出采样时钟信号CLK_ADC。其中，采样单元122根据与***时钟信号CLK对应的采样时钟信号CLK_ADC，对分压部121上输出的分压信号进行采样。
根据本发明的一个优选实施例，如图5所示，其中时钟调节部126包括周期扩展单元127，配置成可接收***时钟信号CLK，并扩展***时钟信号CLK的信号周期，以输出扩展后的中间时钟信号CLK1。周期扩展单元127采用单稳态电路构成，如图6所示，所述单稳态电路包括：第一D触发器1271，由***时钟信号CLK触发，输入端接高电平，输出端输出中间时钟信号CLK1。第一反相器1272，输入端与第一D触发器1271的反向输出端耦接。第三电容1273，第一端与第一反相器1272的输出端耦接，第二端接地。第二反相器1274，输入端与第三电容1273的第一端耦接，输出端与第一D触发器1271的复位端耦接。
如图6所示的单稳态电路中，第一D触发器1271的输入端(D)接高电平(1)，由***时钟信号CLK触发，反向输出端(QN)移位输出低电平(0)，经过两个反相器(第一反相器1272、第二反相器1274)后，向复位端(RST)输出低电平(0)。在D触发器中，复位端(RST)触发的优先级高于输入端(D)，且该D触发器为RST/N触发，即：当向复位端(RST)输出低电平(0)时，反向输出端(QN)输出高电平(1)。当第二反相器1274向复位端(RST)输 出一次低电平(0)时，反向输出端(QN)输出高电平(1)，并保持一段时间，直到下一个时钟周期到来(下一次***时钟信号CLK触发)时，反向输出端(QN)移位输出低电平(0)，此时，两个反相器(第一反相器1272、第二反相器1274)之间的节点，如图6中所示的A点，从低电平(0)变为高电平(1)需要重新充电，当A点充电到高电平(1)时，通过第二反相器1274输出低电平(0)，即向复位端(RST)输出低电平(0)，反向输出端(QN)此时输出高电平(1)，重复上述过程。该单稳态电路既拉长了***时钟信号CLK的周期，获得周期相比于***时钟信号CLK长的中间时钟信号CLK1，又使中间时钟信号CLK1的每一次变化与***时钟信号CLK的变化对齐，从而获得与***时钟信号CLK相对应的周期展宽的时钟信号。
对应的时序图如图8所示，可以看出，第一D触发器1271的反向输出端(QN)输出中间时钟信号CLK1，QN输出高电平(1)由第一D触发器1271的复位端(RST/N)触发，QN输出低电平(0)由下一次***时钟信号CLK触发，QN输出的中间时钟信号CLK1的周期长度由A点的充电时间决定，也就是说，周期扩展单元127对于***时钟信号CLK的周期扩展长度由所述单稳态电路中的第三电容1273的参数来决定。
根据本发明的一个优选实施例，如图5所示，其中时钟调节部126还包括脉宽扩展单元128。脉宽扩展单元128配置成可根据***时钟信号CLK以及中间时钟信号CLK1，来生成采样时钟信号CLK_ADC。其中，采样时钟信号CLK_ADC的脉宽大于***时钟信号CLK的脉宽，并且，采样时钟信号CLK_ADC的周期与中间时钟信号CLK1的周期相同。如图7所示，其中脉宽扩展单元127包括：第二D触发器1281，由***时钟信号CLK的反向信号触发，输入端接高电平，复位端与第一D触发器1271的反向输出端耦接。或非门1282，两个输入端分别与第二D触发器1281的正向输出端和***时钟信号CLK的反向信号耦接。第三反相器1283，输入端与或非门1282的输出端耦接。第四电容1284，第一端与第三反相器1283的输出端耦接，第二端接地。第四反相器1285，输入端与第四电容1284的第一端耦接，第二端作为脉宽扩展单元128的输出端输出采样时钟信号CLK_ADC。
如图7所示，或非门1282的两个输入端分别输入***时钟信号CLK的反向信号，以及第二D触发器1281的输出(Q)，由于第二D触发器1281的输入端(D)接高电平，在没有向第二D触发器1281的复位端(RST)输出触发信号(该D触发器为RST触发，即向复位端输出高电平时触发)的情况下，第二D触发器1281的输出端(Q)持续输出高电平(1)，则或非门1282持续输出低电平(0)。第二D触发器1281的复位端(RST)与单稳态电路中的第一D触发器1271输出端(QN)耦接，当第一D触发器1271输出的中间时钟信号CLK1与***时钟信号CLK的反向信号同时输出低电平(0)时，或非门1282的输出发生反转，即或非门1282输出高电平(1)，并通过两个反相器(第三反相器1283、第四反相器1285)将高电平(1)输出，作为***时钟信号 CLK_ADC，并保持一段时间。当***时钟信号CLK的反向信号重新变为高电平(1)时，或非门1282的输出重新变为低电平(0)，此时，两个反相器(第三反相器1283、第四反相器1285)之间的节点，如图7中所示的B点，从低电平(0)变为高电平(1)需要重新充电，当B点充电到高电平(1)时，通过第四反相器1285输出低电平(0)，即将输出的采样时钟信号CLK_ADC变为低电平(0)。该脉宽扩展单元128输出采样时钟信号CLK_ADC，采样时钟信号CLK_ADC相较于***时钟信号CLK的脉宽得到展宽，且该采样时钟信号CLK_ADC的周期与中间时钟信号CLK1的周期相同，既使***获得了周期拉长、脉宽展宽的采样时钟信号CLK_ADC，且该采样时钟信号CLK_ADC的每一次变化与***时钟信号CLK的变化对齐。
对应的时序图如图8所示，可以看出，采样时钟信号CLK_ADC的上升沿由中间时钟信号CLK1和与之对齐的***时钟信号CLK触发，采样时钟信号CLK_ADC的脉宽由B点的充电时间决定，也就是说，脉宽扩展单元128对于***时钟信号CLK的脉宽扩展长度由第四电容1274的参数来决定。
由于时钟周期的时间受限于采样单元(优选为模数转换器)的转换速度，受工艺、功耗、面积的限制，以10bit的模数转换器为例，其转换速度在1M附近，因此需要把模数转换器的输入时钟周期控制在不低于1μs。扩展脉冲宽度同样是为了降低模数转换器的负担，若脉冲宽度太窄，要求模数转换器的采样网络带宽很大，难以实现。
如图9所示，采样单元，优选地为模数转换器工作需要采样时钟，且要求采样时刻与被采样信号的峰值对齐。在根据本方案的一个实施例中，ADC采样时刻由采样时钟信号CLK_ADC的下降沿触发，亦即，该实施例中，需要采样时钟信号CLK_ADC的下降沿与Vo的峰值对齐。如前所述，采样时钟信号CLK_ADC的脉宽由B点的充电时间决定，因此，通过调节B点处所采用的第四电容1274的性能参数，可使得采样时钟信号CLK_ADC的下降沿与采样电压Vo的峰值点对应。从而获得尽可能准确的采样信息。
在激光雷达发射***的芯片没有全局时钟的情况下，本发明的优选实施例利用周期扩展单元(包括单稳态电路)和脉宽扩展单元(包括整形电路)，将输入***时钟信号转化成模数转换器所需的时钟信号。单稳态电路把重复周期为200ns(或更短)的信号转换成重复周期为1μs的信号，也可看做消除1μs内的重复脉冲。整形电路用于将脉冲宽度从5ns转化成100ns。这样送入模数转换器的为周期1μs，占空比为10％的时钟信号。此外模数转换器的输出是被寄存器锁存的，所以在一个周期内是不会变化的，每次经采样时钟信号CLK_ADC触发之后会刷新对采样电压Vo的峰值电压进行采样得到的波形DOUT的值。假定前一个周期内V HVDD的变化相同，则采样波形DOUT一直输出同一个值，亦即其波形为如图9所示的一直线。本发明的优选实施例通过采用包括单稳态电路的周期扩展单元和包括整形电路的脉宽扩展单元，将***时钟的周期拉长、脉宽展宽，从而为采用中低速模数转换器对高速变化的驱动 电压进行采样成为可能，进而解决了驱动电流的脉冲难以保持、难以同步测量的技术问题。
根据本发明的一个优选实施例，发射端电路10中的驱动电路11为高边管驱动，驱动电路11的驱动电压范围为30-60v。
根据本发明的一个优选实施例，如图10所示，本发明还提供一种检测激光雷达发射端电路的驱动电流的方法100，包括：
在步骤S101中，通过驱动电路，向至少一个激光器施加驱动电压，以使所述至少一个激光器发光；
在步骤S102中，通过分压部对所述驱动电压进行分压，以输出分压信号；
在步骤S103中，通过采样单元，根据所述发射端电路的***时钟信号，对所述分压部上输出的分压信号进行采样，以获得相应的采样值。
根据本发明的一个优选实施例，检测方法100还包括：
通过信号处理单元接收所述采样单元输出的采样值，并确定所述至少一个激光器上的驱动电流。
根据本发明的一个优选实施例，检测方法100还包括：
通过耦接在所述分压部与所述采样单元的输入端之间的低通滤波单元，减缓所述分压部上输出的分压信号的变化速度。
根据本发明的一个优选实施例，检测方法100还包括：
通过耦接在所述低通滤波单元与所述采样单元的输入端之间的增益单元，还原所述分压部上输出的分压信号的电压幅度。
根据本发明的一个优选实施例，检测方法100还包括：
通过时钟调节部调节所述***时钟信号的脉冲周期和/或脉冲宽度，以向所述采样单元输出采样时钟信号。
根据本发明的一个优选实施例，其中所述时钟调节部包括周期扩展单元，所述检测方法100还包括：
通过所述周期扩展单元接收所述***时钟信号，并扩展所述***时钟信号的脉冲周期，以输出扩展后的中间时钟信号。
根据本发明的一个优选实施例，其中所述时钟调节部还包括脉宽扩展单元，所述检测方法100还包括：
通过所述脉宽扩展单元接收所述***时钟信号以及所述中间时钟信号，并扩展所述中间时钟信号的脉冲宽度，以生成所述采样时钟信号。
本发明的优选实施例提供了一种激光雷达的发射端电路，该发射端电路能够实现在低压侧检测高压侧的驱动电流，该电路实现的代价较低，无需高压域的电路元件，节省了电路面积，提高了电路的工作速度，且通过中低速模数转换器即可实现高速检测电流脉冲，解决了电流脉冲难以保持、难以同步测量的问题，本发明还提供了一种检测激光雷达发射端电路的驱动电流的方法。
最后应说明的是：以上所述仅为本发明的优选实施例而已，并不用于限制本发明，尽管参照前述实施例对本发明进行了详细的说明，对于本领域的技术人员来说，其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (23)

  1. 一种用于激光雷达的发射端电路，包括：
    驱动电路，用于向至少一个激光器施加驱动电压，以使所述至少一个激光器发光；
    检测电路，包括分压部和采样单元，用于检测所述至少一个激光器发光时的驱动电流，其中：
    所述分压部配置成对所述驱动电压进行分压，以向所述采样单元输出分压信号；
    所述采样单元配置成可根据所述发射端电路的***时钟信号，对所述分压部上输出的分压信号进行采样，以获得相应的采样值。
  2. 如权利要求1所述的发射端电路，其中所述驱动电路包括电压源和开关器件，所述至少一个激光器的一端连接到所述电压源，另一端连接到所述开关器件以形成发光电流回路，所述开关器件根据所述***时钟信号控制所述发光电流回路的导通和断开，所述电压源通过第一电容接地；
    其中所述分压部包括：
    第一分压电容，所述第一分压电容的第一端与所述电压源耦接；
    第二分压电容，所述第二分压电容的第一端与所述第一分压电容的第二端耦接，所述第二分压电容的第二端接地。
  3. 如权利要求1或2所述的发射端电路，其中所述检测电路还包括：
    信号处理单元，与所述采样单元的输出端耦接，用于根据所述采样单元输出的采样值，确定所述至少一个激光器发光时的驱动电流。
  4. 如权利要求2所述的发射端电路，其中所述检测电路还包括低通滤波单元，耦接在所述分压部与所述采样单元的输入端之间，用以减缓所述分压部上输出的分压信号的变化速度。
  5. 如权利要求4所述的发射端电路，其中所述低通滤波单元包括：
    第一电阻，所述第一电阻的第一端与所述第一分压电容的第二端耦接，所述第一电阻的第二端与所述采样单元的输入端耦接；
    第二电阻，所述第二电阻的第一端与所述第一电阻的第二端耦接；
    第二电容，所述第二电容的第一端与所述采样单元的输入端耦接，所述第二电容的第二端接地；
    直流源，所述直流源与所述第二电阻的第二端耦接。
  6. 如权利要求4或5所述的发射端电路，其中所述检测电路还包括增益单元，耦接在所述低通滤波单元与所述采样单元的输入端之间，用以还原所述分压部上输出的分压信号的电压幅度。
  7. 如权利要求1或2所述的发射端电路，其中所述检测电路还包括：
    时钟调节部，配置成可调节所述***时钟信号的脉冲周期和/或脉冲宽度，以向所述采样单元输出采样时钟信号；
    其中，所述采样单元根据与所述***时钟信号对应的采样时钟信号，对所述分压部上输出的分压信号进行采样。
  8. 根据权利要求7所述的发射端电路，其中所述时钟调节部包括周期扩展单元，配置成可接收所述***时钟信号，并扩展所述***时钟信号的信号周期，以输出扩展后的中间时钟信号。
  9. 根据权利要求8所述的发射端电路，其中所述周期扩展单元采用单稳态电路构成，所述单稳态电路包括：
    第一D触发器，由所述***时钟信号触发，输入端接高电平，反向输出端输出中间时钟信号；
    第一反相器，输入端与所述第一D触发器的反向输出端耦接；
    第三电容，第一端与所述第一反相器的输出端耦接，第二端接地；
    第二反相器，输入端与所述第三电容的第一端耦接，输出端与所述第一D触发器的复位端耦接。
  10. 如权利要求9所述的发射端电路，其中所述周期扩展单元对于所述***时钟信号的周期扩展长度由所述单稳态电路中的第三电容的参数来决定。
  11. 如权利要求9或10所述的发射端电路，其中所述时钟调节部还包括脉宽扩展单元，配置成可根据所述***时钟信号以及所述中间时钟信号，来生成采样时钟信号；其中，所述采样时钟信号的脉宽大于所述***时钟信号的脉宽，并且，所述采样时钟信号的周期与所述中间时钟信号的周期相同。
  12. 根据权利要求11所述的发射端电路，其中所述脉宽扩展单元包括：
    第二D触发器，由所述***时钟信号的反向信号触发，输入端接高电平，复位端与所述第一D触发器的反向输出端耦接；
    或非门，两个输入端分别与所述第二D触发器的正向输出端和所述***时钟信号的反向信号耦接；
    第三反相器，输入端与所述或非门的输出端耦接；
    第四电容，第一端与所述第三反相器的输出端耦接，第二端接地；
    第四反相器，输入端与所述第四电容的第一端耦接，第二端作为所述脉宽扩展单元的输出端输出所述采样时钟信号。
  13. 如权利要求12所述的发射端电路，其中所述脉宽扩展单元对于所述***时钟信号的脉宽扩展长度由所述第四电容的参数来决定。
  14. 如权利要求1或2所述的发射端电路，其中所述采样单元包括模数转换器。
  15. 根据权利要求1或2所述的发射端电路，其中所述驱动电路为高边管驱动。
  16. 根据权利要求1或2所述的发射端电路，其中所述驱动电路的驱动电压范围为30-60v。
  17. 一种检测激光雷达发射端电路的驱动电流的方法，包括：
    S101：通过驱动电路，向至少一个激光器施加驱动电压，以使所述至少一个激光器发光；
    S102：通过分压部对所述驱动电压进行分压，以输出分压信号；
    S103：通过采样单元，根据所述发射端电路的***时钟信号，对所述分压部上输出的分压信号进行采样，以获得相应的采样值。
  18. 如权利要求17所述的检测方法，还包括：
    通过信号处理单元接收所述采样单元输出的采样值，并确定所述至少一个激光器上的驱动电流。
  19. 如权利要求17或18所述的检测方法，还包括：
    通过耦接在所述分压部与所述采样单元的输入端之间的低通滤波单元，减缓所述分压部上输出的分压信号的变化速度。
  20. 如权利要求19所述的检测方法，还包括：
    通过耦接在所述低通滤波单元与所述采样单元的输入端之间的增益单元，还原所述分压部上输出的分压信号的电压幅度。
  21. 如权利要求17或18所述的检测方法，还包括：
    通过时钟调节部调节所述***时钟信号的脉冲周期和/或脉冲宽度，以向所述采样单元输出采样时钟信号。
  22. 如权利要求21所述的检测方法，其中所述时钟调节部包括周期扩展单元，所述检测方法还包括：
    通过所述周期扩展单元接收所述***时钟信号，并扩展所述***时钟信号的脉冲周期，以输出扩展后的中间时钟信号。
  23. 如权利要求22所述的检测方法，其中所述时钟调节部还包括脉宽扩展单元，所述检测方法还包括：
    通过所述脉宽扩展单元接收所述***时钟信号以及所述中间时钟信号， 并扩展所述中间时钟信号的脉冲宽度，以生成所述采样时钟信号。
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