WO2022127061A1 - 一种功率芯片堆叠封装结构 - Google Patents

一种功率芯片堆叠封装结构 Download PDF

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WO2022127061A1
WO2022127061A1 PCT/CN2021/101673 CN2021101673W WO2022127061A1 WO 2022127061 A1 WO2022127061 A1 WO 2022127061A1 CN 2021101673 W CN2021101673 W CN 2021101673W WO 2022127061 A1 WO2022127061 A1 WO 2022127061A1
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Prior art keywords
chip
electrode
pin
package structure
base island
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PCT/CN2021/101673
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English (en)
French (fr)
Inventor
王琇如
唐和明
郑明祥
黄源炜
曹周
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杰群电子科技（东莞）有限公司
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Publication of WO2022127061A1 publication Critical patent/WO2022127061A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a stacking package structure for power chips.
  • a stacked package is a type of multi-chip package. Small package size and good heat dissipation performance are the development trend of power chip stacking package structure.
  • each chip needs to be carried by a substrate, and each chip needs to be packaged, and the size of the packaging structure is large, which is not conducive to the miniaturized design of the product.
  • Another power chip stacking package structure encapsulates two or more chips in the same package body, and the electrodes of the chips are electrically connected to the pins through copper wires to lead the chip electrodes to the outside;
  • the electrodes of the chips are electrically connected to the pins through copper wires to lead the chip electrodes to the outside;
  • double-sided electrode chips of electrodes when two or more double-sided electrode chips need to be stacked and packaged, it is difficult to realize interconnection between chips and external lead-out of electrodes with this package structure.
  • the purpose of the embodiments of the present application is to provide a stacking package structure for power chips, which realizes the stacking package of two or more chips with electrodes on both sides, reduces the package size, and improves the heat dissipation performance.
  • a stacking package structure for power chips comprising metal sheets, a first chip, a lead frame and a second chip that are stacked in sequence to form a stacking structure, and a package body that encapsulates the stacking structure;
  • the lead frame includes a base island, a first pin electrically connected to the base island, and a second pin insulated from the base island;
  • the opposite sides of the first chip are provided with a first electrode and a second electrode, and the opposite sides of the second chip are provided with a third electrode and a fourth electrode;
  • the second electrode is combined with the front surface of the base island and the back surface of the base island and the third electrode respectively through a conductive bonding layer;
  • the fourth electrode is electrically connected with the second pin;
  • the front surface of the metal sheet, a part of the first pin, and a part of the second pin are exposed to the package body.
  • a metal bridge is further included, the front surface of the metal bridge is combined with the fourth electrode through a conductive bonding layer, and the metal bridge is electrically connected to the second pin.
  • the backside of the metal bridge exposes the package body.
  • the base island and the first pin have an integral structure
  • the width of the first pin is a
  • the width of the base island is b
  • the ratio of a to b is 0.5 to 1.
  • the second pins are sheet pins; the width of the portion of the second pins outside the package is c, the width of the package body is d, and the ratio of c to d is 0.4 to d. 0.9.
  • the first chip is a triode chip
  • the second chip is a diode chip
  • the first chip is a diode chip
  • the second chip is a triode chip
  • the opposite sides of the triode chip are respectively provided with a source electrode and a drain electrode; the opposite sides of the diode chip are respectively provided with an anode and a cathode;
  • the second electrode is the drain, and the third electrode is the cathode; when the first chip is a diode chip, the second electrode is the the cathode, and the third electrode is the drain.
  • the first chip is a triode chip, the first electrode is a source electrode, and the second electrode is a drain electrode; the first chip further includes a gate coplanar with the source electrode;
  • the lead frame further includes a third pin insulated from the base island, and the gate is electrically connected to the third pin through a metal wire; or, the power chip stacking package structure further includes a conductive sheet, so The gate electrode is bonded to the back surface of the conductive sheet through a conductive bonding layer, and the package body is exposed from the front surface of the conductive sheet.
  • the first chip is a triode chip, the first electrode is a source electrode, and the second electrode is a drain electrode; the first chip further includes a gate electrode and a detection electrode coplanar with the source electrode ;
  • the lead frame further includes a third pin insulated from the base island and a fourth pin insulated from the base island, the gate is electrically connected to the third pin through a metal wire, and the detection The electrode is electrically connected to the fourth pin through a metal wire; or, the power chip stacking package structure includes two conductive sheets, and the gate is bonded to the back of one of the conductive sheets through a conductive bonding layer, and the The detection electrode is bonded to the back surface of the other conductive sheet through a conductive bonding layer, and the package body is exposed from the front surfaces of the two conductive sheets.
  • the first pin includes a first connection surface
  • the second pin includes a second connection surface; the front surface of the metal sheet, the first connection surface and the second connection surface are located on the same plane Inside.
  • FIG. 1 is a longitudinal cross-sectional view of a power chip stacking package structure according to an embodiment of the present application in the first direction;
  • FIG. 2 is a longitudinal cross-sectional view of the power chip stacking package structure according to an embodiment of the present application in the second direction;
  • FIG. 3 is a front view of the internal structure of the power chip stacking package structure according to an embodiment of the present application.
  • FIG. 4 is a rear view of the internal structure of the power chip stacking package structure according to an embodiment of the present application.
  • FIG. 5 is a rear view of the overall structure of the power chip stacking package structure according to an embodiment of the present application.
  • FIG. 6 is a front view of the overall structure of the power chip stacking package structure according to an embodiment of the present application.
  • FIG. 7 is a longitudinal cross-sectional view of a power chip stacking package structure according to another embodiment of the present application.
  • FIG. 8 is a front view of the internal structure of the power chip stacking package structure according to another embodiment of the present application.
  • FIG. 9 is a rear view of the internal structure of the power chip stacking package structure according to another embodiment of the present application.
  • FIG. 10 is a rear view of the overall structure of the power chip stacking package structure according to another embodiment of the present application.
  • FIG. 11 is a front view of the overall structure of the power chip stacking package structure according to another embodiment of the present application.
  • FIG. 12 is an application schematic diagram of the power chip stacking package structure according to an embodiment of the present application.
  • metal sheet 20, first chip; 21, source electrode; 23, gate electrode; 24, detection electrode; 31, base island; 32, first pin; 33, second pin; 34, The third pin; 35, the fourth pin; 40, the second chip; 41, the cathode; 50, the metal bridge; 61, the conductive bonding layer; 62, the metal wire; 63, the conductive sheet; 70, the package body; 80, circuit board; 90, radiator.
  • connection and “fixed” should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection or an integral body; it may be a mechanical connection , it can also be an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of the two elements or the interaction relationship between the two elements.
  • connection and “fixed” should be understood in a broad sense, for example, it may be a fixed connection, a detachable connection or an integral body; it may be a mechanical connection , it can also be an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of the two elements or the interaction relationship between the two elements.
  • a first feature "on” or “under” a second feature may include direct contact between the first and second features, or may include the first and second features Not directly but through additional features between them.
  • the first feature being “above”, “over” and “above” the second feature includes the first feature being directly above and obliquely above the second feature, or simply means that the first feature is level higher than the second feature.
  • the first feature is “below”, “below” and “below” the second feature includes the first feature is directly below and diagonally below the second feature, or simply means that the first feature has a lower level than the second feature.
  • the present application proposes a stacking package structure for power chips, which reduces the size of the package structure and has better heat dissipation performance. Among them, the lower the heat consumption, the higher the heat dissipation efficiency, and the better the heat dissipation performance.
  • the power chip stacking package structure includes a metal sheet 10 , a first chip 20 , a lead frame, a metal sheet 10 , a first chip 20 , a Two chips 40 and a metal bridge 50, and a package body 70; the package body 70 encapsulates the metal sheet 10, the first chip 20, the lead frame, the second chip 40 and the metal bridge 50, so as to Physical protection and electrical protection through the stack structure of the package body 70;
  • the lead frame includes a base island 31, a first pin 32 electrically connected to the base island 31, and a second pin 33 insulated from the base island 31;
  • the two opposite sides of the first chip 20 are respectively provided with a first electrode and a second electrode, and the two opposite sides of the second chip 40 are respectively provided with a third electrode and a fourth electrode;
  • the metal bridge 50 is electrically connected to the second pin 33;
  • the front surface of the metal sheet 10 , a part of the first pin 32 , and a part of the second pin 33 are exposed to the package body 70 , the first electrode is led out through the metal sheet 10 , the second electrode and the third The electrodes are led out through the first pins 32 , and the fourth electrodes are led out through the second pins 33 .
  • first pin 32 is exposed to the package body 70, and one end of the first pin 32 may protrude from the package body 70, or a surface of the first pin 32 may be exposed to the package body 70; the second The same is true for the limited range where a part of the pin 33 is exposed to the package body 70 .
  • other parts may also be exposed.
  • the first chip 20 and the second chip 40 are respectively combined on opposite sides of the lead frame base island 31 , so that the second electrode of the first chip 20 and the first chip 40 can be realized.
  • the interconnection between the three electrodes can also lead out the second electrode and the third electrode through the first pin 32, so that the gap between the first chip 20 and the second chip 40 can be reduced, and the package size can be reduced , and also meets the design requirements of interconnection and external lead between the electrodes of the two chips.
  • a metal sheet 10 is provided on the side of the first chip 20 away from the base island 31 , and the metal sheet 10 is electrically connected to the first electrode.
  • the metal sheet 10 is used for connecting the first electrode with other
  • the electronic device is connected and used to dissipate heat to the outside.
  • the present application can shorten the electrical conduction path, reduce the resistance, and thus reduce the heat consumption, and the heat inside the package structure can also be reduced.
  • the contact area between the electrodes is large, which can increase the conduction area of electricity and heat, reduce resistance, reduce heat consumption, and improve heat dissipation efficiency, thereby improving heat dissipation performance.
  • the present application also uses a metal bridge 50 .
  • Bridge 50 the fourth electrode is electrically connected to the second pin 33 through the metal bridge 50; compared with the method of using the metal wire 62, the metal bridge 50 with a larger area can be used to increase the distance between the fourth electrode and the metal bridge 50.
  • the contact area can increase the conduction area of electricity and heat, thereby reducing resistance and thermal resistance, reducing heat consumption, improving heat dissipation efficiency, and improving heat dissipation performance.
  • the power chip stacking package structure of the present application reduces the gap between components, reduces the size of the package structure, and has good heat dissipation performance, and has wider applicability and higher reliability.
  • the metal bridge 50 is configured such that the package body 70 is exposed on the side facing away from the second chip 40 , that is, the back surface of the metal bridge 50 is exposed to the package body 70 .
  • the power chip stacking package structure is a double-sided heat dissipation structure, so that the heat inside the package structure can be dissipated to the outside more efficiently.
  • the front side of the metal sheet 10 can be soldered to the circuit board 80 , and the first pins 32 and the second pins 33 can be soldered to the circuit board 80 to realize circuit connection Moreover, on the basis that the backside of the metal bridge 50 is exposed, heat dissipation can be achieved in a more efficient manner.
  • the power chip stack package structure by setting the backside of the metal bridge 50 to expose the package body 70, the power chip stack package structure can have better heat dissipation performance during operation, can achieve higher power, and have better operation performance.
  • the power chip stacking package structure is also suitable for the package structure of an intelligent power module including a plurality of chips.
  • the conductive bonding layer 61 is formed by curing a conductive bonding material, and is provided between the first electrode and the metal sheet 10 , between the second electrode and the base island 31 , and between the third electrode and the base island 31 .
  • Conductive bonding materials are bonded by welding or gluing.
  • the bonding material may be one or more of lead-tin-silver alloy, gold-silicon alloy, and silver paste, or other bonding materials, and the composition of the bonding material is not a limitation of the present application.
  • the entire surface of the first chip 20 with the second electrode may be covered with the conductive bonding material, or only the electrode area of the second electrode may be covered with the conductive bonding material;
  • the entire surface of the second chip 40 provided with the third electrode may be covered with the conductive bonding material, or only the electrode area of the third electrode may be covered with the conductive bonding material.
  • the metal sheet 10 in the present application may be, but not limited to, a copper sheet, and the metal wire 62 may be, but not limited to, a copper wire.
  • an integrated structure in which the base island 31 and the first pin 32 are designed in one piece is adopted.
  • the integrated structure is a monolithic structure. A part of the structure is used as the base island 31, and the other part is used as the first pin 32, which is equivalent to directly extending the base island 31 out of the package body 70; the pins of the power chip stacking package structure in the related art are generally narrow-width tubes.
  • the width of the first pin 32 is equal to the width of the base island 31, thereby providing a larger electrical and thermal conduction area, so that the power chip stacking package structure has a larger current carrying capacity, Higher heat dissipation efficiency, better heat dissipation performance.
  • the width of the first pin 32 is a
  • the width of the base island 31 is b
  • the ratio of a to b is 0.5 to 1.
  • the ratio of a to b (a:b) may be, but not limited to, 0.8, 0.9, 0.95, and 1.
  • the base island 31 refers to the part of the integrated structure located in the package body 70
  • the first pin 32 refers to the part of the integrated structure exposed outside the package body 70 .
  • the first pin 32 protrudes outward from one side wall of the package body 70 . From the outside of the package structure, only one pin is provided on the side of the package body 70 extending out of the first pin 32 , that is, the first pin 32 , so that the width of the first pin 32 is guaranteed.
  • the second pins 33 used are chip pins; the second pins 33 extend out of the package body Outside 70, the width of the portion of the second pin 33 outside the package body 70 is c, the width of the package body 70 is d, and the ratio of c to d (c:d) is 0.4 to 0.9.
  • the second pin 33 provides a larger electrical and thermal conduction area, so that the power chip stack package structure has a larger current carrying capacity, higher heat dissipation efficiency, and better heat dissipation performance.
  • one of the first chip 20 and the second chip 40 is a triode chip, and the other is a diode chip.
  • the diode chip has the functions of forward conduction and reverse cut-off.
  • the triode chip is matched with the diode chip, when the gate 23 is closed, the reverse current generated due to inductance and other reasons can be It is cut off by the diode chip, so that the power device packaging structure can meet the working requirements of higher power.
  • the first chip 20 is a triode chip
  • the second chip 40 is a diode chip
  • the opposite sides of the triode are respectively provided with a source electrode 21 and a drain electrode
  • the opposite sides of the diode chip are respectively provided with an anode and a cathode 41
  • the first electrode is the source electrode 21, the second electrode is the drain electrode
  • the third electrode is the cathode electrode 41
  • the fourth electrode is the anode electrode.
  • the diode chip is connected in parallel, the drain of the triode chip is connected with the cathode 41 of the diode chip, and the reverse current can be cut off through the diode chip.
  • the triode chip is used as the first chip 20 .
  • the source electrode 21 is welded to the metal sheet 10 .
  • the metal sheet 10 can be directly welded to the circuit board 80 to realize the connection between the source electrode 21 and the circuit board 80 . .
  • the lead end of the source electrode 21 of the power chip stacking package structure faces the circuit board 80 , which is safer and more reliable.
  • the source electrode 21 of the triode chip is electrically connected to the second pin 33 through the metal bridge 50, since the source electrode 21 of the triode chip is exposed to a relatively open environment, it is not suitable to be used as the source electrode 21
  • the backside of the metal bridge 50 at the lead-out end exposes the package body 70, so the heat dissipation performance cannot be optimized.
  • Embodiment 2 The first chip 20 is a diode chip, and the second chip 40 is a triode chip; the opposite sides of the triode are respectively provided with a source electrode 21 and a drain electrode, and the opposite sides of the diode chip are respectively provided with an anode and a cathode 41; the first electrode is the anode, the second electrode is the cathode 41 , the third electrode is the drain, and the fourth electrode is the source 21 .
  • the triode chip described in this application can be, but is not limited to, a MOSFET chip; the triode chip is a switching device.
  • the first chip 20 is a triode chip, the first electrode is the source electrode 21 , and the second electrode is the drain electrode; the first chip 20 further includes and the source 21 coplanar gate 23;
  • the lead frame further includes a third pin 34 insulated from the base island 31, and the gate 23 is electrically connected to the third pin 34 through a metal wire 62; or, the power chip stacking package structure further A conductive sheet 63 is included, the gate 23 is bonded to the back of the conductive sheet 63 through a conductive bonding layer 61 , and the package body 70 is exposed on the front surface of the conductive sheet 63 .
  • the first chip 20 is a triode chip, the first electrode is the source electrode 21 , and the second electrode is the drain electrode; the first chip 20 further includes and the The source electrode 21 is coplanar with the gate electrode 23 and the detection electrode 24;
  • the lead frame further includes a third pin 34 insulated from the base island 31 and a fourth pin 35 insulated from the base island 31 , and the gate 23 is connected by a metal wire 62 is electrically connected to the third pin 34, and the detection electrode 24 is electrically connected to the fourth pin 35 through the metal wire 62; or, as shown in FIG. 3-6, the power chip stacking package structure includes: Two conductive sheets 63, the gate 23 is bonded to the back of one of the conductive sheets 63 through the conductive bonding layer 61, the detection electrode 24 is bonded to the back of the other conductive sheet 63 through the conductive bonding layer 61, The front surfaces of the two conductive sheets 63 are exposed to the package body 70 .
  • the detection electrode 24 is an electrode drawn from the source electrode 21.
  • the current of the source electrode 21 can be obtained by detecting the current of the detection electrode 24, so as to facilitate the overcurrent protection of the first chip 20 and improve the reliability of the power chip stacking package structure.
  • the arrangement of the detection electrodes 24 can be arranged by using the related technology.
  • the gate 23 and the detection electrode 24 will not pass a large current when the power chip stacking package structure is applied, when the gate 23 and the detection electrode 24 are connected to the pins by metal wires, excessive loss will not be generated, and the heat dissipation will not be affected. The performance impact is minimal.
  • the detection electrode 24 is combined with another conductive sheet 63 , and the front surfaces of the two conductive sheets 63 are both exposed from the bottom surface of the package body 70 , this method is adopted.
  • the metal sheet 10 can be welded to the source electrode 21 , a conductive sheet 63 can be welded to the gate 23 , and the other conductive sheet 63 can be welded to the detection electrode 24 at the same time.
  • the wire 62 leads the grid 23 and the detection electrode 24 to the outside, and the use of this grid 23 and the detection electrode 24 is beneficial to improve the packaging efficiency; In the mode, there is no need to increase the pins for the external gate 23 and the detection electrode 24. In this way, the second pin 33 with a larger width can be used. As shown in Figure 3-4, the ratio of c to d is greater than 0.65, in this way, the current carrying capacity can be effectively improved.
  • the first pin 32 includes a first connection surface
  • the second pin 33 includes a second connection surface
  • the metal sheet The front surface of 10, the first connecting surface and the second connecting surface are in the same plane.
  • the front surface of the metal sheet 10 is flush with the bottom surface of the package body 70
  • the back surface of the metal bridge 50 is flush with the top surface of the package body 70 .

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本申请提供一种功率芯片堆叠封装结构，该功率芯片堆叠封装结构包括依次堆叠以形成堆叠结构的金属片、第一芯片、引线框架和第二芯片，以及包封堆叠结构的封装体；引线框架包括基岛、与基岛电连接的第一管脚、以及与基岛绝缘的第二管脚；第一芯片相对的两面设有第一电极和第二电极，第二芯片相对的两面设有第三电极和第四电极；金属片与第一电极、第二电极与基岛、基岛与第三电极分别通过导电结合层结合；第四电极与第二管脚电连接；金属片的正面、第一管脚的一部分、第二管脚的一部分露出封装体。该功率芯片堆叠封装结构，将两个芯片固定在引线框架相对的两侧进行堆叠封装，并且金属片外露，在缩小了封装结构的尺寸的同时，兼具更优的散热性能。

Description

一种功率芯片堆叠封装结构 技术领域
本申请涉及半导体技术领域，尤其涉及一种功率芯片堆叠封装结构。
背景技术
目前，半导体封装发展的趋势向多芯片封装的方向发展。堆叠封装是多芯片封装的一种。小封装尺寸以及良好的散热性能，为功率芯片堆叠封装结构的发展趋势。
相关技术中的功率芯片堆叠封装结构，一种是将不同芯片分别封装在不同的封装体内，再将封装体堆叠，通过穿孔、焊球等方式实现多个芯片之间的互连，形成最终的整体封装结构；此种功率芯片堆叠封装结构，每一芯片均需要一基底承载，且需要对每一芯片进行封装，封装结构的尺寸较大，不利于产品的小型化设计。
另一种功率芯片堆叠封装结构，将两个或多个芯片封装于同一个封装体内，芯片的电极通过铜线与管脚电连接，以将芯片电极外引；但是，对于相对两面均设有电极的双面电极芯片而言，当需要将两个或多个双面电极芯片堆叠封装时，此种封装结构较难在实现芯片间互连以及电极的外引。
并且，上述两种功率芯片堆叠封装结构也无法实现高效的散热。
相关技术中，缺乏一种可将双面设有电极的芯片进行堆叠，且可解决功率芯片堆叠封装结构尺寸较大、散热性能不佳的功率芯片堆叠封装结构。
发明内容
本申请实施例的目的在于：提供一种功率芯片堆叠封装结构，其实现了两个或多个双面设有电极的芯片的堆叠封装，缩小了封装尺寸，提升了散热性能。
一种功率芯片堆叠封装结构，包括依次堆叠以形成堆叠结构的金属片、第一芯片、引线框架和第二芯片，以及包封所述堆叠结构的封装体；
所述引线框架包括基岛、与所述基岛电连接的第一管脚、以及与所述基岛绝缘的第二管脚；
所述第一芯片相对的两面设有第一电极和第二电极，所述第二芯片相对的两面设有第三电极和第四电极；所述金属片的背面与所述第一电极、所述第二电极与所述基岛的正面、所述基岛的背面与所述第三电极分别通过导电结合层结合；所述第四电极与所述第二管脚电连 接；
所述金属片的正面、所述第一管脚的一部分、所述第二管脚的一部分露出所述封装体。
作为优选，还包括金属桥，所述金属桥的正面通过导电结合层与所述第四电极结合，所述金属桥与所述第二管脚电连接。
作为优选，所述金属桥的背面露出所述封装体。
作为优选，所述基岛与所述第一管脚为一体结构，所述第一管脚的宽度为a，所述基岛的宽度为b，a与b的比值为0.5至1。
作为优选，所述第二管脚为片状管脚；所述第二管脚位于所述封装体外的部分的宽度为c，所述封装体的宽度为d，c与d的比值为0.4至0.9。
作为优选，所述第一芯片为三极管芯片，所述第二芯片为二极管芯片；或，所述第一芯片为二极管芯片，所述第二芯片为三极管芯片。
作为优选，所述三极管芯片相对的两面分别设有源极和漏极；所述二极管芯片的相对两面分别设有阳极和阴极；
当所述第一芯片为三极管芯片时，所述第二电极为所述漏极，所述第三电极为所述阴极；当所述第一芯片为二极管芯片时，所述第二电极为所述阴极，所述第三电极为所述漏极。
作为优选，所述第一芯片为三极管芯片，所述第一电极为源极，所述第二电极为漏极；所述第一芯片还包括与所述源极共面的栅极；
所述引线框架还包括与所述基岛绝缘的第三管脚，所述栅极通过金属线与所述第三管脚电连接；或，所述功率芯片堆叠封装结构还包括导电片，所述栅极通过导电结合层结合于所述导电片的背面，所述导电片的正面露出所述封装体。
作为优选，所述第一芯片为三极管芯片，所述第一电极为源极，所述第二电极为漏极；所述第一芯片还包括与所述源极共面的栅极和检测电极；
所述引线框架还包括与所述基岛绝缘的第三管脚、与所述基岛绝缘的第四管脚，所述栅极通过金属线与所述第三管脚电连接，所述检测电极通过金属线与所述第四管脚电连接；或，所述功率芯片堆叠封装结构包括两块导电片，所述栅极通过导电结合层结合于其一所述导电片的背面，所述检测电极通过导电结合层结合于另一所述导电片的背面，两个所述导电片的正面均露出所述封装体。
作为优选，所述第一管脚包括第一连接面，所述第二管脚包括第二连接面；所述金属片的正面、所述第一连接面和所述第二连接面位于同一平面内。
本申请的有益效果为：该功率芯片堆叠封装结构，将两个双面设有电极的芯片固定在引 线框架相对的两侧进行堆叠封装，并且金属片外露，在缩小了封装结构的尺寸的同时，兼具更优的散热性能，适用范围更广，更加可靠。
附图说明
下面根据附图和实施例对本申请作进一步详细说明。
图1为本申请其一实施例所述功率芯片堆叠封装结构的第一方向纵剖图；
图2为本申请其一实施例所述功率芯片堆叠封装结构的第二方向纵剖图；
图3为本申请其一实施例所述功率芯片堆叠封装结构的内部结构正面视图；
图4为本申请其一实施例所述功率芯片堆叠封装结构的内部结构背面视图；
图5为本申请其一实施例所述功率芯片堆叠封装结构的整体结构背面视图；
图6为本申请其一实施例所述功率芯片堆叠封装结构的整体结构正面视图；
图7为本申请另一实施例所述功率芯片堆叠封装结构的纵剖图；
图8为本申请另一实施例所述功率芯片堆叠封装结构的内部结构正面视图；
图9为本申请另一实施例所述功率芯片堆叠封装结构的内部结构背面视图；
图10为本申请另一实施例所述功率芯片堆叠封装结构的整体结构背面视图；
图11为本申请另一实施例所述功率芯片堆叠封装结构的整体结构正面视图；
图12为本申请其一实施例所述功率芯片堆叠封装结构的应用示意图；
图中：10、金属片；20、第一芯片；21、源极；23、栅极；24、检测电极；31、基岛；32、第一管脚；33、第二管脚；34、第三管脚；35、第四管脚；40、第二芯片；41、阴极；50、金属桥；61、导电结合层；62、金属线；63、导电片；70、封装体；80、电路板；90、散热器。
具体实施方式
为使本申请解决的技术问题、采用的技术方案和达到的技术效果更加清楚，下面将结合附图对本申请实施例的技术方案作进一步的详细描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，除非另有明确的规定和限定，术语“相连”、“固定”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接或成一体；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的 相互作用关系。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
本申请提出一种功率芯片堆叠封装结构，其缩小了封装结构的尺寸，且兼具更优的散热性能。其中，热耗越低、散热效率越高，散热性能越优。
如图1-12所示，在本申请的功率芯片堆叠封装结构的一实施例中，该功率芯片堆叠封装结构包括依次堆叠以形成堆叠结构的金属片10、第一芯片20、引线框架、第二芯片40和金属桥50，以及封装体70；所述封装体70包封所述金属片10、所述第一芯片20、所述引线框架、所述第二芯片40和金属桥50，以通过封装体70堆叠结构进行物理保护和电气保护；
所述引线框架包括基岛31、与所述基岛31电连接的第一管脚32、以及与所述基岛31绝缘的第二管脚33；
所述第一芯片20相对的两面分别设有第一电极和第二电极，所述第二芯片40相对的两面分别设有第三电极和第四电极；
所述金属片10的背面与所述第一电极之间、所述第二电极与所述基岛31的正面之间、所述基岛31的背面与所述第三电极之间、所述第四电极与所述金属片10的正面之间分别通过导电结合层61结合；所述金属桥50与所述第二管脚33电连接；
所述金属片10的正面、所述第一管脚32的一部分、所述第二管脚33的一部分露出所述封装体70，第一电极通过金属片10外引，第二电极和第三电极通过第一管脚32外引，第四电极通过第二管脚33外引。
需要说明的是，第一管脚32的一部分露出封装体70，可以是第一管脚32的一端伸出封装体70，也可以是第一管脚32的一表面露出封装体70；第二管脚33的一部分露出封装体70的限定范围同理。金属片10除了露出正面，也可以露出其他部位。
本申请的功率芯片堆叠封装结构，将第一芯片20和第二芯片40分别结合于引线框架基岛31相对的两侧，既可实现第一芯片20的第二电极与第二芯片40的第三电极之间的互连，又可通过第一管脚32将第二电极和第三电极外引，如此，既可缩小第一芯片20与第二芯片 40之间的间隙，可缩小封装尺寸，也满足了两个芯片的电极之间互连且外引的设计需求。
并且，本申请的功率芯片堆叠封装结构，在第一芯片20背离基岛31的一侧设置金属片10，金属片10与第一电极电连接，金属片10既用于将第一电极与其他电子器件连接，又用于向外散热；相对于通过金属导线、管脚将第一电极外引的方式，本申请可缩短电传导路径，降低电阻，从而降低热耗，封装结构内部的热量也可通过金属片10外露的部分直接快速地向外散出，无需管脚传导，可缩短热传导路径，提高传热效率，散热效率高；再者，金属片10面积大，金属片10与第一电极之间的接触面积大，可增大电和热的传导面积，降低电阻，降低热耗，提高散热效率，从而提升散热性能。
在采用金属片10将第一芯片20背离基岛31一面上的第一电极外引的基础上，本申请还采用了金属桥50，通过在第二芯片40背离基岛31的一侧设置金属桥50，第四电极通过金属桥50与第二管脚33电连接；相对于采用金属线62的方式，采用面积较大的金属桥50，可以增大第四电极与金属桥50之间的接触面积，可增大电和热的传导面积，从而降低电阻和热阻，降低热耗、提高散热效率，从而提升散热性能。
本申请的功率芯片堆叠封装结构，缩小了各元件之间的间隙，既缩小了封装结构的尺寸，又兼具良好的散热性能，其适用性更广，可靠性更高。
为了进一步提升该功率芯片堆叠封装结构的散热性能，将金属桥50配置为：背离第二芯片40的一面露出封装体70，即金属桥50的背面露出封装体70。如此，该功率芯片堆叠封装结构为双面散热结构，从而能够更加高效地将封装结构内部的热量向外散出。
如图12所示，该功率芯片堆叠封装结构在应用时，可将金属片10的正面焊接于电路板80，将第一管脚32、第二管脚33焊接于电路板80，实现电路连接；并且，在金属桥50的背面外露的基础上，可通过更加高效的方式实现散热，可在封装体70的顶部增加设置散热器90，并且还可以对散热器90进行强制对流散热。
该功率芯片堆叠封装结构，通过将金属桥50的背面设置为露出封装体70，可以使该功率芯片堆叠封装结构运行时具有更加优秀的散热性能，可以实现更高的功率，具有更加优秀的运行性能。
该功率芯片堆叠封装结构，也适用于对包含多个芯片的智能功率模组的封装结构。
在一实施例中，导电结合层61由导电结合材料固化形成，在第一电极与金属片10之间、在第二电极与基岛31之间、在第三电极与基岛31之间提供导电结合材料，通过焊接或粘合的方式，实现结合。其中，结合材料可以为铅锡银合金、金硅合金、银浆中的一种或多种，也可以为其他结合材料，结合材料的成分不作为对本申请的限制。
其中，第一芯片20与基岛31结合时，可以是将第一芯片20设有第二电极的一整面覆盖导电结合材料，也可以是仅在第二电极的电极区域覆盖导电结合材料；第二芯片40与基岛31结合时，可以是将第二芯片40设有第三电极的一整面覆盖导电结合材料，也可以是仅在第三电极的电极区域覆盖导电结合材料。
本申请中的金属片10可以为但不限于铜片，金属线62可以为但不限于铜线。
如图3、4、8、9所示，为了进一步提升该功率芯片堆叠封装结构的性能，采用基岛31与第一管脚32一体设计的一体结构，一体结构为整片式结构，该一体结构的一部分作为基岛31，另一部分作为第一管脚32，如此相当于直接将基岛31伸出封装体70；相关技术中的功率芯片堆叠封装结构的管脚一般为宽度较窄的管脚，而本申请中，第一管脚32的宽度与基岛31的宽度相当，从而提供更大的电和热的传导面积，从而使该功率芯片堆叠封装结构具有更大的载流能力，更高的散热效率，更优的散热性能。
在一实施例中，所述第一管脚32的宽度为a，所述基岛31的宽度为b，a与b的比值为0.5至1。a与b的比值(a：b)可以为但不限于0.8、0.9、0.95和1。
其中，基岛31指的是一体结构位于封装体70内的部分，第一管脚32指的是一体结构露出封装体70外的部分。
在本实施例中，第一管脚32由封装体70的其一侧壁向外伸出，由封装结构的外观看，封装体70伸出第一管脚32的一侧仅设有一管脚，即第一管脚32，如此，保证第一管脚32的宽度。
如图3-6、8-11所示，为了进一步提升该功率芯片堆叠封装结构的性能，采用的第二管脚33为片状管脚；所述第二管脚33伸出所述封装体70外，所述第二管脚33位于所述封装体70外的部分的宽度为c，所述封装体70的宽度为d，c与d的比值(c：d)为0.4至0.9。如此设置，第二管脚33提供更大的电和热的传导面积，从而使该功率芯片堆叠封装结构具有更大的载流能力，更高的散热效率，更优的散热性能。
本申请的功率芯片堆叠封装结构，第一芯片20和第二芯片40中，其一为三极管芯片，另一为二极管芯片。该功率芯片堆叠封装结构应用时，二极管芯片具有正向导通、反向截止的功能，将三极管芯片与二极管芯片的配合，在栅极23关闭的情况下，由于电感等原因产生的反向电流可被二极管芯片截止，从而使该功率器件封装结构满足更高功率的工作需求。
对于三极管芯片和二极管芯片的设置，至少可采用如下两种实施方式实施：
实施方式一：第一芯片20为三极管芯片，第二芯片40为二极管芯片；三极管相对的两面分别设有源极21和漏极，二极管芯片相对的两面分别设有阳极和阴极41；第一电极为源 极21，第二电极为漏极，第三电极为阴极41，第四电极为阳极。
在该功率芯片堆叠封装结构应用时，在三极管芯片与电路板80的电路中，并联二极管芯片，将三极管芯片的漏极和二极管芯片的阴极41相连，可通过二极管芯片截止反向电流。
本实施方式中，将三极管芯片作为第一芯片20，如此，源极21与金属片10焊接，在应用时，金属片10可直接焊接上电路板80，实现源极21与电路板80的连接。
该功率芯片堆叠封装结构在应用时，功率芯片堆叠封装结构的源极21引出端朝向电路板80，更加安全可靠。而若采用三极管芯片作为第二芯片40，将源极21通过金属桥50与第二管脚33电连接，由于三极管芯片的源极21暴露于相对开放的环境内，则不适于将作为源极21引出端的金属桥50的背面露出封装体70，如此无法实现散热性能最优化。
实施方式二：第一芯片20为二极管芯片，第二芯片40为三极管芯片；三极管相对的两面分别设有源极21和漏极，二极管芯片相对的两面分别设有阳极和阴极41；第一电极为阳极、第二电极为阴极41，第三电极为漏极、第四电极为源极21。
本申请中所述的三极管芯片，可以为但不限于MOSFET芯片；三极管芯片为开关器件。
在一实施例中，所述第一芯片20为三极管芯片，所述第一电极为所述源极21，所述第二电极为所述漏极；所述第一芯片20还包括与所述源极21共面的栅极23；
所述引线框架还包括与所述基岛31绝缘的第三管脚34，所述栅极23通过金属线62与所述第三管脚34电连接；或，所述功率芯片堆叠封装结构还包括导电片63，所述栅极23通过导电结合层61结合于所述导电片63的背面，所述导电片63的正面露出所述封装体70。
在一实施例中，所述第一芯片20为三极管芯片，所述第一电极为所述源极21，所述第二电极为所述漏极；所述第一芯片20还包括与所述源极21共面的栅极23和检测电极24；
如图8-11所示，所述引线框架还包括与所述基岛31绝缘的第三管脚34、与所述基岛31绝缘的第四管脚35，所述栅极23通过金属线62与所述第三管脚34电连接，所述检测电极24通过金属线62与所述第四管脚35电连接；或，如图3-6所示，所述功率芯片堆叠封装结构包括两块导电片63，所述栅极23通过导电结合层61结合于其一所述导电片63的背面，所述检测电极24通过导电结合层61结合于另一所述导电片63的背面，两个所述导电片63的正面均露出所述封装体70。
其中，检测电极24为由源极21引出的电极，其与其他器件连接时，可通过检测检测电极24的电流，得到源极21电流大小，从而便于对第一芯片20进行过流保护，提高该功率芯片堆叠封装结构的可靠性。其中，检测电极24的设置方式可采用相关技术设置。
由于功率芯片堆叠封装结构在应用时，栅极23和检测电极24不会经过大电流，故而栅 极23和检测电极24采用金属导线与管脚连接时，也不会产生过多损耗，对散热性能的影响极小。
如图3-6所示，当栅极23与一导电片63结合，检测电极24与另一导电片63结合，两个导电片63的正面均由封装体70的底面露出时，采用此种栅极23、检测电极24外引的方式，在封装时，可同时将金属片10焊接于源极21，将一导电片63焊接于栅极23，将另一导电片63焊接于检测电极24(也可直接在第一芯片20的表面焊接一金属片，再通过蚀刻等方式实现源极21引出端、栅极23引出端和检测电极24引出端之间的绝缘隔离)，相对于采用金属线62将栅极23、检测电极24外引的方式，采用此种栅极23、检测电极24外引的方式有利于提高封装效率；并且，采用此种栅极23、检测电极24外引的方式时，无需再增加设置用于外引栅极23、检测电极24的管脚，如此，可采用宽度较大的第二管脚33，如图3-4所示，c与d的比值大于0.65，如此，可有效提高载流能力。
在一实施例中，为了便于该功率芯片堆叠封装结构装上电路板80，所述第一管脚32包括第一连接面，所述第二管脚33包括第二连接面；所述金属片10的正面、所述第一连接面和所述第二连接面位于同一平面内。
在一实施例中，为了便于加工，金属片10的正面与封装体70的底面齐平，金属桥50的背面与封装体70的顶面齐平。
于本文的描述中，需要理解的是，术语“上”、“下”、“左、”“右”等方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述和简化操作，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”，仅仅用于在描述上加以区分，并没有特殊的含义。
在本说明书的描述中，参考术语“一实施例”、“示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不一定指的是相同的实施例或示例。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以适当组合，形成本领域技术人员可以理解的其他实施方式。
以上结合具体实施例描述了本申请的技术原理。这些描述只是为了解释本申请的原理，而不能以任何方式解释为对本申请保护范围的限制。基于此处的解释，本领域的技术人员不需要付出创造性的劳动即可联想到本申请的其它具体实施方式，这些方式都将落入本申请的 保护范围之内。

Claims (10)

  1. 一种功率芯片堆叠封装结构，其中，包括依次堆叠以形成堆叠结构的金属片、第一芯片、引线框架和第二芯片，以及包封所述堆叠结构的封装体；
    所述引线框架包括基岛、与所述基岛电连接的第一管脚、以及与所述基岛绝缘的第二管脚；
    所述第一芯片相对的两面设有第一电极和第二电极，所述第二芯片相对的两面设有第三电极和第四电极；所述金属片的背面与所述第一电极、所述第二电极与所述基岛的正面、所述基岛的背面与所述第三电极分别通过导电结合层结合；所述第四电极与所述第二管脚电连接；
    所述金属片的正面、所述第一管脚的一部分、所述第二管脚的一部分露出所述封装体。
  2. 根据权利要求1所述的功率芯片堆叠封装结构，其中，还包括金属桥，所述金属桥的正面通过导电结合层与所述第四电极结合，所述金属桥与所述第二管脚电连接。
  3. 根据权利要求2所述的功率芯片堆叠封装结构，其中，所述金属桥的背面露出所述封装体。
  4. 根据权利要求1所述的功率芯片堆叠封装结构，其中，所述基岛与所述第一管脚为一体结构，所述第一管脚的宽度为a，所述基岛的宽度为b，a与b的比值为0.5至1。
  5. 根据权利要求1所述的功率芯片堆叠封装结构，其中，所述第二管脚为片状管脚；所述第二管脚位于所述封装体外的部分的宽度为c，所述封装体的宽度为d，c与d的比值为0.4至0.9。
  6. 根据权利要求1所述的功率芯片堆叠封装结构，其中，所述第一芯片为三极管芯片，所述第二芯片为二极管芯片；或，所述第一芯片为二极管芯片，所述第二芯片为三极管芯片。
  7. 根据权利要求6所述的功率芯片堆叠封装结构，其中，所述三极管芯片相对的两面分别设有源极和漏极；所述二极管芯片的相对两面分别设有阳极和阴极；
    当所述第一芯片为三极管芯片时，所述第二电极为所述漏极，所述第三电极为所述阴极；当所述第一芯片为二极管芯片时，所述第二电极为所述阴极，所述第三电极为所述漏极。
  8. 根据权利要求1述的功率芯片堆叠封装结构，其中，所述第一芯片为三极管芯片，所述第一电极为源极，所述第二电极为漏极；所述第一芯片还包括与所述源极共面的栅极；
    所述引线框架还包括与所述基岛绝缘的第三管脚，所述栅极通过金属线与所述第三管脚电连接；或，所述功率芯片堆叠封装结构还包括导电片，所述栅极通过导电结合层结合于所述导电片的背面，所述导电片的正面露出所述封装体。
  9. 根据权利要求1所述的功率芯片堆叠封装结构，其中，所述第一芯片为三极管芯片， 所述第一电极为源极，所述第二电极为漏极；所述第一芯片还包括与所述源极共面的栅极和检测电极；
    所述引线框架还包括与所述基岛绝缘的第三管脚、与所述基岛绝缘的第四管脚，所述栅极通过金属线与所述第三管脚电连接，所述检测电极通过金属线与所述第四管脚电连接；或，所述功率芯片堆叠封装结构包括两块导电片，所述栅极通过导电结合层结合于其一所述导电片的背面，所述检测电极通过导电结合层结合于另一所述导电片的背面，两个所述导电片的正面均露出所述封装体。
  10. 根据权利要求1所述的功率芯片堆叠封装结构，其中，所述第一管脚包括第一连接面，所述第二管脚包括第二连接面；所述金属片的正面、所述第一连接面和所述第二连接面位于同一平面内。
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CN116631971A (zh) * 2023-04-28 2023-08-22 海信家电集团股份有限公司 功率模块
CN116631971B (zh) * 2023-04-28 2024-04-16 海信家电集团股份有限公司 功率模块
CN117832177A (zh) * 2024-03-04 2024-04-05 深圳市沃芯半导体技术有限公司 开关电源模块封装***及封装方法
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