WO2022111081A1 - 阵列基板和显示面板 - Google Patents

阵列基板和显示面板 Download PDF

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Publication number
WO2022111081A1
WO2022111081A1 PCT/CN2021/123178 CN2021123178W WO2022111081A1 WO 2022111081 A1 WO2022111081 A1 WO 2022111081A1 CN 2021123178 W CN2021123178 W CN 2021123178W WO 2022111081 A1 WO2022111081 A1 WO 2022111081A1
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WIPO (PCT)
Prior art keywords
transistor
pull
edge
shift register
node
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PCT/CN2021/123178
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English (en)
French (fr)
Inventor
毕谣
赵宇
武晓娟
袁洪亮
王建
闫浩
雷利平
Original Assignee
京东方科技集团股份有限公司
北京京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/908,386 priority Critical patent/US12020643B2/en
Publication of WO2022111081A1 publication Critical patent/WO2022111081A1/zh

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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
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    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
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    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
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    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
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    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers

Definitions

  • the embodiments of the present disclosure belong to the field of display technology, and specifically relate to an array substrate and a display panel.
  • the display panel at least includes a display unit located in the display area and a shift register unit arranged in an array located in the peripheral area.
  • the shift register unit is used to provide driving signals to the display unit, so that the display panel forms a display screen.
  • the peripheral area is also a special-shaped area. If a plurality of shift register units adopt the existing arrangement, the area of the occupied area of the shift register unit will increase. , so that it is difficult to form a special-shaped display panel with a narrow frame.
  • the embodiments of the present disclosure at least partially solve the problem of the width of the frame of the existing special-shaped display panel, and provide an array substrate of the special-shaped display panel capable of forming a narrow frame.
  • the technical solution adopted to solve the technical problems of the embodiments of the present disclosure is an array substrate, which has a display area and a peripheral area surrounding the display area, a display unit is arranged in the display area, and the display area includes a curve
  • the peripheral area is provided with a plurality of cascaded shift register units, wherein, at the position corresponding to the curved edge of the display area, any adjacent shift register units are rotated relative to each other, so as to The extension direction of the first edge of the shift register unit is parallel to the outer tangent of the curve edge or consistent with the extension direction of the curve edge, and the first edge is the shift register unit close to the curve The inner edge of the edge.
  • the curved edge includes a plurality of curved segments, each of the shift register units corresponds to one of the curved segments, and the extension direction of the first edge of each of the shift register units corresponds to The extension directions of the curve segments are the same.
  • the curve edge includes a plurality of tangent points, the tangent points are in one-to-one correspondence with the shift register units, and each of the tangent points is the curve edge to the corresponding shift register unit The point with the smallest distance, the first edge of each of the shift register cells is parallel to the tangent of the curved edge at the point corresponding to the tangent.
  • each of the shift register cells further includes a second edge opposite to the first edge, the second edge extending in a direction parallel to an outer tangent of the curved edge.
  • each of the shift register cells further includes a second edge opposite to the first edge, the second edge is consistent with the extending direction of the curved edge.
  • the shape of the curved edge is any one of a circular arc shape and an elliptical arc shape.
  • the extension direction of the center lines of the plurality of shift register units is consistent with the extension direction of the curved edge.
  • a plurality of the shift register units are arranged at intervals in the peripheral region.
  • the display unit includes a plurality of sub-pixels arranged in an array, each row of the sub-pixels is connected to a gate line, and each gate line is connected to an output end of at least one of the shift register units.
  • the display area is further provided with a black matrix, and the black matrix is located on the periphery of the display unit to form a curved edge of the display area.
  • each of the shift register units includes: a cascade line connected to the output end of the shift register unit of the current stage and the first control end of the shift register unit of the previous stage, so The cascading lines are distributed along the first edge of the shift register unit in this stage.
  • each of the shift register units further includes: an input unit, a pull-down unit, a pull-down control unit, an output unit, and an output control unit;
  • the input unit writes the signal at the input end in response to the signal at the input end pulling down the node, writing the signal of the first voltage terminal into the pull-up node in response to the signal of the first control terminal, and writing the signal of the second voltage terminal into the pull-up node in response to the signal of the second control terminal;
  • the output control unit in response to the signal of the second control terminal
  • the signal of the first clock terminal writes the signal of the third voltage terminal into the output terminal;
  • the output unit writes the signal of the second clock terminal into the output terminal in response to the control of the output control unit and the pull-up node;
  • the pull-down control unit The pull-down unit writes the signal of the third voltage terminal into the pull-down node in response to the control of the pull-down control node and the pull-up node.
  • the input unit includes: a first transistor, a second transistor, and a third transistor, the gate of the first transistor is connected to the second control terminal, the first electrode of the first transistor is connected to the second voltage terminal, and the first transistor is connected to the second control terminal.
  • the second pole of a transistor is connected to the pull-up node, the gate of the second transistor and the first pole are connected to the input terminal, the second pole of the second transistor is connected to the pull-down node, the gate of the third transistor is connected to the first control terminal, and the third transistor is connected to the first control terminal.
  • the first electrode of the transistor is connected to the pull-up node, and the second electrode of the first receiving transistor is connected to the first voltage terminal.
  • the output control unit includes: a fourth transistor and a fifth transistor, the gate of the fourth transistor is connected to the pull-down node, the first electrode of the fourth transistor is connected to the output terminal, and the second electrode of the fourth transistor is connected to the pull-down node
  • the third voltage terminal the gate of the fifth transistor is connected to the first clock terminal, the first pole of the fifth transistor is connected to the output terminal, and the second pole of the fifth transistor is connected to the third voltage terminal.
  • the output unit includes: a sixth transistor and a storage capacitor, the gate of the sixth transistor is connected to the pull-up node, the first pole of the sixth transistor is connected to the second clock terminal, and the second pole of the sixth transistor The output terminal is connected, the first pole of the storage capacitor is connected to the pull-up node, and the second pole of the storage capacitor is connected to the output terminal.
  • the pull-down control unit includes: a seventh transistor and an eighth transistor, the gate and first electrode of the seventh transistor are connected to the first clock terminal, the second electrode of the seventh transistor is connected to the pull-down control node, and the seventh transistor is connected to the pull-down control node.
  • the gates of the eight transistors are connected to the pull-down control node, the first electrodes of the eighth transistors are connected to the first clock terminal, and the second electrodes of the eighth transistors are connected to the pull-down nodes.
  • the pull-down unit includes: a ninth transistor, a tenth transistor, and an eleventh transistor, the gate of the ninth transistor is connected to the pull-down node, the first electrode of the ninth transistor is connected to the pull-up node, and the ninth transistor
  • the second pole of the tenth transistor is connected to the third voltage terminal
  • the gate of the tenth transistor is connected to the pull-up node
  • the first pole of the tenth transistor is connected to the pull-down control node
  • the second pole of the tenth transistor is connected to the third voltage terminal
  • the eleventh transistor The gate of the eleventh transistor is connected to the pull-up node
  • the first pole of the eleventh transistor is connected to the pull-down node
  • the second pole of the eleventh transistor is connected to the third voltage terminal.
  • the technical solution adopted to solve the technical problems of the embodiments of the present disclosure is a display panel including the above-mentioned array substrate.
  • FIG. 1 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure
  • FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the disclosure.
  • Fig. 3 is a partial enlarged view in Fig. 2;
  • FIG. 4 is a schematic partial structure diagram of an array substrate according to an embodiment of the disclosure.
  • FIG. 5 is a schematic partial structure diagram of an array substrate according to an embodiment of the disclosure.
  • FIG. 6 is a schematic diagram of a partial structure of an array substrate according to an embodiment of the disclosure.
  • FIG. 7 is a circuit structure diagram of a shift register unit of an array substrate according to an embodiment of the disclosure.
  • FIG. 8 is a structural diagram of a pixel driving circuit of an array substrate according to an embodiment of the disclosure.
  • the reference signs are: 1, display area; 11, sub-pixel; 2, peripheral area; 21, curve edge; 22, curve segment; 23, tangent point; 3, shift register unit; 31, first edge; 32, second edge; 33, cascade line; Gate, gate line; Data, data line; 51, input unit; 52, pull-down unit; 53, pull-down control unit; 54, output unit; 55, output control unit; 6 , integrated chip; 7, flexible circuit board; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor Transistor; T8, the eighth transistor; T9, the ninth transistor; T10, the tenth transistor; T11, the eleventh transistor; T12, the twelfth transistor; T13, the thirteenth transistor; T14, the fourteenth transistor; T15, Fifteenth transistor; T16, sixteenth transistor; T17, seventeenth transistor; T18, eighteenth transistor; C, storage capacitor; C1 first capacitor; D, light-emitting device; S
  • an embodiment of the present disclosure provides an array substrate having a display area 1 and a peripheral area 2 surrounding the display area 1 .
  • a plurality of sub-pixels 11 arranged in an array are arranged in the display area 1 , each row of sub-pixels 11 is connected to a gate line Gate, and each column of sub-pixels 11 is connected to a data line Data. Wherein, as shown in FIG.
  • the plurality of sub-pixels 11 may include sub-pixels 11 of three different colors; for example, red sub-pixels R, green sub-pixels G, and blue sub-pixels B;
  • the color of the sub-pixels 11 may be determined according to the color of the light-emitting device in each sub-pixel 11; for example: the light emitted by the light-emitting device in the sub-pixel 11 is red light, in this case, the sub-pixel 11 It is called the red sub-pixel R; of course, if the light-emitting colors of each light-emitting device in the display substrate are the same, for example, the light emitted by each light-emitting device is white light, at this time, according to the display panel to which the display substrate is applied, The color of the color filter on the color filter substrate opposite to the display substrate depends on the color; for example, if the color of the color filter on the color filter substrate corresponding to a sub-pixel 11 is red, the sub-pixel 11 is called a red sub-
  • the display substrate includes a plurality of columns of data lines Data, and a plurality of rows of gate lines Gate, the gate lines Gate and the data lines Data are crossed and arranged at the intersection.
  • the sub-pixels 11 are defined at the positions; wherein, the sub-pixels 11 located in the same column have the same color, and each adjacent three sub-pixels 11 in the row direction constitute a pixel, and the three sub-pixels 11 in each pixel are respectively red sub-pixels R, green sub-pixel G, blue sub-pixel B; each sub-pixel 11 located in the same row is connected to the same gate line Gate, and each sub-pixel 11 located in the same column is connected to the same data line Data (wherein, the red sub-pixels located in the same column are connected to the same data line Data).
  • the data line Data connected to the subpixel R is Data11, the data line Data12 connected to the green subpixel G located in the same column, and the data line Data13 connected to the blue subpixel B located in the same column);
  • the gate scanning signal is provided by the first-stage shift register unit 3 (for example, the 6-stage shift register unit 3 is illustrated in FIG. 1 , namely GOA1-GOA6, GOA1 provides the gate scanning signal for the gate line Gate of the first row).
  • a plurality of cascaded shift register units 3 are arranged in the peripheral area 2 .
  • the shift register unit 3 is divided into two parts, which are respectively arranged in cascade on the left and right sides of the display area 1 .
  • each gate line Gate is connected to two shift register units 3 .
  • the two shift register units 3 connected to each gate line Gate may be connected to the two ends of the gate line Gate respectively (for example, the left and right ends of the gate line Gate of the first row are respectively connected to a GOA1); of course,
  • the shift register unit 3 can also be connected at the middle position of the gate line Gate, or any other position.
  • the entire signal line of the received signal can be The voltage has better uniformity, which can reduce the voltage difference between the signal received at the end close to the shift register unit 3 and the signal received at the end far from the shift register unit 3 due to the wire resistance of the signal line itself.
  • each shift register unit 3 is connected together in a cascade manner; specifically, except for the first and last level shift register units 3, the signal output terminal Gate(n of the Nth shift register unit 3 ) is connected to the first control terminal Gate(n+1) of the N-1st stage shift register unit 3, and the signal output terminal Gate(n) of the Nth stage shift register unit 3 is connected to the N+1st stage shift register unit 3
  • each shift register unit 3 located on both sides of the display area 1 are arranged in a stepped shape, and each shift register unit 3 has a rectangular structure, which leads to a comparison of the occupied area of the peripheral area 2 Therefore, it is difficult to form an array substrate with a narrow frame.
  • multiple wires such as ground wires, signal wires, etc. located in the peripheral area 2 need manual wiring by staff , resulting in a complicated preparation process of the array substrate, thereby increasing the preparation cost.
  • an embodiment of the present disclosure provides an array substrate having a display area 1 and a peripheral area 2 surrounding the display area 1 .
  • the area 1 includes a curved edge 21, and a plurality of shift register units 3 are arranged in the peripheral area 2, wherein, at a position corresponding to the curved edge 21 of the display area 1, any adjacent shift register units 3 are arranged in rotation relative to each other , so that the extension direction of the first edge 31 of the shift register unit 3 is parallel to the outer tangent of the curved edge 21 or consistent with the extension direction of the curved edge 21 , and the first edge 31 is the inner part of the shift register unit 3 close to the curved edge 21 edge.
  • At least part of the edge of the display area 1 is a curved edge 21 , so that a special-shaped display area 1 can be formed;
  • any adjacent shift register units 3 located on the periphery of the curved edge 21 are rotated relative to each other, that is, the first edge of the shift register units 3 located on the periphery of the curved edge 21 31 is set based on the curvature of the curved edge 21 .
  • the inner edge of each shift register unit 3 close to the curved edge 21 is the first edge 31 of the shift register unit 3 , that is, the first edge 31 of the shift register unit 3 is the closest to the shift register unit 3 Display area 1 edge.
  • the first edges 31 of the shift register cells 3 located at the periphery of the curved edge 21 are arranged based on the curvature of the curved edge 21 .
  • the arrangement of the first edge 31 of the shift register unit 3 is divided into two cases:
  • the extending direction of the first edge 31 of the shift register unit 3 is parallel to the outer tangent of the curved edge 21 .
  • the first edge 31 of the shift register unit 3 is a straight line, as shown in FIG.
  • the extending direction of the first edge 31 of the shift register unit 3 is consistent with the extending direction of the curved edge 21 . That is to say, the first edge 31 of the shift register unit 3 is a curve, and the curvature of the curve and its corresponding partial curve edge 21 are close to or the same, as shown in FIG. 5 and FIG. 6 .
  • the extending direction of the first edge 31 of the shift register unit 3 is parallel to the outer tangent of the curved edge 21 or Consistent with the extending direction of the curved edge 21 .
  • the distribution of the shift register units 3 shown in FIG. The peripheral area 2 is narrower, so that a display panel with a narrow frame can be formed.
  • each shift register unit 3 in the peripheral area 2 can be adjusted based on the curvature of the curved edge 21 .
  • Wires (such as ground wire GND, common voltage wire Vcom, etc.) can be set, and the wires of all shift register units 3 can be laid out through the same wiring formula or program, thereby greatly simplifying the preparation process of the array substrate and greatly reducing the The fabrication cost of the array substrate increases the fabrication efficiency of the array substrate.
  • the curved edge 21 includes a plurality of curved segments 22 , each shift register unit 3 corresponds to one curved segment 22 , and the first edge 31 of each shift register unit 3
  • the extension direction of is consistent with the extension direction of the corresponding curve segment 22 .
  • the first edge 31 of the shift register unit 3 is a curve. Since different parts of the curved edge 21 may have different curvatures, the extension directions corresponding to different positions of the curved edge 21 may also be different. The first edge 31 of each shift register unit 3 only needs to be consistent with the extending direction of the part of the curved edge 21 at the corresponding position to achieve the effect of reducing the area of the peripheral region 2 .
  • the curve The portion of the edge 21 corresponding to the shift register unit 3 is divided into a plurality of curve segments 22, and each shift register unit 3 corresponds to one curve segment 22, so that only the extension of the first edge 31 of each shift register unit 3 is required
  • the effect of reducing the area of the peripheral region 2 can be achieved by making the direction consistent with the extending direction of the corresponding curve segment 22 .
  • each shift register unit 3 When the extending direction of the first edge 31 of each shift register unit 3 is consistent with the extending direction of the corresponding curved segment 22, the distribution of each shift register unit 3 can be further fitted to the curved edge 21 of the display area 1, As a result, the peripheral area 2 is made narrower, so that a display panel with a narrower frame can be formed.
  • the curve edge 21 includes a plurality of tangent points 23 , the tangent points 23 correspond to the shift register units 3 one-to-one, and each tangent point 23 is the curve edge 21 to the corresponding shift point 23 .
  • the first edge 31 of each shift register unit 3 is parallel to the tangent of the curved edge 21 at the corresponding tangent point 23 .
  • the first edge 31 of the shift register unit 3 is a straight line. Since different parts of the curved edge 21 may have different curvatures, the directions of the circumtangent lines corresponding to different positions of the curved edge 21 may also be different. The first edge 31 of each shift register unit 3 only needs to be parallel to the outer tangent of the closer position to achieve the effect of reducing the area of the peripheral region 2 .
  • the curved edge 21 is selected A plurality of tangent points 23, and each tangent point 23 is the closest point of the curve edge 21 to its corresponding shift register unit 3, so only the first edge 31 of each shift register unit 3 and the corresponding tangent point are required
  • the effect of reducing the area of the peripheral area 2 can be achieved if the tangent lines from 23 are parallel.
  • each shift register unit 3 When the first edge 31 of each shift register unit 3 is parallel to the tangent of the curved edge 21 at the corresponding tangent point 23 , the distribution of each shift register unit 3 can be further fitted to the curved edge 21 of the display area 1 , thereby The peripheral area 2 is made narrower, so that a display panel with a narrower frame can be formed.
  • each shift register unit 3 further includes a second edge 32 opposite to the first edge 31 , and the extension direction of the second edge 32 and the curved edge 21 is the same as the curved edge The outer tangents of 21 are parallel.
  • the edge of the shift register unit 3 is the edge of the shift register unit 3 away from the display area 1, that is, the second edge 32 is the edge of the shift register unit 3 closest to the outer edge of the peripheral area 2, so the second edge 32
  • the shape is also an important factor in determining the size of the surrounding area 2.
  • the extending directions of the second edge 32 and the curved edge 21 are parallel to the outer tangent of the curved edge 21 , that is, when the first edge 31 is parallel to the outer tangent of the curved edge 21 , the second edge 32 is parallel to the first edge 31 .
  • the shift register unit 3 when the second edge 32 is parallel to the first edge 31 , the shift register unit 3 also has two third edges connecting the second edge 32 and the first edge 31 , and the third edge may be connected to the first edge 31 .
  • the vertical edge 31 makes the shift register unit 3 a rectangle, as shown in FIG. 3 ; the third edge may not be vertical to the first edge 31 , so that the shift register unit 3 is a trapezoid or other suitable shape.
  • each shift register unit 3 can be further fitted to the curved edge 21 of the display area 1 , thereby making the peripheral area 2 more Narrow, and thus can form a display panel with a narrower frame.
  • each shift register unit 3 further includes a second edge 32 opposite to the first edge 31 , and the second edge 32 is consistent with the extension direction of the curved edge 21 .
  • the extending directions of the second edge 32 and the curved edge 21 are consistent with the extending direction of the curved edge 21 , that is, when the extending directions of the first edge 31 and the curved edge 21 are consistent, the second edge 32 and the first The extending directions of the edges 31 are the same, as shown in FIG. 6 .
  • each shift register unit 3 can be further fitted with the curved edge 21 of the display area 1, thereby making the peripheral area 2 narrower, and further narrower border of the display panel.
  • the shape of the curved edge 21 is any one of a circular arc shape and an elliptical arc shape. It should be noted that, the shape of the curved edge 21 may also be an irregular arc shape required in an actual display panel, which will not be listed one by one here.
  • the extension direction of the center lines of the plurality of shift register units 3 is consistent with the extension direction of the curved edge 21 .
  • the arrangement trend is consistent with the trend of the extension direction of the curve edge 21, so that the distribution of the plurality of shift register units 3 can match the curve edge of the display area 1.
  • 21 is further attached, so that the peripheral area 2 is narrower, so that a display panel with a narrower frame can be formed.
  • the display unit includes a plurality of sub-pixels 11 arranged in an array, each row of sub-pixels 11 is connected to a gate line Gate, and each gate line Gate is connected to the output end Gate(n) of at least one shift register unit 3 .
  • a plurality of sub-pixels 11 arranged in an array are arranged in the display area 1 , each row of sub-pixels 11 is connected to a gate line Gate, and each column of sub-pixels 11 is connected to a data line Data.
  • the plurality of sub-pixels 11 may include sub-pixels 11 of three different colors; for example, red sub-pixels R, green sub-pixels G, and blue sub-pixels B.
  • Each sub-pixel 11 includes at least a pixel circuit; as shown in FIG. 8, an exemplary pixel circuit is given, which includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a tenth transistor The five transistors T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the first capacitor C1, and the light-emitting device D; wherein, the first pole of the twelfth transistor T12 is connected to the initial voltage signal terminal Vint, The second electrode of the twelfth transistor T12 is connected to the second end of the first capacitor C1, the first electrode of the thirteenth transistor T13 and the control electrode of the fourteenth transistor T14, and the control electrode of the twelfth transistor T12 is connected to the reset signal end Reset; the second pole of the thirteenth transistor T13 is connected to the second pole of the fourteenth transistor T14 and the first pole of the seventeenth transistor T17, and the control pole of the thirteenth transistor T13
  • the light-emitting device D may be a current-type light-emitting diode, and further, may be a current-type inorganic light-emitting diode, such as a micro light-emitting diode (Micro Light Emitting Diode, Micro LED) or a mini light-emitting diode (Mini Light Emitting Diode, Mini LED),
  • the light-emitting device D in the disclosed embodiment may also be an organic light-emitting diode (Organic Light Emitting Diode, OLED).
  • One of the first electrode and the second electrode of the light emitting device D is an anode, and the other is a cathode.
  • the display area 1 is further provided with a black matrix, and the black matrix is located at the periphery of the display unit to form the curved edge 21 of the display area 1 .
  • each sub-pixel 11 since the shape of each sub-pixel 11 is a rectangle, and each sub-pixel 11 is arranged in an array, the edge of the display unit cannot form a curved edge 21, so it is necessary to set a black matrix in the display area 1 near the curved edge 21 to form a display
  • the curved edge 21 of the area 1 that is to say at least part of the edge of the black matrix located in the display area 1, coincides with the curved edge 21 of the display area 1.
  • the curved edge 21 of the display area 1 can also be formed by other structures in the display area 1 , such as the connecting lines of the display area 1 .
  • a plurality of shift register units 3 are arranged at intervals in the peripheral area 2, and the plurality of shift register units 3 are cascaded.
  • the signal output terminal Gate(n) of the shift register unit 3 of the Nth stage is connected to the first control terminal Gate of the shift register unit 3 of the N-1st stage (n+1), the signal output terminal Gate(n) of the Nth stage shift register unit 3 is connected to the second control terminal Gate(n-1) of the N+1st stage shift register unit 3, wherein N is greater than 1 Integer.
  • the display substrate is a double-sided driving type display substrate, that is, a row of sub-pixels 11 is driven by two shift register units 3 , and correspondingly, a row of sub-pixels 11 corresponds to two shift register units 3 .
  • the row of sub-pixels 11 is connected to a gate line Gate
  • the signal output terminals Gate(n) of the two shift register units 3 are respectively connected to both ends of the gate line Gate
  • the two The signal output terminals Gate(n) of the shift register are also respectively connected to both ends of the gate line Gate, that is, the first register and the second register are arranged in a one-to-one correspondence.
  • the gate line Gate can be provided with a gate scan signal through the other.
  • the two shift register units 3 may also be located in the middle area of the display substrate.
  • the first shift register unit is located between two columns of sub-pixels 11 and drives two gate lines of the same row.
  • the shift register unit 3 is located between the sub-pixels 11 of different columns. The position of the shift register unit 3 is not limited in any way in the embodiment of the present disclosure.
  • each shift register unit 3 includes: a cascade line 33 , the output terminal Gate(n) of the shift register unit 3 of the current stage and the shift register unit 3 of the previous stage
  • the first control terminal Gate(n+1) of , and the cascade line 33 is distributed along the first edge 31 of the shift register unit 3 of the current stage.
  • the cascade line 33 connects the signal output terminal Gate(n) of the Nth stage shift register unit 3 to the first control terminal Gate(n+1) of the N ⁇ 1th stage shift register unit 3 .
  • the cascade line 33 is distributed along the first edge 31 of the shift register unit 3 of this stage, and is equivalent to the cascade line 33 of the shift register unit 3 being parallel to the outer tangent of the part corresponding to the curved edge 21 or the part corresponding to the curved edge 21 The extending directions of the s are consistent, so that the cascade line 33 is used to define the first edge 31 of the shift register unit 3 .
  • each shift register unit 3 also includes other signal lines, such as clock lines, etc., other signal lines can be arranged on the side of the cascade line 33 away from the display area 1, preferably, the extension direction of the other signal lines Consistent with the extending direction of the cascade line 33 .
  • each shift register unit 3 further includes: an input unit 51 , a pull-down unit 52 , a pull-down control unit 53 , an output unit 54 , and an output control unit 55 .
  • the n-th stage shift register unit 3 will be used for description.
  • the input unit 51 writes the signal of the input end STV to the pull-down node PD in response to the signal of the input end STV, and writes the signal of the first voltage end VSD to the upper node in response to the signal of the first control end Gate(n+1). Pulling the node PU, and writing the signal of the second voltage terminal VDS into the pull-up node PU in response to the signal of the second control terminal Gate(n-1).
  • the output control unit 55 writes the signal of the third voltage terminal VGL to the output terminal Gate(n) in response to the signal of the first clock terminal CLKB.
  • the output unit 54 writes the signal of the second clock terminal CLK into the output terminal Gate(n) in response to the control of the output control unit 55 and the pull-up node PU.
  • the pull-down control unit 53 writes the signal of the first clock terminal CLKB into the pull-down control node PD-CN in response to the signal of the first clock terminal CLKB.
  • the pull-down unit 52 writes the signal of the third voltage terminal VGL into the pull-down node PD in response to the control of the pull-down control node PD-CN and the pull-up node PU.
  • the input unit 51 includes: a first transistor T1, a second transistor T2, and a third transistor T3, the gate of the first transistor T1 is connected to the second control terminal Gate(n-1), and the first pole of the first transistor T1 connected to the second voltage terminal VDS, the second pole of the first transistor T1 is connected to the pull-up node PU, the gate and first pole of the second transistor T2 are connected to the input terminal STV, the second pole of the second transistor T2 is connected to the pull-down node PD, The gate of the third transistor T3 is connected to the first control terminal Gate(n+1), the first pole of the third transistor T3 is connected to the pull-up node PU, and the second pole of the third transistor T3 is connected to the first voltage terminal VSD.
  • the output control unit 55 includes: a fourth transistor T4, a fifth transistor T5, the gate of the fourth transistor T4 is connected to the pull-down node PD, the first pole of the fourth transistor T4 is connected to the output terminal Gate(n), and the first electrode of the fourth transistor T4 is connected.
  • the diode is connected to the third voltage terminal VGL
  • the gate of the fifth transistor T5 is connected to the first clock terminal CLKB
  • the first electrode of the fifth transistor T5 is connected to the output terminal Gate(n)
  • the second electrode of the fifth transistor T5 is connected to the third Voltage terminal VGL.
  • the output unit 54 includes: a sixth transistor T6 and a storage capacitor C, the gate of the sixth transistor T6 is connected to the pull-up node PU, the first pole of the sixth transistor T6 is connected to the second clock terminal CLK, and the second pole of the sixth transistor T6
  • the output terminal Gate(n) is connected, the first pole of the storage capacitor C is connected to the pull-up node PU, and the second pole of the storage capacitor C is connected to the output terminal Gate(n).
  • the pull-down control unit 53 includes: a seventh transistor T7 and an eighth transistor T8, the gate and first pole of the seventh transistor T7 are connected to the first clock terminal CLKB, and the second pole of the seventh transistor T7 is connected to the pull-down control node PD-CN, The gate of the eighth transistor T8 is connected to the pull-down control node PD-CN, the first electrode of the eighth transistor T8 is connected to the first clock terminal CLKB, and the second electrode of the eighth transistor T8 is connected to the pull-down node PD.
  • the pull-down unit 52 includes: a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, the gate of the ninth transistor T9 is connected to the pull-down node PD, the first electrode of the ninth transistor T9 is connected to the pull-up node PU, and the ninth transistor T9
  • the second pole of T9 is connected to the third voltage terminal VGL
  • the gate of the tenth transistor T10 is connected to the pull-up node PU
  • the first pole of the tenth transistor T10 is connected to the pull-down control node PD-CN
  • the second pole of the tenth transistor T10 is connected to the pull-down control node PD-CN.
  • the third voltage terminal VGL, the gate of the eleventh transistor T11 is connected to the pull-up node PU, the first pole of the eleventh transistor T11 is connected to the pull-down node PD, and the second pole of the eleventh transistor T11 is connected to the third voltage terminal VGL.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. There is absolutely no difference.
  • one electrode is called the first electrode
  • the other electrode is called the second electrode
  • the gate electrode is called the control electrode.
  • transistors can be divided into N-type and P-type.
  • the first pole is the source of the P-type transistor
  • the second pole is the drain of the P-type transistor, and when the gate is input low level , the source and drain are turned on
  • the first pole is the source of the N-type transistor
  • the second pole is the drain of the N-type transistor, and when the gate is input with a high level, the source and drain are turned on.
  • the transistors in the pixel circuit and the first data selector below are described by taking N-type transistors as an example. It is conceivable that the implementation of P-type transistors can be realized by those skilled in the art without creative work.
  • the transistors in the first pole register below are all described by taking P-type transistors as an example, and it is conceivable that the implementation of N-type transistors is in the art Those skilled in the art can come up with ideas without creative efforts, and therefore also fall within the protection scope of the embodiments of the present disclosure.
  • the array substrate of the embodiment of the present disclosure further includes an integrated chip 6 and a flexible circuit board 7 located in the peripheral area 2, which are respectively connected to the display unit and used for providing signals to the display unit.
  • an embodiment of the present disclosure provides a display panel including the above-mentioned array substrate.
  • the display panel can be a liquid crystal display panel, an organic light emitting diode (OLED) display panel, electronic paper, mobile phone, tablet computer, TV, monitor, notebook computer, digital photo frame, navigator, etc. any product with display function or part.
  • OLED organic light emitting diode

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Abstract

本公开实施例的一种阵列基板，具有显示区和围设在所述显示区***的周边区，所述显示区中设置有显示单元，所述显示区包括曲线边缘，所述周边区中设置有多个级联的移位寄存器单元，其中，在与所述显示区的曲线边缘对应的位置，任意相邻的所述移位寄存器单元相对于彼此旋转设置，以使所述移位寄存器单元的第一边缘的延伸方向与所述曲线边缘的外切线平行或与所述曲线边缘的延伸方向一致，所述第一边缘为所述移位寄存器单元靠近所述曲线边缘的内边缘。

Description

阵列基板和显示面板 技术领域
本公开实施例属于显示技术领域，具体涉及一种阵列基板和显示面板。
背景技术
随着显示技术的不断发展，用户不仅对显示面板的显示效果的要求不断提高，对显示面板的形状的要求也不断提高，从而使得显示面板的种类也不断增多。目前市场出现多种异形显示面板，并且异形显示面板现已应用到手表、手机或智能手环等的电子设备中。具体的，常见的异形显示面板的形状为扇形、弧形、多边形等。其中，显示面板至少包括位于显示区的显示单元以及位于周边区的阵列排布的移位寄存器单元，移位寄存器单元用于向显示单元提供驱动信号，以使显示面板形成显示画面。
然而，针对异形显示面板，由于其显示区的边缘为曲线边缘，使得周边区也为异型区，多个移位寄存器单元若采用现有的排布方式会增加移位寄存器单元的占用区域的面积，从而不易形成窄边框的异形显示面板。
发明内容
本公开实施例至少部分解决现有的异形显示面板的边框宽的问题，提供一种能够形成窄边框的异形显示面板的阵列基板。
解决本公开实施例技术问题所采用的技术方案是一种阵列基板，具有显示区和围设在所述显示区***的周边区，所述显示区中设置有显示单元，所述显示区包括曲线边缘，所述周边区中设置有多个级联移位寄 存器单元，其中，在与所述显示区的曲线边缘对应的位置，任意相邻的所述移位寄存器单元相对于彼此旋转设置，以使所述移位寄存器单元的第一边缘的延伸方向与所述曲线边缘的外切线平行或与所述曲线边缘的延伸方向一致，所述第一边缘为所述移位寄存器单元靠近所述曲线边缘的内边缘。
在一些实施例中，所述曲线边缘包括多个曲线段，每个所述移位寄存器单元对应一个所述曲线段，每个所述移位寄存器单元的所述第一边缘的延伸方向与对应的所述曲线段的延伸方向一致。
在一些实施例中，所述曲线边缘包括多个切线点，所述切线点与所述移位寄存器单元一一对应，每个所述切线点为所述曲线边缘到对应所述移位寄存器单元的距离最小的点，每个所述移位寄存器单元的所述第一边缘平行于所述曲线边缘在对应所述切线点的切线。
在一些实施例中，每个所述移位寄存器单元还包括与所述第一边缘相对的第二边缘，所述第二边缘与的延伸方向与所述曲线边缘的外切线平行。
在一些实施例中，每个所述移位寄存器单元还包括与所述第一边缘相对的第二边缘，所述第二边缘与所述曲线边缘的延伸方向一致。
在一些实施例中，所述曲线边缘的形状为圆弧状、椭圆弧状中的任意一种。
在一些实施例中，多个所述移位寄存器单元的中心连线的延伸方向与所述曲线边缘的延伸方向一致。
在一些实施例中，多个所述移位寄存器单元在所述周边区间隔排布。
在一些实施例中，所述显示单元包括多个阵列排布的子像素，每行所述子像素连接一条栅线，每条栅线连接至少一个所述移位寄存器单元的输出端。
在一些实施例中，所述显示区中还设置有黑矩阵，所述黑矩阵位于 所述显示单元的***，以形成所述显示区的曲线边缘。
在一些实施例中，每个所述移位寄存器单元包括：级联线，与本级所述移位寄存器单元的输出端以及上一级所述移位寄存器单元的第一控制端连接，所述级联线沿本级所述移位寄存器单元的第一边缘分布。
在一些实施例中，每个所述移位寄存器单元还包括：输入单元、下拉单元、下拉控制单元、输出单元、输出控制单元；所述输入单元，响应于输入端的信号将输入端的信号写入下拉节点、响应于第一控制端的信号将第一电压端的信号写入上拉节点、以及响应于第二控制端的信号将第二电压端的信号写入上拉节点；所述输出控制单元，响应于第一时钟端的信号将第三电压端的信号写入输出端；所述输出单元，响应于所述输出控制单元和上拉节点的控制将第二时钟端的信号写入输出端；所述下拉控制单元，响应于第一时钟端的信号将第一时钟端的信号写入下拉控制节点；所述下拉单元，响应于所述下拉控制节点和上拉节点的控制将第三电压端的信号写入下拉节点。
在一些实施例中，所述输入单元包括：第一晶体管、第二晶体管、第三晶体管，第一晶体管的栅极连接第二控制端，第一晶体管的第一极连接第二电压端，第一晶体管的第二极连接上拉节点，第二晶体管的栅极和第一极连接输入端，第二晶体管的第二极连接下拉节点，第三晶体管的栅极连接第一控制端，第三晶体管的第一极连接上拉节点，第收纳晶体管的第二极连接第一电压端。
在一些实施例中，所述输出控制单元包括：第四晶体管、第五晶体管，第四晶体管的栅极连接下拉节点，第四晶体管的第一极连接输出端，第四晶体管的第二极连接第三电压端，第五晶体管的栅极连接第一时钟端，第五晶体管的第一极连接输出端，第五晶体管的第二极连接第三电压端。
在一些实施例中，所述输出单元包括：第六晶体管和存储电容，第 六晶体管的栅极连接上拉节点，第六晶体管的第一极连接第二时钟端，第六晶体管的第二极连接输出端，存储电容的第一极连接上拉节点，存储电容的第二极连接输出端。
在一些实施例中，所述下拉控制单元包括：第七晶体管和第八晶体管，第七晶体管的栅极和第一极连接第一时钟端，第七晶体管的第二极连接下拉控制节点，第八晶体管的栅极连接下拉控制节点，第八晶体管的第一极连接第一时钟端，第八晶体管的第二极连接下拉节点。
在一些实施例中，所述下拉单元包括：第九晶体管、第十晶体管、第十一晶体管，第九晶体管的栅极连接下拉节点，第九晶体管的第一极连接上拉节点，第九晶体管的第二极连接第三电压端，第十晶体管的栅极连接上拉节点，第十晶体管的第一极连接下拉控制节点，第十晶体管的第二极连接第三电压端，第十一晶体管的栅极连接上拉节点，第十一晶体管的第一极连接下拉节点，第十一晶体管的第二极连接第三电压端。
解决本公开实施例技术问题所采用的技术方案是一种显示面板，包括上述的阵列基板。
附图说明
附图是用来提供对本公开实施例的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开实施例，但并不构成对本公开实施例的限制。在附图中：
图1为本公开实施例的一种阵列基板的结构示意图；
图2为本公开实施例的一种阵列基板的结构示意图；
图3为图2中的局部放大图；
图4为本公开实施例的一种阵列基板的局部结构示意图；
图5为本公开实施例的一种阵列基板的局部结构示意图；
图6为本公开实施例的一种阵列基板的局部结构示意图；
图7为本公开实施例的一种阵列基板的移位寄存器单元的电路结构图；
图8为本公开实施例的一种阵列基板的像素驱动电路结构图；
其中，附图标记为：1、显示区；11、子像素；2、周边区；21、曲线边缘；22、曲线段；23、切线点；3、移位寄存器单元；31、第一边缘；32、第二边缘；33、级联线；Gate、栅线；Data、数据线；51、输入单元；52、下拉单元；53、下拉控制单元；54、输出单元；55、输出控制单元；6、集成芯片；7、柔性线路板；T1、第一晶体管；T2、第二晶体管；T3、第三晶体管；T4、第四晶体管；T5、第五晶体管；T6、第六晶体管；T7、第七晶体管；T8、第八晶体管；T9、第九晶体管；T10、第十晶体管；T11、第十一晶体管；T12、第十二晶体管；T13、第十三晶体管；T14、第十四晶体管；T15、第十五晶体管；T16、第十六晶体管；T17、第十七晶体管；T18、第十八晶体管；C、存储电容；C1第一电容；D、发光器件；STV、输入端；PD、下拉节点；PU、上拉节点；PD-CN、下拉控制节点；Gate(n+1)、第一控制端；Gate(n-1)、第二控制端；VSD、第一电压端；VDS、第二电压端；VGL、第三电压端；CLKB、第一时钟端；CLK、第二时钟端；Gate(n)、输出端；Reset、复位信号端；VDD、第一电源电压端；EM、发光控制线；Vref、电压信号端；VSS、第二电源电压端。
具体实施方式
为使本领域技术人员更好地理解本公开实施例的技术方案，下面结合附图和具体实施方式对本公开实施例作进一步详细描述。
以下将参照附图更详细地描述本公开实施例。在各个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的各个部分没有按比例绘制。此外，在图中可能未示出某些公知的部分。
在下文中描述了本公开实施例的许多特定的细节，例如部件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本公开实施例。但正如本领域的技术人员能够理解的那样，可以不按照这些特定的细节来实现本公开实施例。
如图1所示，本公开实施例提供了一种阵列基板，具有显示区1和围设在显示区1***的周边区2。
在显示区1中设置有多个呈阵列排布的子像素11，每行子像素11连接一条栅线Gate，每列子像素11连接一条数据线Data。其中，如图1所示，多个子像素11可以包括三种不同颜色的子像素11；例如包括红色子像素R、绿色子像素G、蓝色子像素B；在此需要说明的，在本公开实施例中子像素11的颜色可以是根据每个子像素11中的发光器件的颜色而定的；例如：子像素11中的发光器件所发出的光为红光，此时则将该子像素11称之为红色子像素R；当然，若显示基板中的各个发光器件的发光颜色均相同，例如各个发光器件所发出的光均为白光，此时，则根据应用该显示基板的显示面板中，与该显示基板相对设置的彩膜基板中彩膜的颜色而定；例如：某一子像素11所对应的彩膜基板上彩膜的颜色为红色，则将该子像素11称之为红色子像素R。
其中，如图1所示，给出一种示例性的显示基板的具体结构；该显示基板包括多列数据线Data、多行栅线Gate，栅线Gate和数据线Data交叉设置，并在交叉位置处限定出子像素11；其中，位于同一列的子像素11的颜色相同，沿行方向每相邻的三个子像素11构成一个像素，每个像素中的三个子像素11分别为红色子像素R、绿色子像素G、蓝色子像素B；位于同一行的各个子像素11连接同一条栅线Gate，位于同一列的各个子像素11连接同一条数据线Data(其中，位于同一列的红色子像素R所连接的数据线Data为Data11，位于同一列的绿色子像素G所连接的数据线Data12，位于同一列的蓝色子像素B所连接的数据线Data13)；任一行栅线Gate的栅扫描信号由一级移位寄存器单元3(例如，图1中示意了6级移位寄存器单元3，即GOA1-GOA6，GOA1为第 一行栅线Gate提供栅扫描信号)所提供。
在周边区2设置有多个级联的移位寄存器单元3，具体的，移位寄存器单元3分为两部分分别设置在显示区1左右两边级联。如图1所示，以双边驱动为例，也即，每一条栅线Gate连接两个移位寄存器单元3。具体的，每条栅线Gate所连接的两个移位寄存器单元3可以分别连接在该栅线Gate的两端(例如：第一行栅线Gate的左右两端分别连接一个GOA1)；当然，移位寄存器单元3也可以连接在该条栅线Gate的中间位置，或者其它任何位置。在本公开实施例中，由于采用双边驱动，相比于单边驱动，即一条栅线Gate只与一个移位寄存器单元3连接的实施例，能够使接收信号的整根信号线上各处的电压具有较好的均一性，而能够减缓由于信号线本身线阻而出现靠近移位寄存器单元3一端接收到的信号和远离移位寄存器单元3一端接收到的信号存在电压差的情况。其中，对于各个移位寄存器单元3采用级联的方式连接在一起；具体的，除第一级和最后一级移位寄存器单元3以外，第N级移位寄存器单元3信号输出端Gate(n)连接第N-1级移位寄存器单元3的第一控制端Gate(n+1)，第N级移位寄存器单元3信号输出端Gate(n)连接第N+1级移位寄存器单元3的第二控制端Gate(n-1)，其中N为大于1的整数，如图8所示。
具体的，如图1所示，位于显示区1两侧的是移位寄存器单元3呈阶梯状排布，且每个移位寄存器单元3呈矩形结构，这样就导致周边区2的占用面积比较大，从而不易形成窄边框的阵列基板。此外，由于每个移位寄存器单元3与显示区1的相对位置不同，且为了适应周边区2的形状，位于周边区2的多条导线(如接地线、信号线等)需要工作人员手动布线，从而导致阵列基板的制备过程复杂，从而增加制备成本。
第一方面，如图2至图8所示，本公开实施例提供一种阵列基板，具有显示区1和围设在显示区1***的周边区2，显示区1中设置有显示单元，显示区1包括曲线边缘21，周边区2中设置有多个移位寄存器单元3，其中，在与显示区1的曲线边缘21对应的位置，任意相邻的移位寄存器单元3相对于彼此旋转设置，以使移位寄存器单元3的第一边 缘31的延伸方向与曲线边缘21的外切线平行或与曲线边缘21的延伸方向一致，第一边缘31为移位寄存器单元3靠近曲线边缘21的内边缘。
其中，也就是说显示区1的至少部分边缘为曲线边缘21，从而可以形成异形的显示区1；而至少部分移位寄存器单元3设置在曲线边缘21的***。
为了减少周边区2的宽度，本实施例中将位于曲线边缘21***的任意相邻的移位寄存器单元3相对于彼此旋转设置，即位于曲线边缘21***的移位寄存器单元3的第一边缘31基于曲线边缘21的曲率而设置。具体的，每个移位寄存器单元3靠近曲线边缘21的内边缘为该移位寄存器单元3的第一边缘31，即移位寄存器单元3的第一边缘31为该移位寄存器单元3最靠近显示区1的边缘。
位于曲线边缘21***的移位寄存器单元3的第一边缘31基于曲线边缘21的曲率排布。移位寄存器单元3的第一边缘31的排布方式分为两种情况：
第一种情况，移位寄存器单元3的第一边缘31的延伸方向与曲线边缘21的外切线平行。其中，也就是说移位寄存器单元3的第一边缘31为直线，如图3(其中图3为图2中虚线框部分的局部放大图)和图4所示。
第二种情况，移位寄存器单元3的第一边缘31的延伸方向与曲线边缘21的延伸方向一致。其中，也就是说移位寄存器单元3的第一边缘31为曲线，且该曲线与其对应的部分曲线边缘21的曲率接近或者相同，如图5和图6所示。
如图2所示，本公开实施例的阵列基板中，在与显示区1的曲线边缘21对应的位置，移位寄存器单元3的第一边缘31的延伸方向与曲线边缘21的外切线平行或与曲线边缘21的延伸方向一致。与如图1所示的阵列基板中的周边区2相比，图2中所示的移位寄存器单元3的分布与显示区1的曲线边缘21更贴合，从而使得图2中阵列基板的周边区2更窄，进而能够形成窄边框的显示面板。
此外，如图2所示，由于本公开实施例的阵列基板中的各个移位寄 存器单元3与显示区1的边缘的相对位置相近或者相同，从而可基于曲线边缘21的曲率对位于周边区2的导线(如接地线GND、公共电压线Vcom等)进行设置，以及可通过同一布线公式或者程序对所有移位寄存器单元3的导线进行布设，从而大大简化阵列基板的制备的过程，大大减小阵列基板的制备成本，增加阵列基板的制备效率。
在一些实施例中，如图5和图6所示，曲线边缘21包括多个曲线段22，每个移位寄存器单元3对应一个曲线段22，每个移位寄存器单元3的第一边缘31的延伸方向与对应的曲线段22的延伸方向一致。
其中，也就是说移位寄存器单元3的第一边缘31为曲线。由于曲线边缘21的不同部分可以具有不同的曲率，因此，曲线边缘21的不同位置对应的延伸方向也可不同。而每个移位寄存器单元3的第一边缘31只需与其对应位置的那部分曲线边缘21的延伸方向一致即可达到减小周边区2面积的效果，因此，本公开实施例中，将曲线边缘21与移位寄存器单元3对应的部分分为多个曲线段22，且每个移位寄存器单元3对应一个曲线段22，这样只需要每个移位寄存器单元3的第一边缘31的延伸方向与对应的曲线段22的延伸方向一致即可达到减小周边区2面积的效果。
当每个移位寄存器单元3的第一边缘31的延伸方向与对应的曲线段22的延伸方向一致，能够使得每个移位寄存器单元3的分布与显示区1的曲线边缘21进一步贴合，从而使得周边区2更窄，进而能够形成更窄边框的显示面板。
在一些实施例中，如图3和图4所示，曲线边缘21包括多个切线点23，切线点23与移位寄存器单元3一一对应，每个切线点23为曲线边缘21到对应移位寄存器单元3的距离最小的点，每个移位寄存器单元3的第一边缘31平行于曲线边缘21在对应切线点23的切线。
其中，也就是说移位寄存器单元3的第一边缘31为直线。由于曲线边缘21的不同部分可以具有不同的曲率，因此，曲线边缘21的不同位置对应的外切线的方向也可不同。而每个移位寄存器单元3的第一边缘31只需与其较近位置的外切线平行即可达到减小周边区2面积的效果， 因此，本公开实施例中，将在曲线边缘21选定多个切线点23，且每个切线点23分别为曲线边缘21距离其对应的移位寄存器单元3最近的点，这样只需要每个移位寄存器单元3的第一边缘31与对应的切线点23出的切线平行即可达到减小周边区2面积的效果。
当每个移位寄存器单元3的第一边缘31平行于曲线边缘21在对应切线点23的切线，能够使得每个移位寄存器单元3的分布与显示区1的曲线边缘21进一步贴合，从而使得周边区2更窄，进而能够形成更窄边框的显示面板。
在一些实施例中，如图3和图5所示，每个移位寄存器单元3还包括与第一边缘31相对的第二边缘32，第二边缘32与曲线边缘21的延伸方向与曲线边缘21的外切线平行。
其中，移位寄存器单元3的边缘为该移位寄存器单元3远离显示区1的边缘，即第二边缘32为移位寄存器单元3最靠近周边区2的外边缘的边缘，因此第二边缘32的形状也是决定周边区2面积大小的重要因素。
如图3和图5所示，本公开实施例中，第二边缘32与曲线边缘21的延伸方向与曲线边缘21的外切线平行，也即当第一边缘31与曲线边缘21的外切线平行时，第二边缘32与第一边缘31平行。
需要说明的是，当第二边缘32与第一边缘31平行时，移位寄存器单元3还具有将第二边缘32与第一边缘31连接的两个第三边缘，第三边缘可与第一边缘31垂直使得移位寄存器单元3为矩形，如图3所示；第三边缘也可不与第一边缘31垂直，使得移位寄存器单元3为梯形或者是其他适合的形状。
当第二边缘32与曲线边缘21的延伸方向与曲线边缘21的外切线平行，能够使得每个移位寄存器单元3的分布与显示区1的曲线边缘21进一步贴合，从而使得周边区2更窄，进而能够形成更窄边框的显示面板。
在一些实施例中，如图4和图6所示，每个移位寄存器单元3还包括与第一边缘31相对的第二边缘32，第二边缘32与曲线边缘21的延伸方向一致。
本公开实施例中，第二边缘32与曲线边缘21的延伸方向与曲线边缘21的延伸方向一致，也即当第一边缘31与曲线边缘21的延伸方向一致时，第二边缘32与第一边缘31的延伸方向一致，如图6所示。
当第二边缘32与曲线边缘21的延伸方向一致，能够使得每个移位寄存器单元3的分布与显示区1的曲线边缘21进一步贴合，从而使得周边区2更窄，进而能够形成更窄边框的显示面板。
在一些实施例中，曲线边缘21的形状为圆弧状、椭圆弧状中的任意一种。需要说明的是，曲线边缘21的形状也可以是实际显示面板中所需要的不规则弧状，此处不再一一列举。
在一些实施例中，多个移位寄存器单元3的中心连线的延伸方向与曲线边缘21的延伸方向一致。
其中，也就是说对于多个移位寄存器单元3而言，其排布趋势与曲线边缘21的延伸方向的趋势一致，这样能够使得多个移位寄存器单元3的分布与显示区1的曲线边缘21进一步贴合，从而使得周边区2更窄，进而能够形成更窄边框的显示面板。
在一些实施例中，显示单元包括多个阵列排布的子像素11，每行子像素11连接一条栅线Gate，每条栅线Gate连接至少一个移位寄存器单元3的输出端Gate(n)。
如图2所示，在显示区1中设置有多个呈阵列排布的子像素11，每行子像素11连接一条栅线Gate，每列子像素11连接一条数据线Data。其中，多个子像素11可以包括三种不同颜色的子像素11；例如包括红色子像素R、绿色子像素G、蓝色子像素B。
每个子像素11中均至少包括像素电路；如图8所示，给出一种示例性的像素电路，其包括：第十二晶体管T12、第十三晶体管T13、第十四晶体管T14、第十五晶体管T15、第十六晶体管T16、第十七晶体管T17、第十八晶体管T18、第一电容C1，以及发光器件D；其中，第十二晶体管T12的第一极连接初始电压信号端Vint，第十二晶体管T12的第二极连接第一电容C1的第二端、第十三晶体管T13的第一极和第十四晶体管T14的控制极，第十二晶体管T12的控制极连接复位信号端 Reset；第十三晶体管T13的第二极连接第十四晶体管T14的第二极和第十七晶体管T17的第一极，第十三晶体管T13的控制极连接栅线Gate；第十四晶体管T14的第一极连接第一电源电压端VDD；第十五晶体管T15的第一极连接数据线Data，第十五晶体管T15的第二极连接第十六晶体管T16的第二极、第十八晶体管T18的第二极和第一电容C1的第一极；第十五晶体管T15的控制极连接栅线Gate；第十六晶体管T16的第一极连接基准电压信号端Vref，第十六晶体管T16的控制极连接发光控制线EM；第十七晶体管T17的第二极连接发光器件D的第一极，第十七晶体管T17的控制极连接发光控制线EM；第十八晶体管T18的第一极连接基准电压信号端Vref，第十八晶体管T18的控制极连接复位信号端Reset，发光器件的第二极连接第二电源电压端VSS。
其中，发光器件D可以是电流型发光二极管，进一步地，可以为电流型无机发光二极管，如微型发光二极管(Micro Light Emitting Diode，Micro LED)或者迷你发光二极管(Mini Light Emitting Diode，Mini LED)，当然，在公开实施例中的发光器件D还可以是有机电致发光二极管(Organic Light Emitting Diode，OLED)。发光器件D的第一极和第二极中的一者为阳极，另一者为阴极。
在一些实施例中，显示区1中还设置有黑矩阵，黑矩阵位于显示单元的***，以形成显示区1的曲线边缘21。
其中，由于各个子像素11的形状为矩形，且各个子像素11呈阵列排布，因此显示单元的边缘不能形成曲线边缘21，则需要在显示区1靠近曲线边缘21设置黑矩阵，以形成显示区1的曲线边缘21，也就是说位于显示区1中的黑矩阵的至少部分边缘与显示区1的曲线边缘21重合。
需要说明的是，可也通过显示区1其中的其他结构形成显示区1的曲线边缘21，如显示区1的连接线等。
在一些实施例中，多个移位寄存器单元3在周边区2间隔排布，且多个移位寄存器单元3级联。
具体的，除第一级和最后一级移位寄存器单元3以外，第N级移位 寄存器单元3信号输出端Gate(n)连接第N-1级移位寄存器单元3的第一控制端Gate(n+1)，第N级移位寄存器单元3信号输出端Gate(n)连接第N+1级移位寄存器单元3的第二控制端Gate(n-1)，其中N为大于1的整数。
在一些实施例中，显示基板为双边驱动型显示基板，也即，一行子像素11由两个移位寄存器单元3进行驱动，相应的，一行子像素11对应两个移位寄存器单元3。具体的，以一行子像素11为例，该行子像素11连接一条栅线Gate，两个移位寄存器单元3的信号输出端Gate(n)分别连接在该栅线Gate的两端，两个移位寄存器的信号输出端Gate(n)同样分别连接在该栅线Gate的两端，也即，第一位寄存器与第二寄存器一一对应设置。这样一来，若位于栅线Gate两端的移位寄存器中的一者损坏，则可以通过另一者为该栅线Gate提供栅扫描信号。当然，在本公开实施例中两个移位寄存器单元3也可以位于显示基板的中间区域，例如：第一位移寄存器单元位于两列子像素11之间，且驱动同一行的栅线Gate的两个移位寄存器单元3位于不同列的子像素11之间。在本公开实施例中并不对移位寄存器单元3的位置做任何限定。
在一些实施例中，如图3所示，每个移位寄存器单元3包括：级联线33，与本级移位寄存器单元3的输出端Gate(n)以及上一级移位寄存器单元3的第一控制端Gate(n+1)连接，级联线33沿本级移位寄存器单元3的第一边缘31分布。
其中，也就是说级联线33将第N级移位寄存器单元3信号输出端Gate(n)与第N-1级移位寄存器单元3的第一控制端Gate(n+1)连接。级联线33沿本级移位寄存器单元3的第一边缘31分布，相当于移位寄存器单元3的级联线33与对应曲线边缘21的部分的外切线平行或与对应曲线边缘21的部分的延伸方向一致，使得级联线33用于限定该移位寄存器单元3的第一边缘31。
需要说明的是，每个移位寄存器单元3还包括其他信号线，如时钟线等，其他信号线可设置在级联线33远离显示区1的一侧，优选的，其他信号线的延伸方向与级联线33的延伸方向一致。
在一些实施例中，如图7所示，每个移位寄存器单元3还包括：输入单元51、下拉单元52、下拉控制单元53、输出单元54、输出控制单元55。以下以第n级移位寄存器单元3进行说明。
其中，输入单元51，响应于输入端STV的信号将输入端STV的信号写入下拉节点PD、响应于第一控制端Gate(n+1)的信号将第一电压端VSD的信号写入上拉节点PU、以及响应于第二控制端Gate(n-1)的信号将第二电压端VDS的信号写入上拉节点PU。
输出控制单元55，响应于第一时钟端CLKB的信号将第三电压端VGL的信号写入输出端Gate(n)。
输出单元54，响应于输出控制单元55和上拉节点PU的控制将第二时钟端CLK的信号写入输出端Gate(n)。
下拉控制单元53，响应于第一时钟端CLKB的信号将第一时钟端CLKB的信号写入下拉控制节点PD-CN。
下拉单元52，响应于下拉控制节点PD-CN和上拉节点PU的控制将第三电压端VGL的信号写入下拉节点PD。
如图7所述，给出了一种示例性的移位寄存器单元3。具体的，输入单元51包括：第一晶体管T1、第二晶体管T2、第三晶体管T3，第一晶体管T1的栅极连接第二控制端Gate(n-1)，第一晶体管T1的第一极连接第二电压端VDS，第一晶体管T1的第二极连接上拉节点PU，第二晶体管T2的栅极和第一极连接输入端STV，第二晶体管T2的第二极连接下拉节点PD，第三晶体管T3的栅极连接第一控制端Gate(n+1)，第三晶体管T3的第一极连接上拉节点PU，第三晶体管T3的第二极连接第一电压端VSD。
输出控制单元55包括：第四晶体管T4、第五晶体管T5，第四晶体管T4的栅极连接下拉节点PD，第四晶体管T4的第一极连接输出端Gate(n)，第四晶体管T4的第二极连接第三电压端VGL，第五晶体管T5的栅极连接第一时钟端CLKB，第五晶体管T5的第一极连接输出端Gate(n)，第五晶体管T5的第二极连接第三电压端VGL。
输出单元54包括：第六晶体管T6和存储电容C，第六晶体管T6 的栅极连接上拉节点PU，第六晶体管T6的第一极连接第二时钟端CLK，第六晶体管T6的第二极连接输出端Gate(n)，存储电容C的第一极连接上拉节点PU，存储电容C的第二极连接输出端Gate(n)。
下拉控制单元53包括：第七晶体管T7和第八晶体管T8，第七晶体管T7的栅极和第一极连接第一时钟端CLKB，第七晶体管T7的第二极连接下拉控制节点PD-CN，第八晶体管T8的栅极连接下拉控制节点PD-CN，第八晶体管T8的第一极连接第一时钟端CLKB，第八晶体管T8的第二极连接下拉节点PD。
下拉单元52包括：第九晶体管T9、第十晶体管T10、第十一晶体管T11，第九晶体管T9的栅极连接下拉节点PD，第九晶体管T9的第一极连接上拉节点PU，第九晶体管T9的第二极连接第三电压端VGL，第十晶体管T10的栅极连接上拉节点PU，第十晶体管T10的第一极连接下拉控制节点PD-CN，第十晶体管T10的第二极连接第三电压端VGL，第十一晶体管T11的栅极连接上拉节点PU，第十一晶体管T11的第一极连接下拉节点PD，第十一晶体管T11的第二极连接第三电压端VGL。
需要说明的是，本公开实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本公开实施例中，为区分晶体管的源极和漏极，将其中一极称为第一极，另一极称为第二极，栅极称为控制极。此外按照晶体管的特性区分可以将晶体管分为N型和P型，当采用P型晶体管时，第一极为P型晶体管的源极，第二极为P型晶体管的漏极，栅极输入低电平时，源漏极导通；当采用N型晶体管时，第一极为N型晶体管的源极，第二极为N型晶体管的漏极，栅极输入高电平时，源漏极导通。其中，下述的像素电路和第一数据选择器中的晶体管均是以N型晶体管为例进行说明的，可以想到的是采用P型晶体管实现是本领域技术人员可以在没有付出创造性劳动前提下想到的，因此也是在本公开实施例的保护范围内的；下述的第一极为寄存器中的晶体管均是以P型晶体管为例进行说明的，可以想到的是采用N型晶体 管实现是本领域技术人员可以在没有付出创造性劳动前提下想到的，因此也是在本公开实施例的保护范围内的。
需要说明的是，本公开实施例的阵列基板还包括位于周边区2的集成芯片6和柔性线路板7，分别于显示单元连接，用于给显示单元提供信号。
第二方面，本公开实施例提供一种显示面板，包括上述的阵列基板。
具体的，该显示面板可为液晶显示面板、有机发光二极管(OLED)显示面板、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
应当说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括要素的过程、方法、物品或者设备中还存在另外的相同要素。
依照本公开实施例的实施例如上文所述，这些实施例并没有详尽叙述所有的细节，也不限制该公开实施例仅为所述的具体实施例。显然，根据以上描述，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本公开实施例的原理和实际应用，从而使所属技术领域技术人员能很好地利用本公开实施例以及在本公开实施例基础上的修改使用。本公开实施例仅受权利要求书及其全部范围和等效物的限制。

Claims (18)

  1. 一种阵列基板，其中，具有显示区和围设在所述显示区***的周边区，所述显示区中设置有显示单元，所述显示区包括曲线边缘，所述周边区中设置有多个级联的移位寄存器单元，
    其中，在与所述显示区的曲线边缘对应的位置，任意相邻的所述移位寄存器单元相对于彼此旋转设置，以使所述移位寄存器单元的第一边缘的延伸方向与所述曲线边缘的外切线平行或与所述曲线边缘的延伸方向一致，所述第一边缘为所述移位寄存器单元靠近所述曲线边缘的内边缘。
  2. 根据权利要求1所述的阵列基板，其中，所述曲线边缘包括多个曲线段，每个所述移位寄存器单元对应一个所述曲线段，每个所述移位寄存器单元的所述第一边缘的延伸方向与对应的所述曲线段的延伸方向一致。
  3. 根据权利要求1所述的阵列基板，其中，所述曲线边缘包括多个切线点，所述切线点与所述移位寄存器单元一一对应，每个所述切线点为所述曲线边缘到对应所述移位寄存器单元的距离最小的点，每个所述移位寄存器单元的所述第一边缘平行于所述曲线边缘在对应所述切线点的切线。
  4. 根据权利要求1所述的阵列基板，其中，每个所述移位寄存器单元还包括与所述第一边缘相对的第二边缘，所述第二边缘的延伸方向与所述曲线边缘的外切线平行。
  5. 根据权利要求1所述的阵列基板，其中，每个所述移位寄存器单元还包括与所述第一边缘相对的第二边缘，所述第二边缘与所述曲线边 缘的延伸方向一致。
  6. 根据权利要求1所述的阵列基板，其中，所述曲线边缘的形状为圆弧状、椭圆弧状中的任意一种。
  7. 根据权利要求1所述的阵列基板，其中，多个所述移位寄存器单元的中心连线的延伸方向与所述曲线边缘的延伸方向一致。
  8. 根据权利要求1所述的阵列基板，其中，多个所述移位寄存器单元在所述周边区间隔排布。
  9. 根据权利要求1所述的阵列基板，其中，所述显示单元包括多个阵列排布的子像素，每行所述子像素连接一条栅线，每条栅线连接至少一个所述移位寄存器单元的输出端。
  10. 根据权利要求1所述的阵列基板，其中，所述显示区中还设置有黑矩阵，所述黑矩阵位于所述显示单元的***，以形成所述显示区的曲线边缘。
  11. 根据权利要求1所述的阵列基板，其中，每个所述移位寄存器单元包括：级联线，与本级所述移位寄存器单元的输出端以及上一级所述移位寄存器单元的第一控制端连接，所述级联线沿本级所述移位寄存器单元的第一边缘分布。
  12. 根据权利要求11所述的阵列基板，其中，每个所述移位寄存器单元还包括：输入单元、下拉单元、下拉控制单元、输出单元、输出控制单元；
    所述输入单元，响应于输入端的信号将输入端的信号写入下拉节点、响应于第一控制端的信号将第一电压端的信号写入上拉节点、以及响应于第二控制端的信号将第二电压端的信号写入上拉节点；
    所述输出控制单元，响应于第一时钟端的信号将第三电压端的信号写入输出端；
    所述输出单元，响应于所述输出控制单元和上拉节点的控制将第二时钟端的信号写入输出端；
    所述下拉控制单元，响应于第一时钟端的信号将第一时钟端的信号写入下拉控制节点；
    所述下拉单元，响应于所述下拉控制节点和上拉节点的控制将第三电压端的信号写入下拉节点。
  13. 根据权利要求12所述的阵列基板，其中，所述输入单元包括：第一晶体管、第二晶体管、第三晶体管，第一晶体管的栅极连接第二控制端，第一晶体管的第一极连接第二电压端，第一晶体管的第二极连接上拉节点，第二晶体管的栅极和第一极连接输入端，第二晶体管的第二极连接下拉节点，第三晶体管的栅极连接第一控制端，第三晶体管的第一极连接上拉节点，第三晶体管的第二极连接第一电压端。
  14. 根据权利要求12所述的阵列基板，其中，所述输出控制单元包括：第四晶体管、第五晶体管，第四晶体管的栅极连接下拉节点，第四晶体管的第一极连接输出端，第四晶体管的第二极连接第三电压端，第五晶体管的栅极连接第一时钟端，第五晶体管的第一极连接输出端，第五晶体管的第二极连接第三电压端。
  15. 根据权利要求12所述的阵列基板，其中，所述输出单元包括：第六晶体管和存储电容，第六晶体管的栅极连接上拉节点，第六晶体管的第一极连接第二时钟端，第六晶体管的第二极连接输出端，存储电容 的第一极连接上拉节点，存储电容的第二极连接输出端。
  16. 根据权利要求12所述的阵列基板，其中，所述下拉控制单元包括：第七晶体管和第八晶体管，第七晶体管的栅极和第一极连接第一时钟端，第七晶体管的第二极连接下拉控制节点，第八晶体管的栅极连接下拉控制节点，第八晶体管的第一极连接第一时钟端，第八晶体管的第二极连接下拉节点。
  17. 根据权利要求12所述的阵列基板，其中，所述下拉单元包括：第九晶体管、第十晶体管、第十一晶体管，第九晶体管的栅极连接下拉节点，第九晶体管的第一极连接上拉节点，第九晶体管的第二极连接第三电压端，第十晶体管的栅极连接上拉节点，第十晶体管的第一极连接下拉控制节点，第十晶体管的第二极连接第三电压端，第十一晶体管的栅极连接上拉节点，第十一晶体管的第一极连接下拉节点，第十一晶体管的第二极连接第三电压端。
  18. 一种显示面板，其中，包括权利要求1至17中任意一项所述的阵列基板。
PCT/CN2021/123178 2020-11-27 2021-10-12 阵列基板和显示面板 WO2022111081A1 (zh)

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