WO2022067584A1 - 显示基板及显示装置 - Google Patents
显示基板及显示装置 Download PDFInfo
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- WO2022067584A1 WO2022067584A1 PCT/CN2020/119095 CN2020119095W WO2022067584A1 WO 2022067584 A1 WO2022067584 A1 WO 2022067584A1 CN 2020119095 W CN2020119095 W CN 2020119095W WO 2022067584 A1 WO2022067584 A1 WO 2022067584A1
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Definitions
- the embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular, relate to a display substrate and a display device.
- OLED Organic Light Emitting Diode
- VR virtual reality
- some circuits for driving sub-pixels may be directly disposed outside the display area of the display substrate. Obviously, the area where the driving circuit is located cannot be directly displayed, so it corresponds to the "frame" of the display device.
- An embodiment of the present disclosure provides a display substrate including a display area and a peripheral area, the peripheral area includes a circuit area, and the display area includes: a plurality of sub-pixels, a plurality of data lines extending along a first direction, and a plurality of along the a gate line extending in a second direction crossing the first direction, each of the data lines is connected to a plurality of the sub-pixels, and each of the gate lines is connected to a plurality of the sub-pixels;
- the circuit area includes a first sub-area and a second sub-area opposite to both sides of the display area along the first direction, the circuit area includes a plurality of driving unit groups, and the first sub-area includes a plurality of a multiplexing unit group, the second sub-area includes a plurality of test unit groups, the multiplexing unit group includes at least one multiplexing unit, the test unit group includes at least one test unit, the driving unit The group includes at least one drive unit configured to provide drive signals to the gate lines, the multiplexing unit configured to provide data signals to the data lines, and the test unit configured to provide the data signals to the gate lines The data line provides the test signal;
- the driving unit groups and the multiplexing unit groups are alternately arranged; in the second sub-area, the driving unit groups and the test unit groups are alternately arranged.
- the circuit region further includes a connection subregion located between the first subregion and the second subregion, the connection subregion configured to electrically connect the the first subregion and the second subregion;
- the circuit area further includes a signal line protection unit, the signal line protection unit is located on a side of the connection sub-area away from the display area and is electrically connected to the signal lines of the circuit area.
- the signal line protection unit includes at least one polysilicon resistor
- the circuit region further includes a plurality of signal lines, each of the at least one polysilicon resistor is connected between at least two of the signal lines .
- the signal line includes a test signal line connected to the test unit and a drive signal line connected to the drive unit, the drive signal line includes a high-level line and a low-level line,
- the test signal line includes a test control line and a test data line, and at least one of the polysilicon resistors is connected to the test control line and the high-level line.
- the signal line includes a multiplexed signal line connected with the multiplexing unit and a test signal line connected with the test unit, the test signal line including a test control line and a test data
- the multiplexed signal line includes a multiplexed control line and a multiplexed data line, and at least one of the polysilicon resistors is connected to the test control line and the multiplexed control line.
- the signal line protection unit includes at least one electrostatic discharge unit
- the signal line includes a multiplexed signal line connected to the multiplexing unit, a test signal line connected to the test unit and a driving signal line connected with the driving unit, each of the at least one electrostatic discharge unit is connected with one signal line.
- the driving signal lines include high-level lines and low-level lines
- the test signal lines include test control lines and test data lines
- the multiplexed signal lines include multiplexed control lines and multiplexed control lines.
- the number C of multiplexing units included in the multiplexing unit group between two adjacent driving unit groups is the same as the number C of adjacent driving unit groups.
- the size of the gap D between the two drive unit groups satisfies the following relationship:
- a is the size of each multiplexing unit along the arrangement direction of the multiplexing units
- d1 is the size of the gap between the adjacent multiplexing units
- the number E of test units included in the test unit group between two adjacent driving unit groups and the gap F between the two adjacent driving unit groups satisfies the following relationship:
- b is the size of each test unit along the arrangement direction of the test units
- d2 is the size of the gap between adjacent test units.
- d1 is 1 to 5 microns and d2 is 1 to 5 microns.
- the first subregion includes a first circular arc region
- the second subregion includes a second circular arc region
- the driving unit groups and the multiplexing unit groups are alternately arranged, specifically: in the first arc area, the driving unit groups and the multiplexing unit groups are arranged along the The first arc area is alternately arranged near the edge of the display area;
- the drive unit groups and the test unit groups are alternately arranged, specifically: in the second arc area, the drive unit groups and the test unit groups are close to each other along the second arc area The edges of the display area are alternately arranged.
- the connecting line trajectory of the center points of the coverage areas of the plurality of the driving unit groups is the first circular arc trajectory
- the plurality of the multiplexing units The connecting line trajectory of the center points of the coverage area of the group is a second circular arc trajectory, and the center corresponding to the first circular arc trajectory, the circle center corresponding to the second circular arc trajectory and the first circular arc area are close to the The centers of the circles corresponding to the edges of the display area are approximately coincident; and/or
- the line locus connecting the center points of the coverage areas of the plurality of driving unit groups is a third circular arc trajectory
- the line connecting the center points of the coverage areas of the multiple test unit groups The trajectory is a fourth circular arc trajectory, and the center corresponding to the third circular arc trajectory and the circular center corresponding to the fourth circular arc trajectory substantially coincide with the circular center corresponding to the edge of the second circular arc area close to the display area.
- the first arc area is a semicircle
- the second arc area is a semicircle
- the first sub-region includes a first U-ring region
- the second sub-region includes a second U-ring region
- the first U-ring region includes two segments of the first A circular arc area and at least a section of a second rectangular area
- the second U-shaped ring area includes two sections of the second circular arc area and at least a section of a third rectangular area
- a plurality of the multiplexing units are arranged along one side of the second rectangular area close to the display area;
- a plurality of the test cells are arranged along one side of the third rectangular area close to the display area.
- the circuit area further includes a plurality of first rectangular areas, the first rectangular areas are disposed between the first circular arc area and the second circular arc area;
- a plurality of the driving units are arranged along one side of the first rectangular area close to the display area.
- the multiplexing unit group in the first subregion, includes a first multiplexing unit group and a second multiplexing unit group, the first multiplexing unit group
- the used unit group includes M multiplexing units
- the second multiplexing unit group includes N multiplexing units
- N and M are integers greater than 1, and M ⁇ N
- the second multiplexing unit group includes N multiplexing units.
- the multiplexing unit group is located in the middle of the first sub-area, and the first multiplexing unit group is located at both ends of the first sub-area away from the middle of the first sub-area;
- the test unit group includes a first test unit group and a second test unit group
- the first test unit group includes K test units
- the second test unit group includes L test units Test units
- L and K are integers greater than 1, and K ⁇ L
- the second test unit group is located in the middle of the second sub-area
- the first test unit group is located in the second sub-area away from all the two ends of the middle of the second sub-region.
- the peripheral area further includes a joint area located on a side of the first sub-area away from the display area, the joint area includes a plurality of joints, and at least some of the joints are connected to signal lines;
- the signal lines include: a multiplexed signal line connected to the multiplexing unit, a test signal line connected to the test unit, and a driving signal line connected to the driving unit.
- the peripheral area further includes a fan-out area disposed between the joint area and the first sub-area, and the fan-out area includes a plurality of the multiplexed signal lines.
- the multiplexed signal lines include multiple multiplexed control lines and multiple multiplexed data lines;
- At least one of the multiplexing units includes a plurality of multiplexing transistors; the gate of each multiplexing transistor is connected to one of the multiplexing control lines, the first electrode is connected to one of the data lines, and the second electrode is connected to one of the multiplexing control lines. the multiplexed data line;
- the second poles of all the multiplexing transistors of the same multiplexing unit are connected to the same multiplexing data line, and the second poles of the multiplexing transistors of different multiplexing units are connected to different Describe the multiplexed data line.
- the test signal line includes a test control line and a test data line; at least one of the test units includes a plurality of test transistors; the gate of each test transistor is connected to one of the test control lines, The first pole is connected to one of the data lines, and the second pole is connected to one of the test data lines; each of the test data lines is connected to a plurality of the test cells.
- An embodiment of the present disclosure further provides a display device, including: the display substrate as described in any preceding one.
- FIG. 1 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure
- FIG. 2 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure (some leads are not shown);
- FIG. 3 is a schematic circuit diagram of a pixel circuit in a display substrate provided by an embodiment of the present disclosure
- FIG. 4 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure.
- FIG. 5 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure (some leads are not shown);
- FIG. 6 is a schematic circuit diagram of a multiplexing unit in a display substrate according to an embodiment of the present disclosure
- FIG. 7 is a schematic circuit diagram of a test unit in a display substrate provided by an embodiment of the present disclosure.
- FIG. 8 is a schematic circuit diagram of another test unit in a display substrate provided by an embodiment of the present disclosure.
- FIG. 9 is a circuit diagram of a gate shift register in a display substrate provided by an embodiment of the present disclosure.
- FIG. 10 is a driving timing diagram of a gate shift register in a display substrate according to an embodiment of the present disclosure
- FIG. 11 is a circuit diagram of a gate shift register in a display substrate provided by an embodiment of the present disclosure.
- FIG. 12 is a driving timing diagram of a gate shift register in a display substrate according to an embodiment of the present disclosure.
- FIG. 13 is a schematic partial structural diagram of a connection sub-region in a display substrate according to an embodiment of the present disclosure
- FIG. 14 is a schematic diagram of the distribution density of different units in a display substrate provided by an embodiment of the present disclosure.
- 15 is a schematic diagram of the distribution density of different units in another display substrate provided by an embodiment of the present disclosure.
- 16 is a schematic circuit diagram of an electrostatic discharge unit in a display substrate according to an embodiment of the present disclosure
- 17 is a schematic partial structural diagram of a compensation capacitor unit in a display substrate provided by an embodiment of the present disclosure.
- Test unit 31, Test transistor; 311, First test transistor; 312, Second test transistor; 313, Third test transistor; 314, Fourth test transistor; 315, Fifth test transistor;
- Driving unit 41. Gate driving unit; 42. Control electrode driving unit;
- 91 display area; 92, circuit area; 921, first sub area; 922, second sub area; 923, connection sub area; 93, fan-out area; 94, joint area; 95, capacitor area; 991, first direction; 992, second direction;
- T1 the first transistor; T2, the second transistor; T3, the third transistor; T4, the fourth transistor; T5, the fifth transistor; T6, the sixth transistor; T7, the seventh transistor; Cst, the storage capacitor; Reset, the first transistor A reset terminal; Reset', the second reset terminal; Vinit, initialization terminal; Gate, gate line terminal; Data, data line terminal; EM, gate line terminal; VDD, anode signal terminal; VSS; cathode signal terminal ;
- K1 first gate transistor; K2, second gate transistor; K3, third gate transistor; K4, fourth gate transistor; K5, fifth gate transistor; K6, sixth gate transistor; K7, Seventh gate transistor; K8, eighth gate transistor; C1, first gate capacitance; C2, second gate capacitance; N1, first gate node; N2, second gate node; N3, third gate gate node;
- M1 the first gate transistor; M2, the second gate transistor; M3, the third gate transistor; M4, the fourth gate transistor; M5, the fifth gate transistor; M6, the sixth gate transistor; M7, seventh gate transistor; M8, eighth gate transistor; M9, ninth gate transistor; M10, tenth gate transistor; C1', first gate capacitor; C2', second gate capacitor; C3' , the third gate capacitor; N1', the first gate node; N2', the second gate node; N3', the third gate node; N4', the fourth gate node.
- Embodiments of the present disclosure may be described with reference to plan views and/or cross-sectional views with the aid of idealized schematic illustrations of the present disclosure. Accordingly, example illustrations may be modified according to manufacturing techniques and/or tolerances.
- Embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes.
- the regions illustrated in the figures have schematic properties and the shapes of regions illustrated in the figures are illustrative of the specific shapes of regions of elements and are not intended to be limiting.
- ordinal numbers such as “first”, “second”, and “third” are set to avoid confusion of constituent elements, rather than to limit the quantity.
- the terms “installed”, “connected” and “connected” should be interpreted in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
- installed should be interpreted in a broad sense. For example, it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two elements.
- a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
- a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
- the channel region refers to a region through which current mainly flows.
- the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
- the functions of the "source electrode” and the “drain electrode” may be interchanged when using transistors of opposite polarities or when the direction of the current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” may be interchanged with each other.
- electrically connected includes a case where constituent elements are connected together by means of elements having a certain electrical effect.
- the "element having a certain electrical effect” is not particularly limited as long as it can transmit and receive electrical signals between the connected constituent elements.
- Examples of “elements having a certain electrical effect” include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.
- parallel refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, and therefore also includes a state where the angle is -5° or more and 5° or less.
- perpendicular refers to the state where the angle formed by two straight lines is 80° or more and 100° or less, and therefore includes the state where the angle is 85° or more and 95° or less.
- film and “layer” may be interchanged.
- conductive layer may be replaced by “conductive film” in some cases.
- insulating film may be replaced with “insulating layer” in some cases.
- an embodiment of the present disclosure provides a display substrate.
- the display substrate of the embodiment of the present disclosure is a substrate used in a display device, for example, an array substrate provided with a thin film transistor (TFT) array.
- TFT thin film transistor
- the display substrate of the embodiment of the present disclosure includes a display area 91 and a peripheral area surrounding the display area 91, and the peripheral area includes a capacitor area 95, a circuit area 92, a fan-out area 93, and a joint area 94; wherein,
- the display area 91 includes: a plurality of sub-pixels 1; a plurality of data lines 11 extending along a first direction 991, each data line 11 is connected to a plurality of sub-pixels 1; gate lines 12, each gate line 12 is connected to a plurality of sub-pixels 1;
- the circuit area 92 surrounds the display area 91, and the circuit area 92 includes a first sub-area 921 and a second sub-area 922 opposite to both sides of the display area 91 along the first direction 991;
- the first sub-area 921 includes a plurality of multiplexing units group, a plurality of multiplexing unit groups are configured to provide data signals to a plurality of data lines 11, the multiplexing unit group includes at least one multiplexing unit 2;
- the second sub-area 922 includes a plurality of test unit groups, A plurality of test unit groups are configured to provide test signals to a plurality of data lines 11, and the test unit groups include at least one test unit 3;
- the circuit area 92 also includes a plurality of drive unit groups, and the drive unit groups include at least one drive unit 4.
- the driving unit groups and the multiplexing unit groups are alternately arranged along the circumferential direction
- the driving unit groups and the test unit groups are alternately arranged along the circumferential
- the capacitor region 95 is located between the second sub-region 922 and the display region 91, the capacitor region 95 includes a plurality of compensation capacitor units 5, and each compensation capacitor unit 5 is connected to a data line 11;
- the connector area 94 is located on the side of the first sub-area 921 away from the display area 91.
- the connector area 94 includes a plurality of connectors 6, and at least part of the connectors 6 are connected to signal lines; the signal lines include multiplexed signal lines connected to the multiplexing unit 2 62, the test signal line 63 connected with the test unit 3, the drive signal line 64 connected with the drive unit 4;
- the fan-out area 93 is located between the joint area 94 and the first sub-area 921 , and the fan-out area 93 includes a plurality of multiplexed signal lines 62 .
- the display substrate of the embodiment of the present disclosure is divided into a plurality of regions, the display region 91 (or AA region) for displaying is located in the middle, and the sub-regions 91 for displaying are located in the middle.
- the pixel 1 (or called sub-pixel) is arranged in the display area 91 .
- the sub-pixel 1 refers to the smallest structure that can be used to independently display the desired content, that is, the smallest "dot" that can be independently controlled in the display device.
- the specific forms of the sub-pixels 1 are various, as long as independent display can be realized.
- the sub-pixel 1 may include a pixel circuit, and the pixel circuit may emit light with a desired brightness under the control of the corresponding gate line 12, the data line 11, and the like.
- the pixel circuit may be a 7T1C structure (ie, including 7 transistors and 1 capacitor).
- the pixel circuit of the above 7T1C may include a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.
- each transistor can be a P-type transistor (eg PMOS).
- the data line end Data can be connected to the data line 11, the gate line end Gate can be connected to the gate line 12, the gate line end EM can be connected to the gate line 13, the first reset terminal Reset and the second reset terminal Reset'
- the gate lines of the previous row can be connected at the same time, the second reset terminal Reset' can also be connected to the gate lines of the current row, and the other terminals can also be connected to corresponding signal sources.
- an organic light emitting diode OLED can be used as a light emitting device, which is specifically an organic light emitting diode display substrate, which is also an array substrate provided with a thin film transistor (TFT) array.
- TFT thin film transistor
- different sub-pixels 1 can have different colors, so that color display can be realized by light mixing of different sub-pixels 1 .
- a plurality of sub-pixels 1 of different colors arranged together can form a "pixel (or pixel unit)", that is, the light emitted by these sub-pixels 1 is mixed together to form a visual "pixel". point”; for example, three sub-pixels 1 of three colors, red, green, and blue, form one pixel.
- there may be no definite pixels (or pixel units) and color display may be realized by “common” between adjacent sub-pixels 1 .
- the data lines 11 extending along the first direction 991 and the gate lines 12 extending along the second direction 992 are further provided, wherein the first direction 991 is intersected with the second direction 992 (ie not parallel to each other), so that each intersection of the data line 11 and the gate line 12 can define a sub-pixel 1, and the common intersection of the gate line 12 and the data line 11 Control, the sub-pixel 1 at the intersection of the two can be displayed.
- the first direction 991 is perpendicular to the second direction 992 , that is, the first direction 991 may be a column direction (longitudinal in FIG. 1 , FIG. 2 , FIG. 4 , and FIG. 5 ), and the second direction 992 may be the same as The row direction in which the column direction is perpendicular to the row direction (transverse in FIGS. 1, 2, 4, and 5).
- first direction 991 and the second direction 992 are actually only two opposite directions corresponding to the data line 11 and the gate line 12 , which are not necessarily the column direction and the row direction, and are different from the direction of the display substrate (or display device). There is no necessary relationship between the shape, location, placement, etc.
- the sub-pixels 1 in the display area 91 can be arranged in an array, that is, the sub-pixels 1 can be arranged in multiple rows and columns, wherein each row of the sub-pixels 1 is connected to one gate line 12 , and each column of the sub-pixels 1 is connected to A data line 11.
- each data line 11 and each gate line 12 are not necessarily connected to the sub-pixels 1 in the same column and row.
- the area outside the display area 91 is the circuit area 92 surrounding it, so the display area 91 is annular as a whole. Since the peripheral area is not displayed, it corresponds to the "frame" of the display device.
- the peripheral area includes a circuit area 92 surrounding the display area 91, so the circuit area 92 is also annular as a whole, and includes a first sub-area 921 and a second sub-area 922 oppositely arranged on both sides of the display area 91 along the first direction 991, such as The "lower half" and "upper half” in Figure 1 and Figure 2.
- the first sub-area 921 includes a plurality of multiplexing units 2 (MUX), and each multiplexing unit 2 is connected to data lines from one side (the lower side in FIG. 1 , FIG. 2 , FIG. 4 , and FIG.
- the second sub-area 922 includes a plurality of test cells 3 (CT), each test cell 3 from the other side (FIG. 1, FIG. 2, 4 and 5) are connected to the data line 11 for providing a test signal to the data line 11 in the test stage to detect whether the display substrate is defective.
- CT test cells 3
- a plurality of driving units 4 are also provided in the circuit area 92 for providing other driving signals.
- At least some of the driving units 4 are configured to provide driving signals to the gate lines 12 , that is, at least some of the driving units 4 are connected to the above gate lines 12 and are used to provide signals to the gate lines 12 to control and communicate with the gate lines 12 .
- the sub-pixels 1 connected to the corresponding gate lines 12 operate.
- the above multiplexing unit 2 constitutes a plurality of "multiplexing unit groups", and each multiplexing unit group includes one multiplexing unit 2, or multiple multiplexing units arranged continuously 2;
- the test unit 3 constitutes a plurality of "test unit groups”, and each test unit group includes a test unit 3, or a plurality of consecutively arranged test units 3;
- the drive unit 4 constitutes a plurality of "drive unit groups", each The drive unit group includes one drive unit 4 , or a plurality of drive units 4 arranged in series.
- different cells are provided in the circuit area 92, and these cells are "shuffled".
- the driving unit groups and the multiplexing unit groups are alternately arranged along the “circumferential direction”.
- circumferential direction refers to the direction of rotation around the center of the plane figure, or the direction of going around the edge of the figure clockwise or counterclockwise.
- each "group” includes one or more consecutive corresponding units, so that the driving unit 4 and the multiplexing unit 2 in the first sub-area 921 are "shuffled” (but each unit may have a plurality of consecutive units) arranged together)” instead of being concentrated in different positions of the first sub-area 921.
- the driving unit groups and the test unit groups are alternately arranged in the circumferential direction.
- each "group” includes one or more consecutive corresponding units, so that the driving unit 4 and the test unit 3 in the second sub-area 922 are "shuffled” (but each unit may have consecutively arranged together )” instead of being concentrated in different positions of the first sub-area 921.
- the number C of multiplexing units 2 included in the multiplexing unit group between two adjacent driving unit groups is the same as the number C of the multiplexing unit 2 included in the adjacent two driving unit groups.
- the size of the gap D between the drive unit groups satisfies the following relationship:
- a is the size of each multiplexing unit 2 along the arrangement direction of the multiplexing units 2
- d1 is the size of the gap between adjacent multiplexing units 2 .
- the number E of test cells 3 included in the test unit group between two adjacent driving unit groups and the number E between the two adjacent driving unit groups satisfies the following relationship:
- b is the size of each test unit 3 along the arrangement direction of the test units 3
- d2 is the size of the gap between adjacent test units 3 .
- the gap between two adjacent units is 1 ⁇ m to 5 ⁇ m.
- the gap between two adjacent driving units 4 may be 1.5 microns, and the adjacent driving units 4
- the gap between the multiplexing unit 2 and the multiplexing unit 2 may be 1.5 micrometers, and the gap between the adjacent driving unit 4 and the testing unit 3 may be 1.5 micrometers, etc.
- gap refers to the shortest straight-line distance between devices belonging to two adjacent units respectively.
- each circuit in the circuit area 92 also needs a certain signal to work, so the peripheral area also includes a joint area 94 for introducing these signals, the joint area 94 includes a plurality of joints 6, and the joints 6 are connected to signal lines, signal lines It can include multiplexed signal lines 62, test signal lines 63, drive signal lines 64, etc. that supply power to the multiplexing unit 2, test unit 3, and drive unit 4 respectively; of course, each signal line is associated with the corresponding unit and connector. 6 connections.
- the connector 6 (Pad or Pin) refers to a structure in the display substrate that can acquire other signals and introduce signals into signal lines.
- the connector 6 can be used for bonding with a flexible circuit board (FPC) or a driver chip, so as to obtain a signal from the FPC or the driver chip.
- FPC flexible circuit board
- the connector 6 can also be used to make contact with the test probes of the test device to obtain the signal from the test probes.
- the above joint area 94 is provided on the side (ie, the outer side) of the circuit area 92 away from the display area 91 , and a fan-out is also provided between the joint area 94 and the first sub-area 921 Area 93 (Fanout area), the fan-out area 93 includes multiple multiplexed signal lines 62, that is, after the multiplexed signal lines 62 are led out from the joint area 94, they are connected to the corresponding multiplexing unit 2 through the fan-out area 93 .
- the number of the multiplexed signal lines 62 is much more than the sum of the number of the test signal lines 63 and the driving signal lines 64. Therefore, by arranging the fan-out area 93 in the joint area 94 and the number of the multiplexing unit 2 Between a sub-area 921, a large number of multiplexed signal lines 62 can be connected to the multiplexing unit 2 “nearly”; while the driving signal lines 64 and the test signal lines 63 need to extend a long distance before they can be connected to the driving signal line 64 and the test signal line 63 Unit 4 and test unit 3 are connected, but because the number of driving signal lines 64 and test signal lines 63 is small, the total length of the leads will not be too large; thus, the above design can reduce the total length of the leads and the occupied space The layout area is reduced, the frame of the display device is reduced, and the screen ratio is increased.
- some of the driving signal lines 64 and the test signal lines 63 may also be located in the fan-out region 93 .
- a capacitor area 95 is arranged between the area 922 and the display area 91 .
- the capacitor area 95 is provided with a plurality of compensation capacitor units 5 connected to the data lines 11 for compensating for the difference in capacitance of different data lines 11 , the functions of which will be described in detail later.
- each unit (multiplexing unit 2 , testing unit 3 , and driving unit 4 ) in the display substrate according to the embodiment of the present disclosure is shuffled, so that each unit can be directed to the nearest neighbor.
- Corresponding data lines 11, gate lines 12, etc. provide signals; at the same time, various structures are relatively uniformly distributed, making full use of the space at each position of the display substrate, reducing the frame of the display device and increasing the screen ratio.
- the first sub-area 921 includes a first arc area
- the second sub-area 922 includes a second arc area
- the first arc area 921 is closer to the edge of the display area 91 than the second arc area.
- the edge of the display area 92 is closer to the center of the display area 92 .
- the first sub-region 921 and the second sub-region 922 may include “arc-shaped (circular)” portions.
- the main surface of the display substrate may be substantially circular, and the display area 91 may also be substantially circular, so that the circuit area 92 is substantially an annular shape surrounding the circular display area 91, and the first sub-area 921 is substantially circular. and the second sub-region 922 are respectively "half circle” ("upper semicircle” and “lower semicircle” in FIG. 1 and FIG. 2), and the openings of the two are opposite.
- the edge of the first arc area (the first sub-area 921 ) close to the display area 91 is closer to the center of the display area 91 than the edge of the second arc area (the second sub-area 922 ) close to the display area 91 ;
- the inner side of the first circular arc area is “smaller” than the inner side of the second circular arc area, because the capacitor area 95 is also provided in the inner side of the second sub-area 922 .
- the centers of the first circular arc area (the first sub-area 921 ) and the second circular arc area (the second sub-area 922 ) are the same, and the radius ratio of the first circular arc area close to the edge of the display area 91
- the radius of the edge of the second arc region close to the display region 91 is 210-420 ⁇ m smaller.
- the above first circular arc area and the second circular arc area may be "concentric", and the difference between the inner diameters of the two may be 210-420 ⁇ m (the diameter of the first circular arc area is smaller), and further may be 250-420 ⁇ m. 350 ⁇ m.
- the main surface of the display substrate may be one side surface of the substrate thereof, that is, the surface of the substrate of the display substrate in the embodiment of the present disclosure may be circular.
- the substrate is the basis for carrying other structures on the display substrate, which is a basically sheet-like structure composed of materials such as glass, silicon (such as monocrystalline silicon), and polymer materials (such as polyimide). , which can be rigid or flexible, and the thickness can be on the order of millimeters.
- A is basically B means that, on the scale of the whole A, it complies with the feature B, but on a scale that is obviously smaller than the whole of A, A may not completely meet the feature B. of.
- A is substantially circular means that A can be a perfect circle or ellipse, or it can be a circle or ellipse as a whole, but some of its details are not strictly circular: for example, A A small part of the boundary of A may be a straight line, a polyline, etc.; another example, the boundary of A may have some positions with protrusions, depressions, etc.; another example, a small part of the boundary of A may be similar to an arc but not strictly an arc For another example, the boundaries of different positions of A can be circular arcs with different diameters, etc.
- the circuit area 92 when the circuit area 92 is in a “circular shape”, most of its positions correspond to the data lines 11 and the gate lines 12 at the same time (that is, there are corresponding sub-pixels in the row and column directions). 1), so in this case, the multiplexing unit 2, the test unit 3, and the driving unit 4 in the circuit area 92 are arranged in a mixed manner, which is most beneficial for each unit to be connected to the corresponding data line 11, gate line 12, etc.
- the above shape is not a limitation on the specific form of the display substrate and each area therein, and the display substrate and each area therein may also be of other shapes.
- the first sub-region 921 includes a first U-shaped ring region
- the second sub-region 922 includes a second U-shaped ring region.
- the main surface of the display substrate can also be basically a rectangle with arc corners
- the display area 91 is also basically a rectangle with arc corners
- the circuit area 92 is basically a rectangle with arc corners. It is an arc-angled rectangular ring surrounding the circular display area 91 .
- the first sub-region 921 and the second sub-region 922 are respectively “U-shaped rings” (respectively “upper U-shaped ring” and “lower U-shaped ring” in FIG. 4 and FIG. 5 , and the openings of the two are opposite to each other. ), of course the bottom of the U-shaped ring is in the form of a straight line, not an arc.
- arc corner rectangle refers to a shape similar to a rectangle, which has four straight sides, but the difference from a rectangle is that its four corners are not right angles, but relatively uniform transition "arc corners”, which may further be “Rounded Corners”, that is, “Arc Corner Rectangle” can also be “Rounded Corner Rectangle”.
- the circuit area 92 is an “arc corner rectangle ring,” which is an annular area sandwiched between two “arc corner rectangles” of different sizes, so it can also be regarded as a “hollow arc corner rectangle”.
- the circuit area 92 can also be a "rounded rectangular ring” (ie, a "hollow rounded rectangle”).
- the width of the first U-shaped ring region ie the distance between two straight portions of the U shape
- the height of the first U-shaped ring region ie the U The distance from the bottom of the U-shaped ring to its opening
- the height of the second U-shaped ring area is approximately equal to the height of the second U-shaped ring area.
- the size of the first U-shaped ring area and the second U-shaped ring area may be substantially the same, so that the two may be substantially "up and down symmetry".
- the inner edge of the first U-shaped ring area (ie the outer edge of the display area 91 ) includes two first arc-shaped boundaries
- the inner edge of the second U-shaped ring area (ie the outer edge of the display area 91 ) includes two second arc boundaries.
- the inner edge of the circuit area (ie, the outer edge of the display area 91 ) further includes: two first linear boundaries extending along the first direction 991 (each first linear boundary spans the first sub-area 921 and the second sub-area 922 ), a second linear boundary (belonging to the first sub-region 921 ) and a third linear boundary (belonging to the second sub-area 922 ) extending along the second direction 992 .
- the outer edges of the first sub-region 921 and the second sub-region 922 should have substantially similar shapes to their inner edges.
- the distance from the normal direction to the outer edge may be the same, that is, the “width” of each position of the circuit area 91 may be the same.
- a plurality of driving units 4 are arranged along a first linear boundary; in the first sub-area 921, a plurality of multiplexing units 2 are arranged along a The second linear boundary is arranged; in the second sub-area 922, a plurality of test units 3 are arranged along the third linear boundary.
- the driving unit 4 and the multiplexing unit 2 are alternately arranged along the first arc boundary; in the second sub-area 922, the driving unit 4 and the test unit 3 are arranged along the second arc
- the shape boundaries are alternately set.
- the line trajectory of the center points of the coverage areas of the plurality of driving unit groups is a first arc trajectory
- the center points of the coverage areas of the multiplex unit groups are
- the connecting line trajectory of is a second circular arc trajectory
- the circle center corresponding to the first circular arc trajectory, the circle center corresponding to the second circular arc trajectory and the circle center corresponding to the first arc boundary are substantially coincident.
- the circle center corresponding to the first circular arc trajectory and the circle center corresponding to the second circular arc trajectory are substantially coincident with the circle center corresponding to the first arc boundary, which refers to the circle center corresponding to the first circular arc trajectory and the second circular arc
- the center of the circle corresponding to the track and the center of the circle corresponding to the first arc boundary may be completely coincident, or the distance between the centers of the circles may be less than 10 microns.
- the line trajectory connecting the center points of the coverage areas of the multiple driving unit groups is a third circular arc trajectory
- the line connecting the center points of the coverage areas of the multiple test unit groups The trajectory is a fourth circular arc trajectory, the center of the circle corresponding to the third circular arc trajectory, the center of the circle corresponding to the fourth circular arc trajectory and the circle center corresponding to the second arc-shaped boundary substantially coincide.
- the circle center corresponding to the third circular arc trajectory and the circle center corresponding to the fourth circular arc trajectory are substantially coincident with the circle center corresponding to the second arc boundary, which refers to the circle center corresponding to the third circular arc trajectory and the fourth circular arc
- the center of the circle corresponding to the track and the center of the circle corresponding to the second arc boundary may be completely coincident, or the distance between the centers of the circles may be less than 10 microns.
- each type of unit at the corresponding arc-shaped boundary is arranged along a circular trajectory, and the circular trajectories of the two types of units at the same arc-shaped boundary correspond to The circle of , and the corresponding circle of the arc boundary itself, are concentric, or approximately concentric.
- the multiplexing unit group in the first sub-region 921, includes a first multiplexing unit group and a second multiplexing unit group, and the first multiplexing unit group includes M Multiplexing unit 2, the second multiplexing unit group includes N multiplexing units 2, N and M are integers greater than 1, and M ⁇ N, the second multiplexing unit group is located in the first In the middle of the sub-region 921, the first multiplexing unit group is located at both ends of the first sub-region 921 away from the middle of the first sub-region 921;
- the test unit group includes a first test unit group and a second test unit group
- the first test unit group includes K test units 3
- the second test unit group includes L test units, L
- K is an integer greater than 1
- the second test cell group is located in the middle of the second sub-region 922
- the first test cell group is located at both ends of the second sub-region 922 away from the middle of the second sub-region 922 .
- At least one second multiplexing unit group is provided in the middle of the first sub-area 921 (ie, at the arc top of the semi-circle), and each second multiplexing unit group includes N multiplexing units 2 ; And at both ends of the first sub-region 921 (that is, the two ends or the opening side of the semicircle), at least one first multiplexing unit group is provided, and each first multiplexing unit group includes M Multiplexing unit 2, and M is less than N.
- the number of multiplexing units 2 included in the multiplexing unit group (the second multiplexing unit group) is larger in the middle of the first sub-area 921 , and the number of multiplexing units 2 included in the two ends of the first sub-area 921 is larger.
- the number of multiplexing units 2 included in the multiplexing unit group (the first multiplexing unit group) is small. Therefore, from an overall point of view, the number of multiplexing units 2 in the middle of the first sub-area 921 is large and the number of driving units 4 is small, and the number of multiplexing units 2 at both ends of the first sub-area 921 is small and the number of driving units is small.
- the number of units 4 is large.
- N can be 7, or 6, or 5; and in some embodiments, M can be 1, or 2, or 3.
- multiplexing unit groups there may be other multiplexing unit groups between the above first multiplexing unit group and the second multiplexing unit group, and the multiplexing unit groups in these multiplexing unit groups
- the number of multiplexing units may be greater than M and less than N.
- At least one second test unit group is provided in the middle of the second sub-area 922 (ie, at the arc top of the semi-circle), and each second test unit group includes L test units 3; and in the second sub-area 922 At least one first test unit group is provided at the two ends (ie, the two ends or the open side of the semi-circle), and each first test unit group includes K test units 3 , and K is less than L.
- test unit group (the second test unit group) including a larger number of test units 3, while at both ends of the first sub-area 921 there are test unit groups (the first test unit group) group) includes a smaller number of test units 3. Therefore, from the overall point of view, the number of test cells 3 in the middle of the second sub-region 922 is large and the number of driving cells 4 is small, and the number of test cells 3 at both ends of the second sub-region 922 is small and the number of driving cells 4 is large.
- L can be 7, or 6, or 5; and in some embodiments, K can be 1, or 2, or 3.
- test unit groups there may be other test unit groups between the first test unit group and the second test unit group, and the number of test units in these test unit groups may be greater than K but less than L.
- the distribution density of the driving units 4 is gradually reduced, and the multiplexing unit The distribution density of 2 gradually increases;
- the distribution density of the driving units 4 gradually decreases, and the distribution density of the test units 3 gradually increases.
- each sub-area of the circuit area 92 in the direction from both ends of the sub-area (that is, the position adjacent to another sub-area) to the middle of the sub-area (that is, the position farthest from the adjacent position of the other sub-area), all It is that the distribution density of the driving unit 4 gradually decreases, while the distribution density of the test unit 3 gradually increases.
- the increase in the distribution density of unit A along a certain direction does not mean that the number of units A at each alternate location of unit A along the direction increases in turn, but only as long as the overall distribution in a relatively large area is seen. , the number of units A can be gradually increased along this direction.
- the decrease in the distribution density of unit A along a certain direction does not mean that the number of units A at each alternately arranged position of unit A in this direction decreases in turn, but only as long as the overall distribution in a relatively large area Depending on the situation, the number of units A can be gradually reduced along this direction.
- first sub-area 921 and the second sub-area 922 respectively include the above first circular arc area and the second circular arc area
- the more Near the arc top of the semi-circle (upper and lower sides in Figure 1 and Figure 2)
- the smaller the number of rows of sub-pixels 1 corresponding to the same arc length (or corresponding to the same central angle) range that is, the corresponding grid
- the number of polar lines 12 is less
- the number of columns of the corresponding sub-pixels 1 is more (that is, the number of corresponding data lines 11 is more); on the contrary, the closer to the two ends or the opening side of the two semicircles (each attached In the middle of the longitudinal direction in the figure), the smaller the number of columns of sub-pixels 1 corresponding to the same arc length (or corresponding to the same central angle) range (that is, the fewer the corresponding data lines 11), and the corresponding sub-pixels 1
- the closer to the two ends or the opening side of the two semicircles each attached In the middle of the longitudinal
- each unit can be connected to the corresponding row and column, the closer to the arc top of the semicircle, the more multiplexing units 2 or 3 should be. And the drive unit 4 should be less; on the contrary, the closer to the opening of the semicircle, the multiplexing unit 2 or the test unit 3 should be less and the drive unit 4 should be more, that is, the “distribution” of each drive unit 4 Density" conforms to the above rules.
- the specific distribution position, quantity, etc. in the circuit area 92 of each unit should be determined according to the specific distribution position and quantity of the gate lines 12, data lines 11, etc. in the display area 91, so as to make each unit as close as possible to its own connecting leads as allow.
- first sub-area 921 and the second sub-area 922 are the above first U-shaped ring area and the second U-shaped ring area, respectively, referring to FIG. 4 and FIG. 5 , the multiplexing unit 2 and the testing unit 3 .
- the distribution density of the drive units 4 also conforms to the above rules.
- each unit is to be connected to the corresponding row and column, the closer to the top of the U-shaped ring area, the more multiplexing units 2 or 3 should be. And the drive unit 4 should be less; on the contrary, at the two ends of the U-shaped ring area, the multiplexing unit 2 or the test unit 3 should be less and the drive unit 4 should be more, that is, the ""
- the distribution density conforms to the above rules.
- the circuit area 92 is divided into a first half area and a second half area opposite to each other on both sides of the display area 91 along the second direction 992;
- the driving unit 4 includes a plurality of gate driving units 41;
- the first half region includes a plurality of gate driving units 41 configured to provide gate driving signals to the plurality of gate lines 12 .
- the circuit area 92 can be further divided into two “half areas” opposite to each other on both sides of the display area 91 along the second direction 992 , and each “half area” is also basically It is semi-circular (eg, left and right half-circles in Figures 1 and 2) or U-shaped (eg, left and right half-U-rings in Figures 4 and 5).
- the driving unit 4 in the first half area may include the gate driving unit 41 (further may be the driving unit in the first half area 921) that provides gate driving signals to the plurality of gate lines 12 4 are the gate driving units 41), so that the gate driving units 41 are connected to the corresponding gate lines 12 nearby.
- each gate driving unit 41 can be a gate shift register (GOA), and a plurality of gate shift registers are cascaded, so that the plurality of gate shift registers can respectively transmit to a plurality of gate lines 12 . Provide the drive signal.
- GOA gate shift register
- the specific forms of the gate shift register are various. Exemplarily, reference may be made to FIG. 9 and FIG. 10 for the circuit structure and driving timing of the gate shift register.
- the low level of each of the following signals may be specifically equal to the low-level signal VGL, and the high level of each signal may specifically be equal to the high-level signal VGH.
- the first gate clock signal CK is at a low level
- the second gate clock signal CB is at a high level
- the input signal STV is at a low level. Since the first gate clock signal CK is at a low level, the second gate transistor K2 is turned on, and the input signal STV is transmitted to the third gate node N3 through the second gate transistor K2. Since the second gate transistor K2 has a threshold loss, the level of the third gate node N3 is STV-Vth2, ie VGL-Vth2, where Vth2 represents the threshold level of the second gate transistor K2.
- the sixth gate transistor K6 Since the gate of the sixth gate transistor K6 receives the low-level signal VGL, the sixth gate transistor K6 is in an on state, whereby the level VGL-Vth2 is transmitted to the first gate node via the sixth gate transistor K6 N1.
- the threshold level of the sixth gate transistor K6 is represented as Vth6.
- the sixth gate transistor K6 since the sixth gate transistor K6 has a threshold loss, the level of the first gate node N1 is VGL-VthN1, where VthN1 is Vth2 and The smaller one in Vth6.
- the level of the first gate node N1 can control the eighth gate transistor K8 to be turned on, and the second gate clock signal CB is used as the gate output signal GOUT via the eighth gate transistor K8, that is, in the input stage t1, the gate
- the output signal GOUT is the second gate clock signal CB at a high level, that is, equal to VGH.
- the first gate transistor K1 is turned on, and the low level signal VGL is transmitted to the second gate node N2 through the first gate transistor K1.
- the level of the tri-gate node N3 is VGL-Vth2
- the seventh gate transistor K7 is turned on, and the low-level first gate clock signal CK is transmitted to the second gate node N2 through the seventh gate transistor K7.
- the threshold level of the seventh gate transistor K7 is represented as Vth7
- the threshold level of the first gate transistor K1 is represented as Vth1.
- the level of the second gate node N2 is VGL -Vth7-Vth2; and when Vth1>Vth7+Vth2, the level of the second gate node N2 is VGL-Vth1.
- both the third gate transistor K3 and the fourth gate transistor K4 are turned on. Since the second gate clock signal CB is at a high level, the fifth gate transistor K5 is turned off.
- the first gate clock signal CK is at a high level
- the second gate clock signal CB is at a low level
- the input signal SKT is at a high level.
- the eighth gate transistor K8 is turned on, and the second gate clock signal CB is used as the gate output signal GOUT via the eighth gate transistor K8.
- the level of one end of the second gate capacitor C2 connected to the first gate node N1 is VGL-VthN1, and the level of the other end is high level; and in the output stage t2, the second gate capacitance
- the level of one end of C2 connected to the output terminal GOUT becomes VGL, and due to the bootstrap effect of the second gate capacitor C2, the level of one end of the second gate capacitor C2 connected to the first gate node N1 becomes 2VGL- VthN1-VGH, that is, the level of the first gate node N1 becomes 2VGL-VthN1-VGH, at this time, the sixth gate transistor K6 is turned off, the eighth gate transistor K8 can be better turned on, and the gate output signal GOUT It is the low level signal VGL.
- the first gate clock signal CK is at a high level, so that both the second gate transistor K2 and the first gate transistor K1 are turned off.
- the level of the third gate node N3 is still VGL-VthN1
- the seventh gate transistor K7 is turned on, and the high-level first gate clock signal CK is transmitted to the second gate node N2 through the seventh gate transistor K7 , that is, the level of the second gate node N2 is VGH, so that both the third gate transistor K3 and the fourth gate transistor K4 are turned off. Since the second gate clock signal CB is at a low level, the fifth gate transistor K5 is turned on.
- the first gate clock signal CK and the second gate clock signal CB are both at a high level, and the input signal SKT is at a high level.
- the eighth gate transistor K8 is turned on, and the second gate clock signal CB is used as the gate output signal GOUT through the eighth gate transistor K8.
- the gate output signal GOUT is the second gate clock signal CB with a high level , namely VGH. Due to the bootstrap effect of the second gate capacitor C2, the level of the first gate node N1 becomes VGL-VthN1.
- the first gate clock signal CK is at a high level, so that both the second gate transistor K2 and the first gate transistor K1 are turned off.
- the level of the first gate node N1 becomes VGL-VthN1, at this time, the sixth gate transistor K6 is turned on, the level of the third gate node N3 is also VGL-VthN1, and the seventh gate transistor K7 is turned on , the high-level first gate clock signal CK is transmitted to the second gate node N2 through the seventh gate transistor K7, that is, the level of the second gate node N2 is VGH, so that the third gate transistor K3 and the fourth gate transistor K4 are both turned off. Since the second gate clock signal CB is at a high level, the fifth gate transistor K5 is turned off.
- the first gate clock signal CK is at a low level
- the second gate clock signal CB is at a high level
- the input signal SKT is at a high level. Since the first gate clock signal CK is at a low level, the second gate transistor K2 is turned on, and the input signal SKT is transmitted to the third gate node N3 through the second gate transistor K2. Since the second gate transistor K2 transmits a high level The level has no threshold loss, the level of the third gate node N3 is VGH, and the seventh gate transistor K7 is turned off.
- the sixth gate transistor K6 Since the sixth gate transistor K6 is in an on state, the level of the first gate node N1 is the same as that of the third gate node N3, that is, the level of the first gate node N1 is VGH, and the eighth gate transistor K8 deadline. Since the first gate clock signal CK is at a low level, the first gate transistor K1 is turned on, the level of the second gate node N2 is VGL-Vth1, the third gate transistor K3 and the fourth gate transistor K4 are both When turned on, the high-level signal VGH is transmitted through the third gate transistor K3 as the gate output signal GOUT, that is, the gate output signal is the high-level signal VGH.
- the first gate clock signal is at a high level
- the second gate clock signal is at a low level
- the input signal SKT is at a high level.
- the levels of the first gate node N1 and the third gate node N3 are VGH
- the eighth gate transistor K8 and the seventh gate transistor K7 are both turned off.
- the first gate clock signal CK is at a high level, so that both the second gate transistor K2 and the first gate transistor K1 are turned off.
- the level of the second gate node N2 is still For VGL-Vth1
- the third gate transistor K3 and the fourth gate transistor K4 are both turned on, and the high level signal VGH is used as the gate output signal GOUT via the third gate transistor K3, that is, the gate output signal is high level signal VGH.
- the fifth gate transistor K5 is turned on, so that the high level signal VGH passes through the fourth gate transistor K4 and the fifth gate transistor K5 is transmitted to the third gate node N3 and the first gate node N1, so that the level of the first gate node N1 and the level of the third gate node N3 are maintained at a high level.
- the first gate clock signal CK and the second gate clock signal CB are both at a high level, and the input signal SKT is at a high level.
- the levels of the first gate node N1 and the third gate node N3 are VGH, and the eighth gate transistor K8 and the seventh gate transistor K7 are turned off.
- the first gate clock signal CK is at a high level, so that both the second gate transistor K2 and the first gate transistor K1 are turned off, the level of the second gate node N2 is still VGL-Vth1, and the third gate transistor K3 and the fourth gate transistor K4 are both turned on.
- the high-level signal VGH is used as the gate output signal GOUT through the third gate transistor K3, that is, the gate output signal is the high-level signal VGH.
- the display area 91 further includes a plurality of gate lines 13 extending along the second direction 992, and each gate line 13 is connected to a plurality of sub-pixels 1;
- the drive unit 4 is the control electrode drive unit 42;
- the second half area includes a plurality of gate driving units 42 , and the gate driving units 42 are configured to provide gate driving signals to the plurality of gate lines 13 .
- the display area 91 may also be provided with control electrode lines 13 that also extend along the second direction 992 , and each control electrode line 13 may also be connected to one or two rows of sub-pixels 1 , specifically, it can be connected to the gate line terminal EM of the above 7T1C pixel circuit.
- the driving unit 4 in the second half area may include the gate driving unit 42 (further may be the driving unit in the second half area 922) that provides the gate driving signal to the plurality of gate lines 13 4 are the control electrode driving unit 42), so that the control electrode driving unit 42 is connected to the corresponding control electrode line 13 nearby.
- test unit 3 and the gate driving unit 41 are arranged in the upper left area, and the test unit 3 is arranged in the upper right area.
- Unit 3 and gate driving unit 42 are mixed, the multiplexing unit 2 and gate driving unit 41 are mixed in the lower left area, and the multiplexing unit 2 and gate driving unit 42 are mixed in the lower right area.
- each unit corresponding to the above “arc boundary” may also be “rotated” with different arrangement positions, and generally always ensure that its output end faces the center of the circle.
- each unit and sub-pixel 1 in FIG. 1 , FIG. 2 , FIG. 4 , and FIG. 5 are represented by “rectangles” only for schematic representation.
- each unit and sub-pixel 1 is composed of multiple devices, which occupy The area is not necessarily rectangular.
- each unit corresponds to only a small part of the annular shape, so in the subsequent drawings, many structures at local parts of each unit are approximately treated as straight lines.
- the driving units 4 in the two half regions can also be both gate driving units 41, and provide gate driving signals for different gate lines 12 respectively, or provide gate driving signals for each gate line 12 from both sides at the same time Gate drive signal (ie, double-sided drive).
- Gate drive signal ie, double-sided drive
- each gate driving unit 42 can be one gate shift register (EM GOA), and multiple gate shift registers are cascaded, so that multiple gate shift registers can respectively connect to multiple gate lines 12 provides the drive signal.
- EM GOA gate shift register
- control pole shift register The specific forms of the control pole shift register are various. Exemplarily, reference may be made to FIG. 11 and FIG. 12 for the circuit structure and driving timing of the gate shift register.
- the low level of each of the following signals may be specifically equal to the low-level signal VGL, and the high level of each signal may specifically be equal to the high-level signal VGH.
- the first gate clock signal CK' is at a low level, so the first gate transistor M1 and the third gate transistor M3 are turned on, and the turned-on first gate transistor M1 will be high
- the level start signal ESTV is transmitted to the first gate node N1', so that the level of the first gate node N1' becomes a high level, so the second gate transistor M2, the eighth gate transistor M8 and the The tenth gate transistor M10 is turned off.
- the turned-on third gate transistor M3 transmits the low-level low-level signal VGL to the second gate node N2', so that the level of the second gate node N2' becomes a low level, so
- the fifth gate transistor M5 and the sixth gate transistor M6 are turned on.
- the seventh gate transistor M7 Since the second gate clock signal CB' is at a high level, the seventh gate transistor M7 is turned off. In addition, due to the storage function of the third gate capacitor C3', the level of the fourth gate node N4 can be maintained at a high level, so that the ninth gate transistor M9 is turned off. In the first phase P1, since the ninth gate transistor M9 and the tenth gate transistor M10 are both turned off, the gate output signal EMOUT maintains the previous low level.
- the second gate clock signal CB' is at a low level, so the fourth gate transistor M4 and the seventh gate transistor M7 are turned on. Since the first gate clock signal CK' is at a high level, the first gate transistor M1 and the third gate transistor M3 are turned off. Due to the storage function of the first gate capacitor C1', the second gate node N2' can continue to maintain the low level of the previous stage, so the fifth gate transistor M5 and the sixth gate transistor M6 are turned on.
- the high-level signal VGH is transmitted to the first gate node N1' through the turned-on fifth gate transistor M5 and the fourth gate transistor M4, so that the level of the first gate node N1' continues to maintain the previous stage.
- the second gate transistor M2, the eighth gate transistor M8 and the tenth gate transistor M10 are turned off.
- the low-level second gate clock signal CB' is transmitted to the fourth gate node N4' through the turned-on sixth gate transistor M6 and the seventh gate transistor M7, thereby making the fourth gate node N4 ' becomes a low level, so the ninth gate transistor M9 is turned on, and the turned-on ninth gate transistor M9 outputs a high-level signal VGH, so the gate output signal EMOUT is at a high level.
- the first gate clock signal CK' is at a low level, so the first gate transistor M1 and the third gate transistor M3 are turned on.
- the second gate clock signal CB' is at a high level, so the fourth gate transistor M4 and the seventh gate transistor M7 are turned off. Due to the storage function of the third gate capacitor C3', the level of the fourth gate node N4' can maintain the low level of the previous stage, so that the ninth gate transistor M9 remains in an on state, and the turned-on th
- the nine-gate transistor M9 outputs the high level signal VGH, so the gate output signal EMOUT is still at a high level.
- the first gate clock signal CK' is at a high level, so the first gate transistor M1 and the third gate transistor M3 are turned off.
- the second gate clock signal CB' is at a low level, so the fourth gate transistor M4 and the seventh gate transistor M7 are turned on. Due to the storage function of the second gate capacitor C2', the level of the first gate node N1' maintains the high level of the previous stage, so that the second gate transistor M2, the eighth gate transistor M8 and the tenth gate transistor M8 are Gate transistor M10 is turned off. Due to the storage function of the first gate capacitor C1', the second gate node N2 continues to maintain the low level of the previous stage, so that the fifth gate transistor M5 and the sixth gate transistor M6 are turned on.
- the low-level second gate clock signal CB' is transmitted to the fourth gate node N4' through the turned-on sixth gate transistor M6 and the seventh gate transistor M7, thereby making the fourth gate node N4 ' becomes low, so the ninth gate transistor M9 is turned on, and the turned on ninth gate transistor M9 outputs the high-level signal VGH, so the gate output signal EMOUT is still high.
- the first gate clock signal CK' is at a low level, so the first gate transistor M1 and the third gate transistor M3 are turned on.
- the second gate clock signal CB' is at a high level, so the fourth gate transistor M4 and the seventh gate transistor M7 are turned off.
- the turned-on first gate transistor M1 transmits the low-level start signal ESTV to the first gate node N1', so that the level of the first gate node N1' becomes a low level, so the second control The pole transistor M2, the eighth gate transistor M8, and the tenth gate transistor M10 are turned on.
- the turned-on second gate transistor M2 transmits the low-level first gate clock signal CK' to the second gate node N2', so that the level of the second gate node N2' can be further pulled down, so the The second gate node N2' continues to maintain the low level of the previous stage, so that the fifth gate transistor M5 and the sixth gate transistor M6 are turned on.
- the turned-on eighth gate transistor M8 transmits the high-level signal VGH to the fourth gate node N4', so that the level of the fourth gate node N4 becomes a high level, so the ninth gate transistor M9 is cut off.
- the turned-on tenth gate transistor M10 outputs the low level signal VGL, so the gate output signal EMOUT becomes the low level.
- the multiplexed signal lines 62 include multiple multiplexed control lines 621 and multiple multiplexed data lines 621;
- At least one multiplexing unit 2 includes a plurality of multiplexing transistors 21; the gate of each multiplexing transistor 21 is connected to a multiplexing control line 621, the first pole is connected to a data line 11, and the second pole is connected to a multiplexing data line line 621;
- the second poles of all the multiplexing transistors 21 of the same multiplexing unit 2 are connected to the same multiplexing data line 621, and the second poles of the multiplexing transistors 21 of different multiplexing units 2 are connected to different multiplexing data. Line 621.
- the multiplexing signal line 62 includes a multiplexing control line 621 and a multiplexing data line 622
- each multiplexing unit 2 includes a plurality of (in FIG. 6 ) Taking 6 as an example) multiplexing transistors 21, the gate of each multiplexing transistor 21 is connected to the multiplexing control line 621, the first electrode is connected to the data line 11, and the second electrode is connected to the multiplexed data line 621;
- the multiplexing unit 2 is connected to the same multiplexing data line 621 , and different multiplexing units 2 are connected to different multiplexing data lines 621 .
- a turn-on signal (a signal capable of turning on a transistor) may be input in turn to a plurality of multiplexing control lines 621
- a turn-off signal (a signal capable of turning on the transistor) may be input to the other multiplexing control lines 621 in turn.
- a signal to turn off the transistor so that a multiplexed data line 621 is turned on with a plurality of different data lines 11 through a plurality of multiplexing transistors 21 in a multiplexing unit 2 in turn, so as to pass a multiplexed data line 11.
- the line 621 provides the required data signals to the plurality of data lines 11 respectively, that is, the control of the plurality of data lines 11 is realized through a signal source (such as the connector 6) (that is, the realization of "one drag and more", such as one drag 6) , so that the number of signal sources providing signals for the data lines 11 is much smaller than the number of the data lines 11 , so as to simplify the product structure, for example, the number of required driving chips can be reduced.
- a signal source such as the connector 6) (that is, the realization of "one drag and more", such as one drag 6)
- the number of multiplexing control lines 621 may be equal to the number of multiplexing transistors 21 in each multiplexing unit 2 (for example, 6), that is, each multiplexing unit 2
- Each multiplexing transistor 21 in the multiplexing unit 2 can be connected to different multiplexing control lines 621 respectively, and each multiplexing control line 621 is connected to one multiplexing transistor 21 in each multiplexing unit 2 .
- the multiplexing control line 621 may have a portion extending along the circumferential direction of the fan-out region 93, and different positions of the portion are respectively connected to different multiplexers
- Each multiplexing data line 621 is only connected to one multiplexing unit 2 , so each multiplexing data line 621 can be directly connected to the corresponding multiplexing unit 2 from the fan-out area 93 .
- the farther the fan-out area 93 is from the connecting sub-area 923 in the circumferential direction the smaller the number of multiplexed data lines 621, so the size of the fan-out area 93 can also be smaller.
- the test signal line 63 includes a test control line 631 and a test data line 632;
- At least one test unit 3 includes a plurality of test transistors 31; the gate of each test transistor 31 is connected to a test control line 631, the first electrode is connected to a data line 11, and the second electrode is connected to a test data line 632;
- Each test data line 632 is connected to a plurality of test cells 3 .
- the test signal line 63 includes a test control line 631 and a test data line 632; correspondingly, each test unit 3 may include a plurality of test transistors 31, The gate of the test transistor 31 is connected to the test control line 631 , the first electrode is connected to the data line 11 , and the second electrode is connected to the test data line 632 .
- the signals of 100 enter into a plurality of corresponding data lines 11 through the test transistors 31 in different test sheets, so as to realize the detection of the display device.
- each test data line 632 is connected to a plurality of test units 3 , the number of the test data lines 632 is much smaller than the number of the multiplexed data lines 621 . Therefore, although the test unit 3 is located away from the joint area 94, since it can be controlled only by a few test signal lines 63 extending to the test unit 3, these few test signal lines 63 will not Occupy a large layout area.
- test data line 632 The corresponding relationship between the test data line 632, the test control line 631 and the test unit 3 may be various.
- the number of test data lines 632 may be equal to the number of test transistors 31 in each test unit 3 (for example, 3), and there is only one test control line 631, that is, each test data line 632 is connected to
- the second electrodes of each test transistor 31 in each test unit 3 are connected to different data lines 11 at the first electrodes of different test transistors 31 , and the gates of all test transistors 31 of all test units 3 are connected to the test control line. 631.
- the sub-pixels 1 connected to each data line 11 may have the same color (in the figure, R represents the red sub-pixel 1, G represents the green sub-pixel 1, and B represents the blue sub-pixel 1), and
- the sub-pixels 1 connected to the data line 11 corresponding to each test data line 632 are of the same color, so by continuously feeding the same test signal to the test data line 632, the sub-pixels 1 of the same color can display the same brightness (such as the overall display white picture or other monochrome picture), which is convenient for locating defective sub-pixels 1.
- the sub-pixels 1 connected to each data line 11 have different colors. For example, referring to FIG. 8 , in every four columns of sub-pixels 1, two columns of sub-pixels 1 are green, and in each of the remaining two columns of sub-pixels 1, red and blue The sub-pixels 1 are alternately arranged, and in the two columns of sub-pixels 1, the two sub-pixels 1 in any row are blue and red respectively.
- each test unit 3 may include 5 test transistors 31 for controlling 4 data lines 11 (corresponding to the above 4 columns of sub-pixels). 1).
- the first electrodes of the first test transistor 311 and the third test transistor 313 of each test unit 3 are connected to a column of sub-pixels 1 with mixed red and blue colors, and the first electrodes of the second test transistor 312 and the fourth test transistor 314
- the poles are connected to another column of red and blue mixed sub-pixels 1
- the second poles of the first test transistor 311 and the second test transistor 312 are connected to the first test data line 6321, and the third test transistor 313 and the fourth test transistor 314.
- the second electrode is connected to the second test data line 6322, the gates of the first test transistor 311 and the fourth test transistor 314 are connected to the first test control line 6311, and the gates of the second test transistor 312 and the third test transistor 313 are connected to the second test transistor 312 and the third test transistor 313.
- the test control line 6312; the gate of the fifth test transistor 315 is connected to the third test control line 6313, the first electrode is connected to the two columns of green sub-pixels 1, and the second electrode is connected to the third test data line 6323.
- the first test data line 6321 and the second test data line 6322 can respectively control the blue and green sub-wires by providing the turn-on signal to the first test control line 6311 and the second test control line 6312 in turn.
- Pixel 1 while the third test control line 6313 and the third test data line 6323 control all green sub-pixels 1, so that sub-pixels 1 of the same color display the same brightness.
- test signal lines 63 are located on the side of the circuit area 92 away from the display area 91 ; the driving signal lines 64 are located on the side of the circuit area 92 away from the display area 91 .
- test signal line 63 and the drive signal line 64 can be arranged along the circuit area 92 away from the display area 91 side (outside) .
- the fan-out area 93 is also located outside the circuit area 92, part of the test signal lines 63 and the driving signal lines 64 are also located in the fan-out area 93.
- test signal lines 63 and the drive signal lines 64 can be set according to the different forms of their corresponding units.
- the test signal lines 63 may include three test data lines 632 and one test control line 631 , that is, a total of four test signal lines 63 are arranged outside the circuit area 92 .
- its corresponding driving signal lines 64 may be four, which are respectively used to transmit the first gate clock signal CK, the second gate clock signal CB, the high level signal VGH, low level signal VGL.
- the corresponding driving signal lines 64 may be four, which are respectively used to transmit the first gate clock signal CK′ and the second gate clock signal CB′ , high level signal VGH, low level signal VGL.
- the first gate clock signal CK, the second gate clock signal CB, the first gate clock signal CK', and the second gate clock signal CB' are different from each other, they may correspond to four different The driving signal line 64 .
- the high-level signal VGH and the low-level signal VGL in the gate driving unit 41 and the gate driving unit 42 can be the same, all the high-level signals VGH can pass through one driving signal line 64 (such as a high-level line 641), and all low-level signals VGL can be transmitted through a driving signal line 64 (eg, a low-level line 642).
- the high-level lines 641 and the low-level lines 642 should be distributed at positions outside the first half region and the second half region of the circuit region 92 .
- test signal lines 63 may be located on the side (outer side) of the driving signal lines 64 away from the display area 91 .
- the first sub-area 921 is closest to the end of the second sub-area 922 and is closer to the display area 91 than the end of the second sub-area 922 that is closest to the first sub-area 921 .
- the first sub-area 921 may be larger than the second sub-area 922 ” "Inner", so at the end of the two subregions that are adjacent, also the first subregion 921 is "more inward" than the second subregion 922 .
- the radius of the first semi-circular ring may be smaller than the radius of the second semi-circular ring.
- first sub-area 921 and the second sub-area 922 do not include the above “arc area” and have other shapes, they may not have a "radius”, but their ends may still conform to the above positional relationship, that is, the first sub-area Region 921 may still be "smaller” than second sub-region 922 .
- the circuit area 92 further includes: a connection sub-area 923 located between the first sub-area 921 and the second sub-area 922, and the connection sub-area is configured to electrically connect the first sub-area 921 and the second sub-area 922.
- the connecting sub-region 923 is connected between the end of the first sub-region 921 closest to the second sub-region 922 and the end of the second sub-region 922 closest to the first sub-region 921 .
- the end of the first sub-area 921 is "more inward” than the end of the second sub-area 922, so the ends of the two are "unaligned", and it may be necessary to connect the sub-areas through an oblique arrangement 923 connected.
- connection sub-area 923 also belongs to the circuit area 92, in which the driving unit 4 may also be provided (but because it is not the first sub-area 921 and the second sub-area 922, there is no multiplexing unit 2 and Test power supply), but from the perspective of structural regularity, the structure in the connection sub-region 923 should be as simple as possible, for example, there are only necessary leads (such as leads used for cascading between different driving units 4).
- test signal lines 63 and drive signal lines 64 located outside the circuit area 92 can also be bent at the corresponding connection sub-areas 923 to ensure that each test signal line 63 and drive signal line 64 The distance from the circuit area 92 is substantially constant.
- the circuit area further includes a signal line protection unit, the signal line protection unit is located on a side of the connection sub-area 923 away from the display area 91 and is electrically connected to the signal lines of the circuit area 92 , and the signal line protection unit is configured to protect the circuit The signal line of zone 92 serves as a guard.
- the signal line protection unit of the embodiments of the present disclosure includes:
- each of the at least one polysilicon resistor 71 is connected between two signal lines; the polysilicon resistor 71 is located on the side of the first sub-region 921 closest to the end of the second sub-region 922 away from the display region 91 , or on the side of the connection sub-area 923 away from the display area 91 .
- the polysilicon resistor 71 is also called "poly resistor", which is a resistor with a relatively large resistance value made of polysilicon (p-Si) material.
- the polysilicon resistor 71 is connected between different signal lines, so that when one of the signal lines has no signal, the signal in the other signal line can enter the signal line after a delay to a certain extent, so as to avoid the signal line due to floating ( Floating) and the signal fluctuates; at the same time, when both signal lines have signals, because the resistance of the polysilicon resistor 71 is large, the two signal lines will not be short-circuited, and the signals in the two do not affect each other.
- the polysilicon resistor 71 may be a structure in which a linear polysilicon material is bent in a small area in order to achieve the largest possible resistance in the smallest possible layout area.
- the polysilicon resistor 71 can be set at this position.
- the ends of the first sub-region 921 and the outer side of the connection sub-region 923 on both sides of the second direction 992 may be provided with polysilicon resistors 71 .
- test signal line 63 is located on the side of the circuit area 92 away from the display area 91;
- the driving signal line 64 is located on the side of the circuit area 92 away from the display area 91;
- the polysilicon resistor 71 is located on the side of the test signal line 63 and the driving signal line 64 away from the display area 91 .
- the polysilicon resistors 71 can be arranged outside these signal lines to prevent the polysilicon resistors 71 from interacting with these signal lines.
- the connection of the corresponding cells in the circuit area 92 has an effect.
- the driving signal line 64 includes a high-level line 641 and a low-level line 642
- the test signal line 63 includes a test control line 631 and a test data line 632
- the multiplexing signal line 62 includes multiplexing control lines 621 and 632.
- the multiplexed data line 622, at least one polysilicon resistor 71 is connected to the test control line 631 and the high-level line 641, and at least one polysilicon resistor 71 is connected to the test control line 631 and the multiplexed control line 621.
- the signal line protection unit of the embodiments of the present disclosure further includes:
- At least one electrostatic discharge unit 72 each electrostatic discharge unit 72 is connected to a signal line, and is configured to discharge static electricity in the signal line to which it is connected; the electrostatic discharge unit 72 is located in the first sub-area 921 closest to the second sub-area 922 The end portion is on the side away from the display area 91 , or on the side of the connection sub-area 923 away from the display area 91 .
- an electrostatic discharge unit 72 may also be provided to discharge the static electricity accumulated in the signal line to protect the signal line.
- the electrostatic discharge unit 72 can be set at this position.
- the ends of the first sub-region 921 and the outer side of the connection sub-region 923 on both sides of the second direction 992 may be provided with the electrostatic discharge unit 72 .
- the position occupied by the polysilicon resistor 71 and the electrostatic discharge unit 72 should not exceed the position difference between the end of the first sub-region 921 and the end of the second sub-region 922, for example, the size of the two can be 100-150 ⁇ m.
- the polysilicon resistor 71 and the electrostatic discharge unit 72 can also be provided in the first The outer side of the junction of the sub-region 921 and the second sub-region 922 .
- the polysilicon resistors 71 eg, the first polysilicon resistor 711 and the second polysilicon resistor 712 ) shown in the circuit diagrams of the embodiments of the present disclosure (as shown in FIGS. 7 and 16 ) only represent polysilicon resistors
- the electrical connection structure of the polysilicon resistor 71 does not represent the physical positional relationship between the polysilicon resistor 71 and other units.
- test signal line 63 is located on the side of the circuit area 92 away from the display area 91;
- the driving signal line 64 is located on the side of the circuit area 92 away from the display area 91;
- the electrostatic discharge unit 72 is located on the side of the test signal line 63 and the driving signal line 64 away from the display area 91 .
- the electrostatic discharge unit 72 can also be located outside these signal lines to avoid static electricity
- the release unit 72 affects the connection of these signal lines to the corresponding units in the circuit area 92 .
- the multiplexing signal line 62 includes multiple multiplexing control lines 621 and multiple multiplexing data lines 621 ; the signal line connected to each electrostatic discharge unit 72 is the test signal line 63 or the multiplexing control line 621 .
- electrostatic discharge units 72 which are respectively connected to the above test signal lines 63 (eg, 4 test signal lines 63) and multiplexing control lines 621 (eg, 6 multiplexing control lines 621), and connect to them to protect.
- the driving signal line 64 includes a high-level line 641 and a low-level line 642, the high-level line 641 is configured to connect to a high-level signal source, and the low-level line 642 is configured to connect to a low-level signal source ;
- Each electrostatic discharge unit 72 includes a first discharge transistor 721 and a second discharge transistor 722 : the gate and first electrode of the first discharge transistor 721 are connected to the high-level line 641 , and the second electrode is connected to the signal corresponding to the electrostatic discharge unit 72 .
- line test signal line 63 or multiplexing control line 621 ; the gate and first electrode of the second discharge transistor 722 are connected to the signal line corresponding to the electrostatic discharge unit 72 , and the second electrode is connected to the low-level line 642 .
- the electrostatic discharge unit 72 may include two discharge transistors, wherein one pole of each discharge transistor is connected to its own gate, thereby forming an equivalent The diode is connected; the signal line to be protected is connected between the two "diodes", and the other two ends of the two “diodes” are respectively connected to the above high-level line 641 (transmitting the high-level signal VGH) and the low-level line 642 ( transmit low level signal VGL).
- the polysilicon resistors 71 include first polysilicon resistors 711 , and the two signal lines connected to each of the first polysilicon resistors 711 are the high-level line 641 and the test control line 631 respectively.
- the polysilicon resistor 71 may be connected to the high-level line 641 (transmitting the high-level signal VGH) and the test control line 631 (transmitting the control of the test unit 3 signal).
- the test control line 631 obtains a turn-on signal or a turn-off signal as required, and the first polysilicon resistor 711 avoids being affected by the high-level signal VGH; and when performing a normal display , the test is no longer required, so the test control line 631 can be connected to a fixed turn-off signal, and the first polysilicon resistor 711 ensures the stability of its level.
- the polysilicon resistors 71 include second polysilicon resistors 712 , and the two signal lines connected to each second polysilicon resistor 712 are the high-level line 641 and the signal line corresponding to the electrostatic discharge unit 72 , respectively.
- the polysilicon resistor 71 may be connected to the high-level line 641 (transmitting the high-level signal VGH) and the signal line (test signal) corresponding to the electrostatic discharge unit 72. line 63 or multiplex control line 621) to prevent excessive levels.
- the number of sub-pixels 1 connected to at least some different data lines 11 is different;
- each of the other data lines 11 is connected to a compensation capacitor unit 5 .
- the number of sub-pixels connected to different data lines 11 is different.
- the display area 91 is substantially circular, and each data line 11 is connected to a column of sub-pixels 1, since the number of sub-pixels 1 in different columns is different, the number of sub-pixels 1 connected to different data lines 11 is also different. different.
- each sub-pixel 1 has a certain capacitance (pixel capacitance) as a whole, and this capacitance is equivalent to the "load" of the data line 11 connected to it; therefore, the number of sub-pixels connected to the data line 11 is different, which is equivalent to Due to the different loads of the data lines 11 , when the same signal is applied to the data lines 11 , the signals actually obtained by the sub-pixels 1 connected to different data lines 11 are different, which affects the display.
- pixel capacitance pixel capacitance
- each compensation capacitor unit 5 includes one or more compensation capacitors 51;
- n Nmax-N;
- Nmax is the number of sub-pixels 1 connected to the data line 11 with the largest number of connected sub-pixels
- N is the number of sub-pixels 1 connected to the data line 11 connected to the compensation capacitor unit 5 .
- each compensation capacitor unit 5 may include a plurality of compensation capacitors 51, and the number of compensation capacitors 51 is equal to the number (N) of sub-pixels connected to the data line 11 corresponding to the compensation capacitor unit 5, which corresponds to The difference between the number Nmax of sub-pixels 1 connected to the data line 11 with the largest number of sub-pixels 1; in this way, as long as the capacitance value of a single compensation capacitor 51 is basically equal to the capacitance value of a single sub-pixel 1, the compensation The total capacitance (total load) of all data lines 11 connections is substantially the same.
- a plurality of actual sub-pixels 1 can be prepared first, and the actual capacitance value of a single sub-pixel 1 can be detected, and then the actual size of the compensation capacitor 51 can be set according to the actual capacitance value.
- the total capacitance value of a plurality of (such as 10) sub-pixels 1 can usually be detected, and then divided by the number of 1 sub-pixel (such as 10) to obtain the capacitance value of a single sub-pixel 1 (usually about 10). at 20 ⁇ 30fF).
- the data line 11 is connected to the first poles of all the compensation capacitors 51 of the compensation capacitor unit 5 to which it is connected;
- the second poles of the compensation capacitors 51 are all connected to the same constant-level signal line.
- the data line 11 can be specifically connected to one pole of each compensation capacitor 51 in the corresponding compensation capacitor unit 5, and the other poles of all the compensation capacitors 51 only need to be connected to a constant-level signal line to obtain the same , a fixed level.
- the other poles of all compensation capacitors 51 may be connected to the anode signal line 19 that supplies power to the anode signal terminal VDD of the pixel circuit.
- the plurality of sub-pixels 1 connected to each data line 11 are arranged in a column along the first direction 991;
- the compensation capacitor unit 5 connected to each data line 11 is disposed between a column of sub-pixels 1 connected to the data line 11 and the second sub-region 922 along the first direction 991 .
- the compensation capacitor unit 5 may be disposed between the sub-pixel 1 and the second sub-region 922 in its corresponding column.
- connection relationship, specific form, setting position, etc. of the compensation capacitor unit 5 described above do not limit the protection scope of the embodiments of the present disclosure.
- an embodiment of the present disclosure provides a display device, which includes:
- the above display substrates can be combined with other devices (eg, cell cover plates, flexible circuit boards, driving chips, power supply components, etc.) to form a display device with a display function.
- other devices eg, cell cover plates, flexible circuit boards, driving chips, power supply components, etc.
- the display device is a wearable display device.
- the above display device is particularly suitable as a wearable display device that can be worn on the human body.
- the display device can be a smart watch worn on a human wrist.
- the wearable display device may also include devices such as a watch strap that are worn on the human body.
- the above display devices are not limited to wearable display devices, but can also be any products or components with display functions, such as electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, and navigators.
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Abstract
一种显示基板及显示装置,显示基板包括显示区(91)和周边区,周边区包括电路区(92),显示区包括:多个子像素(1)、多条沿第一方向(991)延伸的数据线(11)以及多条沿第二方向(992)延伸的栅极线(12);电路区(92)包括多个驱动单元组,电路区(92)包括沿第一方向(991)在显示区(91)两侧相对的第一子区(921)和第二子区(922),第一子区(921)包括多个多路复用单元组,第二子区(922)包括多个测试单元组,驱动单元(4)配置为向栅极线(12)提供驱动信号,多路复用单元(2)配置为向数据线(11)提供数据信号,测试单元(3)配置为向数据线(11)提供测试信号;在第一子区(921),驱动单元组和多路复用单元组交替设置;在第二子区(922),驱动单元组和测试单元组交替设置。
Description
本公开实施例涉及但不限于显示技术领域,尤其涉及一种显示基板及显示装置。
有机发光二极管(OLED,Organic Light Emitting Diode)显示技术凭借轻薄、可弯曲、抗震性优、响应速度快等优势,在电视、智能手机、佩戴式显示装置、虚拟现实(VR)显示、汽车显示等领域获得了广泛的应用。
随着技术的发展,大“屏占比(即实际显示区的面积在显示侧总面积中的占比)”已成为显示装置追求的外观特性之一。尤其是,对佩戴式显示装置(如智能手表),基于便携、视角效果等方面的考虑,极致窄边框甚至全屏显示成为发展的重要趋势。
在一些相关技术中,可将一些用于驱动子像素的电路直接设置在显示基板的显示区之外。显然,驱动电路所在区域不能直接进行显示,故对应显示装置的“边框”。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种显示基板,包括显示区和周边区,所述周边区包括电路区,所述显示区包括:多个子像素、多条沿第一方向延伸的数据线以及多条沿与所述第一方向交叉的第二方向延伸的栅极线,每条所述数据线连接多个所述子像素,每条所述栅极线连接多个所述子像素;
所述电路区包括沿所述第一方向在所述显示区两侧相对的第一子区和第二子区,所述电路区包括多个驱动单元组,所述第一子区包括多个多路复用 单元组,所述第二子区包括多个测试单元组,所述多路复用单元组包括至少一个复用单元,所述测试单元组包括至少一个测试单元,所述驱动单元组包括至少一个驱动单元,所述驱动单元配置为向所述栅极线提供驱动信号,所述多路复用单元配置为向所述数据线提供数据信号,所述测试单元配置为向所述数据线提供测试信号;
在所述第一子区,所述驱动单元组和多路复用单元组交替设置;在所述第二子区,所述驱动单元组和测试单元组交替设置。
在示例性实施例中,所述电路区还包括连接子区,所述连接子区位于所述第一子区和所述第二子区之间,所述连接子区被配置为电连接所述第一子区和所述第二子区;
所述电路区还包括信号线防护单元,所述信号线防护单元位于所述连接子区远离所述显示区的一侧且与所述电路区的信号线电连接。
在示例性实施例中,所述信号线防护单元包括至少一个多晶硅电阻,所述电路区还包括多条信号线,所述至少一个多晶硅电阻的每一个连接在至少两条所述信号线之间。
在示例性实施例中,所述信号线包括与所述测试单元连接的测试信号线以及与所述驱动单元连接的驱动信号线,所述驱动信号线包括高电平线和低电平线,所述测试信号线包括测试控制线和测试数据线,至少一个所述多晶硅电阻连接所述测试控制线和所述高电平线。
在示例性实施例中,所述信号线包括与所述多路复用单元连接的复用信号线以及与所述测试单元连接的测试信号线,所述测试信号线包括测试控制线和测试数据线,所述复用信号线包括复用控制线和复用数据线,至少一个所述多晶硅电阻连接所述测试控制线和所述复用控制线。
在示例性实施例中,所述信号线防护单元包括至少一个静电释放单元,所述信号线包括与所述多路复用单元连接的复用信号线、与所述测试单元连接的测试信号线以及与所述驱动单元连接的驱动信号线,所述至少一个静电释放单元的每一个与一条信号线连接。
在示例性实施例中,所述驱动信号线包括高电平线和低电平线,所述测 试信号线包括测试控制线和测试数据线,所述复用信号线包括复用控制线和复用数据线,至少一个所述静电释放单元连接所述测试控制线,或,至少一个所述静电释放单元连接所述测试数据线,或,至少一个所述静电释放单元连接所述复用控制线。
在示例性实施例中,在所述第一子区中,相邻的两个所述驱动单元组之间的所述多路复用单元组包括的多路复用单元的数量C和相邻的两个所述驱动单元组之间的间隙D大小满足如下关系:
D=a*C+(C+1)*d1;
其中,a为每个多路复用单元沿所述多路复用单元排布方向的尺寸,d1为相邻所述多路复用单元之间的间隙大小;和/或,
在所述第二子区中,相邻的两个所述驱动单元组之间的所述测试单元组包括的测试单元的数量E和相邻的两个所述驱动单元组之间的间隙F大小满足如下关系:
F=b*E+(E+1)*d2;
其中,b为每个测试单元沿所述测试单元排布方向的尺寸,d2为相邻所述测试单元之间的间隙大小。
在示例性实施例中,d1为1微米至5微米,d2为1微米至5微米。
在示例性实施例中,所述第一子区包括第一圆弧区,所述第二子区包括第二圆弧区;
在所述第一子区,所述驱动单元组和多路复用单元组交替设置,具体为:在所述第一圆弧区,所述驱动单元组和多路复用单元组沿所述第一圆弧区靠近所述显示区的边缘交替设置;
在所述第二子区,所述驱动单元组和测试单元组交替设置,具体为:在所述第二圆弧区,所述驱动单元组和测试单元组沿所述第二圆弧区靠近所述显示区的边缘交替设置。
在示例性实施例中,在所述第一圆弧区中,多个所述驱动单元组的覆盖区域的中心点的连线轨迹为第一圆弧轨迹,多个所述多路复用单元组的覆盖区域的中心点的连线轨迹为第二圆弧轨迹,所述第一圆弧轨迹对应的圆心、 所述第二圆弧轨迹对应的圆心与所述第一圆弧区靠近所述显示区的边缘对应的圆心大致重合;和/或
在所述第二圆弧区中,多个所述驱动单元组的覆盖区域的中心点的连线轨迹为第三圆弧轨迹,多个所述测试单元组的覆盖区域的中心点的连线轨迹为第四圆弧轨迹,所述第三圆弧轨迹对应的圆心、所述第四圆弧轨迹对应的圆心与所述第二圆弧区靠近所述显示区的边缘对应的圆心大致重合。
在示例性实施例中,所述第一圆弧区为半圆形,所述第二圆弧区为半圆形。
在示例性实施例中,所述第一子区包括第一U形环区,所述第二子区包括第二U形环区,所述第一U形环区包括两段所述第一圆弧区以及至少一段第二矩形区,所述第二U形环区包括两段所述第二圆弧区以及至少一段第三矩形区;
在所述第二矩形区中,多个所述多路复用单元沿所述第二矩形区靠近所述显示区的一侧设置;
在所述第三矩形区中,多个所述测试单元沿所述第三矩形区靠近所述显示区的一侧设置。
在示例性实施例中,所述电路区还包括多段第一矩形区,所述第一矩形区设置在所述第一圆弧区和第二圆弧区之间;
在所述第一矩形区中,多个所述驱动单元沿所述第一矩形区靠近所述显示区的一侧设置。
在示例性实施例中,在所述第一子区中,所述多路复用单元组包括第一多路复用单元组和第二多路复用单元组,所述第一多路复用单元组包括M个多路复用单元,所述第二多路复用单元组包括N个多路复用单元,N、M为大于1的整数,且M<N,所述第二多路复用单元组位于所述第一子区的中部,所述第一多路复用单元组位于所述第一子区远离所述第一子区中部的两端;
和/或,
在所述第二子区中,所述测试单元组包括第一测试单元组和第二测试单元组,所述第一测试单元组包括K个测试单元,所述第二测试单元组包括L 个测试单元,L、K为大于1的整数,且K<L,所述第二测试单元组位于所述第二子区的中部,所述第一测试单元组位于所述第二子区远离所述第二子区中部的两端。
在示例性实施例中,所述周边区还包括位于所述第一子区远离所述显示区一侧的接头区,所述接头区包括多个接头,至少部分所述接头与信号线连接;所述信号线包括:与所述多路复用单元连接的复用信号线、与所述测试单元连接的测试信号线以及与所述驱动单元连接的驱动信号线。
在示例性实施例中,所述周边区还包括设置于所述接头区和所述第一子区之间的扇出区,所述扇出区包括多条所述复用信号线。
在示例性实施例中,所述复用信号线包括多条复用控制线和多条复用数据线;
至少一个所述多路复用单元包括多个复用晶体管;每个所述复用晶体管的栅极连接一条所述复用控制线,第一极连接一条所述数据线,第二极连接一条所述复用数据线;
同一所述多路复用单元的所有所述复用晶体管的第二极连接同一条所述复用数据线,不同的所述多路复用单元的复用晶体管的第二极连接不同的所述复用数据线。
在示例性实施例中,所述测试信号线包括测试控制线和测试数据线;至少一个所述测试单元包括多个测试晶体管;每个所述测试晶体管的栅极连接一条所述测试控制线,第一极连接一条所述数据线,第二极连接一条所述测试数据线;每条所述测试数据线与多个所述测试单元连接。
本公开实施例还提供了一种显示装置,包括:如前任一所述的显示基板。
在阅读并理解了附图概述和本公开的实施方式后,可以明白其他方面。
附图用来提供对本公开实施例的进一步理解,并且构成说明书的一部分,与本公开实施例一起用于解释本公开,并不构成对本公开的限制。通过参考附图对详细示例实施例进行描述,以上和其它特征和优点对本领域技术人员 将变得更加显而易见,在附图中:
图1为本公开实施例提供的一种显示基板的结构示意图;
图2为本公开实施例提供的一种显示基板的结构示意图(未示出部分引线);
图3为本公开实施例提供的一种显示基板中的一种像素电路的电路示意图;
图4为本公开实施例提供的另一种显示基板的结构示意图;
图5为本公开实施例提供的另一种显示基板的结构示意图(未示出部分引线);
图6为本公开实施例提供的一种显示基板中的一种多路复用单元的电路示意图;
图7为本公开实施例提供的一种显示基板中的一种测试单元的电路示意图;
图8为本公开实施例提供的一种显示基板中的另一种测试单元的电路示意图;
图9为本公开实施例提供的一种显示基板中的一种栅极移位寄存器的电路图;
图10为本公开实施例提供的一种显示基板中的一种栅极移位寄存器的驱动时序图;
图11为本公开实施例提供的一种显示基板中的一种控制极移位寄存器的电路图;
图12为本公开实施例提供的一种显示基板中的一种控制极移位寄存器的驱动时序图;
图13为本公开实施例提供的一种显示基板中的一个连接子区处的局部结构示意图;
图14本公开实施例提供的一种显示基板中不同单元的分布密度示意图;
图15本公开实施例提供的另一种显示基板中不同单元的分布密度示意 图;
图16为本公开实施例提供的一种显示基板中的一种静电释放单元的电路示意图;
图17为本公开实施例提供的一种显示基板中的一种补偿电容单元的局部结构示意图;
本公开实施例的附图中,附图标记的意义为:
1、子像素;11、数据线;12、栅极线;13、控制极线;19、阳极信号线;
2、多路复用单元;21、复用晶体管;
3、测试单元;31、测试晶体管;311、第一测试晶体管;312、第二测试晶体管;313、第三测试晶体管;314、第四测试晶体管;315、第五测试晶体管;
4、驱动单元;41、栅极驱动单元;42、控制极驱动单元;
5、补偿电容单元;51、补偿电容;
6、接头;62、复用信号线;621、复用控制线;622、复用数据线;63、测试信号线;631、测试控制线;6311、第一测试控制线;6312、第二测试控制线;6313、第三测试控制线;632、测试数据线;6321、第一测试数据线;6322、第二测试数据线;6323、第三测试数据线;
64、驱动信号线;641、高电平线;642、低电平线;
71、多晶硅电阻;711、第一多晶硅电阻;712、第二多晶硅电阻;72、静电释放单元;721、第一释放晶体管;722、第二释放晶体管;
91、显示区;92、电路区;921、第一子区;922、第二子区;923、连接子区;93、扇出区;94、接头区;95、电容区;991、第一方向;992、第二方向;
T1、第一晶体管;T2、第二晶体管;T3、第三晶体管;T4、第四晶体管;T5、第五晶体管;T6、第六晶体管;T7、第七晶体管;Cst、存储电容;Reset、第一重置端;Reset’、第二重置端;Vinit、初始化端;Gate、栅极线端;Data、数据线端;EM、控制极线端;VDD、阳极信号端;VSS;阴极信号端;
K1、第一栅极晶体管;K2、第二栅极晶体管;K3、第三栅极晶体管;K4、第四栅极晶体管;K5、第五栅极晶体管;K6、第六栅极晶体管;K7、第七栅极晶体管;K8、第八栅极晶体管;C1、第一栅极电容;C2、第二栅极电容;N1、第一栅极节点;N2、第二栅极节点;N3、第三栅极节点;
M1、第一控制极晶体管;M2、第二控制极晶体管;M3、第三控制极晶体管;M4、第四控制极晶体管;M5、第五控制极晶体管;M6、第六控制极晶体管;M7、第七控制极晶体管;M8、第八控制极晶体管;M9、第九控制极晶体管;M10、第十控制极晶体管;C1’、第一控制极电容;C2’、第二控制极电容;C3’、第三控制极电容;N1’、第一控制极节点;N2’、第二控制极节点;N3’、第三控制极节点;N4’、第四控制极节点。
为使本领域的技术人员更好地理解本公开实施例的技术方案,下面结合附图对本公开实施例提供的显示基板、显示装置。
在下文中将参考附图更充分地描述本公开实施例,但是所示的实施例可以以不同形式来体现,且不应当被解释为限于本公开阐述的实施例。反之,提供这些实施例的目的在于使本公开透彻和完整,并将使本领域技术人员充分理解本公开的范围。
本公开实施例可借助本公开的理想示意图而参考平面图和/或截面图进行描述。因此,可根据制造技术和/或容限来修改示例图示。
在不冲突的情况下,本公开各实施例及实施例中的各特征可相互组合。
本公开所使用的术语仅用于描述特定实施例,且不意欲限制本公开。如本公开所使用的术语“和/或”包括一个或多个相关列举条目的任何和所有组合。如本公开所使用的单数形式“一个”和“该”也意欲包括复数形式,除非上下文另外清楚指出。如本公开所使用的术语“包括”、“由……制成”,指定存在所述特征、整体、步骤、操作、元件和/或组件,但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。
除非另外限定,否则本公开所用的所有术语(包括技术和科学术语)的 含义与本领域普通技术人员通常理解的含义相同。还将理解,诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义,且将不解释为具有理想化或过度形式上的含义,除非本公开明确如此限定。
本公开实施例不限于附图中所示的实施例,而是包括基于制造工艺而形成的配置的修改。因此,附图中例示的区具有示意性属性,并且图中所示区的形状例示了元件的区的具体形状,但并不是旨在限制性的。
本公开实施例中,在附图中,有时为了明确起见,夸大表示了各构成要素的大小、层的厚度或区域。因此,本公开的一个方式并不一定限定于该尺寸,附图中各部件的形状和大小不反映真实比例。此外,附图示意性地示出了理想的例子,本公开的一个方式不局限于附图所示的形状或数值等。
本公开实施例中,“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置,而不是为了在数量方面上进行限定的。
本公开实施例中,为了方便起见,使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系,仅是为了便于描述本说明书和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此,不局限于在说明书中说明的词句,根据情况可以适当地更换。
本公开实施例中,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应做广义理解。例如,可以是固定连接,或可拆卸连接,或一体地连接;可以是机械连接,或电连接;可以是直接相连,或通过中间件间接相连,或两个元件内部的连通。对于本领域的普通技术人员而言,可以具体情况理解上述术语在本公开中的具体含义。
本公开实施例中,晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域,并且电流能够流过漏电极、沟道区域以及源电极。注意,在本说明书中,沟道区域是指电流主要 流过的区域。
本公开实施例中,第一极可以为漏电极、第二极可以为源电极,或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下,“源电极”及“漏电极”的功能有时互相调换。因此,在本说明书中,“源电极”和“漏电极”可以互相调换。
本公开实施例中,“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受,就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线,而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
本公开实施例中,“平行”是指两条直线形成的角度为-10°以上且10°以下的状态,因此,也包括该角度为-5°以上且5°以下的状态。另外,“垂直”是指两条直线形成的角度为80°以上且100°以下的状态,因此,也包括85°以上且95°以下的角度的状态。
本公开实施例中,“膜”和“层”可以相互调换。例如,有时可以将“导电层”换成为“导电膜”。与此同样,有时可以将“绝缘膜”换成为“绝缘层”。
本公开实施例中,“约”,是指不严格限定界限,允许工艺和测量误差范围内的数值。
第一方面,参照图1至图2、图4至图5,本公开实施例提供一种显示基板。
本公开实施例的显示基板是用于显示装置中的基板,例如是设有薄膜晶体管(TFT)阵列的阵列基板。
本公开实施例的显示基板,包括显示区91和环绕显示区91的周边区,周边区包括电容区95、电路区92、扇出区93、接头区94;其中,
显示区91包括:多个子像素1;多条沿第一方向991延伸的数据线11, 每条数据线11连接多个子像素1;多条沿与第一方向991交叉的第二方向992延伸的栅极线12,每条栅极线12连接多个子像素1;
电路区92环绕显示区91,电路区92包括沿第一方向991在显示区91两侧相对的第一子区921和第二子区922;第一子区921包括多个多路复用单元组,多个多路复用单元组配置为向多条数据线11提供数据信号,多路复用单元组包括至少一个多路复用单元2;第二子区922包括多个测试单元组,多个测试单元组配置为向多条数据线11提供测试信号,测试单元组包括至少一个测试单元3;电路区92还包括多个驱动单元组,驱动单元组包括至少一个驱动单元4,在第一子区921中,驱动单元组和多路复用单元组沿周向交替设置,在第二子区922中,驱动单元组和测试单元组沿周向交替设置;
电容区95位于第二子区922与显示区91之间,电容区95包括多个补偿电容单元5,每个补偿电容单元5连接一条数据线11;
接头区94位于第一子区921远离显示区91一侧,接头区94包括多个接头6,至少部分接头6与信号线连接;信号线包括与多路复用单元2连接的复用信号线62,与测试单元3连接的测试信号线63,与驱动单元4连接的驱动信号线64;
扇出区93位于接头区94与第一子区921之间,扇出区93包括多条复用信号线62。
参照图1、图2、图4、图5,本公开实施例的显示基板分为多个区域,位于中部的是用于进行显示的显示区91(或AA区),用于进行显示的子像素1(或称亚像素)设于该显示区91中。
其中,子像素1是指可用于独立显示所需内容的最小的结构,即是显示装置中可独立的控制的最小的“点”。
其中,子像素1的具体形式是多样的,只要能实现独立的显示即可。
示例性的,子像素1可包括像素电路,该像素电路可在相应的栅极线12、数据线11等的控制下发出所需亮度的光。例如,像素电路可为7T1C结构(即包括7个晶体管和1个电容),参照图3,以上7T1C的像素电路可包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管 T5、第六晶体管T6、第七晶体管T7、存储电容Cst、有机发光二极管OLED、第一重置端Reset、第二重置端Reset’、初始化端Vinit、栅极线端Gate、数据线端Data、控制端EM、阳极信号端VDD、阴极信号端VSS等结构;其中,各晶体管可均为P型晶体管(如PMOS)。其中,数据线端Data可连接数据线11,栅极线端Gate可连接栅极线12,控制极线端EM可连接控制极线13,第一重置端Reset和第二重置端Reset’可同时连接上一行的栅极线,第二重置端Reset’也可连接本行的栅极线,而其它各端也可连接相应的信号源。
也就是说,本公开实施例的显示基板的各子像素1中,可用有机发光二极管OLED作为发光器件,其具体是有机发光二极管显示基板,也是设有薄膜晶体管(TFT)阵列的阵列基板。
其中,不同的子像素1可具有不同的颜色,从而通过不同子像素1的混光可实现彩色显示。其中,当要实现彩色显示时,可以是多个排在一起的不同颜色的子像素1组成一个“像素(或像素单元)”,即这些子像素1发出的光混在一起成为视觉上的一个“点”;例如,可以是红色、绿色、蓝色三种颜色的三个子像素1组成一个像素。或者,也可不存在明确的像素(或像素单元),而是通过临近子像素1间的“公用”实现彩色显示。
参照图1、图2、图4、图5,显示区91中,还设有沿第一方向991延伸的数据线11,以及沿第二方向992延伸的栅极线12,其中,第一方向991是与第二方向992交叉(即不相互平行)的,从而数据线11与栅极线12的每个交叉处可限定出一个子像素1,而通过栅极线12与数据线11的共同控制,可使二者交叉处的子像素1进行显示。
在一些实施例中,第一方向991垂直于第二方向992,即第一方向991可为列方向(图1、图2、图4、图5中为纵向),第二方向992可为与列方向垂直的行方向(图1、图2、图4、图5中为横向)。
应当理解,第一方向991、第二方向992实际只是对应数据线11和栅极线12的两个相对方向,二者不一定是列方向、行方向,且与显示基板(或显示装置)的形状、所处位置、放置方式等没有必然的关系。
在一些实施例中,显示区91中的子像素1可排成阵列,即子像素1可排 成多行、多列,其中每行子像素1连接一条栅极线12,每列子像素1连接一条数据线11。
应当理解,子像素1不一定排成阵列,每条数据线11、栅极线12也不一定连接同列、同行的子像素1。
参照图1、图2、图4、图5,显示区91之外的区域为环绕其的电路区92,故显示区91整体为环形。而由于周边区不进行显示,故其对应显示装置的“边框”。
周边区包括环绕显示区91的电路区92,故电路区92整体也为环形,其包括沿第一方向991在显示区91两侧相对设置的第一子区921和第二子区922,如图1、图2,中的“下半区”和“上半区”。其中,第一子区921包括多个多路复用单元2(MUX),各多路复用单元2从一侧(图1、图2、图4、图5中为下侧)连接数据线11,用于在显示时为数据线11提供数据信号(数据电压);而第二子区922包括多个测试单元3(CT),各测试单元3从另一侧(图1、图2、图4、图5中为上侧)连接数据线11,用于在测试阶段为数据线11提供测试信号,以检测显示基板是否存在不良。
另外,电路区92中还设有多个驱动单元4,用于提供其它的驱动信号。
在一些实施例中,至少部分驱动单元4配置为向栅极线12提供驱动信号,即有至少一部分驱动单元4与以上栅极线12连接,并用于向栅极线12提供信号,以控制与相应栅极线12连接的子像素1工作。
可见,以上多路复用单元2构成多个“多路复用单元组”,每个多路复用单元组包括一个多路复用单元2,或多个连续排布的多路复用单元2;测试单元3构成多个“测试单元组”,每个测试单元组包括一个测试单元3,或多个连续排布的测试单元3;驱动单元4构成多个“驱动单元组”,每个驱动单元组包括一个驱动单元4,或多个连续排布的驱动单元4。由此,电路区92中设有不同的单元,且这些单元是“混排”的。
具体的,参照图1、图2、图4、图5、图14、图15,在第一子区921中,驱动单元组和多路复用单元组沿“周向”交替设置。
其中,“周向”是指绕平面图形的中心转动的方向,或者说是沿说顺时 针或逆时针绕行图形边缘的方向。
即,本公开实施例中,沿顺时针方式或逆时针方式遍历基本为环形的电路区92时,在第一子区921中,驱动单元组和多路复用单元组交替出现,即出现一个驱动单元组-一个多路复用单元组-一个驱动单元组-一个多路复用单元组…以此类推。当然,其中每个“组”包括一个或多个连续的相应单元,从而,第一子区921中驱动单元4和多路复用单元2是“混排(但每种单元可能有连续多个排在一起)”的,而不是分别集中在第一子区921的不同位置。
具体的,图1、图2、图4、图5、图14、图15,在第二子区922中,驱动单元组和测试单元组沿周向交替设置。
即,沿顺时针方式或逆时针方式遍历基本为环形的电路区92时,在第二子区922中,驱动单元组和测试单元组交替出现,即出现一个驱动单元组-一个测试单元组-一个驱动单元组-一个测试单元组…以此类推。。当然,其中每个“组”包括一个或多个连续的相应单元,从而,第二子区922中驱动单元4和测试单元3是“混排(但每种单元可能有连续多个排在一起)”的,而不是分别集中在第一子区921的不同位置。
在一种示例性实施例中,在第一子区921中,相邻的两个驱动单元组之间的多路复用单元组包括的多路复用单元2的数量C和相邻的两个驱动单元组之间的间隙D大小满足如下关系:
D=a*C+(C+1)*d1;
其中,a为每个多路复用单元2沿多路复用单元2排布方向的尺寸,d1为相邻多路复用单元2之间的间隙大小。
在一种示例性实施例中,在第二子区922中,相邻的两个驱动单元组之间的测试单元组包括的测试单元3的数量E和相邻的两个驱动单元组之间的间隙F大小满足如下关系:
F=b*E+(E+1)*d2;
其中,b为每个测试单元3沿测试单元3排布方向的尺寸,d2为相邻测试单元3之间的间隙大小。
在一种示例性实施例中,相邻的两个单元(如多路复用单元2、测试单元3、驱动单元4)之间的间隙为1微米至5微米。示例性的,相邻的两个驱动单元4(或相邻的两个多路复用单元2或相邻的两个测试单元3)之间的间隙可以为1.5微米,相邻的驱动单元4与多路复用单元2之间的间隙可以为1.5微米,相邻的驱动单元4与测试单元3之间的间隙可以为1.5微米等。
其中,以上“间隙”是指分别属于两个相邻的两个单元中的器件间的最短直线距离。
显然,电路区92中的各电路也需要一定的信号才能工作,故周边区还包括用于引入这些信号的接头区94,接头区94包括多个接头6,且接头6连接信号线,信号线可包括分别为多路复用单元2、测试单元3、驱动单元4供电的复用信号线62、测试信号线63、驱动信号线64等;当然,每种信号线都与对应的单元和接头6连接。
其中,接头6(Pad或Pin)是指显示基板中的可获取其它信号并将信号引入信号线的结构。
具体的,接头6可用于与柔性线路板(FPC)或驱动芯片绑定(Bonding)连接,从而获取来自柔性线路板或驱动芯片的信号。
或者,接头6也可用于与测试装置的测试探针接触,从而获得来自测试探针的信号。
参照图1、图2、图4、图5,以上接头区94设于电路区92远离显示区91一侧(即外侧),且接头区94与第一子区921之间还设有扇出区93(Fanout区),扇出区93包括多条的复用信号线62,即复用信号线62从接头区94引出后,经过该扇出区93与相应的多路复用单元2连接。
通常而言,复用信号线62的数量远远多于测试信号线63、驱动信号线64的数量总和,因此,通过将扇出区93设置在接头区94和多路复用单元2的第一子区921之间,可使数量较大的复用信号线62“就近”与多路复用单元2连接;而驱动信号线64、测试信号线63虽然需要延伸较长的距离才能与驱动单元4、测试单元3连接,但因驱动信号线64、测试信号线63的数量较少,故其引线的总长度也不会太大;由此,以上设计可降低引线的总长度 和占用的布图面积,减小显示装置的边框,提高占屏比。
当然,除复用信号线62外,驱动信号线64、测试信号线63也可有一部分位于扇出区93中。
参照图1、图2,由于第二子区922所在侧(图1、图2中的上侧)并无扇出区93,故该侧还可有空间设置其它结构,因此可在第二子区922与显示区91之间设置电容区95,电容区95中设有多个与数据线11连接的补偿电容单元5,用于补偿不同数据线11的电容差距,其作用后续详细描述。
参照图1、图2、图4、图5,本公开实施例的显示基板中各单元(多路复用单元2、测试单元3、驱动单元4)混排,从而各单元都可就近的向相应的数据线11、栅极线12等提供信号;同时,各种结构相对均匀的分布,充分利用了显示基板各位置的空间,降低了显示装置的边框,提高了占屏比。
在一些实施例中,第一子区921包括第一圆弧区,第二子区922包括第二圆弧区,第一圆弧区921靠近显示区91的边缘相比第二圆弧区靠近显示区92的边缘更接近显示区92的中心。
参照图1、图2、图14,第一子区921、第二子区922可包括“圆弧形(圆环形)”部分。
示例性的,显示基板的主表面可基本为圆形,而显示区91也基本为圆形,从而电路区92基本为围绕在圆形显示区91外的圆环形,而第一子区921和第二子区922分别为“半个圆环”(图1、图2中为“上半圆环”和“下半圆环”),且二者的开口相对。
而且,第一圆弧区(第一子区921)靠近显示区91的边缘比第二圆弧区(第二子区922)靠近显示区91的边缘更接近显示区91的中心;或者说,第一圆弧区的内侧比第二圆弧区的内侧“更小”,这是因为第二子区922内侧还设有电容区95。
在一些实施例中,第一圆弧区(第一子区921)和第二圆弧区(第二子区922)的圆心相同,且第一圆弧区靠近显示区91的边缘的半径比第二圆弧区靠近显示区91的边缘的半径小210~420μm。
示例性的,以上第一圆弧区和第二圆弧区可以是“同心”的,且二者内径的差可在210~420μm(第一圆弧区内径较小),进一步可在250~350μm。
其中,显示基板的主表面可以是其衬底的一侧表面,即本公开实施例的显示基板的衬底的表面可为圆形。
其中,衬底是用于承载显示基板上的其它结构的基础,其是由玻璃、硅(如单晶硅)、聚合物材料(如聚酰亚胺)等材料构成的基本为片状的结构,可为刚性,也可为柔性,厚度可在毫米量级。
其中,本公开实施例中,“A基本为B”是指,在A整体的尺度上,其符合特征B,但在从明显比A整体更小的尺度上看,A可以不是完全符合特征B的。例如,“A基本为圆形”表示A可以是完美的圆形或椭圆形,也可以是A的形状整体上是圆形或椭圆形,但其部分细节结构不是严格的圆形:例如,A的边界可有少部分为直线、折线等;再如,A的边界可有部分位置具有凸出、凹陷等;再如,A的边界可有少部分为近似于圆弧但不是严格的圆弧的弧形;再如,A的不同位置的边界可为直径不同的圆弧形等。
参照图1、图2,当电路区92为“圆环形”时,其大部分位置都同时对应有数据线11和栅极线12(即在行方向和列方向上都有对应的子像素1),故在此情况下,电路区92中多路复用单元2、测试单元3、驱动单元4混排,最有利于各单元均就近连接对应的数据线11、栅极线12等。
当然,以上形状也不是对显示基板及其中各区的具体形式的限定,显示基板以及其中各区也可为其它的形状。
例如,在另一些实施例中,第一子区921包括第一U形环区,第二子区922包括第二U形环区。
参照图4、图5、图15,作为本公开实施例的另一种形式,显示基板的主表面也可基本为弧角矩形,而显示区91也基本为弧角矩形,从而电路区92基本为围绕在圆形显示区91外的弧角矩形环。
由此,第一子区921和第二子区922分别为“U形环”(图4、图5中分别为“上U形环”和“下U形环”,且二者的开口相对),当然该U形 环的底部为直线形式,而不是为弧形。
其中,“弧角矩形”是指近似于矩形的形状,其具有四个直边,但与矩形的区别在于其四个角不是直角,而是比较均匀的过渡的“弧角”,进一步可为“圆角”,即“弧角矩形”也可为“圆角矩形”。
相应的,电路区92则为“弧角矩形环,”即为夹在两个尺寸不同的“弧角矩形”之间的环形区域,故其也可视为“中空的弧角矩形”。当然,进一步的,电路区92也可为“圆角矩形环”(即“中空的圆角矩形”)。
在一些实施例中,第一U形环区的宽度(即U形的两个直线部间的距离)约等于第二U形环区的宽度,而第一U形环区的高度(即U形底部到其开口处的距离)约等于第二U形环区的高度。
参照图4,图5,第一U形环区和第二U形环区的尺寸可基本相同,从而二者可基本是“上下对称”的。
在一些实施例中,第一U形环区的内侧边缘(即显示区91的外边缘)包括两段第一弧形边界,第二U形环区的内侧边缘(即显示区91的外边缘)包括两段第二弧形边界。而电路区内侧边缘(即显示区91的外边缘)还包括:沿第一方向991延伸的两条第一直线边界(每条第一直线边界跨越第一子区921和第二子区922),沿第二方向992延伸的第二直线边界(属于第一子区921)和第三直线边界(属于第二子区922)。
当然,应当理解,此时第一子区921、第二子区922的外侧边缘(即电路区92的外边缘)应具有与其内侧边缘基本相似的形状。
进一步的,在电路区91的内边缘的任意一点,沿法线方向到外边缘的距离可以都是相同的,即电路区91的各位置的“宽度”可以相同。
在一些实施例中,在第一子区921和第二子区922中,多个驱动单元4沿第一直线边界设置;在第一子区921中,多个多路复用单元2沿第二直线边界设置;在第二子区922中,多个测试单元3沿第三直线边界设置。
在一些实施例中,在第一子区921,驱动单元4和多路复用单元2沿第一弧形边界交替设置;在第二子区922,驱动单元4和测试单元3沿第二弧形边界交替设置。
即,参照图4、图5,当第一子区921和第二子区922为以上“弧角矩形环”的形式时,可仅在对应“矩形环的弧角”处不同的单元混排,而在对应“矩形环的直边”处则只有一种单元。
在一些实施例中,在第一子区921中,多个驱动单元组的覆盖区域的中心点的连线轨迹为第一圆弧轨迹,多个多路复用单元组的覆盖区域的中心点的连线轨迹为第二圆弧轨迹,第一圆弧轨迹对应的圆心、第二圆弧轨迹对应的圆心与第一弧形边界对应的圆心大致重合。
本实施例中,第一圆弧轨迹对应的圆心、第二圆弧轨迹对应的圆心与第一弧形边界对应的圆心大致重合,指的是第一圆弧轨迹对应的圆心、第二圆弧轨迹对应的圆心与第一弧形边界对应的圆心可以完全重合,或者各圆心之间的间距小于10微米。
在一些实施例中,在第二子区922中,多个驱动单元组的覆盖区域的中心点的连线轨迹为第三圆弧轨迹,多个测试单元组的覆盖区域的中心点的连线轨迹为第四圆弧轨迹,第三圆弧轨迹对应的圆心、第四圆弧轨迹对应的圆心与第二弧形边界对应的圆心大致重合。
本实施例中,第三圆弧轨迹对应的圆心、第四圆弧轨迹对应的圆心与第二弧形边界对应的圆心大致重合,指的是第三圆弧轨迹对应的圆心、第四圆弧轨迹对应的圆心与第二弧形边界对应的圆心可以完全重合,或者各圆心之间的间距小于10微米。
即,参照图4、图5,在每个子区中,对应弧形边界处的每种单元都是分别沿圆形轨迹排列的,且同一个弧形边界处的两种单元的圆形轨迹对应的圆,以及该弧形边界本身的对应圆,是同心的,或者是大致同心的。
在一些实施例中,在第一子区921中,多路复用单元组包括第一多路复用单元组和第二多路复用单元组,第一多路复用单元组包括M个多路复用单元2,第二多路复用单元组包括N个多路复用单元2,N、M为大于1的整数,且M<N,第二多路复用单元组位于第一子区921的中部,第一多路复用单元组位于第一子区921远离第一子区921中部的两端;
和/或,
在第二子区922中,测试单元组包括第一测试单元组和第二测试单元组,第一测试单元组包括K个测试单元3,第二测试单元组包括L个测试单元,L、K为大于1的整数,且K<L,第二测试单元组位于第二子区922的中部,第一测试单元组位于第二子区922远离第二子区922中部的两端。
在第一子区921的中部(即半圆环的弧顶处)设有至少一个第二多路复用单元组,每个第二多路复用单元组包括N个多路复用单元2;而在第一子区921的两端(即半圆环的两端或开口侧)则设有至少一个第一多路复用单元组,每个第一多路复用单元组包括M个多路复用单元2,且M小于N。
即,在第一子区921的中部有多路复用单元组(第二多路复用单元组)包括的多路复用单元2的数量较多,而在第一子区921的两端有多路复用单元组(第一多路复用单元组)包括的多路复用单元2的数量较少。从而,从整体上看,第一子区921的中部多路复用单元2的数量多而驱动单元4的数量少,第一子区921的两端多路复用单元2的数量少而驱动单元4的数量多。
其中,在一些实施例中,N可为7,或为6,或为5;而在一些实施例中,M可为1,或为2,或为3。
在一些实施例中,在以上第一多路复用单元组和第二多路复用单元组之间还可有其它的多路复用单元组,而这些多路复用单元组中多路复用单元的数量可大于M而小于N。
在第二子区922的中部(即半圆环的弧顶处)设有至少一个第二测试单元组,每个第二测试单元组包括L个测试单元3;而在第二子区922的两端(即半圆环的两端或开口侧)则设有至少一个第一测试单元组,每个第一测试单元组包括K个测试单元3,且K小于L。
即,在第二子区922的中部有测试单元组(第二测试单元组)包括的测试单元3的数量较多,而在第一子区921的两端有测试单元组(第一测试单元组)包括的测试单元3的数量较少。从而,从整体上看,第二子区922的中部测试单元3的数量多而驱动单元4的数量少,第二子区922的两端测试 单元3的数量少而驱动单元4的数量多。
其中,在一些实施例中,L可为7,或为6,或为5;而在一些实施例中,K可为1,或为2,或为3。
在一些实施例中,在以上第一测试单元组和第二测试单元组指间还可有其它的测试单元组,而这些测试单元组中测试单元的数量可大于K而小于L。
在一些实施例中,第一子区921中,在从第一子区921的两端指向第一子区921的中部的方向上,驱动单元4的分布密度逐渐减小,多路复用单元2的分布密度逐渐增大;
第二子区922中,在从第二子区922的两端指向第二子区922的中部的方向上,驱动单元4的分布密度逐渐减小,测试单元3的分布密度逐渐增大。
在电路区92的每个子区中,在从子区两端(即与另一个子区相邻的位置)指向子区中部(即最远离另一个子区相邻的位置)的方向上,都是驱动单元4的分布密度逐渐减小,而测试单元3的分布密度逐渐增大。
其中,沿某方向单元A的分布密度增加,并不代表沿该方向每个交替设置单元A的位置处单元A的数量都依次增加,而是只要在相对较大的区域中的总体分布情况看,沿该方向单元A的数量逐渐增加即可。
其中,沿某方向单元A的分布密度减小,并不代表沿该方向每个交替设置单元A的位置处单元A的数量都依次减小,而是只要在相对较大的区域中的总体分布情况看,沿该方向单元A的数量逐渐减小即可。
示例性的,第一子区921和第二子区922分别包括以上第一圆弧区和第二圆弧区时,参照图1、图2,在以上两个半圆环形的子区中,越靠近半圆环的弧顶(图1、图2中上下两侧)处,相同的弧长(或者说对应相同的圆心角)范围所对应的子像素1的行数越少(即对应的栅极线12数越少),而对应的子像素1的列数越多(即对应的数据线11数越多);反之,在越靠近两个半圆环的两端或开口侧(各附图中沿纵向的中部)处,相同的弧长(或者说对应相同的圆心角)范围所对应的子像素1的列数越少(即对应的数据线11数越少),而对应的子像素1行数越多(即对应的栅极线12数越多)。
因此,参照图1、图2,若要让各单元都能就近连接相应的行、列,则在越靠近半圆环的弧顶处,多路复用单元2或测试单元3应越多,而驱动单元4应越少;反之,在越靠近半圆环的开口处,则应多路复用单元2或测试单元3应越少而驱动单元4越多,即各驱动单元4的“分布密度”符合以上的规律。
当然,各单元电路区92中的具体分布位置、数量等,应根据显示区91中栅极线12、数据线11等的具体分布位置、数量等决定,以尽量让各单元靠近自身连接引线为准。
示例性的,第一子区921和第二子区922分别为以上第一U形环区和第二U形环区时,参照图4、图5,多路复用单元2、测试单元3、驱动单元4的分布密度也符合以上规律。
即,在以上两个U形环区中,越靠近U形环区的顶部(图4、图5中上下两端)处,相同的边长范围所对应的子像素1的行数越少(即对应的栅极线12数越少),而对应的子像素1的列数越多(即对应的数据线11数越多);反之,在越靠近两个U形环区的两端(图4、图5中沿纵向的中部)处,相同的边长范围所对应的子像素1的列数越少(即对应的数据线11数越少),而对应的子像素1行数越多(即对应的栅极线12数越多)。
因此,参照图4、图5,若要让各单元都能就近连接相应的行、列,则在越靠近U形环区的顶部处,多路复用单元2或测试单元3应越多,而驱动单元4应越少;反之,在越靠近U形环区的两端处,则应多路复用单元2或测试单元3越少而驱动单元4越多,即各驱动单元4的“分布密度”符合以上的规律。
其中,在图1、图2、照图4、图5中,为了清楚表示其它结构,故各单元的数量较少,故各单元的分布密度的更详细情况可参照图14和图15所示。
在一些实施例中,电路区92分为沿第二方向992在显示区91两侧相对的第一半区和第二半区;
驱动单元4包括多个栅极驱动单元41;
第一半区包括多个栅极驱动单元41,栅极驱动单元41配置为向多条栅极线12提供栅极驱动信号。
参照图1、图2、图4、图5,电路区92还可分为沿第二方向992在显示区91的两侧相对的两个“半区”,且每个“半区”也基本为半圆环形(例如图1、图2中的左半圆环和右半圆环)或U形(例如图4、图5中的左半U形环和右半U形环)。
其中,由于栅极线12是沿第二方向992延伸的,故所有栅极线12均对应第一半区(图1、图2中的左半圆环,或图4、图5中的左半U形环),因此,第一半区中的驱动单元4可包括向多条栅极线12提供栅极驱动信号的栅极驱动单元41(进一步可以是第一半区921中的驱动单元4均为栅极驱动单元41),以便栅极驱动单元41就近连接对应的栅极线12。
具体的,每个栅极驱动单元41可为一个栅极移位寄存器(GOA),而多个栅极移位寄存器级联,从而多个栅极移位寄存器可分别向多条栅极线12提供驱动信号。
栅极移位寄存器的具体形式是多样的。示例性的,栅极移位寄存器的电路结构和驱动时序可参照图9和图10。其中,以下各信号的低电平具体可等于低电平信号VGL,而各信号的高电平具体可等于高电平信号VGH。
在输入阶段t1,第一栅极时钟信号CK为低电平,第二栅极时钟信号CB为高电平,输入信号STV为低电平。由于第一栅极时钟信号CK为低电平,第二栅极晶体管K2导通,输入信号STV经由第二栅极晶体管K2传输至第三栅极节点N3。由于第二栅极晶体管K2具有阈值损失,从而第三栅极节点N3的电平为STV-Vth2,即VGL-Vth2,其中,Vth2表示第二栅极晶体管K2的阈值电平。由于第六栅极晶体管K6的栅极接收低电平信号VGL,从而第六栅极晶体管K6处于开启状态,由此,电平VGL-Vth2经由第六栅极晶体管K6传输至第一栅极节点N1。例如,第六栅极晶体管K6的阈值电平表示为Vth6,同理,由于第六栅极晶体管K6具有阈值损失,第一栅极节点N1的电平为VGL-VthN1,其中,VthN1为Vth2和Vth6中较小的一个。第一栅极节点N1的电平可以控制第八栅极晶体管K8导通,第二栅极时钟信号CB经由第八栅极晶体管K8被作为栅极输出信号GOUT,即在输入阶段t1,栅 极输出信号GOUT为高电平的第二栅极时钟信号CB,即等于VGH。
在输入阶段t1,由于第一栅极时钟信号CK为低电平,第一栅极晶体管K1导通,低电平信号VGL经由第一栅极晶体管K1传输至第二栅极节点N2,由于第三栅极节点N3的电平为VGL-Vth2,第七栅极晶体管K7导通,低电平的第一栅极时钟信号CK经由第七栅极晶体管K7传输至第二栅极节点N2。例如,第七栅极晶体管K7的阈值电平表示为Vth7,第一栅极晶体管K1的阈值电平表示为Vth1,当Vth1<Vth7+Vth2时,则第二栅极节点N2的电平为VGL-Vth7-Vth2;而当Vth1>Vth7+Vth2时,则第二栅极节点N2的电平为VGL-Vth1。此时,第三栅极晶体管K3和第四栅极晶体管K4均导通。由于第二栅极时钟信号CB为高电平,第五栅极晶体管K5截止。
在输出阶段t2,第一栅极时钟信号CK为高电平,第二栅极时钟信号CB为低电平,输入信号SKT为高电平。第八栅极晶体管K8导通,第二栅极时钟信号CB经由第八栅极晶体管K8作为栅极输出信号GOUT。在输入阶段t1,第二栅极电容C2的连接第一栅极节点N1的一端的电平为VGL-VthN1,另一端的电平为高电平;而在输出阶段t2,第二栅极电容C2的连接输出端GOUT的一端的电平变为VGL,由于第二栅极电容C2的自举作用,第二栅极电容C2的连接第一栅极节点N1的一端的电平变为2VGL-VthN1-VGH,即第一栅极节点N1的电平变为2VGL-VthN1-VGH,此时,第六栅极晶体管K6截止,第八栅极晶体管K8可以更好地打开,栅极输出信号GOUT为低电平信号VGL。
在输出阶段t2,第一栅极时钟信号CK为高电平,从而第二栅极晶体管K2和第一栅极晶体管K1均截止。第三栅极节点N3的电平仍为VGL-VthN1,第七栅极晶体管K7导通,高电平的第一栅极时钟信号CK经由第七栅极晶体管K7传输至第二栅极节点N2,即第二栅极节点N2的电平为VGH,由此,第三栅极晶体管K3和第四栅极晶体管K4均截止。由于第二栅极时钟信号CB为低电平,第五栅极晶体管K5导通。
在缓冲阶段t3,第一栅极时钟信号CK和第二栅极时钟信号CB均为高电平,输入信号SKT为高电平。第八栅极晶体管K8导通,第二栅极时钟信号CB经由第八栅极晶体管K8作为栅极输出信号GOUT,此时,栅极输出 信号GOUT为高电平的第二栅极时钟信号CB,即VGH。由于第二栅极电容C2的自举作用,第一栅极节点N1的电平变为VGL-VthN1。
在缓冲阶段t3,第一栅极时钟信号CK为高电平,从而第二栅极晶体管K2和第一栅极晶体管K1均截止。第一栅极节点N1的电平变为VGL-VthN1,此时,第六栅极晶体管K6导通,第三栅极节点N3的电平也为VGL-VthN1,第七栅极晶体管K7导通,高电平的第一栅极时钟信号CK经由第七栅极晶体管K7传输至第二栅极节点N2,即第二栅极节点N2的电平为VGH,由此,第三栅极晶体管K3和第四栅极晶体管K4均截止。由于第二栅极时钟信号CB为高电平,第五栅极晶体管K5截止。
在稳定阶段t4的第一子阶段t41中,第一栅极时钟信号CK为低电平,第二栅极时钟信号CB为高电平,输入信号SKT为高电平。由于第一栅极时钟信号CK为低电平,第二栅极晶体管K2导通,输入信号SKT经由第二栅极晶体管K2传输至第三栅极节点N3,由于第二栅极晶体管K2传递高电平无阈值损失,第三栅极节点N3的电平为VGH,第七栅极晶体管K7截止。由于第六栅极晶体管K6处于开启状态,第一栅极节点N1的电平与第三栅极节点N3相同,也就是说,第一栅极节点N1的电平为VGH,第八栅极晶体管K8截止。由于第一栅极时钟信号CK为低电平,第一栅极晶体管K1导通,第二栅极节点N2的电平为VGL-Vth1,第三栅极晶体管K3和第四栅极晶体管K4均导通,高电平信号VGH经由第三栅极晶体管K3传输作为栅极输出信号GOUT,即栅极输出信号为高电平信号VGH。
在稳定阶段t4的第二子阶段t42中,第一栅极时钟信号为高电平,第二栅极时钟信号为低电平,输入信号SKT为高电平。第一栅极节点N1和第三栅极节点N3的电平为VGH,第八栅极晶体管K8和第七栅极晶体管K7均截止。第一栅极时钟信号CK为高电平,从而第二栅极晶体管K2和第一栅极晶体管K1均截止,由于第一栅极电容C1的保持作用,第二栅极节点N2的电平仍为VGL-Vth1,第三栅极晶体管K3和第四栅极晶体管K4均导通,高电平信号VGH经由第三栅极晶体管K3作为栅极输出信号GOUT,即栅极输出信号为高电平信号VGH。
在第二子阶段t42中,由于第二栅极时钟信号CB为低电平,第五栅极 晶体管K5导通,从而高电平信号VGH经由第四栅极晶体管K4和第五栅极晶体管K5被传输至第三栅极节点N3和第一栅极节点N1,以使第一栅极节点N1的电平和第三栅极节点N3的电平保持为高电平。
在稳定阶段t4的第三子阶段t43中,第一栅极时钟信号CK和第二栅极时钟信号CB均为高电平,输入信号SKT为高电平。第一栅极节点N1和第三栅极节点N3的电平为VGH,第八栅极晶体管K8和第七栅极晶体管K7截止。第一栅极时钟信号CK为高电平,从而第二栅极晶体管K2和第一栅极晶体管K1均截止,第二栅极节点N2的电平仍为VGL-Vth1,第三栅极晶体管K3和第四栅极晶体管K4均导通。高电平信号VGH经由第三栅极晶体管K3作为栅极输出信号GOUT,即栅极输出信号为高电平信号VGH。
在一些实施例中,显示区91还包括多条沿第二方向992延伸的控制极线13,每条控制极线13与多个子像素1连接;
驱动单元4为控制极驱动单元42;
位于第二半区包括多个控制极驱动单元42,控制极驱动单元42配置为向多条控制极线13提供控制极驱动信号。
参照图1、图2、图4、图5,显示区91中还可设有同样沿第二方向992延伸的控制极线13,每条控制极线13也可连接一行或两行子像素1,具体可连接以上7T1C像素电路的控制极线端EM。
其中,由于控制极线13也是沿第二方向992延伸的,故所有控制极线13均对应第二半区(图1、图2中的右半圆环,或图4、图5中的右半U形环),因此,第二半区中的驱动单元4可包括向多条控制极线13提供控制极驱动信号的控制极驱动单元42(进一步可以是第二半区922中的驱动单元4均为控制极驱动单元42),以便控制极驱动单元42就近连接对应的控制极线13。
由此,参照图1、图2、图4、图5,本公开实施例的显示基板的电路区92中,左上区域中是测试单元3和栅极驱动单元41混排,右上区域中是测试单元3和控制极驱动单元42混排,左下区域中是多路复用单元2和栅极驱 动单元41混排,右下区域中是多路复用单元2和控制极驱动单元42混排。
其中,参照图1、图2,由于圆环形不同位置的径向方向不同,故以上排布在其中的各单元也可以是随着排布位置的不同而“旋转”的,一般总是保证其输出端朝向圆心。
另外,参照图4、图5,在对应以上“弧形边界”处的各单元也可以是随着排布位置的不同而“旋转”的,一般总是保证其输出端朝向圆心。
当然,应当理解,图1、图2、图4、图5中各单元和子像素1用“矩形”表示只是示意性的,实际上每个单元和子像素1是由多个器件组成的,其占据的区域并不一定是矩形。
当然,应当理解,对于实际的显示基板,每个单元仅对应圆环形的很小一部分,故在后续部分附图中,将每个单元局部处的许多结构近似处理为直线。
当然,应当理解,基于面积的限制,本公开实施例的许多附图中,子像素1引线(如信号线)、接头、单元、区域等各种结构的形状、尺寸、尺寸比例、个数、个数比例、位置等都只是示例性的,而不是对本公开实施例的限定。例如,实际的测试信号线63、驱动信号线64等的数量应比图1、图2、图4、图5中示出的更多。
当然,以上驱动单元4的具体形式不是对本公开实施例的限定。
例如,两个半区中的驱动单元4也可均为栅极驱动单元41,并分别为不同的栅极线12提供栅极驱动信号,或者是为每条栅极线12从两侧同时提供栅极驱动信号(即双侧驱动)。
具体的,每个控制极驱动单元42可为一个控制极移位寄存器(EM GOA),而多个控制极移位寄存器级联,从而多个控制极移位寄存器可分别向多条控制极线12提供驱动信号。
而控制极移位寄存器的具体形式是多样的。示例性的,控制极移位寄存器的电路结构和驱动时序可参照图11和图12。其中,以下各信号的低电平具体可等于低电平信号VGL,而各信号的高电平具体可等于高电平信号VGH。
其中,在第一阶段P1,第一控制极时钟信号CK’为低电平,所以第一控 制极晶体管M1和第三控制极晶体管M3被导通,导通的第一控制极晶体管M1将高电平的起始信号ESTV传输至第一控制极节点N1’,从而使得第一控制极节点N1’的电平变为高电平,所以第二控制极晶体管M2、第八控制极晶体管M8以及第十控制极晶体管M10被截止。另外,导通的第三控制极晶体管M3将低电平的低电平信号VGL传输至第二控制极节点N2’,从而使得第二控制极节点N2’的电平变为低电平,所以第五控制极晶体管M5和第六控制极晶体管M6被导通。由于第二控制极时钟信号CB’为高电平,所以第七控制极晶体管M7被截止。另外,由于第三控制极电容C3’的存储作用,第四控制极节点N4的电平可以保持高电平,从而使得第九控制极晶体管M9被截止。在第一阶段P1中,由于第九控制极晶体管M9以及第十控制极晶体管M10均被截止,控制极输出信号EMOUT保持之前的低电平。
在第二阶段P2,第二控制极时钟信号CB’为低电平,所以第四控制极晶体管M4、第七控制极晶体管M7被导通。由于第一控制极时钟信号CK’为高电平,所以第一控制极晶体管M1和第三控制极晶体管M3被截止。由于第一控制极电容C1’的存储作用,所以第二控制极节点N2’可以继续保持上一阶段的低电平,所以第五控制极晶体管M5以及第六控制极晶体管M6被导通。高电平信号VGH通过导通的第五控制极晶体管M5以及第四控制极晶体管M4传输至第一控制极节点N1’,从而使得第一控制极节点N1’的电平继续保持上一阶段的高电平,所以第二控制极晶体管M2、第八控制极晶体管M8以及第十控制极晶体管M10被截止。另外,低电平的第二控制极时钟信号CB’通过导通的第六控制极晶体管M6以及第七控制极晶体管M7被传输至第四控制极节点N4’,从而使得第四控制极节点N4’的电平变为低电平,所以第九控制极晶体管M9被导通,导通的第九控制极晶体管M9将高电平信号VGH输出,所以控制极输出信号EMOUT为高电平。
在第三阶段P3,第一控制极时钟信号CK’为低电平,所以第一控制极晶体管M1以及第三控制极晶体管M3被导通。第二控制极时钟信号CB’为高电平,所以第四控制极晶体管M4以及第七控制极晶体管M7被截止。由于第三控制极电容C3’的存储作用,所以第四控制极节点N4’的电平可以保持上一阶段的低电平,从而使得第九控制极晶体管M9保持导通状态,导通的 第九控制极晶体管M9将高电平信号VGH输出,所以控制极输出信号EMOUT仍然为高电平。
在第四阶段P4,第一控制极时钟信号CK’为高电平,所以第一控制极晶体管M1以及第三控制极晶体管M3被截止。第二控制极时钟信号CB’为低电平,所以第四控制极晶体管M4以及第七控制极晶体管M7被导通。由于第二控制极电容C2’的存储作用,所以第一控制极节点N1’的电平保持上一阶段的高电平,从而使得第二控制极晶体管M2、第八控制极晶体管M8以及第十控制极晶体管M10被截止。由于第一控制极电容C1’的存储作用,第二控制极节点N2继续保持上一阶段的低电平,从而使得第五控制极晶体管M5以及第六控制极晶体管M6被导通。另外,低电平的第二控制极时钟信号CB’通过导通的第六控制极晶体管M6以及第七控制极晶体管M7被传输至第四控制极节点N4’,从而使得第四控制极节点N4’的电平变为低电平,所以第九控制极晶体管M9被导通,导通的第九控制极晶体管M9将高电平信号VGH输出,所以控制极输出信号EMOUT仍然为高电平。
在第五阶段P5,第一控制极时钟信号CK’为低电平,所以第一控制极晶体管M1以及第三控制极晶体管M3被导通。第二控制极时钟信号CB’为高电平,所以第四控制极晶体管M4以及第七控制极晶体管M7被截止。导通的第一控制极晶体管M1将低电平的起始信号ESTV传输至第一控制极节点N1’,从而使得第一控制极节点N1’的电平变为低电平,所以第二控制极晶体管M2、第八控制极晶体管M8以及第十控制极晶体管M10被导通。导通的第二控制极晶体管M2将低电平的第一控制极时钟信号CK’传输至第二控制极节点N2’,从而可以进一步拉低第二控制极节点N2’的电平,所以第二控制极节点N2’继续保持上一阶段的低电平,从而使得第五控制极晶体管M5以及第六控制极晶体管M6被导通。另外,导通的第八控制极晶体管M8将高电平信号VGH传输至第四控制极节点N4’,从而使得第四控制极节点N4的电平变为高电平,所以第九控制极晶体管M9被截止。导通的第十控制极晶体管M10将低电平信号VGL输出,所以控制极输出信号EMOUT变为低电平。
在一些实施例中,复用信号线62包括多条复用控制线621和多条复用数 据线621;
至少一个多路复用单元2包括多个复用晶体管21;每个复用晶体管21的栅极连接一条复用控制线621,第一极连接一条数据线11,第二极连接一条复用数据线621;
同一多路复用单元2的所有复用晶体管21的第二极连接同一条复用数据线621,不同的多路复用单元2的复用晶体管21的第二极连接不同的复用数据线621。
参照图1、图2、图4、图5、图6,复用信号线62包括复用控制线621和复用数据线622,而每个多路复用单元2包括多个(图6中以6个为例)复用晶体管21,每个复用晶体管21的栅极连接复用控制线621,第一极连接数据线11,第二极连接复用数据线621;而且,同一多路复用单元2连接同一条复用数据线621,不同多路复用单元2连接不同的复用数据线621。
这样,参照图6,要进行显示时,可向多条复用控制线621轮流通入导通信号(能使晶体管导通的信号),而向其它复用控制线621输入关断信号(能使晶体管关断的信号),以使一条复用数据线621经过一个多路复用单元2中的多个复用晶体管21轮流与多条不同的数据线11导通,从而通过一条复用数据线621向多条数据线11分别提供所需的数据信号,也就是实现了通过一个信号源(如接头6)对多条数据线11的控制(即实现“一拖多”,如一拖6),从而使为数据线11提供信号的信号源的数量大大小于数据线11的数量,以简化产品结构,例如可降低所需的驱动芯片的数量。
其中,从简化结构的角度考虑,复用控制线621的数量可等于每个多路复用单元2中复用晶体管21的数量(如均为6个),即每个多路复用单元2中的各复用晶体管21可分别连接不同的复用控制线621,而每条复用控制线621则与每个多路复用单元2中的各一个复用晶体管21连接。
由于复用控制线621需要连接多个多路复用单元2,故复用控制线621可具有沿扇出区93的周向延伸的部分,该部分的不同位置分别连接不同的多路复用单元2;而每条复用数据线621仅连接一个多路复用单元2,故每条复用数据线621可从扇出区93中直接连接到对应的多路复用单元2。
显然,根据以上结构,扇出区93中在周向上距离连接子区923越远的位置,复用数据线621的数量越少,从而故扇出区93的尺寸也可越小。
在一些实施例中,测试信号线63包括测试控制线631和测试数据线632;
至少一个测试单元3包括多个测试晶体管31;每个测试晶体管31的栅极连接一条测试控制线631,第一极连接一条数据线11,第二极连接一条测试数据线632;
每条测试数据线632与多个测试单元3连接。
参照图1、图2、图4、图5、图7、图8,测试信号线63包括测试控制线631和测试数据线632;相应的,每个测试单元3可包括多个测试晶体管31,测试晶体管31的栅极连接测试控制线631,第一极连接数据线11,第二极连接测试数据线632,故通过向测试控制线631通入导通信号,即可使测试信号线63中的信号经过不同测试单中的测试晶体管31进入多条相应的数据线11,以实现对显示装置的检测。
其中,由于每条测试数据线632与多个测试单元3连接,故测试数据线632的数量远远小于复用数据线621的数量。因此,虽然测试单元3位于远离接头区94的位置,但由于只要通过少数几条延伸到测试单元3的测试信号线63即可实现对其的控制,故这些少数的测试信号线63也不会占据很大的布图面积。
其中,测试数据线632、测试控制线631与测试单元3的对应关系可以是多样的。
例如,参照图7,可以是测试数据线632的数量等于每个测试单元3中测试晶体管31的数量(如均为3个),而测试控制线631只有一条,即每条测试数据线632连接每个测试单元3中的各一个测试晶体管31的第二极,而不同测试晶体管31的第一极连接不同数据线11,所有测试单元3的所有测试晶体管31的栅极均连接该测试控制线631。
这种情况下,参照图7,每条数据线11连接的子像素1颜色可以相同(图中用R表示红色子像素1,G表示绿色子像素1、B表示蓝色子像素1),且 每条测试数据线632对应的数据线11连接的子像素1颜色相同,故通过向测试数据线632持续通入相同的测试信号,可使同一颜色的子像素1显示相同的亮度(如整体显示白色画面或其它单色画面),便于定位有不良的子像素1。
再如,每条数据线11连接的子像素1颜色不同,如可参照图8,每4列子像素1中,两列子像素1为绿色,剩余两列子像素1的每一列中,红色和蓝色的子像素1交替排列,且该两列子像素1中,任意同行的两个子像素1分别为蓝色和红色。
进一步的,参照图8,共有3条测试数据线632,3条测试控制线631,而每个测试单元3可包括5个测试晶体管31,用于控制4条数据线11(对应以上4列子像素1)。其中,每个测试单元3的第一测试晶体管311和第三测试晶体管313的第一极连接一列红色和蓝色混排的子像素1,第二测试晶体管312和第四测试晶体管314的第一极连接另一列红色和蓝色混排的子像素1,第一测试晶体管311和第二测试晶体管312的第二极连接第一测试数据线6321,第三测试晶体管313和第四测试晶体管314的第二极连接第二测试数据线6322,第一测试晶体管311和第四测试晶体管314的栅极连接第一测试控制线6311,第二测试晶体管312和第三测试晶体管313的栅极连接第二测试控制线6312;而第五测试晶体管315则是栅极连接第三测试控制线6313,第一极连接两列绿色的子像素1,第二极连接第三测试数据线6323。
通过以上设置可见,通过轮流向第一测试控制线6311和第二测试控制线6312提供导通信号,即可使第一测试数据线6321和第二测试数据线6322分别控制蓝色和绿色的子像素1,而第三测试控制线6313和第三测试数据线6323则控制所有绿色的子像素1,以实现同种颜色的子像素1显示相同亮度。
在一些实施例中,测试信号线63位于电路区92远离显示区91一侧;驱动信号线64位于电路区92远离显示区91一侧。
参照图1、图2、图4、图5、图13,为便于与对应的单元连接,故测试信号线63和驱动信号线64都可沿电路区92远离显示区91一侧(外侧)设置。当然,由于扇出区93也是位于电路区92外侧的,故测试信号线63和驱 动信号线64也有一部分位于扇出区93中。
其中,测试信号线63、驱动信号线64的具体数量可根据它们对应的单元的形式不同而设定。
例如,当测试单元3为参照图7的形式时,测试信号线63可包括3条测试数据线632和一条测试控制线631,即共4条测试信号线63围绕在电路区92之外设置。
再如,当栅极驱动单元41为参照图9的形式时,其对应的驱动信号线64可为4条,分别用于传递第一栅极时钟信号CK、第二栅极时钟信号CB、高电平信号VGH、低电平信号VGL。
再如,当控制极驱动单元42为参照图11的形式时,对应的驱动信号线64可为4条,分别为用于传递第一控制极时钟信号CK’、第二控制极时钟信号CB’、高电平信号VGH、低电平信号VGL。
其中,由于第一栅极时钟信号CK、第二栅极时钟信号CB、第一控制极时钟信号CK’、第二控制极时钟信号CB’互不相同,故它们对应的可以是4条不同的驱动信号线64。而由于栅极驱动单元41和控制极驱动单元42中的高电平信号VGH、低电平信号VGL可分别相同,故所有高电平信号VGH可通过一条驱动信号线64(如高电平线641)传递,而所有低电平信号VGL可通过一条驱动信号线64(如低电平线642)传递。当然,此时的高电平线641、低电平线642应在电路区92的第一半区和第二半区外侧的位置应均有分布。
示例性的,参照图1、图2、图4、图5、图13,以上测试信号线63可位于驱动信号线64远离显示区91一侧(外侧)。
在一些实施例中,第一子区921最靠近第二子区922的端部,比第二子区922最靠近第一子区921的端部更接近显示区91。
参照图1、图2、图13,由于第一子区921内侧还设有电容区95,而第二子区922内侧就是显示区91,故第一子区921可比第二子区922“更靠内”,因此在两个子区相邻的端部处,也是第一子区921比第二子区922“更靠内”。 例如,可以是以上第一半圆环形的半径小于第二半圆环形的半径。
当然,当第一子区921和第二子区922不包括以上“圆弧区”而为其它形状时,它们可能没有“半径”,但其端部仍可符合以上位置关系,即第一子区921仍可比第二子区922“更小”。
在一些实施例中,电路区92还包括:位于第一子区921和第二子区922之间的连接子区923,连接子区被配置为电连接第一子区921和第二子区922。
在一些实施例中,连接子区923连接在第一子区921最靠近第二子区922的端部,与第二子区922最靠近第一子区921的端部之间。
参照图13,第一子区921的端部比第二子区922的端部“更靠内”,故二者的端部是“不对齐”的,可能需要通过一个斜设的连接子区923相连。
应当理解,该连接子区923也属于电路区92,其中也可也可设有驱动单元4(但因为其不是第一子区921和第二子区922,故没有多路复用单元2和测试电源),但从结构规整的角度考虑,连接子区923中的结构应尽量简单,例如仅有必要的引线(如用于不同驱动单元4间的级联的引线)。
同时,相应的,为了结构的规整,以上位于电路区92外的测试信号线63、驱动信号线64在对应连接子区923处也可弯折,以保证各测试信号线63、驱动信号线64与电路区92间的距离基本不变。
在一些实施例中,电路区还包括信号线防护单元,信号线防护单元位于连接子区923远离显示区91的一侧且与电路区92的信号线电连接,信号线防护单元被配置对电路区92的信号线起防护作用。
在一些实施例中,本公开实施例的信号线防护单元包括:
至少一个多晶硅电阻71,至少一个多晶硅电阻71中的每一个连接在两条信号线之间;多晶硅电阻71位于第一子区921最靠近第二子区922的端部的远离显示区91一侧,或位于连接子区923远离显示区91一侧。
多晶硅电阻71也称“poly电阻”,其是由多晶硅(p-Si)材料构成的阻值较大的电阻。多晶硅电阻71连接在不同的信号线之间,从而在其中一条信号线无信号时,使另一条信号线中的信号可经过延迟而一定程度上进入该信号线,避免该信号线因浮接(Floating)而信号波动;同时,当两条信号线中 均有信号时,由于该多晶硅电阻71的阻值很大,故两条信号线也不会短接,二者中的信号互不影响。
其中,为了在尽量小的布图面积中实现尽量大的电阻,故多晶硅电阻71可以是线状的多晶硅材料在一个较小区域内弯折的结构。
如前,第一子区921的端部比第二子区922的端部“更靠内”,故第一子区921的端部和连接子区923的外侧相对而言会“空出”一定的空间,因此参照图1、图2、图13,正好可将多晶硅电阻71设于该位置。例如,沿第二方向992的两侧(图1、图2中左右两侧)的第一子区921的端部和连接子区923的外侧,均可设有多晶硅电阻71。
在一些实施例中,测试信号线63位于电路区92远离显示区91一侧;
驱动信号线64位于电路区92远离显示区91一侧;
多晶硅电阻71位于测试信号线63和驱动信号线64远离显示区91一侧。
参照图1、图2、图13,当测试信号线63和驱动信号线64也位于电路区92外侧时,多晶硅电阻71可设于这些信号线的外侧,以避免多晶硅电阻71对这些信号线与电路区92中的相应单元的连接造成影响。
在一些实施例中,驱动信号线64包括高电平线641和低电平线642,测试信号线63包括测试控制线631和测试数据线632,复用信号线62包括复用控制线621和复用数据线622,至少一个多晶硅电阻71连接测试控制线631和高电平线641,至少一个多晶硅电阻71连接测试控制线631和复用控制线621。
在一些实施例中,本公开实施例的信号线防护单元还包括:
至少一个静电释放单元72;每个静电释放单元72与一条信号线连接,且配置为释放其连接的信号线中的静电;静电释放单元72位于第一子区921最靠近第二子区922的端部的远离显示区91一侧,或位于连接子区923远离显示区91一侧。
为了防止信号线中的静电积累而引起放电击穿导致损坏,还可设置静电释放单元72(ESD),以释放信号线中积累的静电,实现对信号线的保护。
如前,第一子区921的端部比第二子区922的端部“更靠内”,故第一 子区921的端部和连接子区923的外侧相对而言会“空出”一定的空间,因此参照图1、图2、图13,正好可将静电释放单元72设于该位置。例如,沿第二方向992的两侧(图1、图2中左右两侧)的第一子区921的端部和连接子区923的外侧,均可设有静电释放单元72。
其中,多晶硅电阻71和静电释放单元72所占的位置不应超过以上第一子区921的端部与第二子区922的端部的位置差,例如二者的尺寸可在100~150μm。
当然,即使在第一子区921的尺寸不必第二子区922的尺寸小(例如子区包括U形环区)时,参照图4,多晶硅电阻71和静电释放单元72也可设于第一子区921与第二子区922的交界处的外侧。
其中,应当理解,在本公开实施例的各电路图(如图7、图16)中示出的多晶硅电阻71(如第一多晶硅电阻711、第二多晶硅电阻712)仅表示多晶硅电阻71的电连接结构,而并不表示多晶硅电阻71与其它单元见的物理位置关系。
在一些实施例中,测试信号线63位于电路区92远离显示区91一侧;
驱动信号线64位于电路区92远离显示区91一侧;
静电释放单元72位于测试信号线63和驱动信号线64远离显示区91一侧。
参照图1、图2、图4、图5、图13,当测试信号线63和驱动信号线64位于电路区92外侧时,静电释放单元72也可设于这些信号线的外侧,以避免静电释放单元72对这些信号线与电路区92中的相应单元的连接造成影响。
在一些实施例中,复用信号线62包括多条复用控制线621和多条复用数据线621;每个静电释放单元72连接的信号线为测试信号线63或复用控制线621。
参照图13,静电释放单元72可有多个,分别与以上测试信号线63(如4条测试信号线63)和复用控制线621(如6条复用控制线621)连接,并对它们进行保护。
在一些实施例中,驱动信号线64包括高电平线641和低电平线642,高 电平线641配置为连接高电平信号源,低电平线642配置为连接低电平信号源;
每个静电释放单元72包括第一释放晶体管721和第二释放晶体管722:第一释放晶体管721的栅极和第一极连接高电平线641,第二极连接该静电释放单元72对应的信号线(测试信号线63或复用控制线621);第二释放晶体管722的栅极和第一极连接该静电释放单元72对应的信号线,第二极连接低电平线642。
参照图13、图16,作为本公开实施例的一种形式,静电释放单元72可包括两个释放晶体管,其中,每个释放晶体管的一极都和自身的栅极连接,从而形成等效的二极管连接;而两个“二极管”之间连接要保护的信号线,两个“二极管”的另外两端分别连接以上高电平线641(传输高电平信号VGH)和低电平线642(传输低电平信号VGL)。由此,当信号线中因积累正电荷出现瞬时高压(如100V)时,第一释放晶体管721的“二极管”导通,释放信号线中的正电荷;而当信号线中因积累负电荷出现瞬时低压(如-100V)时,第二释放晶体管722的“二极管”导通,释放信号线中的负电荷。
在一些实施例中,多晶硅电阻71包括第一多晶硅电阻711,每个第一多晶硅电阻711连接的两条信号线分别为高电平线641和测试控制线631。
参照图7、图13,可有至少部分多晶硅电阻71(第一多晶硅电阻711)连接在高电平线641(传输高电平信号VGH)和测试控制线631(传输测试单元3的控制信号)之间。在进行测试(如ET测试)时,测试控制线631根据需要获取导通信号或关断信号,第一多晶硅电阻711避免其受到高电平信号VGH的影响;而在进行正常的显示时,不再需要测试,故测试控制线631可被通入固定的关断信号,第一多晶硅电阻711保证其电平的稳定。
在一些实施例中,多晶硅电阻71包括第二多晶硅电阻712,每个第二多晶硅电阻712连接的两条信号线分别为高电平线641和静电释放单元72对应的信号线。
参照图13、图16,可有至少部分多晶硅电阻71(第二多晶硅电阻712)连接在高电平线641(传输高电平信号VGH)和静电释放单元72对应的信号线(测试信号线63或复用控制线621)之间,以防止出现过高的电平。
当然,应当理解,由于不同的静电释放单元72对应的信号线是不同的,故不同的静电释放单元72也应当连接不同的第二多晶硅电阻712,即第二多晶硅电阻712的数量可与静电释放单元72的数量相同。但在图13中,为了清楚的表示连接关系,故仅示出了部分第二多晶硅电阻712。
在一些实施例中,至少部分不同的数据线11连接的子像素1的个数不同;
除连接的子像素1个数最多的数据线11外,其它每条数据线11均连接一个补偿电容单元5。
参照图1、图2,部分情况下,不同数据线11连接的子像素1个数是不同的。例如,当显示区91基本为圆形,且每条数据线11连接一列子像素1时,因不同列中的子像素1的个数不同,故不同数据线11连接的子像素1个数也不同。
显然,每个子像素1整体上具有一定的电容(像素电容),而该电容相当于与其连接的数据线11的“负载”;因此,数据线11连接的子像素1个数不同,也就相当于数据线11的负载不同,从而会导致给数据线11施加相同信号时,与不同数据线11连接的子像素1实际获得的信号不同,影响显示。
为此,除连接的子像素1个数最多的数据线11(即负载最大的数据线11)外,其它数据线11均可连接补偿电容单元5,补偿电容单元5用于为数据线11“附加(或者说补偿)”一定的负载,以使所有数据线11的总负载(总电容)尽量接近,显示效果均匀。
在一些实施例中,每个补偿电容单元5包括一个或多个补偿电容51;
除连接的子像素1个数最多的数据线11外,与其它数据线11连接的补偿电容单元5的补偿电容51的个数n满足:
n=Nmax-N;
其中,Nmax为连接的子像素1个数最多的数据线11连接的子像素1的个数,N为与该补偿电容单元5连接的数据线11连接的子像素1的个数。
参照图17,每个补偿电容单元5可包括多个补偿电容51,而补偿电容51的个数,等于该补偿电容单元5对应的数据线11连接的子像素1个数(N), 与对应子像素1个数最多的数据线11连接的子像素1的个数Nmax之间的差;这样,只要让单个补偿电容51的电容值基本等于单个子像素1的电容值,即可使补偿后所有数据线11连接的总电容(总负载)基本相同。
通常而言,可先制备出多个实际的子像素1,并检测出单个子像素1的实际电容值,之后根据该实际电容值设定补偿电容51的实际尺寸。具体的,为降低误差,通常可检测多个(如10个)子像素1的总电容值,再除以子像素1个数(如10个),得到单个子像素1的电容值(通常约在20~30fF)。
在一些实施例中,数据线11与其连接的补偿电容单元5的所有补偿电容51的第一极相连接;
补偿电容51的第二极均连接同一个定电平信号线。
参照图17,数据线11具体可与相应的补偿电容单元5中的各补偿电容51的一极连接,而所有补偿电容51的另一极,只要连接一个定电平信号线,以获得相同的、固定的电平即可。示例性的,所有补偿电容51的另一极,可连接为像素电路的阳极信号端VDD供电的阳极信号线19。
在一些实施例中,每条数据线11连接的多个子像素1沿第一方向991排成一列;
与每条数据线11连接的补偿电容单元5,沿第一方向991设于与该数据线11连接的一列子像素1与第二子区922之间。
参照图17,当子像素1排成多列且每条数据线11连接一列子像素1时,“越短”的列中子像素1的个数越少,故其对应的补偿电容单元5中补偿电容51的个数越多,补偿电容单元5所需占的面积也越大。因此,从充分利用空间的角度考虑,可将补偿电容单元5设置在其对应的列的子像素1与第二子区922之间。
当然,以上描述的补偿电容单元5的连接关系、具体形式、设置位置等,也都不是对本公开实施例的保护范围的限定。
第二方面,本公开实施例提供一种显示装置,其包括:
上述的任意一种显示基板。
可将以上显示基板与其它器件(例如对盒盖板、柔性线路板、驱动芯片、电源组件等)组合形成具有显示功能的显示装置。
在一些实施例中,显示装置为佩戴式显示装置。
具体的,以上显示装置特别适用于作为可佩戴在人体上的佩戴式显示装置,例如显示装置可为佩戴在人的手腕上的智能手表等。
当然,对佩戴式显示装置,其中还可包括表带等用于戴在人体上的器件。
当然,以上显示装置不限于佩戴式显示装置,其也可为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开已经公开了示例实施例,并且虽然采用了具体术语,但它们仅用于并仅应当被解释为一般说明性含义,并且不用于限制的目的。在一些实例中,对本领域技术人员显而易见的是,除非另外明确指出,否则可单独使用与特定实施例相结合描述的特征、特性和/或元素,或可与其它实施例相结合描述的特征、特性和/或元件组合使用。因此,本领域技术人员将理解,在不脱离由所附的权利要求阐明的本公开的范围的情况下,可进行各种形式和细节上的改变。
Claims (20)
- 一种显示基板,包括显示区和周边区,所述周边区包括电路区,所述显示区包括:多个子像素、多条沿第一方向延伸的数据线以及多条沿与所述第一方向交叉的第二方向延伸的栅极线,每条所述数据线连接多个所述子像素,每条所述栅极线连接多个所述子像素;所述电路区包括沿所述第一方向在所述显示区两侧相对的第一子区和第二子区,所述电路区包括多个驱动单元组,所述第一子区包括多个多路复用单元组,所述第二子区包括多个测试单元组,所述多路复用单元组包括至少一个复用单元,所述测试单元组包括至少一个测试单元,所述驱动单元组包括至少一个驱动单元,所述驱动单元配置为向所述栅极线提供驱动信号,所述多路复用单元配置为向所述数据线提供数据信号,所述测试单元配置为向所述数据线提供测试信号;在所述第一子区,所述驱动单元组和多路复用单元组交替设置;在所述第二子区,所述驱动单元组和测试单元组交替设置。
- 根据权利要求1所述的显示基板,其中,所述电路区还包括连接子区,所述连接子区位于所述第一子区和所述第二子区之间,所述连接子区被配置为电连接所述第一子区和所述第二子区;所述电路区还包括信号线防护单元,所述信号线防护单元位于所述连接子区远离所述显示区的一侧且与所述电路区的信号线电连接。
- 根据权利要求2所述的显示基板,其中,所述信号线防护单元包括至少一个多晶硅电阻,所述电路区还包括多条信号线,所述至少一个多晶硅电阻的每一个连接在至少两条所述信号线之间。
- 根据权利要求3所述的显示基板,其中,所述信号线包括与所述测试单元连接的测试信号线以及与所述驱动单元连接的驱动信号线,所述驱动信号线包括高电平线和低电平线,所述测试信号线包括测试控制线和测试数据线,至少一个所述多晶硅电阻连接所述测试控制线和所述高电平线。
- 根据权利要求3所述的显示基板,其中,所述信号线包括与所述多路复用单元连接的复用信号线以及与所述测试单元连接的测试信号线,所述测试信号线包括测试控制线和测试数据线,所述复用信号线包括复用控制线和复用数据线,至少一个所述多晶硅电阻连接所述测试控制线和所述复用控制线。
- 根据权利要求2所述的显示基板,其中,所述信号线防护单元包括至少一个静电释放单元,所述信号线包括与所述多路复用单元连接的复用信号线、与所述测试单元连接的测试信号线以及与所述驱动单元连接的驱动信号线,所述至少一个静电释放单元的每一个与一条信号线连接。
- 根据权利要求6所述的显示基板,其中,所述驱动信号线包括高电平线和低电平线,所述测试信号线包括测试控制线和测试数据线,所述复用信号线包括复用控制线和复用数据线,至少一个所述静电释放单元连接所述测试控制线,或,至少一个所述静电释放单元连接所述测试数据线,或,至少一个所述静电释放单元连接所述复用控制线。
- 根据权利要求1至7任一所述的显示基板,其中,在所述第一子区中,相邻的两个所述驱动单元组之间的所述多路复用单元组包括的多路复用单元的数量C和相邻的两个所述驱动单元组之间的间隙D大小满足如下关系:D=a*C+(C+1)*d1;其中,a为每个多路复用单元沿所述多路复用单元排布方向的尺寸,d1为相邻所述多路复用单元之间的间隙大小;和/或,在所述第二子区中,相邻的两个所述驱动单元组之间的所述测试单元组包括的测试单元的数量E和相邻的两个所述驱动单元组之间的间隙F大小满足如下关系:F=b*E+(E+1)*d2;其中,b为每个测试单元沿所述测试单元排布方向的尺寸,d2为相邻所述测试单元之间的间隙大小。
- 根据权利要求8所述的显示基板,其中,d1为1微米至5微米,d2为1微米至5微米。
- 根据权利要求1至9任一项所述的显示基板,其中,所述第一子区包括第一圆弧区,所述第二子区包括第二圆弧区;在所述第一子区,所述驱动单元组和多路复用单元组交替设置,具体为:在所述第一圆弧区,所述驱动单元组和多路复用单元组沿所述第一圆弧区靠近所述显示区的一侧交替设置;在所述第二子区,所述驱动单元组和测试单元组交替设置,具体为:在所述第二圆弧区,所述驱动单元组和测试单元组沿所述第二圆弧区靠近所述显示区的一侧交替设置。
- 根据权利要求10所述的显示基板,其中,在所述第一圆弧区中,多个所述驱动单元组的覆盖区域的中心点的连线轨迹为第一圆弧轨迹,多个所述多路复用单元组的覆盖区域的中心点的连线轨迹为第二圆弧轨迹,所述第一圆弧轨迹对应的圆心、所述第二圆弧轨迹对应的圆心与所述第一圆弧区靠近所述显示区的边缘对应的圆心大致重合;和/或在所述第二圆弧区中,多个所述驱动单元组的覆盖区域的中心点的连线轨迹为第三圆弧轨迹,多个所述测试单元组的覆盖区域的中心点的连线轨迹为第四圆弧轨迹,所述第三圆弧轨迹对应的圆心、所述第四圆弧轨迹对应的圆心与所述第二圆弧区靠近所述显示区的边缘对应的圆心大致重合。
- 根据权利要求10所述的显示基板,其中,所述第一圆弧区为半圆形,所述第二圆弧区为半圆形。
- 根据权利要求10所述的显示基板,其中,所述第一子区包括第一U形环区,所述第二子区包括第二U形环区,所述第一U形环区包括两段所述第一圆弧区以及至少一段第二矩形区,所述第二U形环区包括两段所述第二圆弧区以及至少一段第三矩形区;在所述第二矩形区中,多个所述多路复用单元沿所述第二矩形区靠近所述显示区的一侧设置;在所述第三矩形区中,多个所述测试单元沿所述第三矩形区靠近所述显示区的一侧设置。
- 根据权利要求13所述的显示基板,其中,所述电路区还包括多段第一矩形区,所述第一矩形区设置在所述第一圆弧区和第二圆弧区之间;在所述第一矩形区中,多个所述驱动单元沿所述第一矩形区靠近所述显示区的一侧设置。
- 根据权利要求1至14任一所述的显示基板,其中,在所述第一子区中,所述多路复用单元组包括第一多路复用单元组和第二多路复用单元组,所述第一多路复用单元组包括M个多路复用单元,所述第二多路复用单元组包括N个多路复用单元,N、M为大于1的整数,且M<N,所述第二多路复用单元组位于所述第一子区的中部,所述第一多路复用单元组位于所述第一子区远离所述第一子区中部的两端;和/或,在所述第二子区中,所述测试单元组包括第一测试单元组和第二测试单元组,所述第一测试单元组包括K个测试单元,所述第二测试单元组包括L个测试单元,L、K为大于1的整数,且K<L,所述第二测试单元组位于所述第二子区的中部,所述第一测试单元组位于所述第二子区远离所述第二子区中部的两端。
- 根据权利要求1所述的显示基板,其中,所述周边区还包括位于所述第一子区远离所述显示区一侧的接头区,所述接头区包括多个接头,至少部分所述接头与信号线连接;所述信号线包括:与所述多路复用单元连接的复用信号线、与所述测试单元连接的测试信号线以及与所述驱动单元连接的驱动信号线。
- 根据权利要求16所述的显示基板,其中,所述周边区还包括设置于所述接头区和所述第一子区之间的扇出区,所述扇出区包括多条所述复用信号线。
- 根据权利要求16至17任一所述的显示基板,其中,所述复用信号线包括多条复用控制线和多条复用数据线;至少一个所述多路复用单元包括多个复用晶体管;每个所述复用晶体管的栅极连接一条所述复用控制线,第一极连接一条所述数据线,第二极连接一条所述复用数据线;同一所述多路复用单元的所有所述复用晶体管的第二极连接同一条所述复用数据线,不同的所述多路复用单元的复用晶体管的第二极连接不同的所述复用数据线。
- 根据权利要求16至17任一所述的显示基板,其中,所述测试信号线包括测试控制线和测试数据线;至少一个所述测试单元包括多个测试晶体管;每个所述测试晶体管的栅极连接一条所述测试控制线,第一极连接一条所述数据线,第二极连接一条所述测试数据线;每条所述测试数据线与多个所述测试单元连接。
- 一种显示装置,包括:如权利要求1至19任一所述的显示基板。
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