WO2022102181A1 - Semiconductor device manufacturing method and adhesive used therein - Google Patents

Semiconductor device manufacturing method and adhesive used therein Download PDF

Info

Publication number
WO2022102181A1
WO2022102181A1 PCT/JP2021/029407 JP2021029407W WO2022102181A1 WO 2022102181 A1 WO2022102181 A1 WO 2022102181A1 JP 2021029407 W JP2021029407 W JP 2021029407W WO 2022102181 A1 WO2022102181 A1 WO 2022102181A1
Authority
WO
WIPO (PCT)
Prior art keywords
adhesive
semiconductor device
temporary crimping
manufacturing
pressurized
Prior art date
Application number
PCT/JP2021/029407
Other languages
French (fr)
Japanese (ja)
Inventor
恵子 上野
理子 平
慎 佐藤
Original Assignee
昭和電工マテリアルズ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昭和電工マテリアルズ株式会社 filed Critical 昭和電工マテリアルズ株式会社
Priority to KR1020227006209A priority Critical patent/KR20230107467A/en
Priority to CN202180005952.0A priority patent/CN116490583A/en
Publication of WO2022102181A1 publication Critical patent/WO2022102181A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J11/00—Features of adhesives not provided for in group C09J9/00, e.g. additives
    • C09J11/02—Non-macromolecular additives
    • C09J11/06—Non-macromolecular additives organic
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J11/00—Features of adhesives not provided for in group C09J9/00, e.g. additives
    • C09J11/08—Macromolecular additives
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J163/00—Adhesives based on epoxy resins; Adhesives based on derivatives of epoxy resins
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J201/00—Adhesives based on unspecified macromolecular compounds
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • C09J7/30—Adhesives in the form of films or foils characterised by the adhesive composition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors

Definitions

  • the present disclosure relates to a method for manufacturing a semiconductor device and an adhesive used for the method.
  • FC connection method A flip-chip connection method (FC connection method) that directly connects a circuit board or another semiconductor chip is widely adopted.
  • the FC connection method is, for example, a COB (Chip On Board) type connection method for connecting a semiconductor chip and a wiring circuit board, and a CoC in which a bump or wiring is provided as a connection portion on the semiconductor chip and the semiconductor chips are connected to each other.
  • FC connection method Chip On Chip type connection method, COW (Chip On Wafer) that manufactures a semiconductor package by connecting a semiconductor chip on a wafer and then individualizing it, and WOW that manufactures a semiconductor package by crimping the wafers together. (Wafer On Wafer) or POP (Package On Package) for crimping semiconductor packages to each other.
  • the FC connection method is also used in the manufacture of a chip stack type package in which a semiconductor chip is arranged three-dimensionally instead of in a plane, and a semiconductor device having a TSV (Through-Silicon Via) structure.
  • Patent Document 1 As a method for manufacturing a semiconductor device using such an FC connection method, for example, a manufacturing method disclosed in Patent Document 1 below is known.
  • a step of temporarily crimping semiconductor chips having a connecting portion to each other via a thermosetting adhesive at a temperature lower than the melting point of the connecting portion, and a pair of obtained temporary crimping bodies are arranged facing each other.
  • the process of manufacturing a crimped body by heating while pressurizing at a temperature equal to or higher than the melting point of at least one of the connecting portions of the two semiconductor chips by sandwiching it between the pressing members of the above, and heating the crimped body in a pressurized atmosphere.
  • a method of manufacturing a semiconductor device through the steps of the process is disclosed.
  • the method for manufacturing a semiconductor device described in Patent Document 1 has the following problems. That is, in the method for manufacturing a semiconductor device described in Patent Document 1, although connection reliability is ensured, there is room for improvement in suppressing the generation of voids generated in the temporary crimping process.
  • an object of the present disclosure is to provide a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device in which the generation of voids is suppressed while ensuring good connection reliability, and an adhesive used therefor.
  • a first member having a first connecting portion and a second member having a second connecting portion are connected via an adhesive layer, and the first member is described.
  • the temperature is lower than the melting point of the first connecting portion and the melting point of the second connecting portion, and in the temporary crimping body pressurizing step, the pressure of the temporary crimping body is applied to the melting point of the first connecting portion and the said.
  • the pressure is lower than the melting point of the second connecting portion, and in the main crimping step, the pressurized crimping body is heated at a temperature equal to or higher than the melting point of at least one of the first connecting portion and the second connecting portion.
  • the heating of the pressurized temporary crimping body is performed on the first connection portion and the second connection portion. Since it is performed at a temperature equal to or higher than the melting point of at least one of them, the connection between the first connection portion and the second connection portion is performed.
  • the temporary crimping body pressurizing step performed before the main crimping step the temporary crimping body is pressurized at a temperature lower than the melting point of the first connection portion and the melting point of the second connection portion.
  • the adhesive has not been sufficiently cured and the viscosity of the adhesive is low. Therefore, when the first member and the second member are crimped in this crimping step, the repulsive force from the adhesive to the first member or the second member becomes small, and the first member and the second member Since it becomes easy to pressurize the member, the connection between the first connection portion and the second connection portion can be easily performed. As a result, it is possible to ensure good connection reliability.
  • a gap is likely to be formed between the adhesive and the first member and at least one between the adhesive and the second member, and this gap is likely to be formed. If remains as it is, it will remain as a void in the semiconductor device.
  • the voids can be eliminated by pressurizing and compressing.
  • this pressurization is performed after the main crimping step, the adhesive is heated to a temperature equal to or higher than the melting point of at least one of the first connection portion and the second connection portion in the main crimping step. Curing has progressed and the viscosity of the adhesive has already increased.
  • the connection between the first connecting portion and the second connecting portion is completed, and the position of the second member with respect to the first member is fixed. Therefore, even if the adhesive is pressed, it is difficult to apply sufficient pressure to the adhesive. Therefore, after the main crimping step, the voids cannot be sufficiently compressed and are likely to be left as voids in the adhesive layer of the semiconductor device.
  • the temperature at which the pressure of the void is lower than the melting point of the first connecting portion and the melting point of the second connecting portion in the temporary crimping body pressurizing step before the main crimping step.
  • the adhesive is not cured as compared with the case where it is carried out at a temperature equal to or higher than the melting point of at least one of the first connection portion and the second connection portion, and the viscosity of the adhesive is low. It becomes easy to compress the voids, and the voids are less likely to be left as voids in the adhesive layer of the semiconductor device.
  • the manufacturing method of the present disclosure it is possible to manufacture a semiconductor device in which the generation of voids is suppressed. From the above, according to the method for manufacturing a semiconductor device of the present disclosure, it is possible to manufacture a semiconductor device in which the generation of voids is suppressed while ensuring good connection reliability.
  • the temporary crimping step it is preferable to pressurize the temporary crimping body at a temperature lower than the reaction start temperature of the adhesive.
  • the reaction of the adhesive is less likely to start, and the adhesive has not been cured at the start of the temporary crimping body pressurizing step. Therefore, voids generated in the temporary crimping step can be easily eliminated. can.
  • the temporary crimping body pressurizing step it is preferable to pressurize the temporary crimping body at a pressure of 0.05 to 0.8 MPa in the temporary crimping body pressurizing step.
  • the generation of voids can be suppressed in the adhesive layer of the semiconductor device, and the connection reliability of the semiconductor device can be further improved.
  • the temporary crimping body pressurizing step it is preferable to pressurize the temporary crimping body at a temperature equal to or higher than the reaction start temperature of the adhesive.
  • the voids can be compressed more effectively while the adhesive is flowing.
  • thermosetting adhesive used for adhering the first member and the second member in the method for manufacturing a semiconductor device.
  • the adhesive contains an epoxy resin, a curing agent and a flux agent, exhibits a minimum melt viscosity of 1500 Pa ⁇ s or less, and exhibits a gel time of 35 seconds or more and 80 seconds or less at 150 ° C.
  • the adhesive is less likely to get caught between the first connection portion and the second connection portion as compared with the case where the minimum melt viscosity of the adhesive exceeds 1500 Pa ⁇ s, and the first connection portion and the second connection portion are difficult to bite. Since the connection failure with the semiconductor device is less likely to occur, the connection reliability of the semiconductor device is further improved. Further, as compared with the case where the gel time is longer than 80 seconds, the adhesive is more likely to be cured in the temporary crimping body pressurizing step and the main crimping step, and voids are less likely to remain in the adhesive layer of the semiconductor device, so that voids are generated. It is possible to manufacture a more suppressed semiconductor device.
  • the reaction of the adhesive is less likely to proceed during the temporary crimping step, and the adhesive is less likely to be cured before the voids are removed in the temporary crimping body pressurizing step. Since it becomes easy to remove voids, it is possible to manufacture a semiconductor device in which the generation of voids is further suppressed.
  • the weight average molecular weight of the epoxy resin contained in the adhesive is preferably less than 10,000.
  • the adhesive further contains a polymer component and the weight average molecular weight of the polymer component is 10,000 or more.
  • the adhesive is more excellent in heat resistance and film forming property than in the case where the weight average molecular weight of the polymer component is less than 10,000. Therefore, if an adhesive is used, a semiconductor device having higher heat resistance can be manufactured. Further, the shape of the adhesive is easily maintained in the temporary crimping step, the temporary crimping body pressurizing step, and the main crimping step, and the semiconductor device can be efficiently manufactured.
  • the weight average molecular weight of the polymer component is 30,000 or more and the glass transition temperature of the polymer component is 200 ° C. or less.
  • the adhesive can have good film-forming properties by itself, and the shape of the adhesive can be easily maintained in the temporary crimping step, the temporary crimping body pressurizing step, and the main crimping step. Manufacturing efficiency is further improved. Further, the adhesive makes it easier to embed the unevenness on the surface of the second member side of the first member or the unevenness on the surface of the first member side of the second member, and the effect of suppressing voids is relative. Tends to grow.
  • the adhesive is preferably a film-like adhesive.
  • the adhesive is in the form of a film, the manufacturing efficiency of the semiconductor device is further improved.
  • the "melting point of the first connection portion” means the melting point of the material forming the surface portion of the first connection portion.
  • the “melting point of the second connecting portion” means the melting point of the material forming the surface portion of the second connecting portion.
  • a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device in which the generation of voids is suppressed while ensuring good connection reliability, and an adhesive used therefor.
  • FIG. 1 is a partial cross-sectional view showing a semiconductor device manufactured by one embodiment of the method for manufacturing a semiconductor device of the present disclosure.
  • the semiconductor device 100 includes a semiconductor chip (first member) 1 having a bump 30 as a first connection portion, and a wiring circuit board (second member) having a wiring 16 as a second connection portion.
  • the member) 2 is electrically connected to the member) 2 via the adhesive layer 40A.
  • the semiconductor chip 1 includes a semiconductor chip main body 10, a wiring 15 provided on one surface of the semiconductor chip main body 10, and a bump 30 provided on the wiring 15.
  • the wiring circuit board 2 includes a board main body 20 and a wiring 16 provided on one surface of the board main body 20. In the semiconductor device 100, the bump 30 on the semiconductor chip 1 and the wiring 16 on the wiring circuit board 2 are electrically connected.
  • FIG. 2 is a process diagram showing a temporary crimping process in one embodiment of the semiconductor device manufacturing method of the present disclosure
  • FIG. 3 shows a temporary crimping body pressurizing step in one embodiment of the semiconductor device manufacturing method of the present disclosure.
  • the process diagram and FIG. 4 are process diagrams showing the present crimping process in one embodiment of the method for manufacturing a semiconductor device of the present disclosure.
  • a semiconductor chip 1 having a bump 30 and a wiring circuit board 2 having a wiring 16 are provided with an adhesive layer 40A.
  • a temporary crimping step (see FIG. 2) in which the bump 30 and the wiring 16 are temporarily crimped to obtain a temporary crimping body 4 in a state where the bump 30 and the wiring 16 are opposed to each other via a thermosetting adhesive 40 for forming, and a temporary crimping.
  • a temporary crimping body pressurizing step see FIG.
  • the present crimping step (see FIG. 4) of connecting the bump 30 and the wiring 16 to obtain a crimping body 6 by crimping the chip 1 and the wiring circuit board 2 is included. Then, in the temporary crimping step, the semiconductor chip 1 and the wiring circuit board 2 are temporarily crimped at a temperature lower than the melting point of the bump 30 and the melting point of the wiring 16, and in the temporary crimping body pressurizing step, the temporary crimping body is used.
  • the pressurization of 4 is performed at a temperature lower than the melting point of the bump 30 and the melting point of the wiring 16. Further, in this crimping step, the pressurized temporary crimping body 5 is heated at a temperature equal to or higher than the melting point of at least one of the bump 30 and the wiring 16.
  • the heating of the pressurized temporary crimping body 5 is performed at least among the bump 30 and the wiring 16. Since it is heated to a temperature equal to or higher than one melting point, the bump 30 and the wiring 16 are connected.
  • the pressure of the temporary crimping body 4 is performed at a temperature lower than the melting point of the bump 30 and the melting point of the wiring 16. At the starting point, the adhesive 40 has not been sufficiently cured, and the viscosity of the adhesive 40 is low.
  • the temporary crimping body 4 obtained in the temporary crimping step a gap is likely to be formed between the adhesive 40 and the semiconductor chip 1 and at least one between the adhesive 40 and the wiring circuit board 2. If this void remains as it is, it will remain as a void in the semiconductor device 100.
  • the voids can be eliminated by pressurizing and compressing.
  • this pressurization is performed after the main crimping step, the adhesive 40 is heated to a temperature equal to or higher than the melting point of at least one of the bump 30 and the wiring 16 in the main crimping step, and the curing proceeds. , The viscosity of the adhesive 40 is already high.
  • the connection between the bump 30 and the wiring 16 is completed, and the position of the semiconductor chip 1 with respect to the wiring circuit board 2 is fixed. Therefore, even if the adhesive 40 is pressed, it is difficult to apply sufficient pressure to the adhesive 40. Therefore, after the main crimping step, the voids cannot be sufficiently compressed and are likely to be left as voids in the adhesive layer 40A of the semiconductor device 100.
  • the pressure of the void is heated at a temperature lower than the melting point of the bump 30 and the melting point of the wiring 16 in the temporary crimping body pressurizing step before the main crimping step.
  • the adhesive 40 is not cured as compared with the case where the adhesive 40 is performed at a temperature equal to or higher than the melting point of at least one of the bump 30 and the wiring 16, and the viscosity of the adhesive 40 is low. It becomes easy to compress, and voids are less likely to be left as voids in the adhesive layer 40A of the semiconductor device 100.
  • the manufacturing method of the present embodiment it is possible to manufacture the semiconductor device 100 in which the generation of voids is suppressed. From the above, according to the method for manufacturing a semiconductor device of the present embodiment, it is possible to manufacture a semiconductor device 100 in which the generation of voids is suppressed while ensuring good connection reliability.
  • the semiconductor chip main body 10 and the semiconductor chip 1 having the bump 30 as the first connection portion are used as the substrate main body 20 and the second connection portion.
  • the laminated body 3 is formed by superimposing the adhesive 40 on the wiring circuit board 2 having the wiring 16 while arranging the adhesive 40 between them.
  • the semiconductor chip 1 is formed, for example, by dicing a semiconductor wafer, then is picked up and conveyed onto the wiring circuit board 2, and is aligned so that the bump 30 as the first connection portion and the wiring 16 are arranged so as to face each other. Will be done.
  • the laminated body 3 is formed on the stage 42 of the pressing device 43 having the crimping head 41 and the stage 42 as a pair of temporarily crimping pressing members arranged so as to face each other.
  • the bump 30 is provided on the wiring 15 provided on the semiconductor chip main body 10.
  • the wiring 16 of the wiring circuit board 2 is provided at a predetermined position on the board main body 20.
  • the bump 30 and the wiring 16 each have a surface portion formed of a metal material.
  • the adhesive 40 may be applied to the surface of the semiconductor chip 1 on the wiring circuit board 2 side, or may be applied to the surface of the wiring circuit board 2 on the semiconductor chip 1 side, and is in the form of a film prepared in advance.
  • the adhesive may be attached to the wiring circuit board 2.
  • the film-shaped adhesive 40 can be attached by a heat press, a roll laminate, a vacuum laminate, or the like.
  • the area and thickness of the adhesive 40 are appropriately set according to the size of the semiconductor chip 1 or the wiring circuit board 2, the heights of the bumps 30 and the wiring 16, and the like.
  • the film-shaped adhesive 40 may be attached to the semiconductor chip 1. In this case, for example, by attaching a film-shaped adhesive to a semiconductor wafer and then dicing the semiconductor wafer to separate the semiconductor wafer, a semiconductor chip 1 to which the film-shaped adhesive 40 is attached can be obtained.
  • the laminated body 3 is pressed by being sandwiched between the stage 42 as the temporary crimping pressing member and the crimping head 41, whereby the semiconductor chip 1 and the wiring circuit are pressed.
  • the crimping head 41 is arranged on the semiconductor chip 1 side, and the stage 42 is arranged on the wiring circuit board 2 side.
  • a flip chip bonder or the like can be used as the temporary crimping pressing device 43 having the stage 42 and the crimping head 41.
  • At least one of the stage 42 and the crimping head 41 has the melting point of the bump 30 as the first connection portion of the semiconductor chip 1 and the second connection portion of the wiring circuit board 2.
  • the wiring is performed at a temperature lower than the melting point of the wiring 16.
  • the temporary crimping step from the viewpoint of suppressing transfer of heat to the semiconductor chip 1 due to contact of the temporary crimping pressing member with the semiconductor chip 1 when picking up the semiconductor chip 1 as the first member, temporary crimping is performed. It is preferable that the pressing member is set to a low temperature. On the other hand, while the laminated body 3 is pressed for temporary crimping, the temporary crimping pressing member may be heated to a high temperature to some extent in order to increase the fluidity of the adhesive 40 to the extent that the entrained voids can be eliminated.
  • the temperature of the temporary crimping pressing member when the semiconductor chip 1 is picked up and the laminated body 3 are heated and applied in order to obtain the temporary crimping body 4.
  • this temperature difference is preferably 100 ° C. or lower, more preferably 60 ° C. or lower, and even more preferably substantially 0 ° C. This temperature difference may be constant. When the temperature difference is 100 ° C. or less, the time required for cooling the temporary crimping pressing member can be further shortened.
  • the temperature of the temporary crimping pressing member when the laminated body 3 is pressed to obtain the temporary crimping body 4 may be a temperature equal to or higher than the reaction starting temperature of the adhesive 40, and is lower than the reaction starting temperature of the adhesive 40.
  • the temperature may be, but it is preferably a temperature lower than the reaction start temperature of the adhesive 40. In this case, the reaction of the adhesive 40 is less likely to start, and the adhesive 40 has not been cured at the start of the temporary crimping body pressurizing step. Therefore, voids generated in the temporary crimping step are easily eliminated. be able to.
  • the reaction start temperature was measured using DSC (manufactured by PerkinElmer, product name "DSC-Pyrs1") under the conditions of a sample amount of 10 mg of the adhesive 40, a heating rate of 10 ° C./min, and a measurement atmosphere: nitrogen. It refers to the On-set temperature in the DSC thermogram that is sometimes obtained.
  • the temperature of the temporary crimping pressing member is preferably 70 ° C. or higher from the viewpoint of more easily eliminating the void generated in the temporary crimping step.
  • the pressing load for pressurizing the laminated body 3 in order to obtain the temporary crimping body 4 is appropriately set in consideration of the number of bumps 30, absorption of height variations of the bumps 30, and the amount of deformation of the bumps 30. At this time, it is preferable that the pressing load is set so that the bump 30 of the semiconductor chip 1 and the wiring 16 of the wiring circuit board 2 come into contact with each other in the temporary crimping body 4 by pressurizing the laminated body 3. In this case, a metal bond between the bump 30 and the wiring 16 is likely to be formed in the main crimping step to be performed later, and the adhesive 40 tends to be less likely to be caught between the bump 30 and the wiring 16.
  • the pressing load for pressurizing the laminated body 3 in order to obtain the temporary crimping body 4 is, for example, 0.009 or more per bump 30 of the semiconductor chip 1. It may be set to 0.5N.
  • the time for pressurizing the laminated body 3 to obtain the temporary pressure-bonded body 4 is not particularly limited, but from the viewpoint of improving productivity, it is preferably 5 seconds or less, and preferably 3 seconds or less. It is more preferably 2 seconds or less, and particularly preferably 2 seconds or less. However, the time for pressurizing the laminated body 3 to obtain the temporary crimped body 4 may be 0.1 seconds or longer. Further, when the bump 30 and the wiring 16 are brought into contact with each other, it is desirable that the time for pressurizing the laminated body 3 to obtain the temporary crimping body 4 is the time until the bump 30 and the wiring 16 come into contact with each other.
  • the semiconductor chip main body 10 is not particularly limited, and various semiconductors such as elemental semiconductors composed of elements of the same type such as silicon and germanium, and compound semiconductors such as gallium arsenide and indium phosphorus can be used.
  • the wiring circuit board 2 is not particularly limited, and has an insulating substrate containing glass epoxy, polyimide, polyester, ceramic, epoxy, bismaleimide triazine and the like as a main component as the substrate main body 20, and a metal formed on the surface thereof.
  • a circuit board or the like on which a conductive material is printed and wiring (wiring pattern) is formed can be used.
  • the materials of the bump 30 and the wiring 16 are, for example, gold, silver, copper, solder (main components are, for example, tin-silver, tin-lead, tin-bismuth, tin-copper, tin-silver-copper), tin, and so on. Contains metals such as nickel as the main component.
  • the bump 30 and the wiring 16 may be composed of only a single component, or may be composed of a plurality of components.
  • the bump 30 and the wiring 16 may have a structure in which these metals are laminated.
  • gold, silver or copper is preferable, and silver or copper is more preferable, from the viewpoint of manufacturing a semiconductor device (package) 100 having excellent electrical conductivity and thermal conductivity of the bump 30 and the wiring 16.
  • inexpensive silver, copper or solder is preferable, copper or solder is more preferable, and solder is particularly preferable.
  • Gold, silver, copper or solder is preferable, gold, silver or solder is more preferable, and gold or gold is preferable from the viewpoint of suppressing the formation of an oxide film on the metal surface at room temperature to suppress a decrease in productivity and an increase in cost.
  • Silver is more preferred.
  • Solder is preferable from the viewpoint of improving the connection reliability of the semiconductor device 100 and suppressing warpage.
  • the bump 30 and the wiring 16 are mainly composed of gold, silver, copper, solder (main components are, for example, tin-silver, tin-lead, tin-bismuth, tin-copper), tin, nickel and the like as surface portions. It may have a metal layer. Such a metal layer can be formed, for example, by plating. This metal layer may be composed of only a single component or may be composed of a plurality of components. Further, the metal layer may have a structure composed of a single layer or a structure in which a plurality of metal layers are laminated.
  • Temporal crimping body pressurizing process In the temporary crimping body pressurizing step, after the temporary crimping body 4 is obtained, as shown in FIG. 3, the temporary crimping body 4 is heated while being pressurized under the pressurized atmosphere in the heating furnace 60. At this time, it is preferable to pressurize a plurality of temporary crimping bodies 4 at once in one heating furnace 60. This is due to the following reasons. That is, when a plurality of temporary crimping bodies 4 are collectively pressed by using the pressing member, it is difficult to uniformly pressurize the plurality of temporary crimping bodies 4.
  • a large number of temporary crimping bodies 4 can be easily and uniformly pressed, thereby increasing the productivity of the semiconductor device 100. Is improved.
  • a heating furnace 60 a reflow furnace, a pressure oven, or the like can be used.
  • the fillet suppression means that the fillet width is suppressed to be small, and the fillet width is the length of the adhesive protruding from the outer peripheral portion of the semiconductor device 100.
  • the fillet width can be measured, for example, by taking an external image of the semiconductor device 100 with a digital microscope (manufactured by KEYENCE, product name "VHX-5000") and measuring the obtained image.
  • the fillet value is preferably 150 ⁇ m or less from the viewpoint of mounting many semiconductor chips 1 on the wiring circuit board 2.
  • the atmosphere in the heating furnace 60 is not particularly limited, and may be, for example, air, nitrogen, formic acid, or the like.
  • the pressure (atmospheric pressure) of the pressurized atmosphere in the heating furnace 60 is appropriately set according to the size and number of the semiconductor chips 1 or the wiring circuit board 2 to be connected.
  • the pressure for pressurization is not particularly limited, but may be, for example, higher than atmospheric pressure and 1 MPa or less. At this time, it is preferable that the pressure is large from the viewpoint of suppressing voids and improving connection reliability. On the other hand, from the viewpoint of fillet suppression, it is preferable that the pressure is small. Therefore, in consideration of void suppression and improvement of connection reliability, the pressure for pressurization is preferably 0.05 to 0.8 MPa.
  • the set temperature of the heating furnace 60 is the melting point of the bump 30 as the first connecting portion of the semiconductor chip 1 and the second connecting portion of the wiring circuit board 2.
  • the temperature is lower than the melting point of the wiring 16.
  • the set temperature of the heating furnace 60 is set to a temperature equal to or higher than the melting point of at least one of the bump 30 as the first connection portion of the semiconductor chip 1 and the wiring 16 as the second connection portion of the wiring circuit board 2.
  • the gap between the semiconductor chip 1 and the adhesive 40 or between the wiring circuit board 2 and the adhesive 40 can be easily compressed, and the gap is sufficiently in the adhesive layer 40A of the semiconductor device 100.
  • the generation of voids can be further suppressed. Further, since the curing of the adhesive 40 does not proceed excessively, in the main crimping step, the bump 30 and the wiring 16 can be easily connected in the pressurized temporary crimping body 5, and the semiconductor device 100 can be connected. The reliability can be further improved.
  • the set temperature of the heating furnace 60 when the temporary crimping body 4 is pressurized may be equal to or higher than the reaction start temperature of the adhesive 40, and may be lower than the reaction start temperature. , It is preferable that the temperature is equal to or higher than the reaction start temperature of the adhesive 40. In this case, the voids can be compressed more effectively while the adhesive 40 is made to flow.
  • the difference ( ⁇ T2) between the set temperature of the heating furnace 60 and the reaction start temperature of the adhesive 40 is 5 ° C. or higher. Is preferable, and the temperature is more preferably 10 ° C. or higher. However, ⁇ T2 is preferably 100 ° C. or lower.
  • the set temperature of the heating furnace 60 when the temporary crimping body 4 is pressurized is set when the laminated body 3 is pressed in order to obtain the temporary crimping body 4 (temporary crimping of the semiconductor chip 1 and the wiring circuit board 2).
  • the temperature may be lower than or equal to the temperature of the temporary crimping pressing member (at the time of performing), or higher than the temperature of the temporary crimping pressing member when the laminated body 3 is pressed to obtain the temporary crimping body 4.
  • it is preferable that the temperature is higher than the temperature of the temporary crimping pressing member when the laminated body 3 is pressed in order to obtain the temporary crimping body 4.
  • the set temperature of the heating furnace 60 when the temporary crimping body 4 is pressurized is preferably 140 ° C. or higher, more preferably 145 ° C. or higher, and 150 ° C. or higher, from the viewpoint of effectively compressing the voids while flowing. It is particularly preferable that the temperature is above ° C. However, the set temperature of the heating furnace 60 when pressurizing the temporary crimping body 4 is preferably 260 ° C. or lower.
  • the stage 45 and the crimping head 44 arranged to face each other are used for a pair of main crimping.
  • the pressing device 46 as a member, the pressurized temporary crimping body 5 is pressed while being heated by a hot press sandwiched between the stage 45 and the crimping head 44 to form the crimping body 6.
  • the pressing device 46 may be the same as the pressing device 43, or may be prepared separately.
  • At least one of the stage 45 and the crimping head 44 is heated to a temperature equal to or higher than the melting point of at least one of the melting point of the bump 30 and the melting point of the wiring 16 when the pressurized temporary crimping body 5 is pressurized.
  • the melting point Further, in the crimping body 6, the semiconductor chip 1 and the wiring circuit board 2 are usually electrically connected by metal bonding of the bump 30 and the wiring 16.
  • the crimping body 6 may be used as it is as a semiconductor device, or after the main crimping step, the crimping body 6 is further heated under a pressurized atmosphere to further cure the adhesive 40 to form the adhesive layer 40A, and then the semiconductor. It may be the device 100.
  • the crimping head 44 is arranged on the semiconductor chip 1 side of the pressurized temporary crimping body, and the stage 45 is arranged on the wiring circuit board 2 side of the pressurized temporary crimping body.
  • the wiring 16 and the bump 30 are sealed by the adhesive 40 so as to be shielded from the external environment.
  • the temperature of at least one of the stage 45 and the crimping head 44 may be set to a temperature higher than the temperature at which the oxide film on the surface of at least one of the bump 30 and the wiring 16 is efficiently removed. From this point of view, the temperature of at least one of the stage 45 and the crimping head 44 is preferably 220 ° C. or higher and 330 ° C. or lower.
  • the solder of the bump 30 or the wiring 16 melts as compared with the case where the temperature of at least one of the stage 45 and the crimping head 44 is lower than 220 ° C. Sufficient metal bonds are likely to be formed.
  • the temperature is 330 ° C. or lower, voids are less likely to occur and solder is less likely to scatter than when the temperature exceeds 330 ° C.
  • the temperature of at least one of the stage 45 and the crimping head 44 may be 220 ° C. or higher even when the metal material of at least one of the bump 30 and the wiring 16 contains Sn / Ag having a melting point of about 220 ° C.
  • the pressing load is the removal of the oxide film on the surface of at least one of the bump 30 and the wiring 16, the number of bumps 30, and the number of bumps 30. It is appropriately set in consideration of absorption of height variation, control of the amount of deformation of the bump 30 and the like.
  • the pressing load may be, for example, 0.009 to 0.2 N per bump 30 of the semiconductor chip 1.
  • this pressing load is 0.009 N or more, the oxide film formed on at least one of the bump 30 and the wiring 16 can be easily removed, or the adhesive 40 is applied to at least one of the bump 30 and the wiring 16. It becomes difficult to be trapped. Further, when the pressing load is 0.2 N or less, problems such as bumps containing solder and the like being crushed or scattered are unlikely to occur.
  • the time for pressurizing the pressed temporary crimping body 5 while heating to obtain the crimping body 6 is preferably 5 seconds or less, more preferably 3 seconds or less, and 2 It is particularly preferably less than a second.
  • the time for pressurizing the pressed temporary crimping body 5 while heating to obtain the crimping body 6 may be 0.1 seconds or longer.
  • the method of heating and pressurizing the pressurized temporary crimping body 5 is not limited to the hot press as shown in FIG. 4, for example, using a heating furnace, the pressurized temporary crimping body 5 is pressurized in a pressurized atmosphere in the heating furnace. May be heated.
  • a heating furnace a reflow furnace, a pressure oven, or the like can be used.
  • the atmosphere in the heating furnace is not particularly limited, but may be air, nitrogen, formic acid, or the like.
  • the adhesive used in the embodiment of the above-mentioned method for manufacturing a semiconductor device will be described.
  • the adhesive of the present embodiment is not particularly limited as long as it is a thermosetting adhesive, and contains, for example, an epoxy resin, a curing agent, and a flux agent.
  • Epoxy resin The epoxy resin is not particularly limited as long as it has two or more epoxy groups in the molecule.
  • the epoxy resin bisphenol A type epoxy resin, bisphenol F type epoxy resin, naphthalene type epoxy resin, phenol novolac type epoxy resin, cresol novolac type epoxy resin, phenol aralkyl type epoxy resin, biphenyl type epoxy resin, triphenylmethane type epoxy
  • Various polyfunctional epoxy resins such as resins and dicyclopentadiene type epoxy resins can be used. These can be used alone or in combination of two or more.
  • the weight average molecular weight of the epoxy resin is not particularly limited, but is preferably less than 10,000.
  • Epoxy resin is an epoxy resin with a thermogravimetric reduction rate of 5% or less at the temperature at the time of connection (heating temperature in this crimping process) from the viewpoint of suppressing decomposition and generation of volatile components at the time of connection at high temperature. It is preferable to use it. For example, when the temperature at the time of connection is 250 ° C., it is preferable to use an epoxy resin having a thermogravimetric reduction rate of 5% or less at 250 ° C., and when the temperature is 300 ° C., the thermogravimetric analysis rate at 300 ° C. is 5%. It is preferable to use the following epoxy resin.
  • the content of the epoxy resin is, for example, 5 to 75% by mass, preferably 10 to 50% by mass, and more preferably 15 to 35% by mass based on the total amount of the adhesive 40.
  • the curing agent examples include a phenol resin-based curing agent, an acid anhydride-based curing agent, an amine-based curing agent, an imidazole-based curing agent, and a phosphine-based curing agent.
  • the curing agent is a phenolic resin-based curing agent, an acid anhydride-based curing agent, and the like. It is preferable to contain at least one selected from an amine-based curing agent and an imidazole-based curing agent, and it is more preferable to contain an imidazole-based curing agent.
  • each curing agent will be described.
  • the phenol resin-based curing agent is not particularly limited as long as it has two or more phenolic hydroxyl groups in the molecule, and examples thereof include phenol novolac resin, cresol novolak resin, phenol aralkyl resin, and cresol naphthol formaldehyde polycondensation. Examples thereof include triphenylmethane-type polyfunctional phenols and various polyfunctional phenol resins. These can be used alone or as a mixture of two or more.
  • the equivalent ratio (phenolic hydroxyl group / epoxy group, molar ratio) of the phenol resin-based curing agent to the epoxy resin is preferably 0.3 to 1.5 from the viewpoint of good curability, adhesiveness and storage stability, and is 0. .4 to 1.0 is more preferable, and 0.5 to 1.0 is even more preferable.
  • the equivalent ratio is 0.3 or more, the curability tends to be improved and the adhesive strength tends to be improved, and when it is 1.5 or less, unreacted phenolic hydroxyl groups do not remain excessively and the water absorption rate is high. It is kept low and tends to improve the insulation reliability of the semiconductor device 100.
  • the equivalent ratio is 0.3 to 1.5, it is easy to adjust the gel time to an appropriate range.
  • acid anhydride-based curing agent examples include methylcyclohexanetetracarboxylic acid dianhydride, trimellitic anhydride, pyromellitic anhydride, benzophenonetetracarboxylic acid dianhydride, and ethylene glycol bisanhydrotrimeritate. These can be used alone or as a mixture of two or more.
  • the equivalent ratio of the acid anhydride-based curing agent to the epoxy resin is preferably 0.3 to 1.5 from the viewpoint of good curability, adhesiveness and storage stability. , 0.4 to 1.0 is more preferable, and 0.5 to 1.0 is even more preferable.
  • the equivalent ratio is 0.3 or more, the curability tends to be improved and the adhesive strength tends to be improved, and when it is 1.5 or less, unreacted acid anhydride does not remain excessively and the water absorption rate is high. It is kept low and tends to improve the insulation reliability of the semiconductor device 100.
  • the equivalent ratio is 0.3 to 1.5, it is easy to adjust the gel time to an appropriate range.
  • amine-based curing agent for example, dicyandiamide can be used.
  • the equivalent ratio (amino group / epoxy group, molar ratio) of the amine-based curing agent to the epoxy resin is preferably 0.3 to 1.5, preferably 0.4 to 1.5, from the viewpoint of good curability, adhesiveness and storage stability. 1.0 is more preferable, and 0.5 to 1.0 is even more preferable.
  • the equivalent ratio is 0.3 or more, the curability tends to be improved and the adhesive strength tends to be improved, and when it is 1.5 or less, unreacted amine does not remain excessively, and the insulation of the semiconductor device 100 is insulated. Reliability tends to improve.
  • the equivalent ratio is 0.3 to 1.5, it is easy to adjust the gel time to an appropriate range.
  • imidazole-based curing agent examples include 2-phenylimidazole, 2-phenyl-4-methylimidazole, 1-benzyl-2-methylimidazole, 1-benzyl-2-phenylimidazole, and 1-cyanoethyl-2-undecylimidazole.
  • the imidazole-based curing agent may be selected from the body, 2-phenylimidazole isocyanuric acid ad
  • the content of the imidazole-based curing agent is preferably 0.1 to 20 parts by mass, more preferably 0.1 to 10 parts by mass, and further preferably 3.2 to 5.5 parts by mass with respect to 100 parts by mass of the epoxy resin. preferable.
  • the content of the imidazole-based curing agent is 0.1 parts by mass or more, the curability of the adhesive 40 tends to be improved, and when it is 20 parts by mass or less, a metal bond is formed between the bump 30 and the wiring 16.
  • the adhesive 40 does not harden before the adhesive 40 is formed, and there is a tendency that a poor connection between the bump 30 and the wiring 16 is less likely to occur.
  • the content of the imidazole-based curing agent is 0.1 to 20 parts by mass, it is easy to adjust the gel time to an appropriate range.
  • phosphine-based curing agent examples include triphenylphosphine, tetraphenylphosphonium tetraphenylborate, tetraphenylphosphonium tetra (4-methylphenyl) borate and tetraphenylphosphonium (4-fluorophenyl) borate.
  • the content of the phosphine-based curing agent is preferably 0.1 to 10 parts by mass, more preferably 0.1 to 5 parts by mass with respect to 100 parts by mass of the epoxy resin.
  • the content of the phosphine-based curing agent is 0.1 parts by mass or more, the curability of the adhesive 40 tends to be improved, and when it is 10 parts by mass or less, a metal bond is formed between the bump 30 and the wiring 16.
  • the adhesive 40 does not cure before the adhesive 40 is formed, and there is a tendency that poor connection between the bump 30 and the wiring 16 is unlikely to occur.
  • the phenolic resin-based curing agent, acid anhydride-based curing agent, and amine-based curing agent can be used alone or as a mixture of two or more.
  • the imidazole-based curing agent and the phosphine-based curing agent may be used alone, or may be used together with a phenol resin-based curing agent, an acid anhydride-based curing agent, or an amine-based curing agent.
  • the flux agent is, for example, a compound having a group represented by the formula (1).
  • the flux agent one containing only one type of group represented by the following formula (1) or two or more types can be used.
  • R 1 represents a hydrogen atom or an electron donating group.
  • the electron donating group include an alkyl group, a hydroxyl group, an amino group, an alkoxy group, and an alkylamino group.
  • the electron donating group is preferably one that does not easily react with other components (epoxy resin or the like), preferably an alkyl group, a hydroxyl group or an alkoxyl group, and more preferably an alkyl group.
  • the alkyl group an alkyl group having 1 to 10 carbon atoms is preferable, and an alkyl group having 1 to 5 carbon atoms is more preferable.
  • the alkyl group may be linear or branched, but is preferably linear.
  • the carbon number of the alkyl group is preferably equal to or less than the carbon number of the main chain containing the carboxy group from the viewpoint of reducing steric hindrance. ..
  • the alkoxy group an alkoxy group having 1 to 10 carbon atoms is preferable, and an alkoxy group having 1 to 5 carbon atoms is more preferable.
  • the carbon number thereof is equal to or less than the carbon number of the main chain containing the carboxylic acid from the viewpoint of reducing steric hindrance. Is preferable.
  • alkylamino group examples include a monoalkylamino group and a dialkylamino group.
  • a monoalkylamino group having 1 to 10 carbon atoms is preferable, and a monoalkylamino group having 1 to 5 carbon atoms is more preferable.
  • the alkyl group portion of the monoalkylamino group may be linear or branched, and is preferably linear.
  • dialkylamino group a dialkylamino group having 1 to 20 carbon atoms is preferable, and a dialkylamino group having 1 to 10 carbon atoms is more preferable.
  • the alkyl group portion of the dialkylamino group may be linear or branched, and is preferably linear.
  • the flux agent is preferably a compound (dicarboxylic acid) having two carboxy groups.
  • a compound having two carboxy groups is less likely to volatilize even at a high temperature at the time of connection as compared with a compound having one carboxy group (monocarboxylic acid), and the generation of voids can be further suppressed.
  • a compound represented by the following formula (2) can be preferably used. According to the flux agent composed of the compound represented by the following formula (2), the reflow resistance and the connection reliability of the semiconductor device 100 can be further improved.
  • R 1 and R 2 each independently represent a hydrogen atom or an electron donating group, and n represents an integer of 0 to 10.
  • N in the formula (2) is preferably an integer of 2 to 10, and more preferably an integer of 2 to 8.
  • n 10 or less, the flux activity is expressed in a shorter time, and further excellent connection reliability can be obtained particularly when the connection time is short. Further, when n is 2 or more, it is difficult to volatilize even at a high temperature at the time of connection, and the generation of voids can be further suppressed.
  • R 1 and R 2 may be a hydrogen atom or an electron donating group.
  • R 1 and R 2 are hydrogen atoms, the melting point of the adhesive 40 tends to be low, and the connection reliability (solder wettability) may be improved.
  • a flux agent having the same methyl group in both R 1 and R 2 has a higher melting point than one having a methyl group in one (R 1 or R 2 ), and the wettability of the solder depends on the melting point (for example,). It tends to decrease (above 150 ° C).
  • the flux agent examples include an electron donating group at the 2-position of a dicarboxylic acid selected from succinic acid, glutaric acid, adipic acid, pimelli acid, suberic acid, azelaic acid, sebacic acid, undecanoic acid and dodecanedioic acid. Substituted compounds can be used.
  • the melting point of the flux agent is preferably 150 ° C. or lower, more preferably 140 ° C. or lower, and even more preferably 130 ° C. or lower.
  • a flux agent sufficiently develops the flux activity before the curing reaction between the epoxy resin and the curing agent occurs. Therefore, according to the adhesive 40 containing such a flux agent, it is possible to realize the semiconductor device 100 having further excellent connection reliability.
  • the flux agent is preferably solid at room temperature, and the melting point of the flux agent is preferably 25 ° C. or higher, more preferably 50 ° C. or higher.
  • the melting point of the flux agent can be measured, for example, by a device in which a capillary tube filled with a sample is attached to a double-tube thermometer and heated in a hot bath.
  • the melting point of the flux agent contained in the adhesive 40 of the present embodiment is preferably higher than the temperature of the stage 42 of the pressing device 43 for forming the temporary pressure-bonding body 4.
  • the melting point of the flux agent is higher than the stage temperature of the pressing device 43, the bump 30 and the wiring 16 can be easily brought into contact with each other in the main crimping step, so that the first and last thermal histories of the main crimping step are recorded. Even if they are different, it is possible to manufacture the semiconductor device 100 having excellent connection reliability.
  • the content of the flux agent is preferably 0.5 to 10% by mass, more preferably 0.5 to 5% by mass, based on the total amount of the adhesive 40.
  • the adhesive 40 may further contain a polymer component.
  • the polymer component is composed of a polymer different from the epoxy resin.
  • examples of such polymer components include phenoxy resin, polyimide resin, polyamide resin, polycarbodiimide resin, cyanate ester resin, acrylic resin, polyester resin, polyethylene resin, polyether sulfone resin, polyetherimide resin, and polyvinyl acetal resin. , Urethane resin and acrylic rubber.
  • phenoxy resin, polyimide resin, acrylic rubber, cyanate ester resin and polycarbodiimide resin are preferable, and phenoxy resin, polyimide resin and acrylic rubber are more preferable from the viewpoint of excellent heat resistance and film forming property.
  • These polymer components can also be used alone or as a mixture or copolymer of two or more kinds.
  • the weight average molecular weight of the polymer component is not particularly limited, but is preferably 10,000 or more.
  • the adhesive 40 containing the polymer component is further excellent in heat resistance and film forming property. Therefore, if the adhesive 40 is used, the semiconductor device 100 having higher heat resistance can be manufactured. Further, the shape of the adhesive 40 is easily maintained in the temporary crimping step, the temporary crimping body pressurizing step, and the main crimping step, and the semiconductor device 100 can be efficiently manufactured.
  • the weight average molecular weight of the polymer component imparts good film forming property to the adhesive 40 by itself, and makes it easy to maintain the shape of the adhesive 40 in the temporary crimping step, the temporary crimping body pressurizing step, and the main crimping step. From the viewpoint of efficiently manufacturing the semiconductor device 100, it is preferably 30,000 or more, more preferably 40,000 or more, and further preferably 50,000 or more.
  • the ratio C a / C d of the epoxy resin content Ca to the content C d of the polymer component having a weight average molecular weight of 10,000 or more is preferably 0.01 to 5, more preferably 0.05 to 3, and even more preferably 0.1 to 2.
  • the ratio C a / C d is preferably 0.01 to 5, more preferably 0.05 to 3, and even more preferably 0.1 to 2.
  • the glass transition temperature (Tg) of the polymer component is not particularly limited, but is preferably 200 ° C. or lower, more preferably 180 ° C. or lower, and even more preferably 150 ° C. or lower.
  • the adhesive 40 tends to embed the adhesive 40 in the bumps 30 of the semiconductor chip 1, the electrodes formed on the wiring circuit board 2, and the unevenness of the wiring pattern, and the effect of suppressing voids becomes relatively large.
  • Tg is measured using DSC (manufactured by PerkinElmer Co., Ltd., product name "DSC-7 type") under the conditions of a sample amount of 10 mg, a heating rate of 10 ° C./min, and an air atmosphere.
  • the glass transition temperature (Tg) of the polymer component is preferably 50 ° C. or higher.
  • Tg of the polymer component is 50 ° C. or higher, the tack (viscous) force of the adhesive 40 tends to be moderately weakened.
  • the glass transition temperature (Tg) of the polymer component may be 50 ° C. or higher and 200 ° C. or lower, and may be 50 ° C. or higher, from the viewpoint of excellent adhesion of the adhesive 40 to the wiring circuit board 2 or the semiconductor chip 1.
  • the temperature is preferably 180 ° C. or lower, and more preferably 50 ° C. or higher and 150 ° C. or lower.
  • the adhesive 40 may contain a filler in order to control the viscosity and the physical characteristics of the cured product, and to suppress the generation of voids and the hygroscopicity when the semiconductor chip 1 and the wiring circuit board 2 are connected.
  • the filler may be an inorganic filler, and examples thereof include an insulating inorganic filler such as glass, silica, alumina, titanium oxide, mica, and boron nitride, and a conductive inorganic filler such as carbon black.
  • an insulating inorganic filler selected from silica, alumina, titanium oxide, and boron nitride is used.
  • the filler may be whisker, and examples thereof include aluminum borate, aluminum titanate, zinc oxide, calcium silicate, magnesium sulfate, and boron nitride.
  • the filler may be a resin filler (organic filler), and examples thereof include polyurethane resin, polyimide resin, methyl methacrylate resin, and methyl methacrylate-butadiene-styrene copolymer resin (MBS). These fillers can also be used alone or in combination of two or more.
  • the shape, average particle size, and content of the filler are not particularly limited.
  • the filler may have its physical properties adjusted appropriately by surface treatment.
  • the content of the filler is preferably 10 to 80% by mass, more preferably 15 to 60% by mass, based on the total amount of the adhesive 40, from the viewpoint of adjusting the minimum melt viscosity to an appropriate range.
  • the adhesive 40 may further contain other components such as an ion trapper, an antioxidant, a silane coupling agent, a titanium coupling agent, and a leveling agent. These may be used individually by 1 type, or may be used in combination of 2 or more type. The blending amount of these may be appropriately adjusted so that the effect of each additive is exhibited.
  • the adhesive 40 may be in the form of a film from the viewpoint of improving the manufacturing efficiency of the semiconductor device 100.
  • a resin varnish containing an epoxy resin, a curing agent, a flux agent, and if necessary, an organic solvent and other components is applied onto the base film to form a coating film, and the coating film is dried. It can be manufactured by the method.
  • the resin varnish is prepared by mixing an epoxy resin, a curing agent and a flux agent, and a polymer component and a filler added as necessary with an organic solvent, and dissolving or dispersing them by stirring or kneading.
  • the resin varnish is applied onto the release-treated base film using, for example, a knife coater, a roll coater, an applicator, a die coater, or a comma coater.
  • the organic solvent is reduced from the coating film of the resin varnish by heating, that is, the coating film is dried to form a film-like adhesive on the base film.
  • a film of a resin varnish may be formed on a semiconductor wafer or the like by a method such as spin coating, and then a film-like adhesive may be formed on the semiconductor wafer by a method of drying the coating film.
  • the organic solvent used for the preparation of the resin varnish is preferably one having the property of uniformly dissolving or dispersing each component, and for example, dimethylformamide, dimethylacetamide, N-methyl-2-pyrrolidone, dimethylsulfoxide, diethyleneglycoldimethylether, etc.
  • examples thereof include toluene, benzene, xylene, methyl ethyl ketone, tetrahydrofuran, ethyl cellosolve, ethyl cellosolve acetate, butyl cellosolve, dioxane, cyclohexanone, and ethyl acetate.
  • These organic solvents can be used alone or in combination of two or more.
  • Stirring and kneading at the time of preparing the resin varnish can be performed by using, for example, a stirrer, a raider, a three-roll, a ball mill, a bead mill or a homodisper
  • the base film is not particularly limited as long as it has heat resistance that can withstand the heating conditions when the organic solvent is volatilized, and is a polyolefin film such as a polypropylene film or a polymethylpentene film, a polyethylene terephthalate film, or a polyethylene naphthalate. Examples thereof include polyester films such as films, polyimide films, and polyetherimide films.
  • the base film is not limited to a single-layer film made of these films, and may be a multilayer film made of two or more kinds of materials.
  • the heating performed to volatilize the organic solvent from the resin varnish after application may be heating at 50 to 200 ° C. for 0.1 to 90 minutes.
  • the organic solvent may be removed until the residual amount becomes 1.5% by mass or less within a range that does not substantially affect the suppression of void generation and the viscosity adjustment in the adhesive layer 40A in the semiconductor device 100.
  • the minimum melt viscosity of the adhesive 40 is preferably 1500 Pa ⁇ s or less. When the minimum melt viscosity of the adhesive 40 is in this range, voids are less likely to remain in the adhesive layer 40A of the semiconductor device 100, and good connection reliability between the semiconductor chip 1 and the wiring circuit board 2 can be easily achieved. Can be secured. Further, as compared with the case where the minimum melt viscosity of the adhesive 40 is larger than 1500 Pa ⁇ s, the adhesive 40 is less likely to bite between the bump 30 and the wiring 16, resulting in poor connection between the bump 30 and the wiring 16. Since it becomes difficult, the connection reliability of the semiconductor device 100 is further improved. The minimum melt viscosity of the adhesive 40 can be adjusted to a range of 1500 Pa ⁇ s or less by adjusting the composition of the components in the adhesive 40.
  • the minimum melt viscosity of the adhesive 40 is the viscoelasticity of the adhesive 40 while giving a 1% strain to the test piece and raising the temperature in the temperature range of 35 to 150 ° C. under the conditions of a temperature rise rate of 10 ° C./min and a frequency of 10 Hz. Is the lowest value of viscosity in the relationship between the viscosity (complex viscoelasticity) obtained when measuring.
  • a test piece for measuring viscoelasticity for example, a laminate obtained by laminating a plurality of film-shaped adhesives 40 so as to have a thickness of 400 ⁇ m may be used.
  • a dynamic viscoelasticity measuring device product name "ARES" manufactured by TA Instruments Co., Ltd. is used.
  • the minimum melt viscosity of the adhesive 40 is preferably 1500 Pa ⁇ s or less from the viewpoint of further improving the connection reliability of the semiconductor device 100.
  • the minimum melt viscosity of the adhesive 40 is preferably 100 Pa ⁇ s or more.
  • the adhesive 40 can be easily handled as a film, and the manufacturing efficiency of the semiconductor device 100 is further improved, as compared with the case where the minimum melt viscosity is smaller than 100 Pa ⁇ s.
  • the adhesive 40 preferably exhibits a gel time of 35 seconds or more and 80 seconds or less at 150 ° C. When the gel time is in this range, voids are less likely to remain in the adhesive layer 40A of the semiconductor device 100, and good connection reliability can be ensured between the semiconductor chip 1 and the wiring circuit board 2.
  • the gel time of the adhesive 40 can be adjusted in the range of 35 seconds or more and 80 seconds or less depending on the type and content of the curing agent. By setting the gel time of the adhesive 40 to 35 seconds or more and 80 seconds or less at 150 ° C., voids are less likely to remain in the adhesive layer 40A of the semiconductor device 100 as compared with the case where the gel time is longer than 80 seconds, and voids are generated. A more suppressed semiconductor device 100 can be manufactured.
  • the curing reaction is less likely to proceed during the temporary crimping process (because it is less likely to be cured at a low temperature such as 80 ° C.), and it becomes easier to remove voids, making it easier to remove semiconductors. Since voids are less likely to remain in the adhesive layer 40A of the device 100, the semiconductor device 100 in which the generation of voids is more suppressed can be manufactured.
  • the gel time is the time from when the adhesive 40 is placed on a hot plate at 150 ° C. until the adhesive 40 gels. Specifically, the gel time is the time until the film is cured.
  • the gel time of the adhesive 40 is more preferably 38 seconds or more and 78 seconds or less from the viewpoint of further suppressing the generation of voids in the adhesive layer 40A of the semiconductor device 100.
  • the present disclosure is not limited to the above embodiment.
  • the manufacturing method of the semiconductor device of the present disclosure is the semiconductor device 200 shown in FIGS. 5, 6 and 7.
  • 300, 400, 500 can also be applied when manufacturing.
  • 5, 6 and 7, respectively, are partial cross-sectional views showing a semiconductor device manufactured by another embodiment of the method for manufacturing a semiconductor device of the present disclosure.
  • the semiconductor chip 1 (first member) having the semiconductor chip body 10 and the wiring circuit board 2 (second member) having the substrate body 20 are bonded to each other.
  • a layer 40A is provided.
  • the semiconductor chip 1 has a bump 32 arranged on the surface of the semiconductor chip 1 on the wiring circuit board 2 side as a first connection portion.
  • the wiring circuit board 2 has a bump 33 arranged on the surface of the board body 20 on the semiconductor chip 1 side as a second connection portion.
  • the bump 32 of the semiconductor chip 1 and the bump 33 of the wiring circuit board 2 are electrically connected by metal bonding. That is, the semiconductor chip 1 and the wiring circuit board 2 are flip-chip connected by bumps 32 and 33.
  • the bumps 32 and 33 are shielded from the external environment by being sealed by the adhesive layer 40A.
  • FIG. 6 and 7 show CoC-type semiconductor devices 300 and 400, which are connectors in which semiconductor chips 1 are connected to each other.
  • the configuration of the semiconductor device 300 shown in FIG. 6 is that the two semiconductor chips 1 are connected to the semiconductor device 100 as the first member and the second member by flip-chip connection via the wiring 15 and the bump 30.
  • the configuration of the semiconductor device 400 shown in FIG. 7 is the same as that of the semiconductor device 200, except that the two semiconductor chips 1 having the bumps 32 are flip-chip connected via the bumps 32.
  • the first connection portion or the second connection portion such as the wiring 15 and the bump 32 is a metal film (for example, a pad) called a pad. , Gold plating) or post electrodes (eg, copper pillars).
  • a metal film for example, a pad
  • Gold plating Gold plating
  • post electrodes eg, copper pillars
  • one semiconductor chip 1 has a copper pillar and a connection bump (solder: tin-silver) as a first connection
  • the other semiconductor chip 1 or a wiring circuit board 2 has gold plating as a second connection. May be.
  • FIG. 8 is a partial cross-sectional view showing a semiconductor device manufactured by another embodiment of the method for manufacturing a semiconductor device of the present disclosure.
  • FIG. 8 is a cross-sectional view showing another embodiment of the semiconductor device.
  • the semiconductor device 500 shown in FIG. 8 has a TSV structure in which a plurality of semiconductor chips 1 are laminated.
  • the wiring 15 formed on the interposer main body 50 of the interposer 501 as a second member is connected to the bump 30 of the semiconductor chip 1 to connect the semiconductor chip 1 and the interposer. It is flip-chip connected to 501.
  • An adhesive layer 40A is interposed between the semiconductor chip 1 and the interposer 501.
  • the semiconductor chip 1 is repeatedly laminated on the surface of the semiconductor chip 1 opposite to the interposer 501 via the wiring 15, the bump 30, and the adhesive layer 40A.
  • the wiring 15 on the pattern surface on the front and back of the semiconductor chip 1 is connected to each other by a through electrode 34 filled in a hole penetrating the inside of the semiconductor chip main body 10.
  • a through electrode 34 filled in a hole penetrating the inside of the semiconductor chip main body 10.
  • copper, aluminum, or the like can be used as the material of the through electrode 34.
  • a plurality of semiconductor chips 1 are stacked one by one and temporarily crimped in sequence, and the plurality of semiconductor chips 1 are collectively heated in a heating furnace 60 while being pressurized in a pressurized atmosphere. It can be manufactured by crimping by a crimping process.
  • a motherboard may be used instead of the interposer 501.
  • the semiconductor chip 1 is directly mounted on the motherboard without going through the interposer 501.
  • the semiconductor device having a multi-layered semiconductor chip there are also a chip stack type package and a POP (Package On Package), and the method for manufacturing a semiconductor device of the present disclosure relates to the manufacture of such a semiconductor device. Is also applicable. These semiconductor devices can be manufactured by the same method as the semiconductor device 500 having a TSV structure.
  • Epoxy resin / EP1032H60 Polyphenol methane skeleton-containing polyfunctional solid epoxy resin (manufactured by Japan Epoxy Resin Co., Ltd., trade name "EP1032H60", weight average molecular weight: 800-2000)
  • -YL983U Bisphenol F type liquid epoxy resin (manufactured by Japan Epoxy Resin Co., Ltd., trade name "YL983U", weight average molecular weight: about 336)
  • -YL7175 Flexible epoxy resin (manufactured by Japan Epoxy Resin Co., Ltd., trade name "YL7175", weight average molecular weight: 1000 to 5000)
  • Curing agent, 2MAOK-PW 2,4-diamino-6- [2'-methylimidazolyl- (1')]-ethyl-s-triazine isocyanuric acid adduct (manufactured by Shikoku Chemicals Corporation
  • Example 1 Preparation of film-shaped adhesive 3.1 g of epoxy resin (“EP1032”: 2.4 g, “YL983”: 0.5 g, “YL7175”: 0.2 g), 0.1 g of curing agent “2MAOK” , 0.1 g (0.7 mmol) of glutaric acid, 1.9 g of filler (inorganic filler) (0.4 g of "SE2050", 0.4 g of "SE2050-SEJ", 1.1 g of "SM nanosilica”) , 0.3 g of organic filler (EXL-2655) and methyl ethyl ketone (amount having a solid content of 63% by mass) were charged in a container of a bead mill (Fritsch Japan Co., Ltd., planetary pulverizer P-7).
  • Beads having a diameter of 0.8 mm and beads having a diameter of 2.0 mm were added in the same weight as the total weight of the solid content and stirred for 30 minutes to obtain a mixture.
  • 1.7 g of phenoxy resin (ZX1356-2) was added to the container, and the mixture was stirred again with a bead mill for 30 minutes. Then, the beads used for stirring were removed by filtration to obtain a resin varnish.
  • the obtained resin varnish is coated on a base film (manufactured by Teijin Film Solution Co., Ltd., trade name "Purex A53") with a small precision coating device (manufactured by Yasui Seiki Co., Ltd.) to form a coating film. Formed. Then, this coating film was dried at 70 ° C. for 10 minutes using a clean oven (manufactured by ESPEC) to obtain a film-like adhesive (thickness 0.040 mm). The reaction start temperature of this film-like adhesive was 135 ° C.
  • the average value of the two measured values is used for the test piece. Recorded as gel time. If the higher of the two measurements is greater than 1.05 times the lower, the third measurement is performed and the average of the three measurements from the three measurements is the gel time of the test piece. Recorded as. The results are shown in Table 1.
  • a semiconductor device was manufactured as follows using the film-like adhesive prepared as described above. (Making a temporary crimping body) The produced film-shaped adhesive was cut out to prepare a film-shaped adhesive having a size of 8 mm ⁇ 8 mm ⁇ thickness 0.045 mm. This was attached to a semiconductor chip (10 mm ⁇ 10 mm), thickness 0.1 mm, connection metal: Au, product name: WALTS-TEG IP80, manufactured by WALTS).
  • a semiconductor chip with solder bumps (chip size: 7.3 mm x 7.3 mm x thickness 0.05 mm, solder bump melting point: about 220 ° C, bump height: about 45 ⁇ m in total of copper pillars and solder, number of bumps 1048 A pin, a pitch of 80 ⁇ m, and a product name: WALTS-TEG CC80, manufactured by WALTS) were attached to obtain a laminated body.
  • this laminate is placed on a stage at 80 ° C. of a flip-chip bonder (product name "FCB3", manufactured by Panasonic Corporation) having a stage and a crimping head, and is sandwiched between the stage and the crimping head by a hot press for 3 seconds.
  • the laminate was heated to 80 ° C. while being pressurized with a load of 25 N. In this way, a temporary pressure-bonded body was produced.
  • the temporary crimping body produced as described above was placed in the oven of a pressurized oven device (product name: PCOA-01T, manufactured by NTT-AT Creative Co., Ltd.). Then, first, the pressure in the oven was set to 0.7 MPa, and the temperature was raised from room temperature to 150 ° C. at a heating rate of 20 ° C./min. Then, while maintaining the pressure and temperature, the temporary pressure-bonded body was heated while being pressurized for 30 minutes in a pressurized atmosphere. In this way, a pressurized temporary pressure-bonded body was produced.
  • a pressurized oven device product name: PCOA-01T, manufactured by NTT-AT Creative Co., Ltd.
  • the pressurized temporary crimping body produced as described above is moved onto a stage at 80 ° C. of another flip-chip bonder (product name: FCB3, manufactured by Panasonic Corporation), and the stage and crimping head are loaded with 25 N.
  • a hot press was performed in which the pressed temporary crimping body was heated at 230 ° C. for 1 second while being pressurized. In this way, the semiconductor device was manufactured. This semiconductor device was used as a semiconductor device sample for evaluation.
  • Example 2 to 4 The semiconductor devices of Examples 2 to 4 were produced in the same manner as in Example 1 except that the composition of the adhesive used was changed as shown in Table 1 below.
  • Example 1 The film-like adhesive prepared in the same manner as in Example 1 was cut out, and a film-like adhesive having a size of 8 mm ⁇ 8 mm ⁇ thickness 0.045 mm was prepared. This was attached to a semiconductor chip (10 mm, thickness 0.1 mm, connection metal: Au, product name: WALTS-TEG IP80, manufactured by WALTS).
  • a semiconductor chip with solder bumps (chip size: 7.3 mm x 7.3 mm x thickness 0.05 mm, solder bump melting point: about 220 ° C, bump height: about 45 ⁇ m in total of copper pillars and solder, number of bumps 1048 A pin, pitch 80um, product name: WALTS-TEG CC80, manufactured by WALTS) was attached to obtain a laminated body.
  • the laminate is installed on the stage of a flip-chip bonder (FCB3, manufactured by Panasonic Corporation) having a stage and a crimping head, and the laminate is pressed with a load of 25N for 1 second by a hot press sandwiched between the stage and the crimping head. While heating to 80 ° C. In this way, a temporary pressure-bonded body was produced.
  • the temporary crimping body produced as described above is moved onto the stage of another flip-chip bonder (FCB3, manufactured by Panasonic Corporation) and sandwiched between the stage and the crimping head to pressurize at 230 ° C. with a load of 25N. A hot press was performed to heat the mixture for 3 seconds. In this way, the crimped body was produced.
  • FCB3 flip-chip bonder
  • the crimped body produced as described above was placed in the oven of a pressure oven device (product name: PCOA-01T, manufactured by NTT-AT Creative Co., Ltd.). Then, the pressure in the oven was first set to 0.7 MPa, and the temperature was raised from room temperature to 175 ° C. at a heating rate of 20 ° C./min. Then, the pressure-bonded body was heated while being pressurized for 10 minutes in a pressurized atmosphere while maintaining the pressure and temperature. In this way, the semiconductor device was manufactured. This semiconductor device was used as a semiconductor device sample for evaluation.
  • connection resistance value is within the optimum connection resistance value range (10.0 to 15.0 ⁇ in this example and comparative example) for the semiconductor chip in the evaluation semiconductor device sample.
  • B The connection resistance value is A. The connection resistance value is not measured because it is out of the range (10.0 to 15.0 ⁇ ) or due to a connection failure.
  • To check whether a connection failure has occurred in the evaluation semiconductor device sample check the cross section of the sample and solder. It was determined by confirming that the bumps were not wet, that is, the solder bumps of the semiconductor chip with the solder bumps did not reach the connection portion of the opposing semiconductor chips.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Organic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Adhesive Tapes (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

Disclosed is a manufacturing method for a semiconductor device in which a first and a second member are connected via an adhesive layer, and connecting parts of the first and second members are connected to each other. The manufacturing method comprises: a pre-bonding step in which the first and second members are pre-bonded via a heat-curable adhesive for forming the adhesive layer, thereby obtaining a pre-bonded body; a pre-bonded body pressing step in which the pre-bonded body is pressed in a pressurized atmosphere, thereby obtaining a pressed pre-bonded body; and a main bonding step in which the first and second members in the pressed pre-bonded body are bonded, causing the connecting parts thereof to connect to each other, thereby obtaining a bonded body. In the pre-bonding step, pre-bonding of the first and second members is carried out at a temperature lower than the melting point of the connecting parts. In the pre-bonded body pressing step, the pressing of the pre-bonded body is carried out a temperature lower than the melting point of the connecting parts. In the main bonding step, heating of the pressed pre-bonded body is carried out at a temperature which is at least the melting point of the connecting parts.

Description

半導体装置の製造方法及びこれに用いられる接着剤Manufacturing method of semiconductor device and adhesive used for it
　本開示は、半導体装置の製造方法及びこれに用いられる接着剤に関する。 The present disclosure relates to a method for manufacturing a semiconductor device and an adhesive used for the method.
　近年、半導体装置に対する高機能、高集積、高速化等の要求に対応するため、半導体チップ又は配線回路基板にバンプと呼ばれる導電性突起を接続部として設け、接続部同士の接続によって半導体チップと配線回路基板又は他の半導体チップとを直接接続するフリップチップ接続方式（ＦＣ接続方式）が広く採用されている。ＦＣ接続方式は、例えば、半導体チップと配線回路基板間の接続であるＣＯＢ（Ｃｈｉｐ　Ｏｎ　Ｂｏａｒｄ）型の接続方式、半導体チップ上にバンプ又は配線を接続部として設け、半導体チップ同士間で接続するＣｏＣ（Ｃｈｉｐ　Ｏｎ　Ｃｈｉｐ）型接続方式、ウエハ上に半導体チップを接続した後に個片化して半導体パッケージを作製するＣＯＷ（Ｃｈｉｐ　Ｏｎ　Ｗａｆｅｒ）、ウエハ同士を圧着した後に個片化して半導体パッケージを作製するＷＯＷ（Ｗａｆｅｒ　Ｏｎ　Ｗａｆｅｒ）又は半導体パッケージ同士を圧着するＰＯＰ（Ｐａｃｋａｇｅ　Ｏｎ　Ｐａｃｋａｇｅ）などに用いられている。また、ＦＣ接続方式は、半導体チップを平面状でなく立体的に配置することでパッケージを小さくしたチップスタック型パッケージ、ＴＳＶ（Ｔｈｒｏｕｇｈ－Ｓｉｌｉｃｏｎ　Ｖｉａ）構造の半導体装置の製造にも用いられている。 In recent years, in order to meet the demands for high functionality, high integration, high speed, etc. for semiconductor devices, conductive protrusions called bumps are provided as connection parts on semiconductor chips or wiring circuit boards, and the semiconductor chips and wiring are connected by connecting the connection parts. A flip-chip connection method (FC connection method) that directly connects a circuit board or another semiconductor chip is widely adopted. The FC connection method is, for example, a COB (Chip On Board) type connection method for connecting a semiconductor chip and a wiring circuit board, and a CoC in which a bump or wiring is provided as a connection portion on the semiconductor chip and the semiconductor chips are connected to each other. (Chip On Chip) type connection method, COW (Chip On Wafer) that manufactures a semiconductor package by connecting a semiconductor chip on a wafer and then individualizing it, and WOW that manufactures a semiconductor package by crimping the wafers together. (Wafer On Wafer) or POP (Package On Package) for crimping semiconductor packages to each other. The FC connection method is also used in the manufacture of a chip stack type package in which a semiconductor chip is arranged three-dimensionally instead of in a plane, and a semiconductor device having a TSV (Through-Silicon Via) structure.
　このようなＦＣ接続方式を利用した半導体装置の製造方法として、例えば下記特許文献１に開示される製造方法が知られている。同文献には、接続部を有する半導体チップ同士を、熱硬化性の接着剤を介して、接続部の融点より低温で仮圧着する工程と、得られた仮圧着体を、対向配置された一対の押圧部材の間に挟むことにより、２つの半導体チップの接続部のうち少なくとも一方の融点以上の温度で加圧しながら加熱して圧着体を製造する工程と、圧着体を加圧雰囲気下で加熱する工程とを経て半導体装置を製造する方法が開示されている。 As a method for manufacturing a semiconductor device using such an FC connection method, for example, a manufacturing method disclosed in Patent Document 1 below is known. In the same document, a step of temporarily crimping semiconductor chips having a connecting portion to each other via a thermosetting adhesive at a temperature lower than the melting point of the connecting portion, and a pair of obtained temporary crimping bodies are arranged facing each other. The process of manufacturing a crimped body by heating while pressurizing at a temperature equal to or higher than the melting point of at least one of the connecting portions of the two semiconductor chips by sandwiching it between the pressing members of the above, and heating the crimped body in a pressurized atmosphere. A method of manufacturing a semiconductor device through the steps of the process is disclosed.
国際公開第２０１９／１２３５１８号International Publication No. 2019/1235118
　しかし、上記特許文献１に記載の半導体装置の製造方法は、以下に示す課題を有していた。
　すなわち、上記特許文献１に記載の半導体装置の製造方法では、接続信頼性は確保されるものの、仮圧着の工程で発生したボイドの発生を抑制する点で改善の余地があった。 However, the method for manufacturing a semiconductor device described in Patent Document 1 has the following problems.
That is, in the method for manufacturing a semiconductor device described in Patent Document 1, although connection reliability is ensured, there is room for improvement in suppressing the generation of voids generated in the temporary crimping process.
　そこで、本開示は、良好な接続信頼性を確保しながら、ボイドの発生が抑制された半導体装置を製造できる半導体装置の製造方法及びこれに用いられる接着剤を提供することを目的とする。 Therefore, an object of the present disclosure is to provide a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device in which the generation of voids is suppressed while ensuring good connection reliability, and an adhesive used therefor.
　上記課題を解決するため、本開示の一側面は、第１接続部を有する第一の部材と、第２接続部を有する第二の部材とが、接着層を介して接続され、前記第１接続部と前記第２接続部とが電気的に接続されている半導体装置の製造方法であって、前記第一の部材及び前記第二の部材を、前記接着層を形成するための熱硬化性の接着剤を介して、前記第１接続部と前記第２接続部とが対向配置された状態で仮圧着させて仮圧着体を得る仮圧着工程と、前記仮圧着体を加圧雰囲気下で加圧し、加圧済み仮圧着体を得る仮圧着体加圧工程と、前記加圧済み仮圧着体を、加熱しながら加圧して、前記第一の部材及び前記第二の部材を圧着させることによって、前記第１接続部と前記第２接続部とを接続させて圧着体を得る本圧着工程とを含み、前記仮圧着工程において、前記第一の部材及び前記第二の部材の仮圧着を、前記第１接続部の融点及び前記第２接続部の融点よりも低い温度で行い、前記仮圧着体加圧工程において、前記仮圧着体の加圧を、前記第１接続部の融点及び前記第２接続部の融点よりも低い温度で行い、前記本圧着工程において、前記加圧済み圧着体の加熱を、前記第１接続部及び前記第２接続部のうち少なくとも一方の融点以上の温度で行う、半導体装置の製造方法である。 In order to solve the above problems, in one aspect of the present disclosure, a first member having a first connecting portion and a second member having a second connecting portion are connected via an adhesive layer, and the first member is described. A method for manufacturing a semiconductor device in which a connecting portion and the second connecting portion are electrically connected, wherein the first member and the second member are thermally curable for forming the adhesive layer. A temporary crimping step of obtaining a temporary crimping body by temporarily crimping the first connecting portion and the second connecting portion in a state of facing each other via the adhesive of the above, and a temporary crimping body of the temporary crimping body under a pressurized atmosphere. A temporary crimping body pressurizing step of pressurizing to obtain a pressurized temporary crimping body, and pressurizing the pressurized temporary crimping body while heating to crimp the first member and the second member. Including the main crimping step of connecting the first connecting portion and the second connecting portion to obtain a crimping body, in the temporary crimping step, the temporary crimping of the first member and the second member is performed. , The temperature is lower than the melting point of the first connecting portion and the melting point of the second connecting portion, and in the temporary crimping body pressurizing step, the pressure of the temporary crimping body is applied to the melting point of the first connecting portion and the said. The pressure is lower than the melting point of the second connecting portion, and in the main crimping step, the pressurized crimping body is heated at a temperature equal to or higher than the melting point of at least one of the first connecting portion and the second connecting portion. This is a method for manufacturing a semiconductor device.
　本開示の半導体装置の製造方法によれば、仮圧着工程及び仮圧着体加圧工程の後に行われる本圧着工程において、加圧済み仮圧着体の加熱が、第１接続部及び第２接続部のうち少なくとも一方の融点以上の温度で行われるため、第１接続部と第２接続部との接続が行われる。このとき、本圧着工程の前に行われる仮圧着体加圧工程において、仮圧着体の加圧は、第１接続部の融点及び第２接続部の融点よりも低い温度で行われるため、本圧着工程の開始時点においては、接着剤の硬化が十分に進んでおらず、接着剤の粘度が低くなっている。このため、本圧着工程において第一の部材及び第二の部材を圧着させる際に、第一の部材又は第二の部材に対する接着剤からの反発力が小さくなり、第一の部材と第二の部材とを加圧することが容易となるため、第１接続部と第２接続部との接続を容易に行うことができる。その結果、良好な接続信頼性を確保することが可能となる。 According to the method for manufacturing a semiconductor device of the present disclosure, in the main crimping step performed after the temporary crimping step and the temporary crimping body pressurizing step, the heating of the pressurized temporary crimping body is performed on the first connection portion and the second connection portion. Since it is performed at a temperature equal to or higher than the melting point of at least one of them, the connection between the first connection portion and the second connection portion is performed. At this time, in the temporary crimping body pressurizing step performed before the main crimping step, the temporary crimping body is pressurized at a temperature lower than the melting point of the first connection portion and the melting point of the second connection portion. At the start of the crimping process, the adhesive has not been sufficiently cured and the viscosity of the adhesive is low. Therefore, when the first member and the second member are crimped in this crimping step, the repulsive force from the adhesive to the first member or the second member becomes small, and the first member and the second member Since it becomes easy to pressurize the member, the connection between the first connection portion and the second connection portion can be easily performed. As a result, it is possible to ensure good connection reliability.
　一方、仮圧着工程で得られる仮圧着体において、接着剤と第一の部材との間、及び、接着剤と第二の部材との間の少なくとも一方には、空隙が形成されやすく、この空隙がそのまま残ると、半導体装置においてボイドとして残ることになる。上記空隙は、加圧して圧縮させることによって消滅させることが可能である。ここで、この加圧を、仮に、本圧着工程の後に行う場合には、接着剤が、本圧着工程において第１接続部及び第２接続部のうち少なくとも一方の融点以上の温度に加熱されて硬化が進み、接着剤の粘度が既に高くなっている。また、本圧着工程の後は、第１接続部と第２接続部との接続が完了しており、第一の部材に対する第二の部材の位置が固定されている。このため、接着剤を加圧しても接着剤に十分な圧力を加えることが困難である。従って、本圧着工程の後では、空隙を十分に圧縮することができず、半導体装置の接着層においてボイドとして残されやすくなる。これに対し、本開示の製造方法のように、空隙の加圧が、本圧着工程の前の仮圧着体加圧工程において、第１接続部の融点及び第２接続部の融点よりも低い温度で行われる場合には、第１接続部及び第２接続部のうち少なくとも一方の融点以上の温度で行われる場合に比べて接着剤の硬化が進んでおらず、接着剤の粘度が低いため、空隙を圧縮することが容易となり、空隙が半導体装置の接着層においてボイドとして残されにくくなる。その結果、本開示の製造方法によれば、ボイドの発生が抑制された半導体装置を製造できる。以上のことから、本開示の半導体装置の製造方法によれば、良好な接続信頼性を確保しながら、ボイドの発生が抑制された半導体装置を製造できる。 On the other hand, in the temporary crimping body obtained in the temporary crimping step, a gap is likely to be formed between the adhesive and the first member and at least one between the adhesive and the second member, and this gap is likely to be formed. If remains as it is, it will remain as a void in the semiconductor device. The voids can be eliminated by pressurizing and compressing. Here, if this pressurization is performed after the main crimping step, the adhesive is heated to a temperature equal to or higher than the melting point of at least one of the first connection portion and the second connection portion in the main crimping step. Curing has progressed and the viscosity of the adhesive has already increased. Further, after the main crimping step, the connection between the first connecting portion and the second connecting portion is completed, and the position of the second member with respect to the first member is fixed. Therefore, even if the adhesive is pressed, it is difficult to apply sufficient pressure to the adhesive. Therefore, after the main crimping step, the voids cannot be sufficiently compressed and are likely to be left as voids in the adhesive layer of the semiconductor device. On the other hand, as in the manufacturing method of the present disclosure, the temperature at which the pressure of the void is lower than the melting point of the first connecting portion and the melting point of the second connecting portion in the temporary crimping body pressurizing step before the main crimping step. In the case of the above, the adhesive is not cured as compared with the case where it is carried out at a temperature equal to or higher than the melting point of at least one of the first connection portion and the second connection portion, and the viscosity of the adhesive is low. It becomes easy to compress the voids, and the voids are less likely to be left as voids in the adhesive layer of the semiconductor device. As a result, according to the manufacturing method of the present disclosure, it is possible to manufacture a semiconductor device in which the generation of voids is suppressed. From the above, according to the method for manufacturing a semiconductor device of the present disclosure, it is possible to manufacture a semiconductor device in which the generation of voids is suppressed while ensuring good connection reliability.
　上記製造方法においては、前記仮圧着工程において、前記仮圧着体の加圧を、前記接着剤の反応開始温度よりも低い温度で行うことが好ましい。 In the above manufacturing method, in the temporary crimping step, it is preferable to pressurize the temporary crimping body at a temperature lower than the reaction start temperature of the adhesive.
　この場合、接着剤の反応が開始しにくくなり、仮圧着体加圧工程の開始時点において接着剤の硬化が進んでいないことになるため、仮圧着工程で発生したボイドを容易に排除させることができる。 In this case, the reaction of the adhesive is less likely to start, and the adhesive has not been cured at the start of the temporary crimping body pressurizing step. Therefore, voids generated in the temporary crimping step can be easily eliminated. can.
　上記製造方法においては、前記仮圧着体加圧工程において、前記仮圧着体の加圧を、０．０５～０．８ＭＰａの圧力で行うことが好ましい。 In the above manufacturing method, it is preferable to pressurize the temporary crimping body at a pressure of 0.05 to 0.8 MPa in the temporary crimping body pressurizing step.
　この場合、半導体装置の接着層においてボイドの発生を抑制できるとともに、半導体装置の接続信頼性をより向上させることができる。 In this case, the generation of voids can be suppressed in the adhesive layer of the semiconductor device, and the connection reliability of the semiconductor device can be further improved.
　上記製造方法においては、前記仮圧着体加圧工程において、前記仮圧着体の加圧を、前記接着剤の反応開始温度以上の温度で行うことが好ましい。 In the above manufacturing method, in the temporary crimping body pressurizing step, it is preferable to pressurize the temporary crimping body at a temperature equal to or higher than the reaction start temperature of the adhesive.
　この場合、接着剤を流動させながら空隙をより効果的に圧縮させることができる。 In this case, the voids can be compressed more effectively while the adhesive is flowing.
　また、本開示の別の一側面は、上記半導体装置の製造方法において前記第一の部材と前記第二の部材とを接着するために用いられる熱硬化性の接着剤である。 Further, another aspect of the present disclosure is a thermosetting adhesive used for adhering the first member and the second member in the method for manufacturing a semiconductor device.
　上記接着剤は、エポキシ樹脂、硬化剤及びフラックス剤を含有し、１５００Ｐａ・ｓ以下の最低溶融粘度を示し、且つ、１５０℃において３５秒以上８０秒以下のゲルタイムを示すことが好ましい。 It is preferable that the adhesive contains an epoxy resin, a curing agent and a flux agent, exhibits a minimum melt viscosity of 1500 Pa · s or less, and exhibits a gel time of 35 seconds or more and 80 seconds or less at 150 ° C.
　この場合、接着剤の最低溶融粘度が１５００Ｐａ・ｓを超える場合に比べて、第１接続部と第２接続部との間に接着剤が噛み込みにくくなり、第１接続部と第２接続部との接続不良が生じにくくなるため、半導体装置の接続信頼性がより向上する。また、ゲルタイムが８０秒よりも大きい場合に比べて、仮圧着体加圧工程及び本圧着工程において接着剤が硬化しやすくなり、半導体装置の接着層においてボイドが残りにくくなるため、ボイドの発生がより抑制された半導体装置を製造できる。またゲルタイムが３５秒よりも小さい場合に比べて、仮圧着工程中に接着剤の反応が進行しにくくなり、仮圧着体加圧工程においてボイドを除去する前に接着剤が硬化しにくくなって、ボイドを除去することが容易となるため、ボイドの発生がより抑制された半導体装置を製造できる。 In this case, the adhesive is less likely to get caught between the first connection portion and the second connection portion as compared with the case where the minimum melt viscosity of the adhesive exceeds 1500 Pa · s, and the first connection portion and the second connection portion are difficult to bite. Since the connection failure with the semiconductor device is less likely to occur, the connection reliability of the semiconductor device is further improved. Further, as compared with the case where the gel time is longer than 80 seconds, the adhesive is more likely to be cured in the temporary crimping body pressurizing step and the main crimping step, and voids are less likely to remain in the adhesive layer of the semiconductor device, so that voids are generated. It is possible to manufacture a more suppressed semiconductor device. Further, as compared with the case where the gel time is smaller than 35 seconds, the reaction of the adhesive is less likely to proceed during the temporary crimping step, and the adhesive is less likely to be cured before the voids are removed in the temporary crimping body pressurizing step. Since it becomes easy to remove voids, it is possible to manufacture a semiconductor device in which the generation of voids is further suppressed.
　上記接着剤においては、前記接着剤に含有される前記エポキシ樹脂の重量平均分子量が１００００未満であることが好ましい。 In the adhesive, the weight average molecular weight of the epoxy resin contained in the adhesive is preferably less than 10,000.
　上記接着剤が高分子成分をさらに含有し、前記高分子成分の重量平均分子量が１００００以上であることが好ましい。 It is preferable that the adhesive further contains a polymer component and the weight average molecular weight of the polymer component is 10,000 or more.
　この場合、高分子成分の重量平均分子量が１００００未満である場合に比べて、接着剤が、耐熱性及びフィルム形成性の点でより優れる。このため、接着剤を用いると、より耐熱性に優れた半導体装置を製造できる。また、仮圧着工程、仮圧着体加圧工程及び本圧着工程において接着剤の形状が保持されやすくなり、半導体装置を効率よく製造できる。 In this case, the adhesive is more excellent in heat resistance and film forming property than in the case where the weight average molecular weight of the polymer component is less than 10,000. Therefore, if an adhesive is used, a semiconductor device having higher heat resistance can be manufactured. Further, the shape of the adhesive is easily maintained in the temporary crimping step, the temporary crimping body pressurizing step, and the main crimping step, and the semiconductor device can be efficiently manufactured.
　上記接着剤においては、前記高分子成分の重量平均分子量が３００００以上であり、前記高分子成分のガラス転移温度が２００℃以下であることが好ましい。 In the adhesive, it is preferable that the weight average molecular weight of the polymer component is 30,000 or more and the glass transition temperature of the polymer component is 200 ° C. or less.
　この場合、接着剤が、単独で良好なフィルム形成性を有することが可能となり、仮圧着工程、仮圧着体加圧工程及び本圧着工程において接着剤の形状が保持されやすくなるため、半導体装置の製造効率がより向上する。また、接着剤が、第一の部材のうち第二の部材側の表面における凹凸、又は、第二の部材のうち第一の部材側の表面における凹凸を埋め込み易くなり、ボイド抑制の効果が相対的に大きくなる傾向がある。 In this case, the adhesive can have good film-forming properties by itself, and the shape of the adhesive can be easily maintained in the temporary crimping step, the temporary crimping body pressurizing step, and the main crimping step. Manufacturing efficiency is further improved. Further, the adhesive makes it easier to embed the unevenness on the surface of the second member side of the first member or the unevenness on the surface of the first member side of the second member, and the effect of suppressing voids is relative. Tends to grow.
　前記接着剤は、フィルム状接着剤であることが好ましい。 The adhesive is preferably a film-like adhesive.
　この場合、接着剤がフィルム状であるため、半導体装置の製造効率がより向上する。 In this case, since the adhesive is in the form of a film, the manufacturing efficiency of the semiconductor device is further improved.
　なお、本開示において、「第１接続部の融点」は、第１接続部の表面部を形成している材料の融点をいう。また「第２接続部の融点」は、第２接続部の表面部を形成している材料の融点をいう。 In the present disclosure, the "melting point of the first connection portion" means the melting point of the material forming the surface portion of the first connection portion. Further, the "melting point of the second connecting portion" means the melting point of the material forming the surface portion of the second connecting portion.
　本開示によれば、良好な接続信頼性を確保しながら、ボイドの発生が抑制された半導体装置を製造できる半導体装置の製造方法及びこれに用いられる接着剤が提供される。 According to the present disclosure, there is provided a method for manufacturing a semiconductor device capable of manufacturing a semiconductor device in which the generation of voids is suppressed while ensuring good connection reliability, and an adhesive used therefor.
本開示の半導体装置の製造方法の一実施形態により製造された半導体装置を示す部分断面図である。It is a partial cross-sectional view which shows the semiconductor device manufactured by one Embodiment of the manufacturing method of the semiconductor device of this disclosure. 本開示の半導体装置の製造方法の一実施形態における仮圧着工程を示す工程図である。It is a process diagram which shows the temporary crimping process in one Embodiment of the manufacturing method of the semiconductor device of this disclosure. 本開示の半導体装置の製造方法の一実施形態における仮圧着体加圧工程を示す工程図である。It is a process diagram which shows the temporary pressure-bonding body pressurizing process in one Embodiment of the manufacturing method of the semiconductor device of this disclosure. 本開示の半導体装置の製造方法の一実施形態における本圧着工程を示す工程図である。It is a process diagram which shows this crimping process in one Embodiment of the manufacturing method of the semiconductor device of this disclosure. 本開示の半導体装置の製造方法の他の実施形態により製造された半導体装置を示す部分断面図である。It is a partial cross-sectional view which shows the semiconductor device manufactured by another embodiment of the manufacturing method of the semiconductor device of this disclosure. 本開示の半導体装置の製造方法の他の実施形態により製造された半導体装置を示す部分断面図である。It is a partial cross-sectional view which shows the semiconductor device manufactured by another embodiment of the manufacturing method of the semiconductor device of this disclosure. 本開示の半導体装置の製造方法の他の実施形態により製造された半導体装置を示す部分断面図である。It is a partial cross-sectional view which shows the semiconductor device manufactured by another embodiment of the manufacturing method of the semiconductor device of this disclosure. 本開示の半導体装置の製造方法の他の実施形態により製造された半導体装置を示す部分断面図である。It is a partial cross-sectional view which shows the semiconductor device manufactured by another embodiment of the manufacturing method of the semiconductor device of this disclosure.
　以下、本開示の実施形態について詳細に説明する。 Hereinafter, embodiments of the present disclosure will be described in detail.
　＜半導体装置＞
　まず、本開示の半導体装置の製造方法の説明に先立ち、本開示の半導体装置の製造方法により製造される半導体装置について図１を参照しながら説明する。図１は、本開示の半導体装置の製造方法の一実施形態により製造される半導体装置を示す部分断面図である。 <Semiconductor device>
First, prior to the description of the method for manufacturing the semiconductor device of the present disclosure, the semiconductor device manufactured by the method for manufacturing the semiconductor device of the present disclosure will be described with reference to FIG. FIG. 1 is a partial cross-sectional view showing a semiconductor device manufactured by one embodiment of the method for manufacturing a semiconductor device of the present disclosure.
　図１に示すように、半導体装置１００は、第１接続部としてのバンプ３０を有する半導体チップ（第一の部材）１と、第２接続部としての配線１６を有する配線回路基板（第二の部材）２とが接着層４０Ａを介して電気的に接続されている。 As shown in FIG. 1, the semiconductor device 100 includes a semiconductor chip (first member) 1 having a bump 30 as a first connection portion, and a wiring circuit board (second member) having a wiring 16 as a second connection portion. The member) 2 is electrically connected to the member) 2 via the adhesive layer 40A.
　半導体チップ１は、半導体チップ本体１０と、半導体チップ本体１０の一面上に設けられる配線１５と、配線１５の上に設けられるバンプ３０とを備えている。一方、配線回路基板２は、基板本体２０と、基板本体２０の一面上に設けられる配線１６とを備えている。そして、半導体装置１００においては、半導体チップ１におけるバンプ３０と、配線回路基板２における配線１６とは電気的に接続されている。 The semiconductor chip 1 includes a semiconductor chip main body 10, a wiring 15 provided on one surface of the semiconductor chip main body 10, and a bump 30 provided on the wiring 15. On the other hand, the wiring circuit board 2 includes a board main body 20 and a wiring 16 provided on one surface of the board main body 20. In the semiconductor device 100, the bump 30 on the semiconductor chip 1 and the wiring 16 on the wiring circuit board 2 are electrically connected.
　＜半導体装置の製造方法＞
　次に、上述した半導体装置１００の製造方法について図２～４を参照しながら説明する。図２は、本開示の半導体装置の製造方法の一実施形態における仮圧着工程を示す工程図、図３は、本開示の半導体装置の製造方法の一実施形態における仮圧着体加圧工程を示す工程図、図４は、本開示の半導体装置の製造方法の一実施形態における本圧着工程を示す工程図である。 <Manufacturing method of semiconductor devices>
Next, the manufacturing method of the semiconductor device 100 described above will be described with reference to FIGS. 2 to 4. FIG. 2 is a process diagram showing a temporary crimping process in one embodiment of the semiconductor device manufacturing method of the present disclosure, and FIG. 3 shows a temporary crimping body pressurizing step in one embodiment of the semiconductor device manufacturing method of the present disclosure. The process diagram and FIG. 4 are process diagrams showing the present crimping process in one embodiment of the method for manufacturing a semiconductor device of the present disclosure.
　本開示の半導体装置の製造方法の第一実施形態は、図２～図４に示されるように、バンプ３０を有する半導体チップ１と、配線１６を有する配線回路基板２とを、接着層４０Ａを形成するための熱硬化性の接着剤４０を介して、バンプ３０と配線１６とが対向配置された状態で仮圧着させて仮圧着体４を得る仮圧着工程（図２参照）と、仮圧着体４を加圧雰囲気下で加圧し、加圧済み仮圧着体５を得る仮圧着体加圧工程（図３参照）と、加圧済み仮圧着体５を、加熱しながら加圧して、半導体チップ１と配線回路基板２とを圧着させることによって、バンプ３０と配線１６とを接続させて圧着体６を得る本圧着工程（図４参照）とを含む。そして、仮圧着工程においては、半導体チップ１と配線回路基板２との仮圧着を、バンプ３０の融点及び配線１６の融点よりも低い温度で行い、仮圧着体加圧工程においては、仮圧着体４の加圧を、バンプ３０の融点及び配線１６の融点よりも低い温度で行う。また本圧着工程においては、加圧済み仮圧着体５の加熱を、バンプ３０及び配線１６のうち少なくとも一方の融点以上の温度で行う。 In the first embodiment of the method for manufacturing a semiconductor device of the present disclosure, as shown in FIGS. 2 to 4, a semiconductor chip 1 having a bump 30 and a wiring circuit board 2 having a wiring 16 are provided with an adhesive layer 40A. A temporary crimping step (see FIG. 2) in which the bump 30 and the wiring 16 are temporarily crimped to obtain a temporary crimping body 4 in a state where the bump 30 and the wiring 16 are opposed to each other via a thermosetting adhesive 40 for forming, and a temporary crimping. A temporary crimping body pressurizing step (see FIG. 3) in which the body 4 is pressurized under a pressurized atmosphere to obtain a pressurized temporary crimping body 5, and the pressurized temporary crimping body 5 is pressed while heating to form a semiconductor. The present crimping step (see FIG. 4) of connecting the bump 30 and the wiring 16 to obtain a crimping body 6 by crimping the chip 1 and the wiring circuit board 2 is included. Then, in the temporary crimping step, the semiconductor chip 1 and the wiring circuit board 2 are temporarily crimped at a temperature lower than the melting point of the bump 30 and the melting point of the wiring 16, and in the temporary crimping body pressurizing step, the temporary crimping body is used. The pressurization of 4 is performed at a temperature lower than the melting point of the bump 30 and the melting point of the wiring 16. Further, in this crimping step, the pressurized temporary crimping body 5 is heated at a temperature equal to or higher than the melting point of at least one of the bump 30 and the wiring 16.
　上述した半導体装置１００の製造方法によれば、仮圧着工程及び仮圧着体加圧工程の後に行われる本圧着工程において、加圧済み仮圧着体５の加熱が、バンプ３０及び配線１６のうち少なくとも一方の融点以上の温度に加熱されて行われるため、バンプ３０と配線１６との接続が行われる。このとき、本圧着工程の前に行われる仮圧着体加圧工程において、仮圧着体４の加圧は、バンプ３０の融点及び配線１６の融点よりも低い温度で行われるため、本圧着工程の開始時点において、接着剤４０の硬化が十分に進んでおらず、接着剤４０の粘度が低くなっている。このため、本圧着工程において半導体チップ１と配線回路基板２とを圧着させる際に、半導体チップ１又は配線回路基板２に対する接着剤４０からの反発力が小さくなり、半導体チップ１と配線回路基板２とを加圧することが容易となるため、バンプ３０と配線１６との接続を容易に行うことができる。その結果、良好な接続信頼性を確保することが可能となる。 According to the manufacturing method of the semiconductor device 100 described above, in the main crimping step performed after the temporary crimping step and the temporary crimping body pressurizing step, the heating of the pressurized temporary crimping body 5 is performed at least among the bump 30 and the wiring 16. Since it is heated to a temperature equal to or higher than one melting point, the bump 30 and the wiring 16 are connected. At this time, in the temporary crimping body pressurizing step performed before the main crimping step, the pressure of the temporary crimping body 4 is performed at a temperature lower than the melting point of the bump 30 and the melting point of the wiring 16. At the starting point, the adhesive 40 has not been sufficiently cured, and the viscosity of the adhesive 40 is low. Therefore, when the semiconductor chip 1 and the wiring circuit board 2 are crimped in this crimping step, the repulsive force from the adhesive 40 to the semiconductor chip 1 or the wiring circuit board 2 becomes small, and the semiconductor chip 1 and the wiring circuit board 2 are crimped. Since it becomes easy to pressurize and, the bump 30 and the wiring 16 can be easily connected. As a result, it is possible to ensure good connection reliability.
　一方、仮圧着工程で得られる仮圧着体４において、接着剤４０と半導体チップ１との間、及び、接着剤４０と配線回路基板２との間の少なくとも一方には、空隙が形成されやすく、この空隙がそのまま残ると、半導体装置１００においてボイドとして残ることになる。上記空隙は、加圧して圧縮させることによって消滅させることが可能である。ここで、この加圧を、仮に、本圧着工程の後に行う場合には、接着剤４０が、本圧着工程においてバンプ３０及び配線１６のうち少なくとも一方の融点以上の温度に加熱されて硬化が進み、接着剤４０の粘度が既に高くなっている。また、本圧着工程の後は、バンプ３０と配線１６との接続が完了しており、配線回路基板２に対する半導体チップ１の位置が固定されている。このため、接着剤４０を加圧しても接着剤４０に十分な圧力を加えることが困難である。従って、本圧着工程の後では、空隙を十分に圧縮することができず、半導体装置１００の接着層４０Ａにおいてボイドとして残されやすくなる。これに対し、本実施形態の製造方法のように、空隙の加圧が、本圧着工程の前の仮圧着体加圧工程において、バンプ３０の融点及び配線１６の融点よりも低い温度で加熱して行われる場合には、バンプ３０及び配線１６のうち少なくとも一方の融点以上の温度で行われる場合に比べて接着剤４０の硬化が進んでおらず、接着剤４０の粘度が低いため、空隙を圧縮することが容易となり、空隙が半導体装置１００の接着層４０Ａにおいてボイドとして残されにくくなる。その結果、本実施形態の製造方法によれば、ボイドの発生が抑制された半導体装置１００を製造できる。以上のことから、本実施形態の半導体装置の製造方法によれば、良好な接続信頼性を確保しながら、ボイドの発生が抑制された半導体装置１００を製造できる。 On the other hand, in the temporary crimping body 4 obtained in the temporary crimping step, a gap is likely to be formed between the adhesive 40 and the semiconductor chip 1 and at least one between the adhesive 40 and the wiring circuit board 2. If this void remains as it is, it will remain as a void in the semiconductor device 100. The voids can be eliminated by pressurizing and compressing. Here, if this pressurization is performed after the main crimping step, the adhesive 40 is heated to a temperature equal to or higher than the melting point of at least one of the bump 30 and the wiring 16 in the main crimping step, and the curing proceeds. , The viscosity of the adhesive 40 is already high. Further, after the main crimping step, the connection between the bump 30 and the wiring 16 is completed, and the position of the semiconductor chip 1 with respect to the wiring circuit board 2 is fixed. Therefore, even if the adhesive 40 is pressed, it is difficult to apply sufficient pressure to the adhesive 40. Therefore, after the main crimping step, the voids cannot be sufficiently compressed and are likely to be left as voids in the adhesive layer 40A of the semiconductor device 100. On the other hand, as in the manufacturing method of the present embodiment, the pressure of the void is heated at a temperature lower than the melting point of the bump 30 and the melting point of the wiring 16 in the temporary crimping body pressurizing step before the main crimping step. In this case, the adhesive 40 is not cured as compared with the case where the adhesive 40 is performed at a temperature equal to or higher than the melting point of at least one of the bump 30 and the wiring 16, and the viscosity of the adhesive 40 is low. It becomes easy to compress, and voids are less likely to be left as voids in the adhesive layer 40A of the semiconductor device 100. As a result, according to the manufacturing method of the present embodiment, it is possible to manufacture the semiconductor device 100 in which the generation of voids is suppressed. From the above, according to the method for manufacturing a semiconductor device of the present embodiment, it is possible to manufacture a semiconductor device 100 in which the generation of voids is suppressed while ensuring good connection reliability.
　次に、上記仮圧着工程、上記仮圧着体加圧工程及び本圧着工程について詳細に説明する。 Next, the temporary crimping process, the temporary crimping body pressurizing process, and the main crimping process will be described in detail.
　（仮圧着工程）
　仮圧着工程においては、まず、図２の（ａ）に示されるように、半導体チップ本体１０、及び第１接続部としてのバンプ３０を有する半導体チップ１を、基板本体２０及び第２接続部としての配線１６を有する配線回路基板２に、これらの間に接着剤４０を配置しながら重ね合わせて、積層体３を形成させる。半導体チップ１は、例えば半導体ウエハのダイシングによって形成された後、ピックアップされて配線回路基板２上まで搬送され、第１接続部としてのバンプ３０と配線１６とが対向配置されるように、位置合わせされる。積層体３は、対向配置された一対の仮圧着用押圧部材としての圧着ヘッド４１及びステージ４２を有する押圧装置４３のステージ４２上で形成される。積層体３において、バンプ３０は、半導体チップ本体１０上に設けられた配線１５上に設けられている。配線回路基板２の配線１６は、基板本体２０上の所定の位置に設けられている。バンプ３０及び配線１６はそれぞれ、金属材料によって形成された表面部を有する。 (Temporary crimping process)
In the temporary crimping step, first, as shown in FIG. 2A, the semiconductor chip main body 10 and the semiconductor chip 1 having the bump 30 as the first connection portion are used as the substrate main body 20 and the second connection portion. The laminated body 3 is formed by superimposing the adhesive 40 on the wiring circuit board 2 having the wiring 16 while arranging the adhesive 40 between them. The semiconductor chip 1 is formed, for example, by dicing a semiconductor wafer, then is picked up and conveyed onto the wiring circuit board 2, and is aligned so that the bump 30 as the first connection portion and the wiring 16 are arranged so as to face each other. Will be done. The laminated body 3 is formed on the stage 42 of the pressing device 43 having the crimping head 41 and the stage 42 as a pair of temporarily crimping pressing members arranged so as to face each other. In the laminated body 3, the bump 30 is provided on the wiring 15 provided on the semiconductor chip main body 10. The wiring 16 of the wiring circuit board 2 is provided at a predetermined position on the board main body 20. The bump 30 and the wiring 16 each have a surface portion formed of a metal material.
　接着剤４０は、半導体チップ１のうち配線回路基板２側の表面に塗布されてもよく、配線回路基板２のうち半導体チップ１側の表面に塗布されてもよく、予め準備されたフィルム状の接着剤を配線回路基板２に貼り付けてもよい。フィルム状の接着剤４０は、加熱プレス、ロールラミネート、真空ラミネート等によって貼り付けることができる。接着剤４０の面積及び厚みは、半導体チップ１又は配線回路基板２のサイズ、バンプ３０及び配線１６の高さ等に応じて適宜設定される。なお、フィルム状の接着剤４０を半導体チップ１に貼付してもよい。この場合、例えばフィルム状の接着剤を半導体ウエハに貼付した後、半導体ウエハをダイシングして半導体ウエハを個片化することによって、フィルム状の接着剤４０が貼付された半導体チップ１が得られる。 The adhesive 40 may be applied to the surface of the semiconductor chip 1 on the wiring circuit board 2 side, or may be applied to the surface of the wiring circuit board 2 on the semiconductor chip 1 side, and is in the form of a film prepared in advance. The adhesive may be attached to the wiring circuit board 2. The film-shaped adhesive 40 can be attached by a heat press, a roll laminate, a vacuum laminate, or the like. The area and thickness of the adhesive 40 are appropriately set according to the size of the semiconductor chip 1 or the wiring circuit board 2, the heights of the bumps 30 and the wiring 16, and the like. The film-shaped adhesive 40 may be attached to the semiconductor chip 1. In this case, for example, by attaching a film-shaped adhesive to a semiconductor wafer and then dicing the semiconductor wafer to separate the semiconductor wafer, a semiconductor chip 1 to which the film-shaped adhesive 40 is attached can be obtained.
　続いて、図２の（ｂ）に示されるように、積層体３を、仮圧着用押圧部材としてのステージ４２及び圧着ヘッド４１の間に挟むことによって加圧し、それにより半導体チップ１と配線回路基板２とを仮圧着し、仮圧着体４を得る。図２においては、圧着ヘッド４１は、半導体チップ１側に配置され、ステージ４２は、配線回路基板２側に配置されている。ステージ４２及び圧着ヘッド４１を有する仮圧着用押圧装置４３としては、フリップチップボンダー等を用いることができる。 Subsequently, as shown in FIG. 2B, the laminated body 3 is pressed by being sandwiched between the stage 42 as the temporary crimping pressing member and the crimping head 41, whereby the semiconductor chip 1 and the wiring circuit are pressed. Temporarily crimping the substrate 2 to obtain a temporary crimping body 4. In FIG. 2, the crimping head 41 is arranged on the semiconductor chip 1 side, and the stage 42 is arranged on the wiring circuit board 2 side. As the temporary crimping pressing device 43 having the stage 42 and the crimping head 41, a flip chip bonder or the like can be used.
　仮圧着のための積層体３の加圧は、ステージ４２及び圧着ヘッド４１のうち少なくとも一方が、半導体チップ１の第１接続部としてのバンプ３０の融点、及び配線回路基板２の第２接続部としての配線１６の融点よりも低い温度で行われる。 For the pressurization of the laminate 3 for temporary crimping, at least one of the stage 42 and the crimping head 41 has the melting point of the bump 30 as the first connection portion of the semiconductor chip 1 and the second connection portion of the wiring circuit board 2. The wiring is performed at a temperature lower than the melting point of the wiring 16.
　仮圧着工程では、第一の部材としての半導体チップ１をピックアップする際に仮圧着用押圧部材の半導体チップ１への接触によって熱を半導体チップ１へ転写させることを抑制する観点からは、仮圧着用押圧部材が低温に設定されることが好ましい。
　一方、仮圧着のために積層体３を加圧する間、巻き込まれたボイドを排除できる程度に接着剤４０の流動性を高めるために、仮圧着用押圧部材をある程度高温に加熱してもよい。このとき、仮圧着用押圧部材の冷却時間を短縮する観点からは、半導体チップ１をピックアップする時の仮圧着用押圧部材の温度と、仮圧着体４を得るために積層体３を加熱及び加圧する時の仮圧着用押圧部材の温度との差は小さいことが好ましい。具体的には、この温度差は、好ましくは１００℃以下、より好ましくは６０℃以下、さらに好ましくは実質的に０℃である。この温度差は一定であってもよい。温度差が１００℃以下であると、仮圧着用押圧部材の冷却にかかる時間をより短くすることができる。 In the temporary crimping step, from the viewpoint of suppressing transfer of heat to the semiconductor chip 1 due to contact of the temporary crimping pressing member with the semiconductor chip 1 when picking up the semiconductor chip 1 as the first member, temporary crimping is performed. It is preferable that the pressing member is set to a low temperature.
On the other hand, while the laminated body 3 is pressed for temporary crimping, the temporary crimping pressing member may be heated to a high temperature to some extent in order to increase the fluidity of the adhesive 40 to the extent that the entrained voids can be eliminated. At this time, from the viewpoint of shortening the cooling time of the temporary crimping pressing member, the temperature of the temporary crimping pressing member when the semiconductor chip 1 is picked up and the laminated body 3 are heated and applied in order to obtain the temporary crimping body 4. It is preferable that the difference from the temperature of the temporary crimping pressing member at the time of pressing is small. Specifically, this temperature difference is preferably 100 ° C. or lower, more preferably 60 ° C. or lower, and even more preferably substantially 0 ° C. This temperature difference may be constant. When the temperature difference is 100 ° C. or less, the time required for cooling the temporary crimping pressing member can be further shortened.
　仮圧着体４を得るために積層体３を加圧する時の仮圧着用押圧部材の温度は、接着剤４０の反応開始温度以上の温度であってもよく、接着剤４０の反応開始温度より低い温度であってもよいが、接着剤４０の反応開始温度より低い温度であることが好ましい。この場合、接着剤４０の反応が開始しにくくなり、仮圧着体加圧工程の開始時点において接着剤４０の硬化が進んでいないことになるため、仮圧着工程で発生したボイドを容易に排除させることができる。反応開始温度とは、ＤＳＣ（パーキンエルマー社製、製品名「ＤＳＣ－Ｐｙｉｒｓ１」）を用いて、接着剤４０のサンプル量１０ｍｇ、昇温速度１０℃／分、測定雰囲気：窒素の条件で測定したときに得られるＤＳＣサーモグラムにおけるＯｎ－ｓｅｔ温度をいう。加圧済み仮圧着工程において、仮圧着工程で発生したボイドをより容易に排除させる観点からは、仮圧着用押圧部材の温度は、７０℃以上であることが好ましい。 The temperature of the temporary crimping pressing member when the laminated body 3 is pressed to obtain the temporary crimping body 4 may be a temperature equal to or higher than the reaction starting temperature of the adhesive 40, and is lower than the reaction starting temperature of the adhesive 40. The temperature may be, but it is preferably a temperature lower than the reaction start temperature of the adhesive 40. In this case, the reaction of the adhesive 40 is less likely to start, and the adhesive 40 has not been cured at the start of the temporary crimping body pressurizing step. Therefore, voids generated in the temporary crimping step are easily eliminated. be able to. The reaction start temperature was measured using DSC (manufactured by PerkinElmer, product name "DSC-Pyrs1") under the conditions of a sample amount of 10 mg of the adhesive 40, a heating rate of 10 ° C./min, and a measurement atmosphere: nitrogen. It refers to the On-set temperature in the DSC thermogram that is sometimes obtained. In the pressurized temporary crimping step, the temperature of the temporary crimping pressing member is preferably 70 ° C. or higher from the viewpoint of more easily eliminating the void generated in the temporary crimping step.
　仮圧着体４を得るために積層体３を加圧するための押圧荷重は、バンプ３０の数、バンプ３０の高さばらつきの吸収、及びバンプ３０の変形量を考慮して適宜設定される。このとき、押圧荷重は、積層体３を加圧して、仮圧着体４において半導体チップ１のバンプ３０と配線回路基板２の配線１６とが接触するように設定されることが好ましい。この場合、後に行われる本圧着工程においてバンプ３０と配線１６との金属結合が形成され易くなるとともに、バンプ３０と配線１６との間の接着剤４０の噛み込みが少なくなる傾向がある。バンプ３０及び配線１６を充分に接触させる観点からは、仮圧着体４を得るために積層体３を加圧するための押圧荷重は、例えば、半導体チップ１のバンプ３０の１個あたり０．００９～０．５Ｎに設定すればよい。 The pressing load for pressurizing the laminated body 3 in order to obtain the temporary crimping body 4 is appropriately set in consideration of the number of bumps 30, absorption of height variations of the bumps 30, and the amount of deformation of the bumps 30. At this time, it is preferable that the pressing load is set so that the bump 30 of the semiconductor chip 1 and the wiring 16 of the wiring circuit board 2 come into contact with each other in the temporary crimping body 4 by pressurizing the laminated body 3. In this case, a metal bond between the bump 30 and the wiring 16 is likely to be formed in the main crimping step to be performed later, and the adhesive 40 tends to be less likely to be caught between the bump 30 and the wiring 16. From the viewpoint of sufficiently contacting the bump 30 and the wiring 16, the pressing load for pressurizing the laminated body 3 in order to obtain the temporary crimping body 4 is, for example, 0.009 or more per bump 30 of the semiconductor chip 1. It may be set to 0.5N.
　仮圧着体４を得るために積層体３を加圧する時間は、特に制限されるものではないが、生産性向上の観点からは、５秒以下であることが好ましく、３秒以下であることがより好ましく、２秒以下とすることが特に好ましい。但し、仮圧着体４を得るために積層体３を加圧する時間は０．１秒以上であってもよい。また、バンプ３０と配線１６とを接触させる場合には、仮圧着体４を得るために積層体３を加圧する時間は、バンプ３０と配線１６とが接触するまでの時間とすることが望ましい。 The time for pressurizing the laminated body 3 to obtain the temporary pressure-bonded body 4 is not particularly limited, but from the viewpoint of improving productivity, it is preferably 5 seconds or less, and preferably 3 seconds or less. It is more preferably 2 seconds or less, and particularly preferably 2 seconds or less. However, the time for pressurizing the laminated body 3 to obtain the temporary crimped body 4 may be 0.1 seconds or longer. Further, when the bump 30 and the wiring 16 are brought into contact with each other, it is desirable that the time for pressurizing the laminated body 3 to obtain the temporary crimping body 4 is the time until the bump 30 and the wiring 16 come into contact with each other.
　半導体チップ本体１０としては、特に制限はなく、シリコン、ゲルマニウム等の同一種類の元素から構成される元素半導体、ガリウムヒ素、インジウムリン等の化合物半導体などの各種半導体を用いることができる。 The semiconductor chip main body 10 is not particularly limited, and various semiconductors such as elemental semiconductors composed of elements of the same type such as silicon and germanium, and compound semiconductors such as gallium arsenide and indium phosphorus can be used.
　配線回路基板２としては、特に制限はなく、ガラスエポキシ、ポリイミド、ポリエステル、セラミック、エポキシ、ビスマレイミドトリアジン等を主な成分とする絶縁基板を基板本体２０として有し、その表面に形成された金属層の不要な箇所をエッチング除去して配線（配線パターン）が形成された回路基板、上記絶縁基板の表面に金属めっき等によって配線（配線パターン）が形成された回路基板、上記絶縁基板の表面に導電性物質を印刷して配線（配線パターン）が形成された回路基板などを用いることができる。 The wiring circuit board 2 is not particularly limited, and has an insulating substrate containing glass epoxy, polyimide, polyester, ceramic, epoxy, bismaleimide triazine and the like as a main component as the substrate main body 20, and a metal formed on the surface thereof. A circuit board on which wiring (wiring pattern) is formed by removing unnecessary parts of the layer by etching, a circuit board on which wiring (wiring pattern) is formed by metal plating or the like on the surface of the insulating substrate, and a surface of the insulating substrate. A circuit board or the like on which a conductive material is printed and wiring (wiring pattern) is formed can be used.
　バンプ３０及び配線１６の材質は、例えば、金、銀、銅、はんだ（主成分は、例えば、スズ－銀、スズ－鉛、スズ－ビスマス、スズ－銅、スズ－銀－銅）、スズ、ニッケル等の金属を主成分として含む。バンプ３０及び配線１６は単一の成分のみで構成されていてもよく、複数の成分から構成されていてもよい。バンプ３０及び配線１６は、これらの金属が積層された構造を有していてもよい。 The materials of the bump 30 and the wiring 16 are, for example, gold, silver, copper, solder (main components are, for example, tin-silver, tin-lead, tin-bismuth, tin-copper, tin-silver-copper), tin, and so on. Contains metals such as nickel as the main component. The bump 30 and the wiring 16 may be composed of only a single component, or may be composed of a plurality of components. The bump 30 and the wiring 16 may have a structure in which these metals are laminated.
　上記金属の中でも、バンプ３０及び配線１６の電気伝導性及び熱伝導性に優れた半導体装置（パッケージ）１００を製造する観点からは、金、銀又は銅が好ましく、銀又は銅がより好ましい。コストが低減された半導体装置（パッケージ）１００を製造する観点からは、安価である銀、銅又ははんだが好ましく、銅又ははんだがより好ましく、はんだが特に好ましい。室温において金属の表面における酸化膜の形成を抑制して生産性の低下及びコストの増加を抑制する観点からは、金、銀、銅又ははんだが好ましく、金、銀又ははんだがより好ましく、金又は銀が更に好ましい。半導体装置１００の接続信頼性の向上及び反り抑制の観点からは、はんだが好ましい。 Among the above metals, gold, silver or copper is preferable, and silver or copper is more preferable, from the viewpoint of manufacturing a semiconductor device (package) 100 having excellent electrical conductivity and thermal conductivity of the bump 30 and the wiring 16. From the viewpoint of manufacturing the semiconductor device (package) 100 with reduced cost, inexpensive silver, copper or solder is preferable, copper or solder is more preferable, and solder is particularly preferable. Gold, silver, copper or solder is preferable, gold, silver or solder is more preferable, and gold or gold is preferable from the viewpoint of suppressing the formation of an oxide film on the metal surface at room temperature to suppress a decrease in productivity and an increase in cost. Silver is more preferred. Solder is preferable from the viewpoint of improving the connection reliability of the semiconductor device 100 and suppressing warpage.
　バンプ３０及び配線１６は、表面部として、金、銀、銅、はんだ（主成分は、例えば、スズ－銀、スズ－鉛、スズ－ビスマス、スズ－銅）、スズ、ニッケル等を主な成分とする金属層を有していてもよい。このような金属層は、例えばメッキにより形成することができる。この金属層は単一の成分のみで構成されていても、複数の成分から構成されていてもよい。また、上記金属層は、単層からなる構造又は複数の金属層が積層された構造を有していてもよい。 The bump 30 and the wiring 16 are mainly composed of gold, silver, copper, solder (main components are, for example, tin-silver, tin-lead, tin-bismuth, tin-copper), tin, nickel and the like as surface portions. It may have a metal layer. Such a metal layer can be formed, for example, by plating. This metal layer may be composed of only a single component or may be composed of a plurality of components. Further, the metal layer may have a structure composed of a single layer or a structure in which a plurality of metal layers are laminated.
　（仮圧着体加圧工程）
　仮圧着体加圧工程では、仮圧着体４を得た後、図３に示されるように、仮圧着体４が加熱炉６０内の加圧雰囲気下で加圧されながら加熱される。このとき、１つの加熱炉６０内で複数の仮圧着体４を一括して加圧することが好ましい。これは次の理由による。すなわち、押圧部材を用いて複数の仮圧着体４を一括して加圧すると、複数の仮圧着体４を均一に加圧することが困難である。これに対して、加熱炉６０を用いて複数の仮圧着体４を一括して加圧すると、多数の仮圧着体４を容易に均一に加圧することができ、これにより半導体装置１００の生産性が向上する。加熱炉６０としては、リフロ炉、加圧オーブン等を用いることができる。 (Temporary crimping body pressurization process)
In the temporary crimping body pressurizing step, after the temporary crimping body 4 is obtained, as shown in FIG. 3, the temporary crimping body 4 is heated while being pressurized under the pressurized atmosphere in the heating furnace 60. At this time, it is preferable to pressurize a plurality of temporary crimping bodies 4 at once in one heating furnace 60. This is due to the following reasons. That is, when a plurality of temporary crimping bodies 4 are collectively pressed by using the pressing member, it is difficult to uniformly pressurize the plurality of temporary crimping bodies 4. On the other hand, when a plurality of temporary crimping bodies 4 are collectively pressurized using the heating furnace 60, a large number of temporary crimping bodies 4 can be easily and uniformly pressed, thereby increasing the productivity of the semiconductor device 100. Is improved. As the heating furnace 60, a reflow furnace, a pressure oven, or the like can be used.
　仮圧着体４を加圧雰囲気下で加圧すると、仮圧着体４を、押圧部材を用いて加圧する場合と比較して、フィレットが抑制される傾向がある。フィレット抑制は、小型化及び高密度化した半導体装置１００の製造において、特に重要である。ここで、フィレット抑制とは、フィレット幅を小さく抑制することを意味し、フィレット幅は、半導体装置１００の外周部にはみ出した接着剤の長さである。フィレット幅は、例えば、半導体装置１００の外観画像を、デジタルマイクロスコープ（ＫＥＹＥＮＣＥ製、製品名「ＶＨＸ－５０００」）によって撮影し、得られた画像上で計測することができる。このとき、半導体チップ１の周囲４辺からはみ出した接着剤４０の長さ（フィレット幅）を計測し、その平均値がフィレット値として求められる。フィレット値は、配線回路基板２の上に多くの半導体チップ１を搭載する観点から、１５０μｍ以下であることが好ましい。 When the temporary crimping body 4 is pressurized in a pressurized atmosphere, the fillet tends to be suppressed as compared with the case where the temporary crimping body 4 is pressed by using the pressing member. Fillet suppression is particularly important in the manufacture of miniaturized and high density semiconductor devices 100. Here, the fillet suppression means that the fillet width is suppressed to be small, and the fillet width is the length of the adhesive protruding from the outer peripheral portion of the semiconductor device 100. The fillet width can be measured, for example, by taking an external image of the semiconductor device 100 with a digital microscope (manufactured by KEYENCE, product name "VHX-5000") and measuring the obtained image. At this time, the length (fillet width) of the adhesive 40 protruding from the four peripheral sides of the semiconductor chip 1 is measured, and the average value thereof is obtained as the fillet value. The fillet value is preferably 150 μm or less from the viewpoint of mounting many semiconductor chips 1 on the wiring circuit board 2.
　加熱炉６０内の雰囲気は、特に制限されず、例えば空気、窒素、又は蟻酸等であればよい。 The atmosphere in the heating furnace 60 is not particularly limited, and may be, for example, air, nitrogen, formic acid, or the like.
　加熱炉６０内の加圧雰囲気の圧力（気圧）は、接続される半導体チップ１又は配線回路基板２のサイズ及び数等に応じて適宜設定される。加圧のための圧力は、特に制限されるものではないが、例えば、大気圧を超えて１ＭＰａ以下であってもよい。このとき、ボイド抑制及び接続信頼性向上の観点からは、圧力が大きいことが好ましい。一方、フィレット抑制の観点からは、圧力は小さいほうが好ましい。そのため、ボイド抑制及び接続信頼性向上を考慮すると、加圧のための圧力は０．０５～０．８ＭＰａであることが好ましい。 The pressure (atmospheric pressure) of the pressurized atmosphere in the heating furnace 60 is appropriately set according to the size and number of the semiconductor chips 1 or the wiring circuit board 2 to be connected. The pressure for pressurization is not particularly limited, but may be, for example, higher than atmospheric pressure and 1 MPa or less. At this time, it is preferable that the pressure is large from the viewpoint of suppressing voids and improving connection reliability. On the other hand, from the viewpoint of fillet suppression, it is preferable that the pressure is small. Therefore, in consideration of void suppression and improvement of connection reliability, the pressure for pressurization is preferably 0.05 to 0.8 MPa.
　仮圧着体加圧工程において、仮圧着体４を加圧する時には、加熱炉６０の設定温度が、半導体チップ１の第１接続部としてのバンプ３０の融点、及び配線回路基板２の第２接続部としての配線１６の融点よりも低い温度とされる。この場合、加熱炉６０の設定温度が、半導体チップ１の第１接続部としてのバンプ３０及び配線回路基板２の第２接続部としての配線１６のうちの少なくとも一方の融点以上の温度とされる場合に比べて、半導体チップ１と接着剤４０との間、又は、配線回路基板２と接着剤４０との間における空隙を容易に圧縮することができ、十分に半導体装置１００の接着層４０Ａにおけるボイドの発生をより抑制できる。また、接着剤４０の硬化が過度に進行しなくなるため、本圧着工程において、加圧済み仮圧着体５においてバンプ３０と配線１６との接続を容易に行うことが可能となり、半導体装置１００の接続信頼性をより向上させることができる。 In the temporary crimping body pressurizing step, when the temporary crimping body 4 is pressurized, the set temperature of the heating furnace 60 is the melting point of the bump 30 as the first connecting portion of the semiconductor chip 1 and the second connecting portion of the wiring circuit board 2. The temperature is lower than the melting point of the wiring 16. In this case, the set temperature of the heating furnace 60 is set to a temperature equal to or higher than the melting point of at least one of the bump 30 as the first connection portion of the semiconductor chip 1 and the wiring 16 as the second connection portion of the wiring circuit board 2. Compared with the case, the gap between the semiconductor chip 1 and the adhesive 40 or between the wiring circuit board 2 and the adhesive 40 can be easily compressed, and the gap is sufficiently in the adhesive layer 40A of the semiconductor device 100. The generation of voids can be further suppressed. Further, since the curing of the adhesive 40 does not proceed excessively, in the main crimping step, the bump 30 and the wiring 16 can be easily connected in the pressurized temporary crimping body 5, and the semiconductor device 100 can be connected. The reliability can be further improved.
　仮圧着体加圧工程では、仮圧着体４を加圧する時の加熱炉６０の設定温度は、接着剤４０の反応開始温度以上であってよく、反応開始温度より低い温度であってもよいが、接着剤４０の反応開始温度以上の温度であることが好ましい。この場合、接着剤４０を流動させながら空隙をより効果的に圧縮させることができる。このとき、仮圧着体加圧工程において、ボイドをより容易に排除させる観点からは、加熱炉６０の設定温度と接着剤４０の反応開始温度との差（ΔＴ２）は、５℃以上であることが好ましく、１０℃以上であることがより好ましい。但し、ΔＴ２は、１００℃以下であることが好ましい。 In the temporary crimping body pressurizing step, the set temperature of the heating furnace 60 when the temporary crimping body 4 is pressurized may be equal to or higher than the reaction start temperature of the adhesive 40, and may be lower than the reaction start temperature. , It is preferable that the temperature is equal to or higher than the reaction start temperature of the adhesive 40. In this case, the voids can be compressed more effectively while the adhesive 40 is made to flow. At this time, from the viewpoint of more easily eliminating voids in the temporary pressure-bonding body pressurizing step, the difference (ΔT2) between the set temperature of the heating furnace 60 and the reaction start temperature of the adhesive 40 is 5 ° C. or higher. Is preferable, and the temperature is more preferably 10 ° C. or higher. However, ΔT2 is preferably 100 ° C. or lower.
　仮圧着体４を加圧する時の加熱炉６０の設定温度は、仮圧着工程において、仮圧着体４を得るために積層体３を加圧する時（半導体チップ１と配線回路基板２の仮圧着を行う時）の仮圧着用押圧部材の温度以下の温度であってもよいし、仮圧着体４を得るために積層体３を加圧する時の仮圧着用押圧部材の温度より高い温度であってもよいが、仮圧着体４を得るために積層体３を加圧する時の仮圧着用押圧部材の温度より高い温度であることが好ましい。 The set temperature of the heating furnace 60 when the temporary crimping body 4 is pressurized is set when the laminated body 3 is pressed in order to obtain the temporary crimping body 4 (temporary crimping of the semiconductor chip 1 and the wiring circuit board 2). The temperature may be lower than or equal to the temperature of the temporary crimping pressing member (at the time of performing), or higher than the temperature of the temporary crimping pressing member when the laminated body 3 is pressed to obtain the temporary crimping body 4. However, it is preferable that the temperature is higher than the temperature of the temporary crimping pressing member when the laminated body 3 is pressed in order to obtain the temporary crimping body 4.
　仮圧着体４を加圧する時の加熱炉６０の設定温度は、流動させながら空隙を効果的に圧縮させる観点から、１４０℃以上であることが好ましく、１４５℃以上であることがより好ましく、１５０℃以上であることが特に好ましい。但し、仮圧着体４を加圧する時の加熱炉６０の設定温度は、２６０℃以下であることが好ましい。 The set temperature of the heating furnace 60 when the temporary crimping body 4 is pressurized is preferably 140 ° C. or higher, more preferably 145 ° C. or higher, and 150 ° C. or higher, from the viewpoint of effectively compressing the voids while flowing. It is particularly preferable that the temperature is above ° C. However, the set temperature of the heating furnace 60 when pressurizing the temporary crimping body 4 is preferably 260 ° C. or lower.
　（本圧着工程）
　本圧着工程においては、加圧済み仮圧着体５を得た後、図４の（ａ）及び（ｂ）に示されるように、対向配置されたステージ４５及び圧着ヘッド４４を一対の本圧着用部材として有する押圧装置４６を用いて、加圧済み仮圧着体５を、ステージ４５及び圧着ヘッド４４で挟む熱プレスによって加熱しながら加圧することにより、圧着体６を形成させる。このとき、押圧装置４６は押圧装置４３と同一であってもよく、別に準備されたものであってもよい。また、ステージ４５及び圧着ヘッド４４のうち少なくとも一方が、加圧済み仮圧着体５を加圧するときに、バンプ３０の融点及び配線１６の融点のうち少なくともいずれか一方の融点以上の温度に加熱される。また、圧着体６においては、通常、半導体チップ１と配線回路基板２は、バンプ３０及び配線１６が金属接合することにより電気的に接続される。圧着体６はそのまま半導体装置として用いてもよいし、本圧着工程の後、圧着体６を加圧雰囲気下で更に加熱して、接着剤４０を更に硬化させて接着層４０Ａを形成した後に半導体装置１００としてもよい。 (Main crimping process)
In the main crimping step, after the pressurized temporary crimping body 5 is obtained, as shown in FIGS. 4A and 4B, the stage 45 and the crimping head 44 arranged to face each other are used for a pair of main crimping. Using the pressing device 46 as a member, the pressurized temporary crimping body 5 is pressed while being heated by a hot press sandwiched between the stage 45 and the crimping head 44 to form the crimping body 6. At this time, the pressing device 46 may be the same as the pressing device 43, or may be prepared separately. Further, at least one of the stage 45 and the crimping head 44 is heated to a temperature equal to or higher than the melting point of at least one of the melting point of the bump 30 and the melting point of the wiring 16 when the pressurized temporary crimping body 5 is pressurized. The melting point. Further, in the crimping body 6, the semiconductor chip 1 and the wiring circuit board 2 are usually electrically connected by metal bonding of the bump 30 and the wiring 16. The crimping body 6 may be used as it is as a semiconductor device, or after the main crimping step, the crimping body 6 is further heated under a pressurized atmosphere to further cure the adhesive 40 to form the adhesive layer 40A, and then the semiconductor. It may be the device 100.
　なお、図４において、圧着ヘッド４４は、加圧済み仮圧着体の半導体チップ１側に配置され、ステージ４５は、加圧済み仮圧着体の配線回路基板２側に配置されている。圧着体６において、配線１６及びバンプ３０は、接着剤４０によって、外部環境から遮断されるように封止されている。 In FIG. 4, the crimping head 44 is arranged on the semiconductor chip 1 side of the pressurized temporary crimping body, and the stage 45 is arranged on the wiring circuit board 2 side of the pressurized temporary crimping body. In the crimping body 6, the wiring 16 and the bump 30 are sealed by the adhesive 40 so as to be shielded from the external environment.
　圧着体６を得るために加圧済み仮圧着体５を加熱及び加圧したときに、バンプ３０及び配線１６のうちの少なくとも一方の表面の酸化膜が除去されてもよい。そのために、ステージ４５及び圧着ヘッド４４の少なくとも一方の温度が、バンプ３０及び配線１６のうちの少なくとも一方の表面の酸化膜が効率的に除去される温度以上に設定してもよい。係る観点からは、ステージ４５及び圧着ヘッド４４の少なくとも一方の温度は、２２０℃以上３３０℃以下であることが好ましい。この場合、バンプ３０又は配線１６の金属材料がはんだを含むと、ステージ４５及び圧着ヘッド４４の少なくとも一方の温度が２２０℃未満である場合に比べて、バンプ３０又は配線１６のはんだが溶融して充分な金属結合が形成され易くなる。温度が３３０℃以下であると、温度が３３０℃を超える場合に比べて、ボイドが発生し難くなったり、はんだが飛散し難くなったりする。ステージ４５及び圧着ヘッド４４の少なくとも一方の温度は、バンプ３０及び配線１６のうちの少なくとも一方の金属材料が融点約２２０℃のＳｎ／Ａｇを含む場合も、２２０℃以上であってもよい。 When the pressurized temporary crimping body 5 is heated and pressurized to obtain the crimping body 6, the oxide film on the surface of at least one of the bump 30 and the wiring 16 may be removed. Therefore, the temperature of at least one of the stage 45 and the crimping head 44 may be set to a temperature higher than the temperature at which the oxide film on the surface of at least one of the bump 30 and the wiring 16 is efficiently removed. From this point of view, the temperature of at least one of the stage 45 and the crimping head 44 is preferably 220 ° C. or higher and 330 ° C. or lower. In this case, when the metal material of the bump 30 or the wiring 16 contains solder, the solder of the bump 30 or the wiring 16 melts as compared with the case where the temperature of at least one of the stage 45 and the crimping head 44 is lower than 220 ° C. Sufficient metal bonds are likely to be formed. When the temperature is 330 ° C. or lower, voids are less likely to occur and solder is less likely to scatter than when the temperature exceeds 330 ° C. The temperature of at least one of the stage 45 and the crimping head 44 may be 220 ° C. or higher even when the metal material of at least one of the bump 30 and the wiring 16 contains Sn / Ag having a melting point of about 220 ° C.
　押圧装置４６を用いて加圧済み仮圧着体５を加熱しながら加圧する場合、押圧荷重は、バンプ３０及び配線１６のうちの少なくとも一方の表面の酸化膜除去、バンプ３０の数、バンプ３０の高さばらつきの吸収、及びバンプ３０の変形量の制御等を考慮して適宜設定される。押圧荷重が大きいと、酸化膜が除去され易くなる傾向がある。押圧荷重は、例えば、半導体チップ１の１個のバンプ３０あたり、０．００９～０．２Ｎであってもよい。この押圧荷重が０．００９Ｎ以上であると、バンプ３０及び配線１６のうちの少なくとも一方に形成された酸化膜が除去され易くなったり、接着剤４０がバンプ３０及び配線１６のうちの少なくとも一方にトラップされ難くなったりする。また、押圧荷重が０．２Ｎ以下であると、はんだ等を含むバンプが潰れたり、飛散したりするといった不具合が生じ難い。 When the pressed temporary crimping body 5 is pressurized while being heated by using the pressing device 46, the pressing load is the removal of the oxide film on the surface of at least one of the bump 30 and the wiring 16, the number of bumps 30, and the number of bumps 30. It is appropriately set in consideration of absorption of height variation, control of the amount of deformation of the bump 30 and the like. When the pressing load is large, the oxide film tends to be easily removed. The pressing load may be, for example, 0.009 to 0.2 N per bump 30 of the semiconductor chip 1. When this pressing load is 0.009 N or more, the oxide film formed on at least one of the bump 30 and the wiring 16 can be easily removed, or the adhesive 40 is applied to at least one of the bump 30 and the wiring 16. It becomes difficult to be trapped. Further, when the pressing load is 0.2 N or less, problems such as bumps containing solder and the like being crushed or scattered are unlikely to occur.
　圧着体６を得るために加圧済み仮圧着体５を加熱しながら加圧する時間は、生産性向上の観点から、５秒以下であることが好ましく、３秒以下であることがより好ましく、２秒以下であることが特に好ましい。但し、圧着体６を得るために加圧済み仮圧着体５を加熱しながら加圧する時間は０．１秒以上であってもよい。 From the viewpoint of improving productivity, the time for pressurizing the pressed temporary crimping body 5 while heating to obtain the crimping body 6 is preferably 5 seconds or less, more preferably 3 seconds or less, and 2 It is particularly preferably less than a second. However, the time for pressurizing the pressed temporary crimping body 5 while heating to obtain the crimping body 6 may be 0.1 seconds or longer.
　加圧済み仮圧着体５を加熱及び加圧する方法は、図４のような熱プレスに限られず、例えば、加熱炉を用いて、加熱炉内の加圧雰囲気下で加圧済み仮圧着体５を加熱してもよい。加熱炉としては、リフロ炉、加圧オーブン等を用いることができる。加熱炉内の雰囲気は、特に制限されないが、空気、窒素、又は蟻酸等であってもよい。 The method of heating and pressurizing the pressurized temporary crimping body 5 is not limited to the hot press as shown in FIG. 4, for example, using a heating furnace, the pressurized temporary crimping body 5 is pressurized in a pressurized atmosphere in the heating furnace. May be heated. As the heating furnace, a reflow furnace, a pressure oven, or the like can be used. The atmosphere in the heating furnace is not particularly limited, but may be air, nitrogen, formic acid, or the like.
　＜接着剤＞
　次に、上述した半導体装置の製造方法の実施形態に用いる接着剤について説明する。
　本実施形態の接着剤は、熱硬化性の接着剤であれば特に制限されるものではなく、例えばエポキシ樹脂、硬化剤、及びフラックス剤を含有する。 <Adhesive>
Next, the adhesive used in the embodiment of the above-mentioned method for manufacturing a semiconductor device will be described.
The adhesive of the present embodiment is not particularly limited as long as it is a thermosetting adhesive, and contains, for example, an epoxy resin, a curing agent, and a flux agent.
　（エポキシ樹脂）
　エポキシ樹脂は、分子内に２個以上のエポキシ基を有するものであれば特に制限されない。エポキシ樹脂としては、ビスフェノールＡ型エポキシ樹脂、ビスフェノールＦ型エポキシ樹脂、ナフタレン型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂、フェノールアラルキル型エポキシ樹脂、ビフェニル型エポキシ樹脂、トリフェニルメタン型エポキシ樹脂、ジシクロペンタジエン型エポキシ樹脂等の各種多官能エポキシ樹脂等を用いることができる。これらは単独で又は２種以上を組み合わせて用いることができる。 (Epoxy resin)
The epoxy resin is not particularly limited as long as it has two or more epoxy groups in the molecule. As the epoxy resin, bisphenol A type epoxy resin, bisphenol F type epoxy resin, naphthalene type epoxy resin, phenol novolac type epoxy resin, cresol novolac type epoxy resin, phenol aralkyl type epoxy resin, biphenyl type epoxy resin, triphenylmethane type epoxy Various polyfunctional epoxy resins such as resins and dicyclopentadiene type epoxy resins can be used. These can be used alone or in combination of two or more.
　エポキシ樹脂の重量平均分子量は、特に制限されるものではないが、１００００未満であることが好ましい。 The weight average molecular weight of the epoxy resin is not particularly limited, but is preferably less than 10,000.
　エポキシ樹脂は、高温での接続時に分解して揮発成分が発生することを抑制する観点から、接続時の温度（本圧着工程における加熱温度）における熱重量減少量率が５％以下のエポキシ樹脂を用いることが好ましい。例えば接続時の温度が２５０℃の場合は、２５０℃における熱重量減少量率が５％以下のエポキシ樹脂を用いることが好ましく、３００℃の場合は、３００℃における熱重量減少量率が５％以下のエポキシ樹脂を用いることが好ましい。 Epoxy resin is an epoxy resin with a thermogravimetric reduction rate of 5% or less at the temperature at the time of connection (heating temperature in this crimping process) from the viewpoint of suppressing decomposition and generation of volatile components at the time of connection at high temperature. It is preferable to use it. For example, when the temperature at the time of connection is 250 ° C., it is preferable to use an epoxy resin having a thermogravimetric reduction rate of 5% or less at 250 ° C., and when the temperature is 300 ° C., the thermogravimetric analysis rate at 300 ° C. is 5%. It is preferable to use the following epoxy resin.
　エポキシ樹脂の含有量は、接着剤４０の全量基準で、例えば５～７５質量％であり、好ましくは１０～５０質量％であり、より好ましくは１５～３５質量％である。 The content of the epoxy resin is, for example, 5 to 75% by mass, preferably 10 to 50% by mass, and more preferably 15 to 35% by mass based on the total amount of the adhesive 40.
　（硬化剤）
　硬化剤としては、例えば、フェノール樹脂系硬化剤、酸無水物系硬化剤、アミン系硬化剤、イミダゾール系硬化剤及びホスフィン系硬化剤が挙げられる。バンプ３０又は配線１６に酸化膜が生じることを抑制するフラックス活性を示し、接続信頼性及び絶縁信頼性を向上させる観点からは、硬化剤がフェノール性樹脂系硬化剤、酸無水物系硬化剤、アミン系硬化剤及びイミダゾール系硬化剤から選ばれる少なくとも一種を含むことが好ましく、イミダゾール系硬化剤を含むことがさらに好ましい。以下、各硬化剤について説明する。 (Hardener)
Examples of the curing agent include a phenol resin-based curing agent, an acid anhydride-based curing agent, an amine-based curing agent, an imidazole-based curing agent, and a phosphine-based curing agent. From the viewpoint of exhibiting flux activity that suppresses the formation of an oxide film on the bump 30 or the wiring 16 and improving connection reliability and insulation reliability, the curing agent is a phenolic resin-based curing agent, an acid anhydride-based curing agent, and the like. It is preferable to contain at least one selected from an amine-based curing agent and an imidazole-based curing agent, and it is more preferable to contain an imidazole-based curing agent. Hereinafter, each curing agent will be described.
　フェノール樹脂系硬化剤は、分子内に２個以上のフェノール性水酸基を有するものであれば特に制限はなく、その例としては、フェノールノボラック樹脂、クレゾールノボラック樹脂、フェノールアラルキル樹脂、クレゾールナフトールホルムアルデヒド重縮合物、トリフェニルメタン型多官能フェノール及び各種多官能フェノール樹脂が挙げられる。これらは単独で又は２種以上の混合物として用いることができる。 The phenol resin-based curing agent is not particularly limited as long as it has two or more phenolic hydroxyl groups in the molecule, and examples thereof include phenol novolac resin, cresol novolak resin, phenol aralkyl resin, and cresol naphthol formaldehyde polycondensation. Examples thereof include triphenylmethane-type polyfunctional phenols and various polyfunctional phenol resins. These can be used alone or as a mixture of two or more.
　エポキシ樹脂に対するフェノール樹脂系硬化剤の当量比（フェノール性水酸基／エポキシ基、モル比）は、良好な硬化性、接着性及び保存安定性の観点から、０．３～１．５が好ましく、０．４～１．０がより好ましく、０．５～１．０が更に好ましい。当量比が０．３以上であると、硬化性が向上し接着力が向上する傾向があり、１．５以下であると未反応のフェノール性水酸基が過剰に残存することがなく、吸水率が低く抑えられ、半導体装置１００の絶縁信頼性が向上する傾向がある。当量比が０．３～１．５であると、ゲルタイムを適切な範囲に調整し易い。 The equivalent ratio (phenolic hydroxyl group / epoxy group, molar ratio) of the phenol resin-based curing agent to the epoxy resin is preferably 0.3 to 1.5 from the viewpoint of good curability, adhesiveness and storage stability, and is 0. .4 to 1.0 is more preferable, and 0.5 to 1.0 is even more preferable. When the equivalent ratio is 0.3 or more, the curability tends to be improved and the adhesive strength tends to be improved, and when it is 1.5 or less, unreacted phenolic hydroxyl groups do not remain excessively and the water absorption rate is high. It is kept low and tends to improve the insulation reliability of the semiconductor device 100. When the equivalent ratio is 0.3 to 1.5, it is easy to adjust the gel time to an appropriate range.
　酸無水物系硬化剤としては、例えば、メチルシクロヘキサンテトラカルボン酸二無水物、無水トリメリット酸、無水ピロメリット酸、ベンゾフェノンテトラカルボン酸二無水物及びエチレングリコールビスアンヒドロトリメリテートが挙げられる。これらは単独で又は２種以上の混合物として用いることができる。 Examples of the acid anhydride-based curing agent include methylcyclohexanetetracarboxylic acid dianhydride, trimellitic anhydride, pyromellitic anhydride, benzophenonetetracarboxylic acid dianhydride, and ethylene glycol bisanhydrotrimeritate. These can be used alone or as a mixture of two or more.
　エポキシ樹脂に対する酸無水物系硬化剤の当量比（酸無水物基／エポキシ基、モル比）は、良好な硬化性、接着性及び保存安定性の観点から、０．３～１．５が好ましく、０．４～１．０がより好ましく、０．５～１．０が更に好ましい。当量比が０．３以上であると、硬化性が向上し接着力が向上する傾向があり、１．５以下であると未反応の酸無水物が過剰に残存することがなく、吸水率が低く抑えられ、半導体装置１００の絶縁信頼性が向上する傾向がある。当量比が０．３～１．５であると、ゲルタイムを適切な範囲に調整し易い。 The equivalent ratio of the acid anhydride-based curing agent to the epoxy resin (acid anhydride group / epoxy group, molar ratio) is preferably 0.3 to 1.5 from the viewpoint of good curability, adhesiveness and storage stability. , 0.4 to 1.0 is more preferable, and 0.5 to 1.0 is even more preferable. When the equivalent ratio is 0.3 or more, the curability tends to be improved and the adhesive strength tends to be improved, and when it is 1.5 or less, unreacted acid anhydride does not remain excessively and the water absorption rate is high. It is kept low and tends to improve the insulation reliability of the semiconductor device 100. When the equivalent ratio is 0.3 to 1.5, it is easy to adjust the gel time to an appropriate range.
　アミン系硬化剤としては、例えば、ジシアンジアミドを用いることができる。 As the amine-based curing agent, for example, dicyandiamide can be used.
　エポキシ樹脂に対するアミン系硬化剤の当量比（アミノ基／エポキシ基、モル比）は、良好な硬化性、接着性及び保存安定性の観点から０．３～１．５が好ましく、０．４～１．０がより好ましく、０．５～１．０が更に好ましい。当量比が０．３以上であると、硬化性が向上し接着力が向上する傾向があり、１．５以下であると未反応のアミンが過剰に残存することがなく、半導体装置１００の絶縁信頼性が向上する傾向がある。当量比が０．３～１．５であると、ゲルタイムを適切な範囲に調整し易い。 The equivalent ratio (amino group / epoxy group, molar ratio) of the amine-based curing agent to the epoxy resin is preferably 0.3 to 1.5, preferably 0.4 to 1.5, from the viewpoint of good curability, adhesiveness and storage stability. 1.0 is more preferable, and 0.5 to 1.0 is even more preferable. When the equivalent ratio is 0.3 or more, the curability tends to be improved and the adhesive strength tends to be improved, and when it is 1.5 or less, unreacted amine does not remain excessively, and the insulation of the semiconductor device 100 is insulated. Reliability tends to improve. When the equivalent ratio is 0.3 to 1.5, it is easy to adjust the gel time to an appropriate range.
　イミダゾール系硬化剤としては、例えば、２－フェニルイミダゾール、２－フェニル－４－メチルイミダゾール、１－ベンジル－２－メチルイミダゾール、１－ベンジル－２－フェニルイミダゾール、１－シアノエチル－２－ウンデシルイミダゾール、１－シアノ－２－フェニルイミダゾール、１－シアノエチル－２－ウンデシルイミダゾールトリメリテイト、１－シアノエチル－２－フェニルイミダゾリウムトリメリテイト、２，４－ジアミノ－６－［２’－メチルイミダゾリル－（１’）］－エチル－ｓ－トリアジン、２，４－ジアミノ－６－［２’－ウンデシルイミダゾリル－（１’）］－エチル－ｓ－トリアジン、２，４－ジアミノ－６－［２’－エチル－４’－メチルイミダゾリル－（１’）］－エチル－ｓ－トリアジン、２，４－ジアミノ－６－［２’－メチルイミダゾリル－（１’）］－エチル－ｓ－トリアジンイソシアヌル酸付加体、２－フェニルイミダゾールイソシアヌル酸付加体、２－フェニル－４，５－ジヒドロキシメチルイミダゾール、２－フェニル－４－メチル－５－ヒドロキシメチルイミダゾール、及び、エポキシ樹脂とイミダゾール類の付加体が挙げられる。優れた硬化性、保存安定性及び接続信頼性の観点からは、１－シアノエチル－２－ウンデシルイミダゾール、１－シアノ－２－フェニルイミダゾール、１－シアノエチル－２－ウンデシルイミダゾールトリメリテイト、１－シアノエチル－２－フェニルイミダゾリウムトリメリテイト、２，４－ジアミノ－６－［２’－メチルイミダゾリル－（１’）］－エチル－ｓ－トリアジン、２，４－ジアミノ－６－［２’－エチル－４’－メチルイミダゾリル－（１’）］－エチル－ｓ－トリアジン、２，４－ジアミノ－６－［２’－メチルイミダゾリル－（１’）］－エチル－ｓ－トリアジンイソシアヌル酸付加体、２－フェニルイミダゾールイソシアヌル酸付加体、２－フェニル－４，５－ジヒドロキシメチルイミダゾール及び２－フェニル－４－メチル－５－ヒドロキシメチルイミダゾールからイミダゾール系硬化剤を選択してもよい。これらは単独で又は２種以上を併用して用いることができる。これらを含むマイクロカプセルを潜在性硬化剤として用いることもできる。 Examples of the imidazole-based curing agent include 2-phenylimidazole, 2-phenyl-4-methylimidazole, 1-benzyl-2-methylimidazole, 1-benzyl-2-phenylimidazole, and 1-cyanoethyl-2-undecylimidazole. , 1-Cyano-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole trimellitate, 1-cyanoethyl-2-phenylimidazolium trimellitate, 2,4-diamino-6- [2'-methylimidazolyl -(1')]-Ethyl-s-triazine, 2,4-diamino-6- [2'-undecylimidazolyl- (1')]-ethyl-s-triazine, 2,4-diamino-6- [ 2'-Ethyl-4'-methylimidazolyl- (1')]-ethyl-s-triazine, 2,4-diamino-6- [2'-methylimidazolyl- (1')]-ethyl-s-triazine isocyanul Acid adducts, 2-phenylimidazole isocyanuric acid adducts, 2-phenyl-4,5-dihydroxymethylimidazole, 2-phenyl-4-methyl-5-hydroxymethylimidazole, and adducts of epoxy resins and imidazoles Can be mentioned. From the viewpoint of excellent curability, storage stability and connection reliability, 1-cyanoethyl-2-undecylimidazole, 1-cyano-2-phenylimidazole, 1-cyanoethyl-2-undecylimidazole trimellitate, 1 -Cyanoethyl-2-phenylimidazolium trimellitate, 2,4-diamino-6- [2'-methylimidazolyl- (1')]-ethyl-s-triazine, 2,4-diamino-6- [2' -Ethyl-4'-methylimidazolyl- (1')]-ethyl-s-triazine, 2,4-diamino-6- [2'-methylimidazolyl- (1')]-ethyl-s-triazine isocyanuric acid addition The imidazole-based curing agent may be selected from the body, 2-phenylimidazole isocyanuric acid adduct, 2-phenyl-4,5-dihydroxymethylimidazole and 2-phenyl-4-methyl-5-hydroxymethylimidazole. These can be used alone or in combination of two or more. Microcapsules containing these can also be used as a latent curing agent.
　イミダゾール系硬化剤の含有量は、エポキシ樹脂１００質量部に対して、０．１～２０質量部が好ましく、０．１～１０質量部がより好ましく、３．２～５．５質量部がさらに好ましい。イミダゾール系硬化剤の含有量が０．１質量部以上であると接着剤４０の硬化性が向上する傾向があり、２０質量部以下であると、バンプ３０と配線１６とで金属接合が形成される前に接着剤４０が硬化することがなく、バンプ３０と配線１６との接続不良が発生しにくくなる傾向がある。イミダゾール系硬化剤の含有量が０．１～２０質量部であると、ゲルタイムを適切な範囲に調整し易い。 The content of the imidazole-based curing agent is preferably 0.1 to 20 parts by mass, more preferably 0.1 to 10 parts by mass, and further preferably 3.2 to 5.5 parts by mass with respect to 100 parts by mass of the epoxy resin. preferable. When the content of the imidazole-based curing agent is 0.1 parts by mass or more, the curability of the adhesive 40 tends to be improved, and when it is 20 parts by mass or less, a metal bond is formed between the bump 30 and the wiring 16. The adhesive 40 does not harden before the adhesive 40 is formed, and there is a tendency that a poor connection between the bump 30 and the wiring 16 is less likely to occur. When the content of the imidazole-based curing agent is 0.1 to 20 parts by mass, it is easy to adjust the gel time to an appropriate range.
　ホスフィン系硬化剤としては、例えば、トリフェニルホスフィン、テトラフェニルホスホニウムテトラフェニルボレート、テトラフェニルホスホニウムテトラ（４－メチルフェニル）ボレート及びテトラフェニルホスホニウム（４－フルオロフェニル）ボレートが挙げられる。 Examples of the phosphine-based curing agent include triphenylphosphine, tetraphenylphosphonium tetraphenylborate, tetraphenylphosphonium tetra (4-methylphenyl) borate and tetraphenylphosphonium (4-fluorophenyl) borate.
　ホスフィン系硬化剤の含有量は、エポキシ樹脂１００質量部に対して、０．１～１０質量部が好ましく、０．１～５質量部がより好ましい。ホスフィン系硬化剤の含有量が０．１質量部以上であると接着剤４０の硬化性が向上する傾向があり、１０質量部以下であると、バンプ３０と配線１６とで金属接合が形成される前に接着剤４０が硬化することがなく、バンプ３０と配線１６との接続不良が発生しにくい傾向がある。 The content of the phosphine-based curing agent is preferably 0.1 to 10 parts by mass, more preferably 0.1 to 5 parts by mass with respect to 100 parts by mass of the epoxy resin. When the content of the phosphine-based curing agent is 0.1 parts by mass or more, the curability of the adhesive 40 tends to be improved, and when it is 10 parts by mass or less, a metal bond is formed between the bump 30 and the wiring 16. The adhesive 40 does not cure before the adhesive 40 is formed, and there is a tendency that poor connection between the bump 30 and the wiring 16 is unlikely to occur.
　フェノール樹脂系硬化剤、酸無水物系硬化剤及びアミン系硬化剤は、それぞれ１種を単独で又は２種以上の混合物として用いることができる。イミダゾール系硬化剤及びホスフィン系硬化剤はそれぞれ単独で用いてもよいが、フェノール樹脂系硬化剤、酸無水物系硬化剤又はアミン系硬化剤と共に用いてもよい。 The phenolic resin-based curing agent, acid anhydride-based curing agent, and amine-based curing agent can be used alone or as a mixture of two or more. The imidazole-based curing agent and the phosphine-based curing agent may be used alone, or may be used together with a phenol resin-based curing agent, an acid anhydride-based curing agent, or an amine-based curing agent.
　（フラックス剤）
　フラックス剤は、例えば式（１）で表される基を有する化合物である。フラックス剤としては、下記式（１）で表される基を１種のみ、又は２種以上含むものを用いることができる。 (Flux agent)
The flux agent is, for example, a compound having a group represented by the formula (1). As the flux agent, one containing only one type of group represented by the following formula (1) or two or more types can be used.
Figure JPOXMLDOC01-appb-C000001
 　式（１）中、Ｒ１は、水素原子又は電子供与性基を示す。電子供与性基としては、例えば、アルキル基、水酸基、アミノ基、アルコキシ基、アルキルアミノ基が挙げられる。電子供与性基は、他の成分（エポキシ樹脂等）と反応しにくいものが好ましく、アルキル基、水酸基又はアルコキシル基であることが好ましく、アルキル基であることがより好ましい。
Figure JPOXMLDOC01-appb-C000001
 In formula (1), R 1 represents a hydrogen atom or an electron donating group. Examples of the electron donating group include an alkyl group, a hydroxyl group, an amino group, an alkoxy group, and an alkylamino group. The electron donating group is preferably one that does not easily react with other components (epoxy resin or the like), preferably an alkyl group, a hydroxyl group or an alkoxyl group, and more preferably an alkyl group.
　アルキル基としては、炭素数１～１０のアルキル基が好ましく、炭素数１～５のアルキル基がより好ましい。基本的に、電子供与基は、多い方が電子供与性が強く好ましいが、立体障害も大きくなる。そのため、アルキル基は、直鎖状であっても分岐状であってもよいが、直鎖状であることが好ましい。アルキル基が直鎖状である場合、立体障害を小さくする観点からは、アルキル基の炭素数は、カルボキシ基を含む主鎖の炭素数に対して同等であるか又はそれ以下であることが好ましい。 As the alkyl group, an alkyl group having 1 to 10 carbon atoms is preferable, and an alkyl group having 1 to 5 carbon atoms is more preferable. Basically, the larger the number of electron donating groups, the stronger the electron donating property, which is preferable, but the steric hindrance also increases. Therefore, the alkyl group may be linear or branched, but is preferably linear. When the alkyl group is linear, the carbon number of the alkyl group is preferably equal to or less than the carbon number of the main chain containing the carboxy group from the viewpoint of reducing steric hindrance. ..
　アルコキシ基としては、炭素数１～１０のアルコキシ基が好ましく、炭素数１～５のアルコキシ基がより好ましい。電子供与基は、多い方が電子供与性が強いが、立体障害も大きくなる。そのため、アルコキシ基のアルキル基部分は、直鎖状であっても分岐状であってもよく、直鎖状であることが好ましい。アルコキシ基のアルキル基部分が直鎖状である場合、立体障害を小さくする観点からは、その炭素数が、カルボン酸を含む主鎖の炭素数に対して同等であるか又はそれ以下であることが好ましい。 As the alkoxy group, an alkoxy group having 1 to 10 carbon atoms is preferable, and an alkoxy group having 1 to 5 carbon atoms is more preferable. The larger the number of electron donating groups, the stronger the electron donating property, but the steric hindrance also increases. Therefore, the alkyl group portion of the alkoxy group may be linear or branched, and is preferably linear. When the alkyl group portion of the alkoxy group is linear, the carbon number thereof is equal to or less than the carbon number of the main chain containing the carboxylic acid from the viewpoint of reducing steric hindrance. Is preferable.
　アルキルアミノ基としては、モノアルキルアミノ基及びジアルキルアミノ基が挙げられる。モノアルキルアミノ基としては、炭素数１～１０のモノアルキルアミノ基が好ましく、炭素数１～５のモノアルキルアミノ基がより好ましい。モノアルキルアミノ基のアルキル基部分は、直鎖状であっても分岐状であってもよく、直鎖状であることが好ましい。 Examples of the alkylamino group include a monoalkylamino group and a dialkylamino group. As the monoalkylamino group, a monoalkylamino group having 1 to 10 carbon atoms is preferable, and a monoalkylamino group having 1 to 5 carbon atoms is more preferable. The alkyl group portion of the monoalkylamino group may be linear or branched, and is preferably linear.
　ジアルキルアミノ基としては、炭素数１～２０のジアルキルアミノ基が好ましく、炭素数１～１０のジアルキルアミノ基がより好ましい。ジアルキルアミノ基のアルキル基部分は、直鎖状であっても分岐状であってもよく、直鎖状であることが好ましい。 As the dialkylamino group, a dialkylamino group having 1 to 20 carbon atoms is preferable, and a dialkylamino group having 1 to 10 carbon atoms is more preferable. The alkyl group portion of the dialkylamino group may be linear or branched, and is preferably linear.
　フラックス剤は、カルボキシ基を２つ有する化合物（ジカルボン酸）であることが好ましい。カルボキシ基を２つ有する化合物は、カルボキシ基を１つ有する化合物（モノカルボン酸）と比較して、接続時の高温によっても揮発し難く、ボイドの発生を一層抑制できる。また、カルボキシ基を２つ有する化合物を用いると、カルボキシ基を３つ以上有する化合物を用いた場合と比較して、保管時及び接続作業時等における接着剤４０の粘度上昇を一層抑制することができる。その結果、半導体装置１００の接続信頼性を一層向上させることができる。 The flux agent is preferably a compound (dicarboxylic acid) having two carboxy groups. A compound having two carboxy groups is less likely to volatilize even at a high temperature at the time of connection as compared with a compound having one carboxy group (monocarboxylic acid), and the generation of voids can be further suppressed. Further, when a compound having two carboxy groups is used, it is possible to further suppress an increase in the viscosity of the adhesive 40 during storage, connection work, etc., as compared with the case where a compound having three or more carboxy groups is used. can. As a result, the connection reliability of the semiconductor device 100 can be further improved.
　フラックス剤としては、下記式（２）で表される化合物を好適に用いることができる。下記式（２）で表される化合物からなるフラックス剤によれば、半導体装置１００の耐リフロー性及び接続信頼性を一層向上させることができる。
Figure JPOXMLDOC01-appb-C000002
 　式（２）中、Ｒ１及びＲ２はそれぞれ独立に、水素原子又は電子供与性基を示し、ｎは０～１０の整数を示す。 As the flux agent, a compound represented by the following formula (2) can be preferably used. According to the flux agent composed of the compound represented by the following formula (2), the reflow resistance and the connection reliability of the semiconductor device 100 can be further improved.
Figure JPOXMLDOC01-appb-C000002
 In formula (2), R 1 and R 2 each independently represent a hydrogen atom or an electron donating group, and n represents an integer of 0 to 10.
　式（２）におけるｎは、２～１０の整数であることが好ましく、２～８の整数であることがより好ましい。ｎが１０以下であると、フラックス活性がより短時間で発現するようになり、特に接続時間が短い場合において、一層優れた接続信頼性が得られる。また、ｎが２以上であると、接続時の高温によっても揮発し難く、ボイドの発生を一層抑制することができる。 N in the formula (2) is preferably an integer of 2 to 10, and more preferably an integer of 2 to 8. When n is 10 or less, the flux activity is expressed in a shorter time, and further excellent connection reliability can be obtained particularly when the connection time is short. Further, when n is 2 or more, it is difficult to volatilize even at a high temperature at the time of connection, and the generation of voids can be further suppressed.
　Ｒ１及びＲ２は、水素原子であっても電子供与性基であってもよい。Ｒ１及びＲ２が水素原子であると、接着剤４０の融点が低くなる傾向があり、接続信頼性（はんだ濡れ性）がよくなる場合がある。例えば、Ｒ１、Ｒ２共に同じメチル基であるフラックス剤は、片方（Ｒ１又はＲ２）にメチル基があるものに比べて融点が高くなり、はんだの濡れ性は、融点によっては（例えば１５０℃以上になると）低下する傾向がある。 R 1 and R 2 may be a hydrogen atom or an electron donating group. When R 1 and R 2 are hydrogen atoms, the melting point of the adhesive 40 tends to be low, and the connection reliability (solder wettability) may be improved. For example, a flux agent having the same methyl group in both R 1 and R 2 has a higher melting point than one having a methyl group in one (R 1 or R 2 ), and the wettability of the solder depends on the melting point (for example,). It tends to decrease (above 150 ° C).
　フラックス剤としては、例えば、コハク酸、グルタル酸、アジピン酸、ピメリン酸、スベリン酸、アゼライン酸、セバシン酸、ウンデカン二酸及びドデカン二酸から選択されるジカルボン酸の２位に電子供与性基が置換した化合物を用いることができる。 Examples of the flux agent include an electron donating group at the 2-position of a dicarboxylic acid selected from succinic acid, glutaric acid, adipic acid, pimelli acid, suberic acid, azelaic acid, sebacic acid, undecanoic acid and dodecanedioic acid. Substituted compounds can be used.
　フラックス剤の融点は、１５０℃以下であることが好ましく、１４０℃以下であることがより好ましく、１３０℃以下であることがさらに好ましい。このようなフラックス剤は、エポキシ樹脂と硬化剤との硬化反応が生じる前にフラックス活性が十分に発現する。そのため、このようなフラックス剤を含有する接着剤４０によれば、接続信頼性に一層優れる半導体装置１００を実現できる。また、上記フラックス剤は、室温で固形であるものが好ましく、フラックス剤の融点は、２５℃以上であることが好ましく、５０℃以上であることがより好ましい。フラックス剤の融点は、例えば二重管式温度計に試料を詰めた毛細管を取り付けて温浴で加温する装置により測定することができる。 The melting point of the flux agent is preferably 150 ° C. or lower, more preferably 140 ° C. or lower, and even more preferably 130 ° C. or lower. Such a flux agent sufficiently develops the flux activity before the curing reaction between the epoxy resin and the curing agent occurs. Therefore, according to the adhesive 40 containing such a flux agent, it is possible to realize the semiconductor device 100 having further excellent connection reliability. The flux agent is preferably solid at room temperature, and the melting point of the flux agent is preferably 25 ° C. or higher, more preferably 50 ° C. or higher. The melting point of the flux agent can be measured, for example, by a device in which a capillary tube filled with a sample is attached to a double-tube thermometer and heated in a hot bath.
　本実施形態の接着剤４０に含有されるフラックス剤の融点は、仮圧着体４を形成するための押圧装置４３のステージ４２の温度よりも高いことが好ましい。フラックス剤の融点が押圧装置４３のステージ温度よりも高い場合には、本圧着工程において、バンプ３０と配線１６とを容易に接触させることができるため、本圧着工程の最初と最後の熱履歴が異なっても接続信頼性に優れる半導体装置１００を製造することが可能となる。 The melting point of the flux agent contained in the adhesive 40 of the present embodiment is preferably higher than the temperature of the stage 42 of the pressing device 43 for forming the temporary pressure-bonding body 4. When the melting point of the flux agent is higher than the stage temperature of the pressing device 43, the bump 30 and the wiring 16 can be easily brought into contact with each other in the main crimping step, so that the first and last thermal histories of the main crimping step are recorded. Even if they are different, it is possible to manufacture the semiconductor device 100 having excellent connection reliability.
　フラックス剤の含有量は、接着剤４０の全量基準で、０．５～１０質量％であることが好ましく、０．５～５質量％であることがより好ましい。 The content of the flux agent is preferably 0.5 to 10% by mass, more preferably 0.5 to 5% by mass, based on the total amount of the adhesive 40.
　（高分子成分）
　接着剤４０は、高分子成分をさらに含有していてもよい。 (Polymer component)
The adhesive 40 may further contain a polymer component.
　高分子成分は、エポキシ樹脂とは異なる高分子で構成される。このような高分子成分としては、例えば、フェノキシ樹脂、ポリイミド樹脂、ポリアミド樹脂、ポリカルボジイミド樹脂、シアネートエステル樹脂、アクリル樹脂、ポリエステル樹脂、ポリエチレン樹脂、ポリエーテルスルホン樹脂、ポリエーテルイミド樹脂、ポリビニルアセタール樹脂、ウレタン樹脂及びアクリルゴムが挙げられる。これらの中でも耐熱性及びフィルム形成性に優れる観点から、フェノキシ樹脂、ポリイミド樹脂、アクリルゴム、シアネートエステル樹脂及びポリカルボジイミド樹脂が好ましく、フェノキシ樹脂、ポリイミド樹脂及びアクリルゴムがより好ましい。これらの高分子成分は単独で又は２種以上の混合物又は共重合体として使用することもできる。 The polymer component is composed of a polymer different from the epoxy resin. Examples of such polymer components include phenoxy resin, polyimide resin, polyamide resin, polycarbodiimide resin, cyanate ester resin, acrylic resin, polyester resin, polyethylene resin, polyether sulfone resin, polyetherimide resin, and polyvinyl acetal resin. , Urethane resin and acrylic rubber. Among these, phenoxy resin, polyimide resin, acrylic rubber, cyanate ester resin and polycarbodiimide resin are preferable, and phenoxy resin, polyimide resin and acrylic rubber are more preferable from the viewpoint of excellent heat resistance and film forming property. These polymer components can also be used alone or as a mixture or copolymer of two or more kinds.
　高分子成分の重量平均分子量は、特に制限されるものではないが、１００００以上であることが好ましい。この場合、高分子成分を含有する接着剤４０は、耐熱性及びフィルム形成性の点で一層優れる。このため、接着剤４０を用いると、より耐熱性に優れた半導体装置１００を製造できる。また、仮圧着工程、仮圧着体加圧工程及び本圧着工程において接着剤４０の形状が保持されやすくなり、半導体装置１００を効率よく製造できる。 The weight average molecular weight of the polymer component is not particularly limited, but is preferably 10,000 or more. In this case, the adhesive 40 containing the polymer component is further excellent in heat resistance and film forming property. Therefore, if the adhesive 40 is used, the semiconductor device 100 having higher heat resistance can be manufactured. Further, the shape of the adhesive 40 is easily maintained in the temporary crimping step, the temporary crimping body pressurizing step, and the main crimping step, and the semiconductor device 100 can be efficiently manufactured.
　高分子成分の重量平均分子量は、接着剤４０に単独で良好なフィルム形成性を付与し、仮圧着工程、仮圧着体加圧工程及び本圧着工程において接着剤４０の形状を保持しやすくして半導体装置１００を効率よく製造する観点からは、３００００以上であることが好ましく、４００００以上であることがより好ましく、５００００以上であることが更に好ましい。 The weight average molecular weight of the polymer component imparts good film forming property to the adhesive 40 by itself, and makes it easy to maintain the shape of the adhesive 40 in the temporary crimping step, the temporary crimping body pressurizing step, and the main crimping step. From the viewpoint of efficiently manufacturing the semiconductor device 100, it is preferably 30,000 or more, more preferably 40,000 or more, and further preferably 50,000 or more.
　接着剤４０が、重量平均分子量が１００００以上の高分子成分を含有する場合、重量平均分子量が１００００以上の高分子成分の含有量Ｃｄに対するエポキシ樹脂の含有量Ｃａの比Ｃａ／Ｃｄ（質量比）は、０．０１～５であることが好ましく、０．０５～３であることがより好ましく、０．１～２であることがさらに好ましい。比Ｃａ／Ｃｄを０．０１以上とすることで、より良好な硬化性及び接着力が得られる。また、比Ｃａ／Ｃｄを５以下とすることで接着剤４０において、より良好なフィルム形成性が得られるため、仮圧着工程、仮圧着体加圧工程及び本圧着工程において接着剤４０の形状が保持されやすくなり、半導体装置１００を効率よく製造できる。 When the adhesive 40 contains a polymer component having a weight average molecular weight of 10,000 or more, the ratio C a / C d of the epoxy resin content Ca to the content C d of the polymer component having a weight average molecular weight of 10,000 or more . The (mass ratio) is preferably 0.01 to 5, more preferably 0.05 to 3, and even more preferably 0.1 to 2. By setting the ratio C a / C d to 0.01 or more, better curability and adhesive strength can be obtained. Further, since better film forming property can be obtained in the adhesive 40 by setting the ratio C a / C d to 5 or less, the adhesive 40 is used in the temporary crimping step, the temporary crimping body pressurizing step, and the main crimping step. The shape is easily maintained, and the semiconductor device 100 can be efficiently manufactured.
　高分子成分のガラス転移温度（Ｔｇ）は、特に制限されるものではないが、２００℃以下であることが好ましく、１８０℃以下であることがより好ましく、１５０℃以下であることがさらに好ましい。この場合、接着剤４０が、半導体チップ１のバンプ３０、配線回路基板２に形成された電極及び配線パターン等の凹凸に接着剤４０が埋め込まれ易くなり、ボイド抑制の効果が相対的に大きくなる傾向がある。ここで、Ｔｇは、ＤＳＣ（株式会社パーキンエルマー社製、製品名「ＤＳＣ－７型」）を用いて、サンプル量１０ｍｇ、昇温速度１０℃／分、空気雰囲気下の条件で測定される。 The glass transition temperature (Tg) of the polymer component is not particularly limited, but is preferably 200 ° C. or lower, more preferably 180 ° C. or lower, and even more preferably 150 ° C. or lower. In this case, the adhesive 40 tends to embed the adhesive 40 in the bumps 30 of the semiconductor chip 1, the electrodes formed on the wiring circuit board 2, and the unevenness of the wiring pattern, and the effect of suppressing voids becomes relatively large. Tend. Here, Tg is measured using DSC (manufactured by PerkinElmer Co., Ltd., product name "DSC-7 type") under the conditions of a sample amount of 10 mg, a heating rate of 10 ° C./min, and an air atmosphere.
　高分子成分のガラス転移温度（Ｔｇ）は、５０℃以上であることが好ましい。高分子成分のＴｇが５０℃以上であると、接着剤４０のタック（粘性）力が適度に弱くなる傾向がある。 The glass transition temperature (Tg) of the polymer component is preferably 50 ° C. or higher. When the Tg of the polymer component is 50 ° C. or higher, the tack (viscous) force of the adhesive 40 tends to be moderately weakened.
　なお、高分子成分のガラス転移温度（Ｔｇ）は、接着剤４０の配線回路基板２又は半導体チップ１への貼付性に優れる観点から、５０℃以上２００℃以下であってもよく、５０℃以上１８０℃以下であることが好ましく、５０℃以上１５０℃以下であることがさらに好ましい。 The glass transition temperature (Tg) of the polymer component may be 50 ° C. or higher and 200 ° C. or lower, and may be 50 ° C. or higher, from the viewpoint of excellent adhesion of the adhesive 40 to the wiring circuit board 2 or the semiconductor chip 1. The temperature is preferably 180 ° C. or lower, and more preferably 50 ° C. or higher and 150 ° C. or lower.
　（フィラ）
　粘度及び硬化物の物性を制御するため、並びに、半導体チップ１と配線回路基板２とを接続した際のボイドの発生及び吸湿率の抑制のために、接着剤４０はフィラを含有してもよい。フィラは無機フィラであってもよく、その例としては、ガラス、シリカ、アルミナ、酸化チタン、マイカ、窒化ホウ素等の絶縁性無機フィラ、及び、カーボンブラックなどの導電性無機フィラが挙げられる。これらの中でも、接着剤４０の特性という観点からは、シリカ、アルミナ、酸化チタン、及び窒化ホウ素から選ばれる絶縁性無機フィラ、又は、シリカ、アルミナ、及び窒化ホウ素から選ばれる絶縁性無機フィラを用いることが好ましい。フィラはウィスカーであってもよく、その例としては、ホウ酸アルミニウム、チタン酸アルミニウム、酸化亜鉛、珪酸カルシウム、硫酸マグネシウム及び窒化ホウ素が挙げられる。フィラは樹脂フィラ（有機フィラ）であってもよく、その例としては、ポリウレタン樹脂、ポリイミド樹脂、メタクリル酸メチル樹脂、メタクリル酸メチル－ブタジエン－スチレン共重合樹脂（ＭＢＳ）が挙げられる。これらのフィラは単独で又は２種以上の組み合わせとして用いることもできる。フィラの形状、平均粒径、および含有量については、特に制限されない。 (Fila)
The adhesive 40 may contain a filler in order to control the viscosity and the physical characteristics of the cured product, and to suppress the generation of voids and the hygroscopicity when the semiconductor chip 1 and the wiring circuit board 2 are connected. .. The filler may be an inorganic filler, and examples thereof include an insulating inorganic filler such as glass, silica, alumina, titanium oxide, mica, and boron nitride, and a conductive inorganic filler such as carbon black. Among these, from the viewpoint of the characteristics of the adhesive 40, an insulating inorganic filler selected from silica, alumina, titanium oxide, and boron nitride, or an insulating inorganic filler selected from silica, alumina, and boron nitride is used. Is preferable. The filler may be whisker, and examples thereof include aluminum borate, aluminum titanate, zinc oxide, calcium silicate, magnesium sulfate, and boron nitride. The filler may be a resin filler (organic filler), and examples thereof include polyurethane resin, polyimide resin, methyl methacrylate resin, and methyl methacrylate-butadiene-styrene copolymer resin (MBS). These fillers can also be used alone or in combination of two or more. The shape, average particle size, and content of the filler are not particularly limited.
　フィラは、表面処理によって物性を適宜調整されたものであってもよい。 The filler may have its physical properties adjusted appropriately by surface treatment.
　フィラの含有量は、最低溶融粘度を適切な範囲に調整する観点から、接着剤４０の全量基準で、１０～８０質量％であることが好ましく、１５～６０質量％であることがより好ましい。 The content of the filler is preferably 10 to 80% by mass, more preferably 15 to 60% by mass, based on the total amount of the adhesive 40, from the viewpoint of adjusting the minimum melt viscosity to an appropriate range.
　（その他の成分）
　接着剤４０は、イオントラッパー、酸化防止剤、シランカップリング剤、チタンカップリング剤、及びレベリング剤等の他の成分を更に含んでもよい。これらは１種を単独で用いてもよいし、２種以上組み合わせて用いてもよい。これらの配合量については、各添加剤の効果が発現するように適宜調整すればよい。 (Other ingredients)
The adhesive 40 may further contain other components such as an ion trapper, an antioxidant, a silane coupling agent, a titanium coupling agent, and a leveling agent. These may be used individually by 1 type, or may be used in combination of 2 or more type. The blending amount of these may be appropriately adjusted so that the effect of each additive is exhibited.
　接着剤４０は、半導体装置１００の製造効率向上の観点から、フィルム状であってもよい。フィルム状接着剤は、エポキシ樹脂、硬化剤、フラックス剤、及び、必要に応じて有機溶媒その他の成分を含む樹脂ワニスを基材フィルム上に塗布して塗膜を形成し、塗膜を乾燥させる方法によって製造することができる。 The adhesive 40 may be in the form of a film from the viewpoint of improving the manufacturing efficiency of the semiconductor device 100. For the film-like adhesive, a resin varnish containing an epoxy resin, a curing agent, a flux agent, and if necessary, an organic solvent and other components is applied onto the base film to form a coating film, and the coating film is dried. It can be manufactured by the method.
　樹脂ワニスは、エポキシ樹脂、硬化剤及びフラックス剤、並びに、必要に応じて添加される高分子成分及びフィラ等を有機溶媒と混合し、それらを攪拌又は混練により溶解又は分散させて調製される。樹脂ワニスは、離型処理を施した基材フィルム上に、例えばナイフコーター、ロールコーター、アプリケーター、ダイコーター、又はコンマコーターを用いて塗布される。その後、加熱により樹脂ワニスの塗膜から有機溶媒を減少させて、すなわち塗膜を乾燥させて、基材フィルム上にフィルム状の接着剤を形成する。樹脂ワニスの膜を半導体ウエハ等の上にスピンコート等の方法によって形成し、その後、塗膜を乾燥する方法で、半導体ウエハ上にフィルム状の接着剤を形成してもよい。 The resin varnish is prepared by mixing an epoxy resin, a curing agent and a flux agent, and a polymer component and a filler added as necessary with an organic solvent, and dissolving or dispersing them by stirring or kneading. The resin varnish is applied onto the release-treated base film using, for example, a knife coater, a roll coater, an applicator, a die coater, or a comma coater. Then, the organic solvent is reduced from the coating film of the resin varnish by heating, that is, the coating film is dried to form a film-like adhesive on the base film. A film of a resin varnish may be formed on a semiconductor wafer or the like by a method such as spin coating, and then a film-like adhesive may be formed on the semiconductor wafer by a method of drying the coating film.
　樹脂ワニスの調製に用いる有機溶媒としては、各成分を均一に溶解又は分散し得る特性を有するものが好ましく、例えば、ジメチルホルムアミド、ジメチルアセトアミド、Ｎ－メチル－２－ピロリドン、ジメチルスルホキシド、ジエチレングリコールジメチルエーテル、トルエン、ベンゼン、キシレン、メチルエチルケトン、テトラヒドロフラン、エチルセロソルブ、エチルセロソルブアセテート、ブチルセロソルブ、ジオキサン、シクロヘキサノン、及び酢酸エチルが挙げられる。これらの有機溶媒は、単独で又は２種類以上を組み合わせて使用することができる。樹脂ワニス調製の際の攪拌及び混練は、例えば、攪拌機、らいかい機、３本ロール、ボールミル、ビーズミル又はホモディスパーを用いて行うことができる。 The organic solvent used for the preparation of the resin varnish is preferably one having the property of uniformly dissolving or dispersing each component, and for example, dimethylformamide, dimethylacetamide, N-methyl-2-pyrrolidone, dimethylsulfoxide, diethyleneglycoldimethylether, etc. Examples thereof include toluene, benzene, xylene, methyl ethyl ketone, tetrahydrofuran, ethyl cellosolve, ethyl cellosolve acetate, butyl cellosolve, dioxane, cyclohexanone, and ethyl acetate. These organic solvents can be used alone or in combination of two or more. Stirring and kneading at the time of preparing the resin varnish can be performed by using, for example, a stirrer, a raider, a three-roll, a ball mill, a bead mill or a homodisper.
　基材フィルムとしては、有機溶媒を揮発させる際の加熱条件に耐え得る耐熱性を有するものであれば特に制限はなく、ポリプロピレンフィルム、ポリメチルペンテンフィルム等のポリオレフィンフィルム、ポリエチレンテレフタレートフィルム、ポリエチレンナフタレートフィルム等のポリエステルフィルム、ポリイミドフィルム及びポリエーテルイミドフィルムを例示できる。基材フィルムは、これらのフィルムからなる単層のものに限られず、２種以上の材料からなる多層フィルムであってもよい。 The base film is not particularly limited as long as it has heat resistance that can withstand the heating conditions when the organic solvent is volatilized, and is a polyolefin film such as a polypropylene film or a polymethylpentene film, a polyethylene terephthalate film, or a polyethylene naphthalate. Examples thereof include polyester films such as films, polyimide films, and polyetherimide films. The base film is not limited to a single-layer film made of these films, and may be a multilayer film made of two or more kinds of materials.
　塗布後の樹脂ワニスから有機溶媒を揮発させるために行われる加熱は、具体的には、５０～２００℃、０．１～９０分間の加熱であってもよい。半導体装置１００における接着層４０Ａにおけるボイド発生抑制及び粘度調製に実質的に影響しない範囲で、残存量が１．５質量％以下になるまで有機溶媒を除去してもよい。 Specifically, the heating performed to volatilize the organic solvent from the resin varnish after application may be heating at 50 to 200 ° C. for 0.1 to 90 minutes. The organic solvent may be removed until the residual amount becomes 1.5% by mass or less within a range that does not substantially affect the suppression of void generation and the viscosity adjustment in the adhesive layer 40A in the semiconductor device 100.
　接着剤４０の最低溶融粘度は、１５００Ｐａ・ｓ以下であることが好ましい。接着剤４０の最低溶融粘度がこの範囲にあると、半導体装置１００の接着層４０Ａにボイドが残存し難くなるとともに、半導体チップ１と配線回路基板２との間で良好な接続信頼性を容易に確保することができる。また、接着剤４０の最低溶融粘度が１５００Ｐａ・ｓよりも大きい場合に比べて、バンプ３０と配線１６との間で接着剤４０が噛み込みにくくなり、バンプ３０と配線１６との接続不良が生じにくくなるため、半導体装置１００の接続信頼性がより向上する。接着剤４０の最低溶融粘度は、接着剤４０中の成分の配合を調整することで、１５００Ｐａ・ｓ以下の範囲に調整することができる。 The minimum melt viscosity of the adhesive 40 is preferably 1500 Pa · s or less. When the minimum melt viscosity of the adhesive 40 is in this range, voids are less likely to remain in the adhesive layer 40A of the semiconductor device 100, and good connection reliability between the semiconductor chip 1 and the wiring circuit board 2 can be easily achieved. Can be secured. Further, as compared with the case where the minimum melt viscosity of the adhesive 40 is larger than 1500 Pa · s, the adhesive 40 is less likely to bite between the bump 30 and the wiring 16, resulting in poor connection between the bump 30 and the wiring 16. Since it becomes difficult, the connection reliability of the semiconductor device 100 is further improved. The minimum melt viscosity of the adhesive 40 can be adjusted to a range of 1500 Pa · s or less by adjusting the composition of the components in the adhesive 40.
　接着剤４０の最低溶融粘度は、昇温速度１０℃／分、周波数１０Ｈｚの条件で、試験片に１％の歪みを与え３５～１５０℃の温度範囲で昇温しながら接着剤４０の粘弾性を測定したときに得られる粘度（複素粘性率）と温度との関係における、粘度の最低値である。粘弾性測定の試験片として、例えば、複数のフィルム状の接着剤４０を厚さが４００μｍになるように積層して得られる積層体を用いてもよい。粘度測定装置としては、ティー・エイ・インスツルメント社製の動的粘弾性測定装置（製品名「ＡＲＥＳ」）が用いられる。 The minimum melt viscosity of the adhesive 40 is the viscoelasticity of the adhesive 40 while giving a 1% strain to the test piece and raising the temperature in the temperature range of 35 to 150 ° C. under the conditions of a temperature rise rate of 10 ° C./min and a frequency of 10 Hz. Is the lowest value of viscosity in the relationship between the viscosity (complex viscoelasticity) obtained when measuring. As a test piece for measuring viscoelasticity, for example, a laminate obtained by laminating a plurality of film-shaped adhesives 40 so as to have a thickness of 400 μm may be used. As the viscosity measuring device, a dynamic viscoelasticity measuring device (product name "ARES") manufactured by TA Instruments Co., Ltd. is used.
　接着剤４０の最低溶融粘度は、半導体装置１００の接続信頼性をより向上させるという観点からは、１５００Ｐａ・ｓ以下であることが好ましい。 The minimum melt viscosity of the adhesive 40 is preferably 1500 Pa · s or less from the viewpoint of further improving the connection reliability of the semiconductor device 100.
　接着剤４０の最低溶融粘度は、１００Ｐａ・ｓ以上であることが好ましい。この場合、最低溶融粘度が１００Ｐａ・ｓよりも小さい場合に比べて、接着剤４０のフィルムとしての取り扱いが容易となり、半導体装置１００の製造効率がより向上する。 The minimum melt viscosity of the adhesive 40 is preferably 100 Pa · s or more. In this case, the adhesive 40 can be easily handled as a film, and the manufacturing efficiency of the semiconductor device 100 is further improved, as compared with the case where the minimum melt viscosity is smaller than 100 Pa · s.
　接着剤４０は、１５０℃おいて３５秒以上８０秒以下のゲルタイムを示すことが好ましい。ゲルタイムがこの範囲にあることにより、半導体装置１００の接着層４０Ａにボイドが残存し難くなるとともに、半導体チップ１と配線回路基板２との間で良好な接続信頼性を確保することができる。接着剤４０のゲルタイムは、硬化剤の種類及び含有量等により、３５秒以上８０秒以下の範囲に調整することができる。接着剤４０のゲルタイムを１５０℃で３５秒以上８０秒以下にすることで、ゲルタイムが８０秒よりも大きい場合に比べて、半導体装置１００の接着層４０Ａにおいてボイドが残りにくくなり、ボイドの発生がより抑制された半導体装置１００を製造できる。またゲルタイムが３５秒よりも小さい場合に比べて、仮圧着工程中に硬化反応が進行しにくくなり（８０℃のような低温では硬化しにくくなるため）、ボイドを除去することが容易となり、半導体装置１００の接着層４０Ａにおいてボイドが残りにくくなるため、ボイドの発生がより抑制された半導体装置１００を製造できる。 The adhesive 40 preferably exhibits a gel time of 35 seconds or more and 80 seconds or less at 150 ° C. When the gel time is in this range, voids are less likely to remain in the adhesive layer 40A of the semiconductor device 100, and good connection reliability can be ensured between the semiconductor chip 1 and the wiring circuit board 2. The gel time of the adhesive 40 can be adjusted in the range of 35 seconds or more and 80 seconds or less depending on the type and content of the curing agent. By setting the gel time of the adhesive 40 to 35 seconds or more and 80 seconds or less at 150 ° C., voids are less likely to remain in the adhesive layer 40A of the semiconductor device 100 as compared with the case where the gel time is longer than 80 seconds, and voids are generated. A more suppressed semiconductor device 100 can be manufactured. In addition, compared to the case where the gel time is less than 35 seconds, the curing reaction is less likely to proceed during the temporary crimping process (because it is less likely to be cured at a low temperature such as 80 ° C.), and it becomes easier to remove voids, making it easier to remove semiconductors. Since voids are less likely to remain in the adhesive layer 40A of the device 100, the semiconductor device 100 in which the generation of voids is more suppressed can be manufactured.
　ここで、ゲルタイムとは、接着剤４０を１５０℃のホットプレート上に置いてから、接着剤４０がゲル化するまでの時間である。具体的には、ゲルタイムとは、フィルムが硬化するまでの時間である。 Here, the gel time is the time from when the adhesive 40 is placed on a hot plate at 150 ° C. until the adhesive 40 gels. Specifically, the gel time is the time until the film is cured.
　接着剤４０のゲルタイムは、半導体装置１００の接着層４０Ａにおけるボイドの発生をより抑制する観点からは、３８秒以上７８秒以下であることがより好ましい。 The gel time of the adhesive 40 is more preferably 38 seconds or more and 78 seconds or less from the viewpoint of further suppressing the generation of voids in the adhesive layer 40A of the semiconductor device 100.
　本開示は、上記実施形態に限定されるものではない。例えば上記実施形態では、本開示の半導体装置の製造方法を半導体装置１００に適用する例を示したが、本開示の半導体装置の製造方法は、図５、図６及び図７に示す半導体装置２００，３００，４００，５００を製造する場合にも適用可能である。図５、図６及び図７はそれぞれ、本開示の半導体装置の製造方法の他の実施形態によって製造される半導体装置を示す部分断面図である。 The present disclosure is not limited to the above embodiment. For example, in the above embodiment, an example of applying the manufacturing method of the semiconductor device of the present disclosure to the semiconductor device 100 has been shown, but the manufacturing method of the semiconductor device of the present disclosure is the semiconductor device 200 shown in FIGS. 5, 6 and 7. , 300, 400, 500 can also be applied when manufacturing. 5, 6 and 7, respectively, are partial cross-sectional views showing a semiconductor device manufactured by another embodiment of the method for manufacturing a semiconductor device of the present disclosure.
　図５に示す半導体装置２００は、半導体チップ本体１０を有する半導体チップ１（第一の部材）と、基板本体２０を有する配線回路基板２（第二の部材）と、これらの間に介在する接着層４０Ａとを備える。半導体装置２００の場合、半導体チップ１は、第１接続部として、半導体チップ１の配線回路基板２側の面に配置されたバンプ３２を有する。配線回路基板２は、第２接続部として、基板本体２０の半導体チップ１側の面上に配置されたバンプ３３を有する。半導体チップ１のバンプ３２と、配線回路基板２のバンプ３３とは金属接合によって電気的に接続されている。すなわち、半導体チップ１及び配線回路基板２は、バンプ３２，３３によりフリップチップ接続されている。バンプ３２，３３は、接着層４０Ａによって封止されることで、外部環境から遮断されている。 In the semiconductor device 200 shown in FIG. 5, the semiconductor chip 1 (first member) having the semiconductor chip body 10 and the wiring circuit board 2 (second member) having the substrate body 20 are bonded to each other. A layer 40A is provided. In the case of the semiconductor device 200, the semiconductor chip 1 has a bump 32 arranged on the surface of the semiconductor chip 1 on the wiring circuit board 2 side as a first connection portion. The wiring circuit board 2 has a bump 33 arranged on the surface of the board body 20 on the semiconductor chip 1 side as a second connection portion. The bump 32 of the semiconductor chip 1 and the bump 33 of the wiring circuit board 2 are electrically connected by metal bonding. That is, the semiconductor chip 1 and the wiring circuit board 2 are flip-chip connected by bumps 32 and 33. The bumps 32 and 33 are shielded from the external environment by being sealed by the adhesive layer 40A.
　図６及び図７は、半導体チップ１同士が接続された接続体であるＣｏＣ型の半導体装置３００，４００を示す。図６に示す半導体装置３００の構成は、２つの半導体チップ１が第一の部材及び第二の部材として、配線１５及びバンプ３０を介してフリップチップ接続されている点を除き、半導体装置１００と同様である。図７に示す半導体装置４００の構成は、バンプ３２を有する２つの半導体チップ１がバンプ３２を介してフリップチップ接続されている点を除き、半導体装置２００と同様である。 6 and 7 show CoC- type semiconductor devices 300 and 400, which are connectors in which semiconductor chips 1 are connected to each other. The configuration of the semiconductor device 300 shown in FIG. 6 is that the two semiconductor chips 1 are connected to the semiconductor device 100 as the first member and the second member by flip-chip connection via the wiring 15 and the bump 30. The same is true. The configuration of the semiconductor device 400 shown in FIG. 7 is the same as that of the semiconductor device 200, except that the two semiconductor chips 1 having the bumps 32 are flip-chip connected via the bumps 32.
　また、図１及び図５～図７に示される半導体装置１００、２００、３００、及び４００において、配線１５、バンプ３２等の第１接続部又は第２接続部は、パッドと呼ばれる金属膜（例えば、金めっき）であってもよく、ポスト電極（例えば、銅ピラー）であってもよい。例えば、一方の半導体チップ１が第１接続部として銅ピラー及び接続バンプ（はんだ：スズ－銀）を有し、他方の半導体チップ１又は配線回路基板２が第２接続部として金めっきを有していてもよい。 Further, in the semiconductor devices 100, 200, 300, and 400 shown in FIGS. 1 and 5 to 7, the first connection portion or the second connection portion such as the wiring 15 and the bump 32 is a metal film (for example, a pad) called a pad. , Gold plating) or post electrodes (eg, copper pillars). For example, one semiconductor chip 1 has a copper pillar and a connection bump (solder: tin-silver) as a first connection, and the other semiconductor chip 1 or a wiring circuit board 2 has gold plating as a second connection. May be.
　また、本開示の半導体装置の製造方法は、図８に示す半導体装置５００の製造にも適用可能である。図８は、本開示の半導体装置の製造方法の他の実施形態によって製造される半導体装置を示す部分断面図である。 Further, the method for manufacturing a semiconductor device of the present disclosure is also applicable to the manufacturing of the semiconductor device 500 shown in FIG. FIG. 8 is a partial cross-sectional view showing a semiconductor device manufactured by another embodiment of the method for manufacturing a semiconductor device of the present disclosure.
　図８は、半導体装置の他の一実施形態を示す断面図である。図８に示す半導体装置５００は、複数の半導体チップ１が積層されたＴＳＶ構造を有する。図８に示す半導体装置５００では、第二の部材としてのインターポーザー５０１のインターポーザー本体５０上に形成された配線１５が半導体チップ１のバンプ３０と接続されることにより、半導体チップ１とインターポーザー５０１とがフリップチップ接続されている。半導体チップ１とインターポーザー５０１との間には接着層４０Ａが介在している。半導体チップ１におけるインターポーザー５０１と反対側の表面上に、配線１５、バンプ３０及び接着層４０Ａを介して半導体チップ１が繰り返し積層されている。半導体チップ１の表裏におけるパターン面の配線１５は、半導体チップ本体１０の内部を貫通する孔内に充填された貫通電極３４により互いに接続されている。貫通電極３４の材質としては、銅、アルミニウム等を用いることができる。 FIG. 8 is a cross-sectional view showing another embodiment of the semiconductor device. The semiconductor device 500 shown in FIG. 8 has a TSV structure in which a plurality of semiconductor chips 1 are laminated. In the semiconductor device 500 shown in FIG. 8, the wiring 15 formed on the interposer main body 50 of the interposer 501 as a second member is connected to the bump 30 of the semiconductor chip 1 to connect the semiconductor chip 1 and the interposer. It is flip-chip connected to 501. An adhesive layer 40A is interposed between the semiconductor chip 1 and the interposer 501. The semiconductor chip 1 is repeatedly laminated on the surface of the semiconductor chip 1 opposite to the interposer 501 via the wiring 15, the bump 30, and the adhesive layer 40A. The wiring 15 on the pattern surface on the front and back of the semiconductor chip 1 is connected to each other by a through electrode 34 filled in a hole penetrating the inside of the semiconductor chip main body 10. As the material of the through electrode 34, copper, aluminum, or the like can be used.
　図８の半導体装置５００は、複数の半導体チップ１を一つずつ積み重ねて順次仮圧着し、複数の半導体チップ１を加熱炉６０内で一括して加圧雰囲気下で加圧しながら加熱し、本圧着工程によって圧着を行うことによって製造することができる。 In the semiconductor device 500 of FIG. 8, a plurality of semiconductor chips 1 are stacked one by one and temporarily crimped in sequence, and the plurality of semiconductor chips 1 are collectively heated in a heating furnace 60 while being pressurized in a pressurized atmosphere. It can be manufactured by crimping by a crimping process.
　また、図８の半導体装置５００においては、インターポーザー５０１の代わりにマザーボードが用いられてもよい。この場合、半導体チップ１が、インターポーザー５０１を介さないでそのままマザーボードに直接実装されることになる。 Further, in the semiconductor device 500 of FIG. 8, a motherboard may be used instead of the interposer 501. In this case, the semiconductor chip 1 is directly mounted on the motherboard without going through the interposer 501.
　さらに、多層の半導体チップを有する半導体装置の他の例として、チップスタック型パッケージ及びＰＯＰ（Ｐａｃｋａｇｅ　Ｏｎ　Ｐａｃｋａｇｅ）もあり、本開示の半導体装置の製造方法は、このような半導体装置の製造に対しても適用可能である。これらの半導体装置は、ＴＳＶ構造を有する半導体装置５００と同様の方法により製造することができる。 Further, as another example of the semiconductor device having a multi-layered semiconductor chip, there are also a chip stack type package and a POP (Package On Package), and the method for manufacturing a semiconductor device of the present disclosure relates to the manufacture of such a semiconductor device. Is also applicable. These semiconductor devices can be manufactured by the same method as the semiconductor device 500 having a TSV structure.
　以下、本開示を、実施例を挙げてより具体的に説明するが、本開示はこれらの実施例に限定されるものではない。 Hereinafter, the present disclosure will be described in more detail with reference to examples, but the present disclosure is not limited to these examples.
　以下、実施例により本開示をより具体的に説明するが、本開示は実施例に限定されるものではない。 Hereinafter, the present disclosure will be described in more detail by way of examples, but the present disclosure is not limited to the examples.
　各実施例及び比較例で使用した材料は以下の通りである。
（ｉ）エポキシ樹脂
・ＥＰ１０３２Ｈ６０：トリフェノールメタン骨格含有多官能固形エポキシ樹脂（ジャパンエポキシレジン株式会社製、商品名「ＥＰ１０３２Ｈ６０」、重量平均分子量：８００～２０００）
・ＹＬ９８３Ｕ：ビスフェノールＦ型液状エポキシ樹脂（ジャパンエポキシレジン株式会社製、商品名「ＹＬ９８３Ｕ」、重量平均分子量：約３３６）
・ＹＬ７１７５：柔軟性エポキシ樹脂（ジャパンエポキシレジン株式会社製、商品名「ＹＬ７１７５」、重量平均分子量：１０００～５０００）
（ｉｉ）硬化剤
・２ＭＡＯＫ－ＰＷ：２，４－ジアミノ－６－［２’－メチルイミダゾリル－（１’）］－エチル－ｓ－トリアジンイソシアヌル酸付加体（四国化成工業株式会社製、商品名「２ＭＡＯＫ－ＰＷ」）
（ｉｉｉ）フラックス剤
・グルタル酸（東京化成株式会社製、融点約９８℃）
（ｉｖ）高分子成分
・ＺＸ１３５６－２：フェノキシ樹脂（東都化成株式会社製、商品名「ＺＸ１３５６－２」、Ｔｇ：約７１℃、重量平均分子量：約６３０００）
（ｖ）フィラ
（無機フィラ）
・ＳＥ２０５０：シリカフィラ（株式会社アドマテックス製、商品名「ＳＥ２０５０」、平均粒径０．５μｍ）
・ＳＥ２０５０－ＳＥＪ：エポキシシラン処理シリカフィラ（株式会社アドマテックス製、商品名「ＳＥ２０５０－ＳＥＪ」、平均粒径０．５μｍ）
・ＳＭナノシリカ：アクリル表面処理ナノシリカフィラ（株式会社アドマテックス製、商品名「ＹＡ０５０Ｃ－ＳＭ」、平均粒径約５０ｎｍ）
・ＳＭナノシリカ２：アクリル表面処理ナノシリカフィラ（株式会社アドマテックス製、商品名「ＹＡ１８０Ｃ－ＳＭ」、平均粒径約１８０ｎｍ）
（有機フィラ）
・ＥＸＬ２６５５：コアシェルタイプ有機微粒子（ロームアンドハースジャパン株式会社製、商品名「ＥＸＬ２６５５」） The materials used in each Example and Comparative Example are as follows.
(I) Epoxy resin / EP1032H60: Polyphenol methane skeleton-containing polyfunctional solid epoxy resin (manufactured by Japan Epoxy Resin Co., Ltd., trade name "EP1032H60", weight average molecular weight: 800-2000)
-YL983U: Bisphenol F type liquid epoxy resin (manufactured by Japan Epoxy Resin Co., Ltd., trade name "YL983U", weight average molecular weight: about 336)
-YL7175: Flexible epoxy resin (manufactured by Japan Epoxy Resin Co., Ltd., trade name "YL7175", weight average molecular weight: 1000 to 5000)
(Ii) Curing agent, 2MAOK-PW: 2,4-diamino-6- [2'-methylimidazolyl- (1')]-ethyl-s-triazine isocyanuric acid adduct (manufactured by Shikoku Chemicals Corporation, trade name) "2MAOK-PW")
(Iii) Flux agent, glutaric acid (manufactured by Tokyo Kasei Co., Ltd., melting point of about 98 ° C)
(Iv) Polymer component-ZX1356-2: Phenoxy resin (manufactured by Toto Kasei Co., Ltd., trade name "ZX1356-2", Tg: about 71 ° C., weight average molecular weight: about 63000)
(V) Fira (inorganic Fira)
SE2050: Silica Fila (manufactured by Admatex Co., Ltd., trade name "SE2050", average particle size 0.5 μm)
SE2050-SEJ: Epoxysilane treated silica filler (manufactured by Admatex Co., Ltd., trade name "SE2050-SEJ", average particle size 0.5 μm)
-SM nanosilica: Acrylic surface-treated nanosilica filler (manufactured by Admatex Co., Ltd., trade name "YA050C-SM", average particle size of about 50 nm)
-SM Nanosilica 2: Acrylic surface-treated nanosilica filler (manufactured by Admatex Co., Ltd., trade name "YA180C-SM", average particle size of about 180 nm)
(Organic Fila)
-EXL2655: Core shell type organic fine particles (manufactured by Rohm and Haas Japan Co., Ltd., trade name "EXL2655")
（実施例１）
（１）フィルム状接着剤の作製
　エポキシ樹脂を３．１ｇ（「ＥＰ１０３２」：２．４ｇ、「ＹＬ９８３」：０．５ｇ、「ＹＬ７１７５」：０．２ｇ）、硬化剤「２ＭＡＯＫ」を０．１ｇ、グルタル酸を０．１ｇ（０．７ｍｍｏｌ）、フィラ（無機フィラ）を１．９ｇ（「ＳＥ２０５０」を０．４ｇ、「ＳＥ２０５０－ＳＥＪ」を０．４ｇ、「ＳＭナノシリカ」を１．１ｇ）、有機フィラ（ＥＸＬ－２６５５）を０．３ｇ、及びメチルエチルケトン（固形分量が６３質量％になる量）をビーズミル（フリッチュ・ジャパン株式会社、遊星型微粉砕機Ｐ－７）の容器内に仕込み、直径０．８ｍｍのビーズ及び直径２．０ｍｍのビーズを固形分の総重量と同重量加えて３０分撹拌し、混合物を得た。次いで、容器内にフェノキシ樹脂（ＺＸ１３５６－２）を１．７ｇ加え、再度ビーズミルで３０分撹拌を行った。その後、撹拌に用いたビーズをろ過によって除去し、樹脂ワニスを得た。 (Example 1)
(1) Preparation of film-shaped adhesive 3.1 g of epoxy resin (“EP1032”: 2.4 g, “YL983”: 0.5 g, “YL7175”: 0.2 g), 0.1 g of curing agent “2MAOK” , 0.1 g (0.7 mmol) of glutaric acid, 1.9 g of filler (inorganic filler) (0.4 g of "SE2050", 0.4 g of "SE2050-SEJ", 1.1 g of "SM nanosilica") , 0.3 g of organic filler (EXL-2655) and methyl ethyl ketone (amount having a solid content of 63% by mass) were charged in a container of a bead mill (Fritsch Japan Co., Ltd., planetary pulverizer P-7). Beads having a diameter of 0.8 mm and beads having a diameter of 2.0 mm were added in the same weight as the total weight of the solid content and stirred for 30 minutes to obtain a mixture. Next, 1.7 g of phenoxy resin (ZX1356-2) was added to the container, and the mixture was stirred again with a bead mill for 30 minutes. Then, the beads used for stirring were removed by filtration to obtain a resin varnish.
　得られた樹脂ワニスを、基材フィルム（帝人フィルムソリューション株式会社製、商品名「ピューレックスＡ５３」）上に、小型精密塗工装置（株式会社廉井精機製）で塗工して塗膜を形成した。そして、この塗膜を、クリーンオーブン（ＥＳＰＥＣ製）を用いて７０℃で１０分間乾燥した後、フィルム状接着剤（厚み０．０４０ｍｍ）を得た。このフィルム状接着剤の反応開始温度は１３５℃であった。 The obtained resin varnish is coated on a base film (manufactured by Teijin Film Solution Co., Ltd., trade name "Purex A53") with a small precision coating device (manufactured by Yasui Seiki Co., Ltd.) to form a coating film. Formed. Then, this coating film was dried at 70 ° C. for 10 minutes using a clean oven (manufactured by ESPEC) to obtain a film-like adhesive (thickness 0.040 mm). The reaction start temperature of this film-like adhesive was 135 ° C.
（２）最低溶融粘度の測定
　複数のフィルム状の接着剤を厚さが４００μｍになるように積層して積層体を得た。そして、この積層体を試験片として用い、昇温速度１０℃／分、周波数１０Ｈｚの条件で、試験片に１％の歪みを与え３５～１５０℃の温度範囲で昇温しながら接着剤の粘弾性を測定した。そして、このときに得られる粘度（複素粘性率）と温度との関係における粘度の最低値を接着剤の最低溶融粘度とした。結果を表１に示す。 (2) Measurement of Minimum Melt Viscosity A laminated body was obtained by laminating a plurality of film-shaped adhesives so as to have a thickness of 400 μm. Then, using this laminate as a test piece, under the conditions of a temperature rise rate of 10 ° C./min and a frequency of 10 Hz, the test piece is distorted by 1% and the temperature is raised in the temperature range of 35 to 150 ° C. The elasticity was measured. Then, the lowest value of the viscosity in the relationship between the viscosity (complex viscosity) obtained at this time and the temperature was set as the minimum melt viscosity of the adhesive. The results are shown in Table 1.
（３）ゲルタイムの測定
　複数枚（３枚）のフィルム状接着剤を８０℃の雰囲気下で積層することで全体の厚みを１２０μｍとした。形成されたラミネートフィルムから、１１ｍｍ四方のサイズの試験片を切り抜いた。得られた試験片を１５０℃のホットプレート上に置いて溶融させ、試験片を攪拌棒によって小さな円を描くように攪拌した。試験片が増粘し始めたら全体を攪拌し、試験片がゲル化して流動性を失った状態となるまで、撹拌を続けた。試験片をホットプレート上に置いた時点から試験片がゲル化して流動性を失った状態となるまでの時間を「ゲルタイム」として１秒単位で測定した。同様の測定を２回実施し、２回の測定による２つの測定値のうち、高い値が低い値の１．０５倍以下である場合には、２つの測定値の平均値を当該試験片のゲルタイムとして記録した。２つの測定値のうち高い値が、低い値の１．０５倍よりも大きい場合には、３回目の測定を実施し、３回の測定による３つの測定値の平均値を当該試験片のゲルタイムとして記録した。結果を表１に示す。 (3) Measurement of gel time A plurality of (three) film-like adhesives were laminated in an atmosphere of 80 ° C. to make the total thickness 120 μm. A test piece having a size of 11 mm square was cut out from the formed laminated film. The obtained test piece was placed on a hot plate at 150 ° C. to melt, and the test piece was stirred with a stirring rod in a small circle. When the test piece began to thicken, the whole was stirred, and stirring was continued until the test piece gelled and lost its fluidity. The time from the time when the test piece was placed on the hot plate until the test piece gelled and lost its fluidity was measured in units of 1 second as "gel time". If the same measurement is performed twice and the high value is 1.05 times or less of the low value among the two measured values obtained by the two measurements, the average value of the two measured values is used for the test piece. Recorded as gel time. If the higher of the two measurements is greater than 1.05 times the lower, the third measurement is performed and the average of the three measurements from the three measurements is the gel time of the test piece. Recorded as. The results are shown in Table 1.
（４）半導体装置の作製
　次に、上記のようにして作製したフィルム状接着剤を用いて以下のようにして半導体装置を作製した。
　（仮圧着体の作製）
　作製したフィルム状接着剤を切り抜き、８ｍｍ×８ｍｍ×厚さ０．０４５ｍｍのサイズを有するフィルム状接着剤を準備した。これを半導体チップ（１０ｍｍ×１０ｍｍ）、厚さ０．１ｍｍ、接続部金属：Ａｕ、製品名：ＷＡＬＴＳ－ＴＥＧ　ＩＰ８０、ＷＡＬＴＳ製）に貼付した。そこに、はんだバンプ付き半導体チップ（チップサイズ：７．３ｍｍ×７．３ｍｍ×厚み０．０５ｍｍ、はんだバンプ融点：約２２０℃、バンプ高さ：銅ピラーとはんだの合計で約４５μｍ、バンプ数１０４８ピン、ピッチ８０μｍ、製品名：ＷＡＬＴＳ－ＴＥＧ　ＣＣ８０、ＷＡＬＴＳ製）を貼付し、積層体を得た。次いで、この積層体を、ステージ及び圧着ヘッドを有するフリップチップボンダー（製品名「ＦＣＢ３」、パナソニック株式会社製）の８０℃のステージ上に設置し、ステージ及び圧着ヘッドで挟む熱プレスにより、３秒間、２５Ｎの荷重で積層体を加圧しながら８０℃に加熱した。こうして仮圧着体を作製した。 (4) Preparation of Semiconductor Device Next, a semiconductor device was manufactured as follows using the film-like adhesive prepared as described above.
(Making a temporary crimping body)
The produced film-shaped adhesive was cut out to prepare a film-shaped adhesive having a size of 8 mm × 8 mm × thickness 0.045 mm. This was attached to a semiconductor chip (10 mm × 10 mm), thickness 0.1 mm, connection metal: Au, product name: WALTS-TEG IP80, manufactured by WALTS). There, a semiconductor chip with solder bumps (chip size: 7.3 mm x 7.3 mm x thickness 0.05 mm, solder bump melting point: about 220 ° C, bump height: about 45 μm in total of copper pillars and solder, number of bumps 1048 A pin, a pitch of 80 μm, and a product name: WALTS-TEG CC80, manufactured by WALTS) were attached to obtain a laminated body. Next, this laminate is placed on a stage at 80 ° C. of a flip-chip bonder (product name "FCB3", manufactured by Panasonic Corporation) having a stage and a crimping head, and is sandwiched between the stage and the crimping head by a hot press for 3 seconds. , The laminate was heated to 80 ° C. while being pressurized with a load of 25 N. In this way, a temporary pressure-bonded body was produced.
　（加圧済み仮圧着体の作製）
　上記のようにして作製した仮圧着体を加圧式オーブン装置（製品名：ＰＣＯＡ－０１Ｔ、ＮＴＴ－ＡＴクリエイティブ株式会社製）のオーブン内に配置した。そして、まずオーブン内の圧力を０．７ＭＰａに設定し、室温から昇温速度２０℃／分で１５０℃まで昇温した。次いで圧力及び温度を維持しながら仮圧着体を加圧雰囲気下で３０分間加圧しながら加熱した。こうして加圧済み仮圧着体を作製した。 (Making a pressurized temporary crimping body)
The temporary crimping body produced as described above was placed in the oven of a pressurized oven device (product name: PCOA-01T, manufactured by NTT-AT Creative Co., Ltd.). Then, first, the pressure in the oven was set to 0.7 MPa, and the temperature was raised from room temperature to 150 ° C. at a heating rate of 20 ° C./min. Then, while maintaining the pressure and temperature, the temporary pressure-bonded body was heated while being pressurized for 30 minutes in a pressurized atmosphere. In this way, a pressurized temporary pressure-bonded body was produced.
　（圧着体の作製）
　上記のようにして作製した加圧済み仮圧着体を、別のフリップチップボンダー（製品名：ＦＣＢ３、パナソニック株式会社製）の８０℃のステージ上に移動させ、ステージ及び圧着ヘッドで２５Ｎの荷重で加圧済み仮圧着体を加圧しながら２３０℃で１秒間加熱する熱プレスを行った。こうして半導体装置を作製した。この半導体装置を評価用の半導体装置サンプルとした。 (Making a crimp body)
The pressurized temporary crimping body produced as described above is moved onto a stage at 80 ° C. of another flip-chip bonder (product name: FCB3, manufactured by Panasonic Corporation), and the stage and crimping head are loaded with 25 N. A hot press was performed in which the pressed temporary crimping body was heated at 230 ° C. for 1 second while being pressurized. In this way, the semiconductor device was manufactured. This semiconductor device was used as a semiconductor device sample for evaluation.
　（実施例２～４）
　使用した接着剤の組成を下記表１に記載のとおりに変更したこと以外は実施例１と同様にして、実施例２～４の半導体装置を作製した。 (Examples 2 to 4)
The semiconductor devices of Examples 2 to 4 were produced in the same manner as in Example 1 except that the composition of the adhesive used was changed as shown in Table 1 below.
　（比較例１）
　実施例１と同様にして用意したフィルム状接着剤を切り抜き、８ｍｍ×８ｍｍ×厚さ０．０４５ｍｍのサイズを有するフィルム状接着剤を準備した。これを半導体チップ（１０ｍｍ、厚さ０．１ｍｍ、接続部金属：Ａｕ、製品名：ＷＡＬＴＳ－ＴＥＧ　ＩＰ８０、ＷＡＬＴＳ製）に貼付した。そこに、はんだバンプ付き半導体チップ（チップサイズ：７．３ｍｍ×７．３ｍｍ×厚み０．０５ｍｍ、はんだバンプ融点：約２２０℃、バンプ高さ：銅ピラーとはんだの合計で約４５μｍ、バンプ数１０４８ピン、ピッチ８０ｕｍ、製品名：ＷＡＬＴＳ－ＴＥＧ　ＣＣ８０、ＷＡＬＴＳ製）を貼付し、積層体を得た。積層体を、ステージ及び圧着ヘッドを有するフリップチップボンダー（ＦＣＢ３、パナソニック株式会社製）のステージ上に設置し、ステージ及び圧着ヘッドで挟む熱プレスにより、１秒間、２５Ｎの荷重で積層体を加圧しながら８０℃に加熱した。こうして仮圧着体を作製した。 (Comparative Example 1)
The film-like adhesive prepared in the same manner as in Example 1 was cut out, and a film-like adhesive having a size of 8 mm × 8 mm × thickness 0.045 mm was prepared. This was attached to a semiconductor chip (10 mm, thickness 0.1 mm, connection metal: Au, product name: WALTS-TEG IP80, manufactured by WALTS). There, a semiconductor chip with solder bumps (chip size: 7.3 mm x 7.3 mm x thickness 0.05 mm, solder bump melting point: about 220 ° C, bump height: about 45 μm in total of copper pillars and solder, number of bumps 1048 A pin, pitch 80um, product name: WALTS-TEG CC80, manufactured by WALTS) was attached to obtain a laminated body. The laminate is installed on the stage of a flip-chip bonder (FCB3, manufactured by Panasonic Corporation) having a stage and a crimping head, and the laminate is pressed with a load of 25N for 1 second by a hot press sandwiched between the stage and the crimping head. While heating to 80 ° C. In this way, a temporary pressure-bonded body was produced.
　上記のようにして作製した仮圧着体を、別のフリップチップボンダー（ＦＣＢ３、パナソニック株式会社製）のステージ上に移動させ、ステージ及び圧着ヘッドで挟むことにより、２５Ｎの荷重で加圧しながら２３０℃で３秒間加熱する熱プレスを行った。こうして圧着体を作製した。 The temporary crimping body produced as described above is moved onto the stage of another flip-chip bonder (FCB3, manufactured by Panasonic Corporation) and sandwiched between the stage and the crimping head to pressurize at 230 ° C. with a load of 25N. A hot press was performed to heat the mixture for 3 seconds. In this way, the crimped body was produced.
　上記のようにして作製した圧着体を加圧オーブン装置（製品名：ＰＣＯＡ－０１Ｔ、ＮＴＴ－ＡＴクリエイティブ株式会社製）のオーブン内に配置した。そして、まずオーブン内の圧力を０．７ＭＰａに設定し、室温から昇温速度２０℃／分で１７５℃まで昇温した。次いで圧力及び温度を維持しながら圧着体を加圧雰囲気下で１０分間加圧しながら加熱した。こうして半導体装置を作製した。この半導体装置を評価用の半導体装置サンプルとした。 The crimped body produced as described above was placed in the oven of a pressure oven device (product name: PCOA-01T, manufactured by NTT-AT Creative Co., Ltd.). Then, the pressure in the oven was first set to 0.7 MPa, and the temperature was raised from room temperature to 175 ° C. at a heating rate of 20 ° C./min. Then, the pressure-bonded body was heated while being pressurized for 10 minutes in a pressurized atmosphere while maintaining the pressure and temperature. In this way, the semiconductor device was manufactured. This semiconductor device was used as a semiconductor device sample for evaluation.
　＜評価＞
　上記のようにして得られた実施例１～４及び比較例１で得られた評価用半導体装置サンプルについて、ボイド抑制効果及び接続信頼性の評価を行った。 <Evaluation>
The void suppression effect and connection reliability were evaluated for the evaluation semiconductor device samples obtained in Examples 1 to 4 and Comparative Example 1 obtained as described above.
　（ボイド抑制効果の評価）
　実施例１～４及び比較例１で得られた評価用半導体装置サンプルについて、超音波映像診断装置（製品名：Ｉｎｓｉｇｈｔ－３００、インサイト製）により、外観画像を撮影した。得られた画像から、スキャナ（製品名：ＧＴ－９３００ＵＦ、セイコーエプソン株式会社製）でチップ上の接着層の部分を取り込んだ。画像処理ソフトＡｄｏｂｅ　Ｐｈｏｔｏｓｈｏｐ（登録商標）を用いて、色調補正、二階調化によりボイド部分を識別し、接着層の面積を１００％として、ヒストグラムによりボイド部分の占める割合（ボイド発生率）を算出した。以下の基準によりボイドの発生状態を評価した。結果を表１に示した。
 
Ａ：ボイド発生率が５％以下
Ｂ：ボイド発生率が５％より多い
  (Evaluation of void suppression effect)
External images of the evaluation semiconductor device samples obtained in Examples 1 to 4 and Comparative Example 1 were taken with an ultrasonic image diagnostic device (product name: Insight-300, manufactured by Insight). From the obtained image, the adhesive layer portion on the chip was captured by a scanner (product name: GT-9300UF, manufactured by Seiko Epson Corporation). Using the image processing software Adobe Photoshop (registered trademark), the void portion was identified by color tone correction and two-gradation, and the area occupied by the void portion (void generation rate) was calculated from the histogram with the area of the adhesive layer as 100%. .. The state of void generation was evaluated according to the following criteria. The results are shown in Table 1.

A: Void occurrence rate is 5% or less B: Void occurrence rate is more than 5%
　（接続信頼性の評価）
　実施例１～４及び比較例１で得られた評価用半導体装置サンプルについて、マルチメータ（ＡＤＶＡＮＴＥＳＴ製、製品名：Ｒ６８７１Ｅ）を用いて初期接続抵抗値を測定した。そして、以下の基準で接続信頼性を判定した。結果を表１に示す。
 
Ａ：接続抵抗値が評価用半導体装置サンプルにおける半導体チップについて最適とされる接続抵抗値の範囲（本実施例及び比較例では１０．０～１５．０Ω）内にある
Ｂ：接続抵抗値がＡの範囲（１０．０～１５．０Ω）を外れる、又は接続不良によって接続抵抗値が測定されない
　なお、評価用半導体装置サンプルにおいて接続不良が生じているかどうかについては、サンプルの断面を確認してはんだバンプが濡れていないこと、すなわち、はんだバンプ付き半導体チップのはんだバンプが、対向する半導体チップの接続部に到達していないこと、を確認することにより判断した。
  (Evaluation of connection reliability)
The initial connection resistance values of the evaluation semiconductor device samples obtained in Examples 1 to 4 and Comparative Example 1 were measured using a multimeter (manufactured by ADVANTEST, product name: R6781E). Then, the connection reliability was determined based on the following criteria. The results are shown in Table 1.

A: The connection resistance value is within the optimum connection resistance value range (10.0 to 15.0Ω in this example and comparative example) for the semiconductor chip in the evaluation semiconductor device sample. B: The connection resistance value is A. The connection resistance value is not measured because it is out of the range (10.0 to 15.0Ω) or due to a connection failure. To check whether a connection failure has occurred in the evaluation semiconductor device sample, check the cross section of the sample and solder. It was determined by confirming that the bumps were not wet, that is, the solder bumps of the semiconductor chip with the solder bumps did not reach the connection portion of the opposing semiconductor chips.
Figure JPOXMLDOC01-appb-T000003
Figure JPOXMLDOC01-appb-T000003
　実施例１～４の半導体装置においてはいずれも、ボイド発生率が低く、ボイドの発生が抑制されるとともに、接続抵抗値が適度な値を示し、接続信頼性も良好であることが確認された。これに対し、比較例１の半導体装置においてはボイド発生率が高く、ボイドの発生が抑制されていないことが確認された。 It was confirmed that in all of the semiconductor devices of Examples 1 to 4, the void generation rate was low, the void generation was suppressed, the connection resistance value showed an appropriate value, and the connection reliability was good. .. On the other hand, in the semiconductor device of Comparative Example 1, it was confirmed that the void generation rate was high and the void generation was not suppressed.
　１…半導体チップ（第一の部材）、２…配線回路基板（第二の部材）、１５…配線（第２接続部）、１６…配線（第２接続部）、３０…バンプ（第１接続部）、３２…バンプ（第１接続部又は第２接続部）、３３…バンプ（第２接続部）、４０…接着剤、４０Ａ…接着層、５０１…インターポーザー（第二の部材）、１００，２００，３００，４００，５００…半導体装置。 1 ... Semiconductor chip (first member), 2 ... Wiring circuit board (second member), 15 ... Wiring (second connection part), 16 ... Wiring (second connection part), 30 ... Bump (first connection) Part), 32 ... Bump (first connection part or second connection part), 33 ... Bump (second connection part), 40 ... Adhesive, 40A ... Adhesive layer, 501 ... Interposer (second member), 100 , 200, 300, 400, 500 ... Semiconductor device.

Claims (14)

  1. 　第１接続部を有する第一の部材と、第２接続部を有する第二の部材とが、接着層を介して接続され、前記第１接続部と前記第２接続部とが電気的に接続されている半導体装置の製造方法であって、
    　前記第一の部材及び前記第二の部材を、前記接着層を形成するための熱硬化性の接着剤を介して、前記第１接続部と前記第２接続部とが対向配置された状態で仮圧着させて仮圧着体を得る仮圧着工程と、
    　前記仮圧着体を加圧雰囲気下で加圧し、加圧済み仮圧着体を得る仮圧着体加圧工程と、
    　前記加圧済み仮圧着体を、加熱しながら加圧して、前記第一の部材及び前記第二の部材を圧着させることによって、前記第１接続部と前記第２接続部とを接続させて圧着体を得る本圧着工程とを含み、
    　前記仮圧着工程において、前記第一の部材及び前記第二の部材の仮圧着を、前記第１接続部の融点及び前記第２接続部の融点よりも低い温度で行い、
    　前記仮圧着体加圧工程において、前記仮圧着体の加圧を、前記第１接続部の融点及び前記第２接続部の融点よりも低い温度で行い、
    　前記本圧着工程において、前記加圧済み仮圧着体の加熱を、前記第１接続部及び前記第２接続部のうち少なくとも一方の融点以上の温度で行う、半導体装置の製造方法。     The first member having the first connection portion and the second member having the second connection portion are connected via the adhesive layer, and the first connection portion and the second connection portion are electrically connected to each other. It is a manufacturing method of semiconductor devices that are used.
    The first member and the second member are arranged so that the first connecting portion and the second connecting portion face each other via a thermosetting adhesive for forming the adhesive layer. Temporary crimping process to obtain a temporary crimping body by temporary crimping,
    The temporary crimping body pressurizing step of pressurizing the temporary crimping body in a pressurized atmosphere to obtain a pressurized temporary crimping body, and
    By pressurizing the pressurized temporary crimping body while heating to crimp the first member and the second member, the first connecting portion and the second connecting portion are connected and crimped. Including this crimping process to obtain the body
    In the temporary crimping step, the temporary crimping of the first member and the second member is performed at a temperature lower than the melting point of the first connecting portion and the melting point of the second connecting portion.
    In the temporary crimping body pressurizing step, the temporary crimping body is pressurized at a temperature lower than the melting point of the first connection portion and the melting point of the second connection portion.
    A method for manufacturing a semiconductor device, wherein in the main crimping step, the pressurized temporary crimping body is heated at a temperature equal to or higher than the melting point of at least one of the first connecting portion and the second connecting portion.
  2. 　前記仮圧着工程において、前記仮圧着体の加圧を、前記接着剤の反応開始温度よりも低い温度で行う、請求項１に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1, wherein in the temporary crimping step, the temporary crimping body is pressurized at a temperature lower than the reaction start temperature of the adhesive.
  3. 　前記仮圧着体加圧工程において、前記仮圧着体の加圧を、０．０５～０．８ＭＰａの圧力で行う、請求項１又は２に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1 or 2, wherein in the temporary crimping body pressurizing step, the temporary crimping body is pressurized at a pressure of 0.05 to 0.8 MPa.
  4. 　前記仮圧着体加圧工程において、前記仮圧着体の加圧を、前記接着剤の反応開始温度以上の温度で行う、請求項１～３のいずれか一項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein in the temporary crimping body pressurizing step, the temporary crimping body is pressurized at a temperature equal to or higher than the reaction start temperature of the adhesive.
  5. 　前記接着剤が、エポキシ樹脂、硬化剤及びフラックス剤を含有し、１５００Ｐａ・ｓ以下の最低溶融粘度を示し、且つ、１５０℃において３５秒以上８０秒以下のゲルタイムを示す、請求項１～４のいずれか一項に記載の半導体装置の製造方法。 Claims 1 to 4, wherein the adhesive contains an epoxy resin, a curing agent and a flux agent, exhibits a minimum melt viscosity of 1500 Pa · s or less, and exhibits a gel time of 35 seconds or more and 80 seconds or less at 150 ° C. The method for manufacturing a semiconductor device according to any one of the above.
  6. 　前記接着剤に含有される前記エポキシ樹脂の重量平均分子量が１００００未満である、請求項５に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 5, wherein the epoxy resin contained in the adhesive has a weight average molecular weight of less than 10,000.
  7. 　前記接着剤が高分子成分をさらに含有し、
    　前記高分子成分の重量平均分子量が１００００以上である、請求項５又は６に記載の半導体装置の製造方法。     The adhesive further contains a polymer component,
    The method for manufacturing a semiconductor device according to claim 5 or 6, wherein the polymer component has a weight average molecular weight of 10,000 or more.
  8. 　前記高分子成分の重量平均分子量が３００００以上であり、前記高分子成分のガラス転移温度が２００℃以下である、請求項７に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 7, wherein the polymer component has a weight average molecular weight of 30,000 or more and the glass transition temperature of the polymer component is 200 ° C. or less.
  9. 　前記接着剤がフィルム状接着剤である、請求項１～８のいずれか一項に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the adhesive is a film-like adhesive.
  10. 　請求項１～４のいずれか一項に記載の半導体装置の製造方法において前記第一の部材と前記第二の部材とを接着するために用いられる熱硬化性の接着剤。 A thermosetting adhesive used for adhering the first member and the second member in the method for manufacturing a semiconductor device according to any one of claims 1 to 4.
  11. 　エポキシ樹脂、硬化剤及びフラックス剤を含有し、
    　１５００Ｐａ・ｓ以下の最低溶融粘度を示し、且つ、１５０℃において３５秒以上８０秒以下のゲルタイムを示す、請求項１０に記載の接着剤。     Contains epoxy resin, curing agent and flux agent,
    The adhesive according to claim 10, which has a minimum melt viscosity of 1500 Pa · s or less and a gel time of 35 seconds or more and 80 seconds or less at 150 ° C.
  12. 　前記エポキシ樹脂の重量平均分子量が１００００未満である、請求項１１に記載の接着剤。 The adhesive according to claim 11, wherein the epoxy resin has a weight average molecular weight of less than 10,000.
  13. 　前記接着剤が高分子成分をさらに含有し、
    　前記高分子成分の重量平均分子量が１００００以上である、請求項１１又は１２に記載の接着剤。     The adhesive further contains a polymer component,
    The adhesive according to claim 11 or 12, wherein the polymer component has a weight average molecular weight of 10,000 or more.
  14. 　前記高分子成分の重量平均分子量が３００００以上であり、前記高分子成分のガラス転移温度が２００℃以下である、請求項１３に記載の接着剤。 The adhesive according to claim 13, wherein the polymer component has a weight average molecular weight of 30,000 or more and the glass transition temperature of the polymer component is 200 ° C. or less.
PCT/JP2021/029407 2020-11-13 2021-08-06 Semiconductor device manufacturing method and adhesive used therein WO2022102181A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020227006209A KR20230107467A (en) 2020-11-13 2021-08-06 Manufacturing method of semiconductor device and adhesive used therein
CN202180005952.0A CN116490583A (en) 2020-11-13 2021-08-06 Method for manufacturing semiconductor device and adhesive used for the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020189328A JP2022078574A (en) 2020-11-13 2020-11-13 Manufacturing method for semiconductor device and adhesive used for the same
JP2020-189328 2020-11-13

Publications (1)

Publication Number Publication Date
WO2022102181A1 true WO2022102181A1 (en) 2022-05-19

Family

ID=81601062

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2021/029407 WO2022102181A1 (en) 2020-11-13 2021-08-06 Semiconductor device manufacturing method and adhesive used therein

Country Status (5)

Country Link
JP (1) JP2022078574A (en)
KR (1) KR20230107467A (en)
CN (1) CN116490583A (en)
TW (1) TW202229493A (en)
WO (1) WO2022102181A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008144021A (en) * 2006-12-08 2008-06-26 Sekisui Chem Co Ltd Adhesive for joining semiconductor chip
JP2016072400A (en) * 2014-09-29 2016-05-09 積水化学工業株式会社 Semiconductor device manufacturing method
WO2018194156A1 (en) * 2017-04-21 2018-10-25 日立化成株式会社 Semiconductor device, and method for manufacturing same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7176532B2 (en) 2017-12-18 2022-11-22 昭和電工マテリアルズ株式会社 Semiconductor device, method for manufacturing semiconductor device, and adhesive

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008144021A (en) * 2006-12-08 2008-06-26 Sekisui Chem Co Ltd Adhesive for joining semiconductor chip
JP2016072400A (en) * 2014-09-29 2016-05-09 積水化学工業株式会社 Semiconductor device manufacturing method
WO2018194156A1 (en) * 2017-04-21 2018-10-25 日立化成株式会社 Semiconductor device, and method for manufacturing same

Also Published As

Publication number Publication date
TW202229493A (en) 2022-08-01
CN116490583A (en) 2023-07-25
JP2022078574A (en) 2022-05-25
KR20230107467A (en) 2023-07-17

Similar Documents

Publication Publication Date Title
WO2017073630A1 (en) Adhesive for semiconductor, semiconductor device, and method for manufacturing said device
WO2013125086A1 (en) Adhesive for semiconductor, fluxing agent, manufacturing method for semiconductor device, and semiconductor device
WO2013125684A1 (en) Semiconductor device and production method therefor
TWI721150B (en) Manufacturing method of semiconductor device
WO2013125685A1 (en) Semiconductor device and production method therefor
JP7196839B2 (en) Semiconductor film adhesive, film adhesive with substrate, method for producing film adhesive for semiconductor, method for producing semiconductor device, and semiconductor device
JP2024023787A (en) Method for manufacturing semiconductor device
KR102455212B1 (en) Semiconductor device, semiconductor device manufacturing method and adhesive
JP6859708B2 (en) How to manufacture semiconductor devices
JP7172167B2 (en) Semiconductor device manufacturing method and semiconductor adhesive used therefor
JP6544146B2 (en) Semiconductor device and method of manufacturing the same
WO2022102181A1 (en) Semiconductor device manufacturing method and adhesive used therein
JP7363798B2 (en) Semiconductor adhesive, semiconductor device manufacturing method, and semiconductor device
JP6690308B2 (en) Method for manufacturing semiconductor device
JP2019125691A (en) Manufacturing method of semiconductor device and adhesive for semiconductor
JP7238453B2 (en) Adhesive for semiconductor
WO2022024648A1 (en) Method for producing semiconductor device and film adhesive
JP7384171B2 (en) Film adhesive for semiconductors, semiconductor devices and manufacturing methods thereof
JP2019160839A (en) Semiconductor device and manufacturing method thereof
JP2022043572A (en) Semiconductor device manufacturing method

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 202180005952.0

Country of ref document: CN

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21891429

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21891429

Country of ref document: EP

Kind code of ref document: A1