WO2022062990A1 - 一种芯片封装结构及其制备方法、以及电子器件 - Google Patents

一种芯片封装结构及其制备方法、以及电子器件 Download PDF

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Publication number
WO2022062990A1
WO2022062990A1 PCT/CN2021/118483 CN2021118483W WO2022062990A1 WO 2022062990 A1 WO2022062990 A1 WO 2022062990A1 CN 2021118483 W CN2021118483 W CN 2021118483W WO 2022062990 A1 WO2022062990 A1 WO 2022062990A1
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WIPO (PCT)
Prior art keywords
components
plastic
substrate
group
level
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PCT/CN2021/118483
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English (en)
French (fr)
Inventor
陈建超
于上家
Original Assignee
青岛歌尔微电子研究院有限公司
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Publication of WO2022062990A1 publication Critical patent/WO2022062990A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present application relates to the technical field of semiconductor packaging structures, and in particular, to a chip packaging structure, a preparation method thereof, and an electronic device.
  • SIP package is one of the most important and most potential technologies to meet this high-density system integration.
  • SIP packaging refers to the integration of multiple functional wafers, including processors, memory and other functional wafers, into one package according to the application scenarios, the number of packaging substrate layers and other factors, so as to achieve a basically complete functional packaging solution.
  • the thickness of some components is much larger than other components, and the thickness of the final packaging structure depends on the thickness of the components, which often results in a waste of packaging structure space, which is not conducive to improving the system chip packaging.
  • the packing density of the structure is one of the most important and most potential technologies to meet this high-density system integration.
  • the main purpose of the present application is to propose a chip packaging structure, a preparation method thereof, and an electronic device, aiming at improving the space utilization rate of the system chip packaging structure and increasing the packaging density.
  • a chip packaging structure including:
  • the components include a first group of components and a second group of components, the first group of components and the second group of components are distributed on the mounting side at intervals, and the first group of components includes
  • the bottom-level components and the high-level components are sequentially arranged in the direction away from the substrate, and the height of the side of the high-level components facing the substrate relative to the substrate is lower than that of the second group of components relative to all the components. the height of the substrate;
  • a plastic packaging body is arranged on the installation side, the plastic packaging body includes a first plastic packaging body and a second plastic packaging body, the first plastic packaging body is arranged to surround the bottom element, and the second plastic packaging body is arranged to surround the high-level components and The second group of components is set.
  • the material of the first plastic package includes LDS material.
  • the underlying components include at least one of chips, resistors and capacitors; and/or,
  • the high-level components include at least one of chips, resistors and capacitors; and/or,
  • the second set of components includes at least one of an inductor and a crystal oscillator.
  • the first group of components is provided with multiple groups; and/or,
  • a connecting circuit is provided on the side of the first plastic package facing the high-level component, and the high-level component is provided on the connecting circuit.
  • the present application also proposes a preparation method of the above-mentioned chip packaging structure, comprising the following steps:
  • a substrate is provided, the substrate has a mounting side, and underlying components are arranged on the mounting side of the substrate;
  • a high-level component is arranged on the side of the first plastic package away from the substrate;
  • a second group of components is arranged on the mounting side of the substrate
  • the second group of components and the high-level components are plastic-encapsulated to form a second plastic package that simultaneously wraps the second group of components and the high-level components to obtain a chip package structure.
  • the step of disposing high-level components on the side of the first plastic package away from the substrate includes:
  • a connection circuit is provided on the side of the first plastic package away from the substrate;
  • connection circuit High-level components are arranged on the connection circuit.
  • the material of the first plastic-sealing body is LDS material
  • the step of disposing a connection circuit on the side of the first plastic package away from the substrate includes:
  • a mask is arranged on the side of the first plastic package away from the substrate, and then the exposed part of the surface of the first plastic package is activated and then the mask is removed;
  • a circuit is depicted on the surface of the activated first plastic package, and then a circuit layer is deposited on the surface of the first plastic package by means of electroless plating to form a connection circuit.
  • the mounting side of the substrate is further provided with conductive pads disposed adjacent to the underlying components;
  • the method further includes:
  • An opening is provided on a side of the first plastic package away from the substrate, and the opening communicates with the conduction pad;
  • a mask is arranged on the side of the first plastic package away from the substrate, and after the step of removing the mask after activating the exposed part of the surface of the first plastic package, after the activation of the first plastic package
  • a circuit is depicted on the surface of a plastic package, and then a circuit layer is deposited on the surface of the first plastic package by means of electroless plating, and before the step of forming a connecting circuit, the method further includes:
  • a conductive material is filled in the openings.
  • the surface of the conduction pad is provided with solder paste; and/or,
  • the conductive material is tin or silver.
  • this application also proposes an electronic device, including a chip packaging structure, and the chip packaging structure includes:
  • the components include a first group of components and a second group of components, the first group of components and the second group of components are distributed on the mounting side at intervals, and the first group of components includes
  • the bottom-level components and the high-level components are sequentially arranged in the direction away from the substrate, and the height of the side of the high-level components facing the substrate relative to the substrate is lower than that of the second group of components relative to all the components. the height of the substrate;
  • a plastic packaging body is arranged on the installation side, the plastic packaging body includes a first plastic packaging body and a second plastic packaging body, the first plastic packaging body is arranged to surround the bottom element, and the second plastic packaging body is arranged to surround the high-level components and The second group of components is set.
  • the chip packaging structure includes a substrate component and a plastic package, the component includes a first group of components and a second group of components, and the first group of components and the second group of components are spaced apart Distributed on the installation side of the substrate, the first group of components includes bottom-level components and high-level components arranged in sequence along the direction away from the substrate, and the high-level components are opposite to the side facing the substrate
  • the height of the substrate is lower than the height of the second group of components relative to the substrate;
  • the plastic packaging body is arranged on the installation side, and the plastic packaging body includes a first plastic packaging body and a second plastic packaging body, and the plastic packaging body includes a first plastic packaging body and a second plastic packaging body.
  • the first plastic sealing body is arranged to wrap around the bottom element, and the second plastic sealing body is arranged to surround the high-level element and the second group of components.
  • the packaging space is fully utilized, the space utilization rate of the packaging structure is improved, more components can be integrated in the same space, the packaging density is improved, the chip integration degree of the SIP packaging is improved, and it is more conducive to realize the system chip packaging. Higher density requirements and more diversity requirements.
  • FIG. 1 is a schematic structural diagram of an embodiment of a chip packaging structure provided by the present application.
  • FIG. 2 is a schematic flowchart of an embodiment of a method for manufacturing a chip packaging structure provided by the present application
  • FIG. 3 is a schematic view of the structure after the underlying components are arranged on the substrate in FIG. 2;
  • FIG. 4 is a schematic view of the structure after solder paste is arranged on the conduction pad of the substrate in FIG. 2;
  • FIG. 5 is a schematic structural diagram after the first plastic sealing body is arranged in FIG. 2;
  • Fig. 6 is the structural representation after setting the opening in Fig. 2;
  • Fig. 7 is the structural schematic diagram after setting the mask in Fig. 2;
  • FIG. 8 is a schematic view of the structure after the circuit is depicted on the surface of the first plastic package in FIG. 2;
  • FIG. 9 is a schematic view of the structure of FIG. 2 after the conductive material is filled in the opening;
  • FIG. 10 is a schematic structural diagram of the connection circuit provided on the surface of the first plastic package in FIG. 2;
  • FIG. 11 is a schematic structural diagram after the high-level components are arranged in FIG. 2;
  • FIG. 12 is a schematic view of the structure after solder paste is arranged on the pads of the substrate in FIG. 2;
  • FIG. 13 is a schematic structural diagram of the second group of components in FIG. 2 after being arranged.
  • the existing packaging method usually firstly arranges the components that need to be arranged on the substrate, and then performs the overall plastic packaging, and the plastic packaging body wraps all the components on the substrate at the same time, forming the first element device layer, and then set a transfer substrate on the plastic package, arrange another layer of components on the transfer substrate, and then plastic-encapsulate it as a whole to form a plastic package that completely covers the surface of the first component layer, forming a second component layer , for this method, whether it is the first component layer or the second component layer, the thickness of some components is much larger than other components, and the final package thickness of each layer depends on the thickness of the layer. components, which often results in a waste of packaging structure space, which is not conducive to improving the packaging density of the system chip packaging structure.
  • the present application proposes a chip packaging structure
  • FIG. 1 shows an embodiment of the chip packaging structure 100 proposed in the present application.
  • the chip package structure 100 includes a substrate 10 (usually a PCB board, that is, a printed circuit board, which is well known to those skilled in the art and will not be described here), components and a plastic package, wherein the substrate 10 has a mounting side; the components include a first group of components and a second group of components 30, and the first group of components and the second group of components 30 are spaced apart from each other.
  • a substrate 10 usually a PCB board, that is, a printed circuit board, which is well known to those skilled in the art and will not be described here
  • the substrate 10 has a mounting side
  • the components include a first group of components and a second group of components 30, and the first group of components and the second group of components 30 are spaced apart from each other.
  • the first group of components includes bottom-level components 21 and high-level components 22 arranged in sequence in a direction away from the substrate 10 , and the high-level components 22 are opposite to the side facing the substrate 10 .
  • the height of the substrate 10 is lower than the height of the second group of components 30 relative to the substrate 10 ;
  • the plastic packaging body is disposed on the mounting side, and the plastic packaging body includes a first plastic packaging body 41 and a second plastic packaging body
  • the plastic sealing body 42, the first plastic sealing body 41 is arranged to wrap the bottom element, and the second plastic sealing body 42 is arranged to surround the high-level element and the second group of components 30.
  • the chip package structure 100 includes components on the substrate 10 and a plastic package, and the components include a first group of components and a second group of components 30 .
  • the first group of components and the second group of components The components 30 are distributed at intervals on the mounting side of the substrate 10 , and the first group of components includes bottom-level components 21 and high-level components 22 arranged in sequence along the direction away from the substrate 10 .
  • the high-level components 22 The high-level components 22.
  • the height of the side facing the substrate 10 relative to the substrate 10 is lower than the height of the second group of components 30;
  • the plastic packaging body is arranged on the installation side, and the plastic packaging body includes a first plastic packaging body 41 and a second plastic sealing body 42 , the first plastic sealing body 41 is arranged to wrap the bottom element, and the second plastic body 42 is arranged to surround the high-level element and the second group of components 30 .
  • the height space of the second group of components 30 in the package structure is fully utilized, thus improving the package structure Space utilization, more components can be integrated in the same space, the packaging density is improved, and the chip integration degree of SIP packaging is improved, which is more conducive to the realization of higher density requirements and more diversified requirements of system chip packaging.
  • the first group of components are some components with relatively small thickness, including chips and passive components, such as resistors, capacitors, etc.
  • the bottom layer components 21 include chips, resistors and capacitors and/or
  • the high-level component 22 includes at least one of a chip, a resistor and a capacitor
  • the specific component type can be selected according to the actual structural requirements of the chip package structure 100 .
  • the number of the first group of components is not limited, and may be multiple groups or multiple groups. In this embodiment, there are multiple groups. Referring to FIG. 1, the first component The device is provided with two groups as an example. The two groups of the first group of components are respectively arranged on opposite sides of the second group of components 30.
  • the first plastic body 41 is also provided with two , the two first plastic encapsulation bodies 41 are respectively arranged to wrap the bottom layer components 21 in the two groups of the first group components, wherein the bottom layer components 21 in the first group components are chips,
  • the bottom component 21 of the other set of said first set of components includes resistors and capacitors.
  • multiple groups of the first group of components may also be arranged on the same side of the second group of components 30 at intervals.
  • the second group of components 30 are some components with larger thickness, such as inductors, crystal oscillators, etc.
  • the second group of components 30 includes at least one of an inductor and a crystal oscillator.
  • the number of the second group of components 30 is also not limited, and may be one group or multiple groups. In FIG. 1, only one group of the second group of components 30 in this embodiment is provided, and the The second group of components 30 includes either an inductor or a crystal oscillator as an example for illustration, and is not intended to limit the scope of protection of the present application.
  • the plastic packaging body includes a first plastic packaging body 41 arranged to wrap the bottom-level components 21, and a second plastic packaging body 41 arranged to surround the high-level components 22 and the second group of components 30 at the same time.
  • the plastic sealing body 42 belongs to the protection scope of the present application.
  • a side of the first plastic package 41 facing the high-level component 22 is provided with a connection circuit 50 , and the high-level component 22 is provided on the connection circuit 50 .
  • the connection circuit 50 can be realized by using a transfer substrate, and as a preferred implementation manner, in this embodiment, the material of the first plastic package 41 includes LDS material.
  • LDS material is a modified plastic containing organometallic complexes. After the material is irradiated by laser, metal particles can be released from the organometallic complexes in the material.
  • the material of the second plastic sealing body 42 is not limited, and the above-mentioned LDS material can also be used, and the conventional plastic sealing material in the field can also be used. More preferably, the second plastic sealing body 42 is also made of the above-mentioned LDS material. , a circuit layer can be formed directly on the surface of the second plastic package 42 by chemical deposition, which saves the transfer substrate and also helps to reduce the thickness of the chip package structure 100 .
  • FIG. 2 shows an embodiment of the method for manufacturing the chip package structure 100 provided by the present application.
  • the manufacturing method of the chip package structure 100 includes the following steps:
  • Step S10 providing a substrate 10 , the substrate 10 has a mounting side, and a bottom layer component 21 is arranged on the mounting side of the substrate 10 ;
  • the substrate 10 can be a pre-processed PCB board, or can be made from a wafer as a raw material.
  • the preparation process is as follows: firstly, the raw wafer is thinned to a corresponding thickness by back grinding, and then the backside of the wafer is thinned to a corresponding thickness.
  • an insulating layer such as silicon oxide or silicon nitride, or set an insulating layer on the back of the wafer by direct thermal oxidation, and then cut the wafer into chips, and then pass the patch, curing, wire bonding, flip chip, reflow soldering, cleaning , underfill and other processes, use low-thickness components, including chips and passive components (such as resistors and capacitors, etc.) as the underlying components 21, and mount them on the mounting side of the substrate 10, as shown in FIG. 3. Structure.
  • an insulating layer such as silicon oxide or silicon nitride, or set an insulating layer on the back of the wafer by direct thermal oxidation, and then cut the wafer into chips, and then pass the patch, curing, wire bonding, flip chip, reflow soldering, cleaning , underfill and other processes, use low-thickness components, including chips and passive components (such as resistors and capacitors, etc.) as the underlying components 21, and mount them on the mounting side of the substrate 10,
  • Step S20 plastic-sealing the bottom-layer components 21 to form a first plastic-sealing body 41 arranged to wrap the bottom-layer components 21 ;
  • the structure obtained in FIG. 3 is partially plastic-sealed for the first time to form a first plastic-encapsulated body 41 that wraps the bottom layer components 21.
  • the bottom layer components 21 are also formed. If there are multiple groups, each group of the bottom layer components 21 is partially plastic-sealed to form a plurality of the first plastic seal bodies 41 , and each of the first plastic seal bodies 41 corresponds to a group of the bottom layer components. 21 , that is, forming a plastic sealing body in a special shape on the mounting side of the substrate 10 to obtain the structure shown in FIG. 5 .
  • Step S30 disposing high-level components 22 on the side of the first plastic package 41 away from the substrate 10;
  • Step S30 specifically includes:
  • Step S31 providing a connection circuit 50 on the side of the first plastic package 41 away from the substrate 10 ;
  • Step S32 setting the high-level components 22 on the connection circuit 50 .
  • a connecting circuit 50 is disposed on the side of the first plastic package 41 away from the substrate 10 , and then a second mounting is performed on the connecting circuit 50 to obtain the structure shown in FIG. 11 , and the high-level element is completed.
  • the connection circuit 50 can be set by selecting a transfer substrate.
  • the material of the first plastic sealing body 41 is LDS material.
  • step S31 includes:
  • Step S31b setting a mask 60 on the side of the first plastic body 41 away from the substrate 10, and then activating the exposed part of the surface of the first plastic body 41 and removing the mask 60;
  • step S31d a circuit is drawn on the surface of the activated first plastic package 41 , and then a circuit layer is deposited on the surface of the first plastic package 41 by electroless plating to form a connection circuit 50 .
  • first plastic package 41 Apply a mask 60 on the side of the first plastic package 41 away from the substrate 10 (as shown in FIG. 7 ), then use laser to activate the exposed part of the surface of the first plastic package 41 , and use laser irradiation to activate
  • the organometallic compound in the LDS material releases metal particles, thereby forming a conductive seed layer on the surface of the first plastic package 41, then removing the mask 60, and using a laser or other conventional methods
  • the required circuit is engraved on the surface of the first plastic package 41 to obtain the structure as shown in FIG. 8 , and finally a circuit is deposited on the surface of the first plastic package 41 after activation and engraved with the circuit by electroless plating. layer to form the connection circuit 50 to obtain the structure shown in FIG. 10 .
  • the LDS material as the material for making the first plastic sealing body 41 , after the surface of the first plastic sealing body 41 is activated, the surface of the first plastic sealing body 41 is directly processed by chemical
  • the circuit layer is deposited by plating to form the connection circuit 50, thereby eliminating the need for the setting of the transfer substrate, not only saving the transfer substrate, but also because the thickness of the circuit layer formed by chemical deposition is significantly smaller than the thickness of the transfer substrate, which is beneficial to The thickness of the chip package structure 100 is reduced.
  • the high-level components 22 may be electrically connected to the substrate 10 or may not be electrically connected, and the specific setting method may be selected according to the actual requirements of the chip packaging structure 100 .
  • the high-level components 22 in at least one group of the first group of components are set to be electrically connected to the substrate 10 as an example for description.
  • the mounting side of the substrate 10 There is also a conduction pad 71 disposed adjacent to the bottom layer component 21.
  • step S31a an opening 411 is provided on the side of the first plastic package 41 away from the substrate 10, and the opening 411 communicates with the conductive pad 71;
  • step S31b and before step S31d it also includes:
  • Step S31c filling the opening 411 with a conductive material.
  • an opening 411 is provided on the side of the first plastic sealing body 41 away from the substrate 10 by means of laser or machining. As shown in FIG. 6 , the opening The holes 411 are connected to the conductive pads 71, and then the surface of the first plastic package 41 is activated and the circuit is drawn. After the circuit is drawn, the openings 411 are filled with conductive materials, as shown in Figure 9. As shown in the conductive connection portion 90 , a circuit layer is then disposed on the surface of the first plastic package 41 by chemical deposition to form the connection circuit 50 . In this way, the high-level component 22 is electrically connected to the substrate 10 through the connection circuit 50 and the conductive connection portion 90 .
  • the conductive material can be selected from tin, silver, copper, etc., preferably tin or silver, which has good conductivity and convenient filling process. Then reflow or bake is performed to cure the conductive material.
  • the surface of the conductive pad 71 is preferably provided with solder paste 80.
  • solder paste 80 is placed on the conductive pads 71 provided on the substrate 10 adjacent to the underlying components 21 to obtain as shown in FIG. 4 , the solder paste 80 can be set by using a dispensing device to place solder paste on the conduction pad 71 , or directly printing the solder paste on the conduction pad 71 by cleaning paste printing. on pad 71.
  • Step S40 disposing a second group of components 30 on the mounting side of the substrate 10;
  • a second group of components 30 with high thickness are mounted on the mounting side of the substrate 10.
  • the specific mounting method may be as follows: the mounting side is also provided with a second set of components for mounting the first A plurality of pads 72 of the second group of components 30 are provided with solder paste 80 on the pads 72 (the setting method of the solder paste 80 is referred to above, and will not be repeated here), and the structure shown in FIG. 12 is obtained. Then, after the second group of components 30 are mounted, the solder paste 80 is cured by reflow or baking to obtain the structure shown in FIG. 13 , and the mounting of the second group of components 30 is completed.
  • Step S50 plastic-encapsulating the second group of components 30 and the high-level components 22 to form a second plastic package 42 that encapsulates the second group of components 30 and the high-level components 22 at the same time, thereby obtaining the chip package structure 100 .
  • a second plastic sealing is performed to form a second plastic package 42 that wraps the second group of components 30 and the high-level components 22 at the same time, as shown in the figure.
  • the material of the second plastic sealing body 42 is not limited.
  • the LDS material can also be used, or the conventional plastic sealing material in the field. More preferably, the second plastic sealing body 42 is also made of the LDS material. In this way, the circuit layer can be directly formed on the surface of the second plastic package 42 by chemical deposition, which saves the transfer substrate and further reduces the thickness of the chip package structure 100 .
  • the order of the mounting steps of the high-level components 22 and the mounting steps of the second group of components 30 is not limited, and the high-level components 22 may be performed first.
  • the placement of the second group of components 30 is performed first, and the placement of the second group of components 30 may be performed first, followed by the placement of the high-level components 22, or it may be
  • the placement of the high-level components 22 and the second group of components 30 is performed simultaneously, and it is only necessary to complete the high-level components respectively after the setting of the first plastic package 41 is completed and before the second plastic package is performed. 22 and the mounting of the second group of components 30 are sufficient.
  • the preparation method of the chip packaging structure 100 provided by the present application has a simple preparation process, is easy to perform quantitative production, and can be applied to stacked integrated packaging of different types of chips. In this way, the space utilization rate of the chip packaging structure 100 is improved, the packaging density is improved, more components can be integrated in the same space, the chip integration degree of the system chip packaging is improved, and the transfer substrate is saved, which is conducive to the realization of the system. Higher density requirements and more diversified requirements for chip packaging.
  • the present application also proposes an electronic device, including a chip package structure 100 , and the structure of the chip package structure 100 refers to the above-mentioned embodiments. It can be understood that, since the electronic device of the present application adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

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Abstract

本申请公开一种芯片封装结构及其制备方法、以及电子器件，所述芯片封装结构包括基板、元器件以及塑封体，元器件包括第一组元器件和第二组元器件，第一组元器件和第二组元器件间隔分布于基板的安装侧，第一组元器件包括沿远离基板的方向上依次排布的底层元器件和高层元器件，高层元器件朝向基板的一侧相对于基板的高度低于第二组元器件的高度；塑封体设于基板的安装侧，塑封体包括第一塑封体和第二塑封体，第一塑封体包裹底层元件设置，第二塑封体包裹高层元件和所述第二组元器件设置。

Description

一种芯片封装结构及其制备方法、以及电子器件
本申请要求于2020年9月28日提交中国专利局、申请号为202011048066.X、申请名称为“一种芯片封装结构及其制备方法、以及电子器件”的中国专利申请的优先权，其全部内容通过引用结合在申请中。
技术领域
本申请涉及半导体封装结构技术领域，具体涉及一种芯片封装结构及其制备方法、以及电子器件。
 背景技术
电子产品的迅猛发展是当今封装技术进化的主要驱动力，小型化、高密度、高频高速、高性能、高可靠性和低成本是先进封装的主流发展方向，其中***级封装（System In a Package，SIP封装）是最重要也是最有潜力满足这种高密度***集成的技术之一。SIP封装是指将多种功能晶圆，包括处理器、存储器等功能晶圆根据应用场景、封装基板层数等因素，集成在一个封装内，从而实现一个基本完整功能的封装方案。在实际封装过程中，部分元器件的厚度远大于其他元器件，最终封装结构的厚度尺寸取决于该厚度较大的元器件，这样往往会造成封装结构空间上的浪费，不利于提高***芯片封装结构的封装密度。
 技术问题
本申请的主要目的是提出一种芯片封装结构及其制备方法、以及电子器件，旨在提高***芯片封装结构的空间利用率，提高封装密度。
 技术解决方案
为实现上述目的，本申请提出一种芯片封装结构，包括：
基板，所述基板具有安装侧；
元器件，所述元器件包括第一组元器件和第二组元器件，所述第一组元器件和第二组元器件间隔分布于所述安装侧，所述第一组元器件包括沿远离所述基板的方向上依次排布的底层元器件和高层元器件，所述高层元器件朝向所述基板的一侧相对于所述基板的高度低于所述第二组元器件相对于所述基板的高度；以及，
塑封体，设于所述安装侧，所述塑封体包括第一塑封体和第二塑封体，所述第一塑封体包裹所述底层元件设置，所述第二塑封体包裹所述高层元件和所述第二组元器件设置。
在一实施例中，所述第一塑封体的材质包括LDS材料。
在一实施例中，所述底层元器件包括芯片、电阻器和电容器中的至少一种；和/或，
所述高层元器件包括芯片、电阻器和电容器中的至少一种；和/或，
所述第二组元器件包括电感器和晶体振荡器中的至少一种。
在一实施例中，所述第一组元器件设置有多组；和/或，
所述第一塑封体朝向所述高层元器件的一侧设有连接电路，所述高层元器件设于所述连接电路上。
进一步地，本申请还提出一种如上所述的芯片封装结构的制备方法，包括以下步骤：
提供一基板，所述基板具有安装侧，在所述基板的安装侧设置底层元器件；
对所述底层元器件进行塑封，形成包裹所述底层元器件设置的第一塑封体；
在所述第一塑封体远离所述基板的一侧设置高层元器件；
在所述基板的安装侧设置第二组元器件；
对所述第二组元器件和高层元器件进行塑封，形成同时包裹所述第二组元器件和高层元器件设置的第二塑封体，得到芯片封装结构。
在一实施例中，在所述第一塑封体远离所述基板的一侧设置高层元器件的步骤，包括：
在所述第一塑封体远离所述基板的一侧设置连接电路；
在所述连接电路上设置高层元器件。
在一实施例中，对所述底层元器件进行塑封，形成包裹所述底层元器件设置的第一塑封体的步骤中：所述第一塑封体的材质为LDS材料；
在所述第一塑封体远离所述基板的一侧设置连接电路的步骤包括：
在所述第一塑封体远离所述基板的一侧设置掩膜，然后对暴露出的部分所述第一塑封体表面进行活化后去掉所述掩膜；
在活化后的所述第一塑封体表面刻画电路，然后通过化学镀的方式在所述第一塑封体的表面沉积电路层，形成连接电路。
在一实施例中，所述基板的安装侧还设有邻近所述底层元器件设置的导通焊盘；
对所述底层元器件进行塑封，形成包裹所述底层元器件设置的第一塑封体的步骤之后、在所述第一塑封体远离所述基板的一侧设置掩膜，然后对暴露出的部分所述第一塑封体表面进行活化后去掉掩膜的步骤之前，还包括：
在所述第一塑封体远离所述基板的一侧设置开孔，所述开孔连通所述导通焊盘；
在所述第一塑封体远离所述基板的一侧设置掩膜，然后对暴露出的部分所述第一塑封体表面进行活化后去掉所述掩膜的步骤之后、在活化后的所述第一塑封体表面刻画电路，然后通过化学镀的方式在所述第一塑封体的表面沉积电路层，形成连接电路的步骤之前，还包括：
在所述开孔内填充导电材料。
在一实施例中，所述导通焊盘的表面设置有锡膏；和/或，
所述导电材料为锡或银。
此外，本申请还提出一种电子器件，包括芯片封装结构，所述芯片封装结构包括：
基板，所述基板具有安装侧；
元器件，所述元器件包括第一组元器件和第二组元器件，所述第一组元器件和第二组元器件间隔分布于所述安装侧，所述第一组元器件包括沿远离所述基板的方向上依次排布的底层元器件和高层元器件，所述高层元器件朝向所述基板的一侧相对于所述基板的高度低于所述第二组元器件相对于所述基板的高度；以及，
塑封体，设于所述安装侧，所述塑封体包括第一塑封体和第二塑封体，所述第一塑封体包裹所述底层元件设置，所述第二塑封体包裹所述高层元件和所述第二组元器件设置。
 有益效果
本申请提供的技术方案中，芯片封装结构包括基板元器件以及塑封体，所述元器件包括第一组元器件和第二组元器件，所述第一组元器件和第二组元器件间隔分布于所述基板的安装侧，所述第一组元器件包括沿远离所述基板的方向上依次排布的底层元器件和高层元器件，所述高层元器件朝向所述基板的一侧相对于所述基板的高度低于所述第二组元器件相对于所述基板的高度；所述塑封体设于所述安装侧，所述塑封体包括第一塑封体和第二塑封体，所述第一塑封体包裹所述底层元件设置，所述第二塑封体包裹所述高层元件和所述第二组元器件设置。如此，充分利用了封装空间，提高了封装结构的空间利用率，相同空间内可以集成更多的元器件，提升了封装密度，提高了SIP封装的芯片集成度，更有利于实现***芯片封装的更高密度要求和更加多元化要求。
 附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅为本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请提供的芯片封装结构的一实施例的结构示意图；
图2为本申请提供的芯片封装结构的制备方法的一实施例的流程示意图；
图3为图2中在基板上设置底层元器件后的结构示意图；
图4为图2中在基板的导通焊盘上设置锡膏后的结构示意图；
图5为图2中设置第一塑封体后的结构示意图；
图6为图2中设置开孔后的结构示意图；
图7为图2中设置掩膜后的结构示意图；
图8为图2中在第一塑封体表面刻画电路后的结构示意图；
图9为图2中在开孔内填充导电材料后的结构示意图；
图10为图2中在第一塑封体表面设置连接电路后的结构示意图；
图11为图2中设置高层元器件后的结构示意图；
图12为图2中在基板的焊盘上设置锡膏后的结构示意图；
图13为图2中设置第二组元器件后的结构示意图。
附图标号说明：
100 芯片封装结构 42 第二塑封体
10 基板 50 连接电路
21 底层元器件 60 掩膜
22 高层元器件 71 导通焊盘
30 第二组元器件 72 焊盘
41 第一塑封体 80 锡膏
411 开孔 90 导电连接部
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
 本发明的实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将对本申请实施例中的技术方案进行清楚、完整地描述。实施例中未注明具体条件者，按照常规条件或制造商建议的条件进行。所用试剂或仪器未注明生产厂商者，均为可以通过市售购买获得的常规产品。另外，全文中出现的“和/或”的含义，包括三个并列的方案，以“A和/或B”为例，包括A方案、或B方案、或A和B同时满足的方案。此外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在SIP封装芯片的实际封装过程中，现有封装方式通常是先将需要设置于基板上的元器件都布设完成之后，进行整体塑封，塑封体同时包裹基板上的所有元器件，形成第一元器件层，然后再在该塑封体上设置转载基板，在该转载基板上布设另一层元器件后再整体塑封，形成完全覆盖在第一元器件层表面的塑封体，形成第二元器件层，对于此种方式而言，无论是第一元器件层还是第二元器件层，其中部分元器件的厚度远大于其他元器件，每一层的最终封装厚度尺寸取决于该层厚度较大的元器件，这样往往会造成封装结构空间上的浪费，不利于提高***芯片封装结构的封装密度。
鉴于此，本申请提出一种芯片封装结构，图1所示为本申请提出的芯片封装结构100的一实施例。参阅图1所示，在本实施例中，所述芯片封装结构100包括基板10（通常为PCB板，即印制电路板，为本领域技术人员所熟知，在此不做赘述）、元器件以及塑封体，其中，所述基板10具有安装侧；所述元器件包括第一组元器件和第二组元器件30，所述第一组元器件和第二组元器件30间隔分布于所述安装侧，所述第一组元器件包括沿远离所述基板10的方向上依次排布的底层元器件21和高层元器件22，所述高层元器件22朝向所述基板10的一侧相对于所述基板10的高度低于所述第二组元器件30相对于所述基板10的高度；所述塑封体设于所述安装侧，所述塑封体包括第一塑封体41和第二塑封体42，所述第一塑封体41包裹所述底层元件设置，所述第二塑封体42包裹所述高层元件和所述第二组元器件30设置。
本申请提供的技术方案中，芯片封装结构100包括基板10元器件以及塑封体，所述元器件包括第一组元器件和第二组元器件30，所述第一组元器件和第二组元器件30间隔分布于所述基板10的安装侧，所述第一组元器件包括沿远离所述基板10的方向上依次排布的底层元器件21和高层元器件22，所述高层元器件22朝向所述基板10的一侧相对于所述基板10的高度低于所述第二组元器件30的高度；所述塑封体设于所述安装侧，所述塑封体包括第一塑封体41和第二塑封体42，所述第一塑封体41包裹所述底层元件设置，所述第二塑封体42包裹所述高层元件和所述第二组元器件30设置。通过在所述基板10的安装侧叠设所述底层元器件21和高层元器件22的方式，充分利用了封装结构中所述第二组元器件30的高度空间，如此，提高了封装结构的空间利用率，相同空间内可以集成更多的元器件，提升了封装密度，提高了SIP封装的芯片集成度，更有利于实现***芯片封装的更高密度要求和更加多元化要求。
所述第一组元器件为厚度相对较小的一些元器件，包括芯片以及被动元器件，例如电阻器、电容器等，在本实施例中，所述底层元器件21包括芯片、电阻器和电容器中的至少一种；和/或，所述高层元器件22包括芯片、电阻器和电容器中的至少一种，具体的元器件类型可以根据所述芯片封装结构100的实际结构需求进行选择。进一步地，所述第一组元器件的个数不做限制，可以是多组也可以是多组，在本实施例中设置有多组，参阅图1所示，以所述第一组元器件设置有两组为例进行说明，两组所述第一组元器件分别布设于所述第二组元器件30的相对两侧，对应地，所述第一塑封体41也设置有两个，两个所述第一塑封体41分别包裹两组所述第一组元器件中的所述底层元器件21设置，其中一组所述第一组元器件中的底层元器件21为芯片，另一组所述第一组元器件中的底层元器件21包括电阻器和电容器。在本申请的其他实施例中，也可以是多组所述第一组元器件间隔布设于所述第二组元器件30的同一侧。
所述第二组元器件30为厚度较大的一些元器件，例如电感器、晶体振荡器等，在本实施例中，所述第二组元器件30包括电感器和晶体振荡器中的至少一种。所述第二组元器件30的个数也不做限制，可以是一组也可以是多组，图1中仅以本实施例的所述第二组元器件30设置有一组，且所述第二组元器件30包括电感器和晶体振荡器中的任意一种为例进行说明，并不用于限定本申请的保护范围，凡是所述第一组元器件设置有所述底层元器件21和所述高层元器件22，且所述塑封体包括包裹所述底层元器件21设置的第一塑封体41、以及同时包裹所述高层元器件22和所述第二组元器件30设置的第二塑封体42，均属于本申请的保护范围。
在本实施例中，参阅图1所示，所述第一塑封体41朝向所述高层元器件22的一侧设有连接电路50，所述高层元器件22设于所述连接电路50上。进一步地，所述连接电路50可以采用转载基板实现，而作为一种优选的实施方式，在本实施例中，所述第一塑封体41的材质包括LDS材料。LDS材料是一种内含有机金属复合物的改性塑料，该材料经过激光照射后，可以使其中的有机金属复合物释放出金属粒子，通过选用上述LDS材料作为制作所述第一塑封体41的材料，从而使得对所述第一塑封体41的表面进行活化处理后，直接在所述第一塑封体41的表面通过化学镀的方式沉积电路层，形成所述连接电路50，从而省去了转载基板的设置，不仅节约了转载基板，且由于通过化学沉积形成的电路层的厚度小于转载基板的厚度，从而有利于减小所述芯片封装结构100的厚度。此外，所述第二塑封体42的材质不做限制，可以采用上述LDS材料，也可以采用本领域常规的塑封材料，更优选为所述第二塑封体42也选用上述LDS材料制成，如此，可以直接在所述第二塑封体42的表面通过化学沉积形成电路层，节约了转载基板，也有利于减少所述芯片封装结构100的厚度。
基于上述芯片封装结构100，本申请还提出一种芯片封装结构100的制备方法，图2所示为本申请提供的芯片封装结构100的制备方法的一实施例。参阅图2所示，在本实施例中，所述芯片封装结构100的制备方法包括以下步骤：
步骤S10、提供一基板10，所述基板10具有安装侧，在所述基板10的安装侧设置底层元器件21；
所述基板10可以是已经经过预加工得到的PCB板，也可以是以晶圆为原材料制得，其制备流程如下：首先通过背部研磨将原料晶圆减薄到相应厚度，然后在晶圆背部沉积氧化硅或氮化硅等绝缘层，或者通过直接热氧化的方式在晶圆背部设置绝缘层，再将晶圆切割成芯片，通过贴片、固化、焊线、倒装、回流焊、清洗、底部填充等工艺，将低厚度的元器件，包括芯片以及被动元器件（例如电阻器和电容器等）作为底层元器件21，贴装在所述基板10的安装侧，得到如图3所示的结构。
步骤S20、对所述底层元器件21进行塑封，形成包裹所述底层元器件21设置的第一塑封体41；
对图3得到的结构进行第一次局部塑封，形成包裹所述底层元器件21设置的第一塑封体41，当所述第一组元器件设置有多组时，所述底层元器件21也设置有多组，则对每一组所述底层元器件21均进行局部塑封，形成多个所述第一塑封体41，每一所述第一塑封体41对应包裹一组所述底层元器件21，即在所述基板10的安装侧形成呈异形设置的塑封体，得到如图5所示的结构。
步骤S30、在所述第一塑封体41远离所述基板10的一侧设置高层元器件22；
所述第一塑封体41设置完毕后，将被动元器件例如电阻器或电容器等作为所高层元器件22，设置于所述第一塑封体41远离所述基板10的一侧。优选地，在本实施例中，所述第一塑封体41朝向所述高层元器件22的一侧设有连接电路50，所述高层元器件22设于所述连接电路50上，对应地，步骤S30具体包括：
步骤S31、在所述第一塑封体41远离所述基板10的一侧设置连接电路50；
步骤S32、在所述连接电路50上设置高层元器件22。
先在所述第一塑封体41远离所述基板10的一侧设置连接电路50，然后再在所述连接电路50上进行第二次贴装，得到如图11所示的结构，完成高层元器件22的设置。其中，所述连接电路50可以选用转载基板进行设置，作为一优选的实施方式，在本实施例中，所述第一塑封体41的材质为LDS材料，对应地，步骤S31包括：
步骤S31b、在所述第一塑封体41远离所述基板10的一侧设置掩膜60，然后对暴露出的部分所述第一塑封体41表面进行活化后去掉所述掩膜60；
步骤S31d、在活化后的所述第一塑封体41表面刻画电路，然后通过化学镀的方式在所述第一塑封体41的表面沉积电路层，形成连接电路50。
先在所述第一塑封体41远离所述基板10的一侧施加掩膜60（如图7所示），然后采用激光活化暴露出的部分所述第一塑封体41表面，利用激光照射激发出所述LDS材料中的有机金属复合物释放出金属粒子，从而在所述第一塑封体41的表面形成导电种子层，然后去掉掩膜60，并利用镭射激光或其他本领常规的方式将所需的电路刻画在所述第一塑封体41的表面，得到如图8所示的结构，最后再通过化学镀的方式在活化后且刻画有电路的所述第一塑封体41的表面沉积电路层，形成所述连接电路50，得到如图10所示的结构。如此，通过选用所述LDS材料作为制作所述第一塑封体41的材料，从而使得对所述第一塑封体41的表面进行活化处理后，直接在所述第一塑封体41的表面通过化学镀的方式沉积电路层，形成所述连接电路50，从而省去了转载基板的设置，不仅节约了转载基板，且由于通过化学沉积形成的电路层的厚度明显小于转载基板的厚度，从而有利于减小所述芯片封装结构100的厚度。
所述高层元器件22可以与所述基板10导通，也可以不导通，具体设置方式可以根据所述芯片封装结构100的实际需求进行选择。在本实施例中，以至少一组所述第一组元器件中的高层元器件22设置为与所述基板10导通为例进行说明，参阅图4所示，所述基板10的安装侧还设有邻近所述底层元器件21设置的导通焊盘71，对应地，在本实施例中，步骤S20之后、步骤S31b之前，还包括：
步骤S31a、在所述第一塑封体41远离所述基板10的一侧设置开孔411，所述开孔411连通所述导通焊盘71；
且在步骤S31b之后、步骤S31d之前，还包括：
步骤S31c、在所述开孔411内填充导电材料。
在完成所述第一塑封体41的设置之后，通过激光或机械加工等方式在所述第一塑封体41远离所述基板10的一侧设置开孔411，如图6所示，所述开孔411连通所述导通焊盘71，然后再对所述第一塑封体41的表面进行活化处理和刻画电路，电路刻画完毕后，在所述开孔411中填充导电材料，形成如图9所示的导电连接部90，然后在所述第一塑封体41表面通过化学沉积设置电路层，形成所述连接电路50。如此，所述高层元器件22通过所述连接电路50以及所述导电连接部90与所述基板10导通。其中，所述导电材料可以选用锡、银或铜等，优选为锡或银，导电性能好且填充工艺较为方便，具体工艺可以是在所述开孔411中灌入锡膏80或者银浆，然后进行回流或者烘烤实现导电材料固化。
此外，为避免在步骤S31a中进行开孔411时损伤所述导通焊盘71或者基板10，在本实施例中优选为所述导通焊盘71的表面设置有锡膏80，具体地，在完成所述底层元器件21的贴装，得到如图3所示的结构之后，再在所述基板10上邻近所述底层元器件21设置的导通焊盘71上设置锡膏80，得到如图4的结构，所述锡膏80的设置方式可以是利用点胶设备在所述导通焊盘71上点设锡膏，也可以直接通过洗膏印刷将锡膏印刷在所述导通焊盘71上。
步骤S40、在所述基板10的安装侧设置第二组元器件30；
第二次贴装完毕后，再在所述基板10的安装侧贴装高厚度的第二组元器件30，其具体贴装方式可以为：所述安装侧还设有用以贴装所述第二组元器件30的多个焊盘72，在所述焊盘72上设置锡膏80（所述锡膏80的设置方式参考上述，在此不做赘述），得到如图12所示的结构，然后贴装所述第二组元器件30后，通过回流或烘烤实现锡膏80固化，得到如图13所示的结构，完成所述第二组元器件30的贴装。
步骤S50、对所述第二组元器件30和高层元器件22进行塑封，形成同时包裹所述第二组元器件30和高层元器件22设置的第二塑封体42，得到芯片封装结构100。
在所述第二组元器件30贴装完毕后，再进行第二次塑封，形成同时包裹所述第二组元器件30和高层元器件22设置的第二塑封体42，即制得如图1所示的芯片封装结构100。其中，所述第二塑封体42的材质不做限制，可以同样采用所述LDS材料，也可以采用本领域常规的塑封材料，更优选为所述第二塑封体42也选用所述LDS材料制成，如此，可以直接在所述第二塑封体42的表面通过化学沉积形成电路层，节约了转载基板，也有利于进一步减少所述芯片封装结构100的厚度。
此外，需要说明的是，所述高层元器件22的贴装步骤和所述所述第二组元器件30的贴装步骤的先后顺序不做限定，既可以是先进行所述高层元器件22的贴装，再进行所述第二组元器件30的贴装，也可以是先进行所述第二组元器件30的贴装，再进行所述高层元器件22的贴装，也可以是所述高层元器件22和所述第二组元器件30的贴装同步进行，只需要在完成所述第一塑封体41的设置之后、进行第二次塑封之前，分别完成所述高层元器件22和所述第二组元器件30的贴装即可。
本申请提供的芯片封装结构100的制备方法，制备工艺简单，易于进行量化生产，可以适用于不用类型芯片的叠型集成封装，通过第一次局部塑封、第二次局部塑封以及二次布线的方式，提高了芯片封装结构100的空间利用率，提高了封装密度，在相同空间内可以集成更多的元器件，提高了***芯片封装的芯片集成度，且节约了转载基板，有利于实现***芯片封装的更高密度要求和更多元化要求。
此外，本申请还提出一种电子器件，包括芯片封装结构100，所述芯片封装结构100的结构参照上述实施例。可以理解的是，由于本申请电子器件采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
以上仅为本申请的优选实施例，并非因此限制本申请的专利范围，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包括在本申请的专利保护范围内。

Claims (10)

  1. 一种芯片封装结构，其中，包括：
    基板，所述基板具有安装侧；
    元器件，所述元器件包括第一组元器件和第二组元器件，所述第一组元器件和第二组元器件间隔分布于所述安装侧，所述第一组元器件包括沿远离所述基板的方向上依次排布的底层元器件和高层元器件，所述高层元器件朝向所述基板的一侧相对于所述基板的高度低于所述第二组元器件相对于所述基板的高度；以及，
    塑封体，设于所述安装侧，所述塑封体包括第一塑封体和第二塑封体，所述第一塑封体包裹所述底层元件设置，所述第二塑封体包裹所述高层元件和所述第二组元器件设置。
  2. 如权利要求1所述的芯片封装结构，其中，所述第一塑封体的材质包括LDS材料。
  3. 如权利要求1所述的芯片封装结构，其中，所述底层元器件包括芯片、电阻器和电容器中的至少一种；和/或，
    所述高层元器件包括芯片、电阻器和电容器中的至少一种；和/或，
    所述第二组元器件包括电感器和晶体振荡器中的至少一种。
  4. 如权利要求1所述的芯片封装结构，其中，所述第一组元器件设置有多组；和/或，
    所述第一塑封体朝向所述高层元器件的一侧设有连接电路，所述高层元器件设于所述连接电路上。
  5. 一种如权利要求1至4任意一项所述的芯片封装结构的制备方法，其中，包括以下步骤：
    提供一基板，所述基板具有安装侧，在所述基板的安装侧设置底层元器件；
    对所述底层元器件进行塑封，形成包裹所述底层元器件设置的第一塑封体；
    在所述第一塑封体远离所述基板的一侧设置高层元器件；
    在所述基板的安装侧设置第二组元器件；
    对所述第二组元器件和高层元器件进行塑封，形成同时包裹所述第二组元器件和高层元器件设置的第二塑封体，得到芯片封装结构。
  6. 如权利要求5所述的芯片封装结构的制备方法，其中，在所述第一塑封体远离所述基板的一侧设置高层元器件的步骤，包括：
    在所述第一塑封体远离所述基板的一侧设置连接电路；
    在所述连接电路上设置高层元器件。
  7. 如权利要求6所述的芯片封装结构的制备方法，其中，对所述底层元器件进行塑封，形成包裹所述底层元器件设置的第一塑封体的步骤中：所述第一塑封体的材质为LDS材料；
    在所述第一塑封体远离所述基板的一侧设置连接电路的步骤包括：
    在所述第一塑封体远离所述基板的一侧设置掩膜，然后对暴露出的部分所述第一塑封体表面进行活化后去掉所述掩膜；
    在活化后的所述第一塑封体表面刻画电路，然后通过化学镀的方式在所述第一塑封体的表面沉积电路层，形成连接电路。
  8. 如权利要求7所述的芯片封装结构的制备方法，其中，所述基板的安装侧还设有邻近所述底层元器件设置的导通焊盘；
    对所述底层元器件进行塑封，形成包裹所述底层元器件设置的第一塑封体的步骤之后、在所述第一塑封体远离所述基板的一侧设置掩膜，然后对暴露出的部分所述第一塑封体表面进行活化后去掉掩膜的步骤之前，还包括：
    在所述第一塑封体远离所述基板的一侧设置开孔，所述开孔连通所述导通焊盘；
    在所述第一塑封体远离所述基板的一侧设置掩膜，然后对暴露出的部分所述第一塑封体表面进行活化后去掉所述掩膜的步骤之后、在活化后的所述第一塑封体表面刻画电路，然后通过化学镀的方式在所述第一塑封体的表面沉积电路层，形成连接电路的步骤之前，还包括：
    在所述开孔内填充导电材料。
  9. 如权利要求8所述的芯片封装结构的制备方法，其中，所述导通焊盘的表面设置有锡膏；和/或，
    所述导电材料为锡或银。
  10. 一种电子器件，其中，包括如权利要求1至4任意一项所述的芯片封装结构。
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