WO2022061892A1 - 像素结构及其驱动方法、显示装置 - Google Patents

像素结构及其驱动方法、显示装置 Download PDF

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Publication number
WO2022061892A1
WO2022061892A1 PCT/CN2020/118415 CN2020118415W WO2022061892A1 WO 2022061892 A1 WO2022061892 A1 WO 2022061892A1 CN 2020118415 W CN2020118415 W CN 2020118415W WO 2022061892 A1 WO2022061892 A1 WO 2022061892A1
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Prior art keywords
light
reset
emitting
line
circuit
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PCT/CN2020/118415
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English (en)
French (fr)
Inventor
向炼
陈文波
税禹单
余正茂
李尚鸿
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2020/118415 priority Critical patent/WO2022061892A1/zh
Priority to CN202080002143.XA priority patent/CN115867960A/zh
Priority to US17/425,773 priority patent/US11847965B2/en
Publication of WO2022061892A1 publication Critical patent/WO2022061892A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel structure, a driving method thereof, and a display device.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • OLED Organic Light-Emitting Diode
  • a driving transistor generates a driving current in a saturated state to drive the light-emitting device to emit light.
  • the embodiments of the present disclosure propose a pixel structure, a driving method thereof, and a display device.
  • an embodiment of the present disclosure provides a method for driving a pixel structure, the pixel structure includes: a pixel circuit and a plurality of light-emitting devices, the pixel circuit includes: a driving transistor, a storage capacitor, a write compensation sub-circuit, a first a reset sub-circuit, a first light-emitting control sub-circuit, a plurality of second light-emitting control sub-circuits and a plurality of second reset sub-circuits, two ends of the storage capacitor are respectively connected to the gate of the driving transistor and the first power line ; Both the second light-emitting control sub-circuit and the second reset sub-circuit are connected to a plurality of the light-emitting devices in one-to-one correspondence; the plurality of second reset sub-circuits are respectively connected to a plurality of second reset lines, the The plurality of second light-emitting control sub-circuits are respectively connected to the plurality of second light-emitting control lines;
  • the pixel circuit has a plurality of display periods, and the display period includes: a first reset phase, a data writing phase, a second reset phase, and a light-emitting phase, and the driving method includes:
  • an active level signal is provided to the first reset line, so that the first reset sub-circuit writes the voltage signal on the initialization signal line into the gate of the driving transistor;
  • an active level signal is provided to the scan line, so that the write compensation sub-circuit writes the voltage signal on the data line into the first pole of the drive transistor, and the drive transistor The gate is connected to the second pole;
  • an active level signal is provided to at least one second reset line, so that the corresponding second reset sub-circuit writes the voltage on the initialization signal line into the first reset line of the light-emitting device pole;
  • an active-level signal is provided to the first light-emitting control line, and an active-level signal is provided to at least one second light-emitting control line, so that the first light-emitting control sub-circuit connects the first power line with all the The first electrode of the driving transistor is turned on, and at least one of the second light-emitting control sub-circuits conducts the second electrode of the driving transistor and the corresponding light-emitting device.
  • At least two of the plurality of light-emitting devices connected to the same pixel circuit have different colors
  • the providing an active level signal to at least one second reset line includes: providing an active level signal to each of the second reset lines;
  • the providing a valid level signal to at least one second light emitting control line includes: providing a valid level signal to a plurality of the second light emitting control lines respectively.
  • the colors of the multiple light-emitting devices connected to the same pixel circuit are the same;
  • the n second light-emitting control lines are provided with active level signals in turn; wherein, n is the number of light-emitting devices in the pixel structure.
  • the colors of the plurality of light-emitting devices connected to the same pixel circuit are the same; one of the plurality of second light-emitting control lines connected to the pixel circuit is the preferred light-emitting control line, and the rest are the second light-emitting control line.
  • the light-emitting control line is an optional light-emitting control line;
  • an active level signal is provided to the first light-emitting control line and the first light-emitting control line;
  • the first light-emitting control line, the primary light-emitting control line and at least one of the alternative light-emitting control lines provide an effective level signal; wherein, m is determined according to a luminance decay curve of the light-emitting device.
  • the first reset sub-circuit includes: a first reset transistor, a gate of the first reset transistor is connected to the first reset line, and a first electrode of the first reset transistor is connected to the first reset line the gate of the driving transistor, the second pole of the first reset transistor is connected to the initialization signal line;
  • an active level signal is provided to the first reset line, so that the first reset sub-circuit writes the voltage signal on the initialization signal line into the gate of the driving transistor, which specifically includes:
  • an active level signal is supplied to the first reset line, so that the first pole and the second pole of the first reset line are turned on.
  • the second reset sub-circuit includes: a second reset transistor, a gate of the second reset transistor is connected to the second reset line, and a first electrode of the second reset transistor is connected to the second reset line a light-emitting device, wherein the second pole of the second reset transistor is connected to the initialization signal line;
  • an active level signal is provided to at least one second reset line, so that the corresponding second reset sub-circuit writes the voltage on the initialization signal line into the first reset line of the light-emitting device poles, including:
  • an active level signal is supplied to at least one of the second reset lines to turn on the first and second electrodes of the corresponding second reset transistors.
  • the first light-emitting control sub-circuit includes: a first light-emitting control transistor, a gate of the first light-emitting control transistor is connected to the first light-emitting control line, and a second light-emitting control transistor of the first light-emitting control transistor One pole is connected to the first power line, the second pole of the first light-emitting control transistor is connected to the first pole of the driving transistor;
  • the second light-emitting control sub-circuit includes: a second light-emitting control transistor, the first light-emitting control transistor The gates of the two light-emitting control transistors are connected to the second light-emitting control line, the first electrodes of the second light-emitting control transistors are connected to the second electrodes of the driving transistors, and the second electrodes of the second light-emitting control transistors are connected to the the light-emitting device;
  • an active-level signal is provided to the first light-emitting control line, and an active-level signal is provided to at least one second light-emitting control line, so that the first light-emitting control sub-circuit connects the first power line with all the The first pole of the driving transistor is turned on, and at least one of the second light-emitting control subcircuits turns on the second pole of the driving transistor and the corresponding light-emitting device, which specifically includes:
  • an active-level signal is provided to the first light-emitting control line, and an active-level signal is provided to at least one second light-emitting control line, so that the first electrode of the first light-emitting control transistor and the second light-emitting control transistor are The diodes are turned on, and the first electrode and the second electrode of at least one of the second light-emitting control transistors are turned on.
  • an embodiment of the present disclosure further provides a pixel structure, including: a pixel circuit and a plurality of light-emitting devices, the pixel circuit including: a driving transistor, a storage capacitor, a write compensation sub-circuit, a first reset sub-circuit, a first a light-emitting control sub-circuit, a plurality of second light-emitting control sub-circuits and a plurality of second reset sub-circuits, two ends of the storage capacitor are respectively connected to the gate of the driving transistor and the first power line; the second light-emitting The control sub-circuit and the second reset sub-circuit are connected to the plurality of light-emitting devices in one-to-one correspondence;
  • the write compensation sub-circuit is configured to, in response to the control of the signal of the scan line, write the voltage signal on the data line into the first pole of the driving transistor, and connect the gate and the second pole of the driving transistor turn on;
  • the first reset sub-circuit is configured to, in response to the control of the signal of the first reset line, write the voltage signal on the initialization signal line into the gate of the driving transistor;
  • the second reset sub-circuit is configured to write the voltage on the initialization signal line into the first pole of the light-emitting device connected to the second reset sub-circuit in response to the control of the signal of the corresponding second reset line ;
  • the first light-emitting control sub-circuit is configured to, in response to the control of the signal of the first light-emitting control line, conduct the first power line and the first electrode of the driving transistor;
  • the second light-emitting control sub-circuit is configured to, in response to the control of the signal of the corresponding second light-emitting control line, turn on the second electrode of the driving transistor and the light-emitting device connected to the second light-emitting control sub-circuit .
  • the second reset sub-circuit includes: a second reset transistor, a gate of the second reset transistor is connected to the second reset line, and a first electrode of the second reset transistor is connected to the second reset line a light-emitting device, wherein the second pole of the second reset transistor is connected to the initialization signal line;
  • the second light-emitting control sub-circuit includes: a second light-emitting control transistor, the gate of the second light-emitting control transistor is connected to the second light-emitting control line, and the first electrode of the second light-emitting control transistor is connected to the drive The second pole of the transistor, and the second pole of the second light-emitting control transistor is connected to the light-emitting device.
  • At least two of the plurality of light-emitting devices in the pixel structure have different light-emitting colors; or,
  • the light-emitting colors of a plurality of the light-emitting devices in the pixel structure are the same.
  • the number of the light-emitting devices in the pixel structure is two, and the width-to-length ratio of the driving transistor is between 1/8 and 1/12; or,
  • the number of the light emitting devices in the pixel structure is three, and the width to length ratio of the driving transistor is between 1/3 and 1/5.
  • an embodiment of the present disclosure further provides a display device, including a display substrate, a first driving circuit and a second driving circuit, the display substrate includes a plurality of pixels, and at least one of the pixels is provided with the pixels according to claims 8 to 8.
  • a display device including a display substrate, a first driving circuit and a second driving circuit, the display substrate includes a plurality of pixels, and at least one of the pixels is provided with the pixels according to claims 8 to 8.
  • the first drive circuit is configured to, in the first reset stage of the pixel circuit, provide an effective level signal to the first reset line connected to the pixel circuit, so that the first reset sub-circuit will reset the initialization signal.
  • the voltage signal on the line is written to the gate of the driving transistor; in the data writing stage of the pixel circuit, an active level signal is provided to the scan line connected to the pixel circuit, so that the data writing sub- The circuit writes the voltage signal on the data line into the first pole of the drive transistor; and in the second reset phase of the pixel circuit, provides an active level signal to at least one second reset line connected to the pixel circuit , so that the corresponding second reset sub-circuit writes the voltage on the initialization signal line into the first pole of the light-emitting device;
  • the second driving circuit is configured to, in the light-emitting phase of the pixel circuit, provide an active level signal to the first light-emitting control line connected to the pixel circuit, and to at least one of the connected pixel circuits
  • the second light-emitting control line provides an effective level signal, so that the first light-emitting control sub-circuit conducts the first power line and the first electrode of the driving transistor, and at least one of the second light-emitting control sub-circuits connects all the The second electrode of the driving transistor is turned on with the corresponding light emitting device.
  • At least two of the plurality of light-emitting devices connected to the same pixel circuit have different colors
  • the first drive circuit is specifically configured to, in the first reset phase, provide an active level signal to the first reset line; in the data writing phase, provide an active level signal to the scan line; and in the data writing phase In the second reset stage of the pixel circuit, an active level signal is provided to each second reset line, so that the corresponding second reset sub-circuit writes the voltage on the initialization signal line into the light-emitting device. first pole;
  • the second driving circuit is specifically configured to, in the light-emitting stage, provide an active-level signal to the first light-emitting control line, and respectively provide an active-level signal to the plurality of second light-emitting control lines.
  • the colors of the multiple light-emitting devices connected to the same pixel circuit are the same;
  • the second driving circuit is specifically configured to provide an effective level signal to the first light-emitting control line connected to the pixel circuit in the light-emitting phase of each display period;
  • the n second light-emitting control lines connected to the pixel circuit are provided with active level signals in turn; wherein, n is the number of light-emitting devices in the pixel structure.
  • the colors of the plurality of light-emitting devices connected to the same pixel circuit are the same; one of the plurality of second light-emitting control lines connected to the pixel structure is the first light-emitting control line, and the rest are the second light-emitting control line.
  • the light-emitting control line is an optional light-emitting control line;
  • the second driving circuit is specifically configured to provide an effective level signal to the first light-emitting control line and the first-select light-emitting control line in the light-emitting stages of the first m display periods; In the light-emitting phase of the cycle, an active level signal is provided to the first light-emitting control line, the primary light-emitting control line, and at least one of the alternate light-emitting control lines; wherein m is based on the number of pixels connected to the pixel circuit.
  • the brightness decay curve of each light-emitting device is determined.
  • FIG. 1A is a schematic diagram of an exemplary display substrate.
  • FIG. 1B is a schematic structural diagram of a pixel structure according to an embodiment of the present disclosure.
  • FIG. 1C is a schematic diagram of a driving method of the pixel structure shown in FIG. 1B .
  • FIG. 2 is a schematic diagram of another pixel structure provided in an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of another pixel structure provided by an embodiment of the present disclosure.
  • FIG. 4 is a working timing diagram of the pixel structure provided in the embodiment of the present disclosure.
  • FIG. 5 is another working timing diagram of the pixel structure provided in the embodiment of the present disclosure.
  • FIG. 6 is still another working timing diagram of the pixel structure provided in the embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of luminance decay curves of light-emitting devices of different colors.
  • FIG. 8 is a schematic diagram of an overall structure of a display device provided in an embodiment of the present disclosure.
  • the light-emitting device is an organic light-emitting diode (Organic Light Emitting Diode, OLED for short) as an example for description.
  • the first pole of the light-emitting device is the anode, and the second pole is the cathode.
  • each transistor involved in the embodiments of the present disclosure may be independently selected from one of polysilicon thin film transistors, amorphous silicon thin film transistors, oxide thin film transistors, and organic thin film transistors.
  • the "first electrode” referred to in the present disclosure specifically refers to the source electrode of the transistor, and the corresponding “second electrode” refers specifically to the drain electrode of the transistor.
  • first pole and the “second pole” can be interchanged.
  • transistors can be divided into N-type transistors and P-type transistors, and each transistor in the present disclosure can be independently selected from N-type transistors or P-type transistors; in the following embodiments, it will be shown that each transistor in the driving circuit is a P-type transistor.
  • a type transistor is taken as an example for illustrative description, and in this case, the transistors in the display driving circuit can be fabricated simultaneously by using the same fabrication process.
  • the valid level signal is a low level signal
  • the invalid level signal is a high level signal.
  • FIG. 1A is a schematic diagram of an exemplary display substrate.
  • the display area of the display substrate includes a plurality of pixels P arranged in an array, and each of the plurality of pixels P includes a pixel structure, and the pixel structure includes Pixel circuits and light-emitting devices.
  • a driving circuit is also arranged around the display area, the driving circuit provides a scanning signal, a reset signal and other signals for the pixel circuit, and the pixel circuit provides a driving current for the light-emitting device according to the received signal.
  • the pixel structure includes: a pixel circuit and a plurality of light-emitting devices 21 to 22 , and the pixel circuit includes: a driving transistor T3 , a storage capacitor Cs, Write compensation sub-circuit 11, first reset sub-circuit 12, first light-emitting control sub-circuit 13, multiple second light-emitting control sub-circuits 141-142 and multiple second reset sub-circuits 151-152, two of the storage capacitor Cs.
  • the terminals are respectively connected to the gate of the driving transistor T3 and the first power supply line VDD; the second light-emitting control sub-circuits 141-142 and the second reset sub-circuits 151-152 are connected to the light-emitting devices 21-22 in one-to-one correspondence.
  • the second light-emitting control sub-circuits 141-142 and the second reset sub-circuits 151-152 are connected to the first poles of the corresponding light-emitting devices 21-22, and the second poles of the light-emitting devices 21-22 are connected to the second power line VSS .
  • the plurality of second reset sub-circuits 151 to 152 are respectively connected to the plurality of second reset lines Reset2_1 to Reset2_2.
  • the plurality of second light emission control sub-circuits 141 to 142 are respectively connected to the plurality of second light emission control lines EM2_1 to EM2_2.
  • the writing compensation sub-circuit 11 is configured to, in response to the control of the signal of the scan line Scan, conduct the gate and the second electrode of the driving transistor T3.
  • the first reset sub-circuit 12 is configured to, in response to the control of the signal of the first reset line Reset1, write the voltage signal on the initialization signal line Init into the gate of the driving transistor T3, thereby resetting the gate potential of the driving transistor T3 .
  • the second reset sub-circuits 151/152 are configured to, in response to the control of the signals of the corresponding second reset lines Reset2_1/Reset2_2, write the voltage on the initialization signal line Init into the light-emitting device connected to the second reset sub-circuits 151/152 1st pole of 21/22. It should be understood that the second reset lines Reset2_1 and Reset2_1 connected to different second reset sub-circuits 151 and 152 are independent of each other.
  • the first light emission control sub-circuit 13 is configured to turn on the first power line VDD and the first electrode of the driving transistor T3 in response to the control of the signal of the first light emission control line EM1.
  • the second lighting control sub-circuits 141/142 are configured to connect the second pole of the driving transistor T3 with the second electrode of the second lighting control sub-circuit 141/142 in response to the control of the signals of the corresponding second lighting control lines EM2_1/EM2_2
  • the light emitting devices 21/22 are turned on. It should be understood that the second lighting control lines EM2_1 and EM2_2 to which different second lighting control sub-circuits 141 and 142 are connected are independent of each other.
  • the pixel structure has a plurality of display periods, and each display period is a time period during which the display substrate displays one frame of image.
  • Each display period of the pixel structure may include a first reset phase, a data writing phase, a second reset phase, and a light-emitting phase.
  • FIG. 1C is a schematic diagram of a driving method of the pixel structure shown in FIG. 1B . As shown in Figure 1C, the driving method includes:
  • an active level signal is provided to the first reset line Reset1, so that the first reset sub-circuit 12 writes the voltage signal on the initialization signal line Init into the gate of the driving transistor T3, so that the gate of the driving transistor T3 is affected.
  • the gate potential is reset.
  • an active level signal is provided to the scan line Scan, so that the write compensation sub-circuit 11 writes the voltage signal on the data line Data into the first pole of the driving transistor T3 and the gate of the driving transistor T3
  • the second electrode is turned on, so that the voltage stored in the storage capacitor Cs is related to the voltage signal on the data line Data and the threshold voltage of the driving transistor T3.
  • an active level signal is provided to at least one second reset line Reset2_1/Reset2_2, so that the corresponding second reset subcircuit 151/152 writes the voltage signal on the initialization signal line Init into the light emitting device 21/22 , so as to reset the potential of the first electrodes of the light emitting devices 21/22.
  • an active-level signal is provided to the first light-emitting control line EM1, and an active-level signal is provided to at least one of the second light-emitting control lines EM2_1 to EM2_2, so that the first light-emitting control sub-circuit 13 connects the first power line VDD Conducting with the first pole of the driving transistor T3, at least one second light-emitting control sub-circuit 141/142 conducts the second pole of the driving transistor T3 with the corresponding light-emitting device 21/22, so that the driving transistor T3 is at least one light-emitting Devices 21/22 provide the drive current.
  • the light-emitting devices 21 to 22 are red light-emitting devices and green light-emitting devices respectively; for another example, the same pixel circuit is connected to one light-emitting device at the same time.
  • a red light-emitting device, a green light-emitting device, and a blue light-emitting device; for another example, a red light-emitting device, two green light-emitting devices, and a blue light-emitting device are simultaneously connected to the same pixel circuit.
  • an active level signal is provided to each of the second reset lines Reset2_1 ⁇ Reset2_2 , so that each second reset sub-circuit 151 / 152 can make the corresponding light emitting device 21 / 22 .
  • the potential of the first pole is reset.
  • an active-level signal is provided to the first light-emitting control line EM1, and an active-level signal is provided to a plurality of second light-emitting control lines EM2_1-EM2_2 respectively, so that the driving transistor T3 provides a plurality of light-emitting devices 21-22
  • the driving current wherein, the size of the driving current that the driving transistor T3 can output is related to the voltage stored in the storage capacitor Cs, that is, related to the voltage signal on the data line Data;
  • the magnitude of the current is related to the turn-on time of the second light-emitting control sub-circuits 141/142. Therefore, by controlling the time when the effective level signal is loaded on each of the second light-emitting control lines EM2_1/EM2_2, the flow through the light-emitting device 21 can be controlled. /22 current, thereby controlling the light-emitting brightness of the light-emitting device 21/22. At this time, the same pixel circuit can drive multiple light-emitting devices 21 to 22 to emit light at the same time, thereby facilitating the realization of high resolution of the display device.
  • each display period of the pixel circuit only one light-emitting device 21/22 may be driven to emit light.
  • the colors of the plurality of light-emitting devices 21 to 22 in each pixel structure are the same, and in the light-emitting stage in consecutive n display periods (that is, when displaying consecutive n-frame images), the n second light-emitting controls are turned in turn.
  • the line provides an effective level signal, so as to drive the plurality of light-emitting devices 21 to 22 to emit light in turn.
  • the light-emitting devices 21 to 22 in the pixel structure in the area can be controlled. 22 alternately emit light to prevent display burn-in problems caused by prolonged light emission of light emitting devices 21/22 in a certain area.
  • the pixel circuit can drive a plurality of light-emitting devices 21 to 22.
  • each light-emitting stage one of the light-emitting devices 21/22 is driven to emit light by the pixel circuit; In the stage, at least two light-emitting devices 21-22 are driven to emit light at the same time by the pixel circuit, thereby compensating for the luminance attenuation of the light-emitting devices 21/22.
  • FIG. 2 is a schematic diagram of another pixel structure provided in an embodiment of the present disclosure, wherein the pixel structure shown in FIG. 2 is a specific implementation based on the pixel structure shown in FIG. 1B .
  • the writing compensation sub-circuit 11 includes: a data writing transistor T4 and a compensation transistor T1 , the gate of the data writing transistor T4 is connected to the scan line Scan, and the first gate of the data writing transistor T4 is connected to the scan line Scan. One pole is connected to the data line Data, and the second pole of the data writing transistor T4 is connected to the first pole of the driving transistor T3.
  • the gate of the compensation transistor T1 is connected to the scan line Scan, the first electrode of the compensation transistor T1 is connected to the second electrode of the driving transistor T3, and the second electrode of the compensation transistor T1 is connected to the gate of the driving transistor T3.
  • the first reset sub-circuit 12 includes: a first reset transistor T2, the gate of the first reset transistor T2 is connected to the first reset line Reset1, and the first electrode of the first reset transistor T2 is connected to the gate of the driving transistor T3 pole, the second pole of the first reset transistor T2 is connected to the initialization signal line Init.
  • the first reset sub-circuit 12 writes the voltage signal on the initialization signal line Init into the gate of the driving transistor T3, specifically, the first and second electrodes of the first reset transistor T2 are turned on, thereby The gate of the drive transistor T3 is turned on with the initialization signal line Init.
  • the second reset sub-circuit 151/152 includes: a second reset transistor T7_1/T7_2, the gate of the second reset transistor T7_1/T7_2 is connected to the second reset line Reset2_1/Reset2_2, and the second reset transistor T7_1/T7_2
  • the first pole of the second reset transistor T7_1/T7_2 is connected to the first pole of the light emitting device 21/22, and the second pole of the second reset transistor T7_1/T7_2 is connected to the initialization signal line Init.
  • the second reset subcircuit 151/152 writes the voltage signal on the initialization signal line Init into the first pole of the light-emitting device 21/22, specifically, the first pole of the second reset transistor T7_1/T7_2 And the second electrode is conductive, so that the first electrode of the light emitting device 21/22 is conductive with the initialization signal line Init.
  • the first light-emitting control sub-circuit 13 includes: a first light-emitting control transistor T5, the gate of the first light-emitting control transistor T5 is connected to the first light-emitting control line EM1, and the first electrode of the first light-emitting control transistor T5 is connected to the first light-emitting control line EM1
  • the first power line VDD, the second pole of the first light-emitting control transistor T5 is connected to the first pole of the driving transistor T3.
  • the first light-emitting control sub-circuit 13 conducts the first power supply line VDD with the first electrode of the driving transistor T3, specifically, the first and second electrodes of the first light-emitting control transistor T5 are conductive, so that The first power line VDD is turned on with the first electrode of the driving transistor T3.
  • the second light-emitting control sub-circuit 141/142 includes: a second light-emitting control transistor T6_1/T6_2, the gate of the second light-emitting control transistor T6_1/T6_2 is connected to the second light-emitting control line EM2_1/EM2_2, the second light-emitting control transistor T6_1/T6_2 is connected to the second light-emitting control line EM2_1/EM2_2.
  • the first electrodes of the control transistors T6_1/T6_2 are connected to the second electrodes of the driving transistors T3, and the second electrodes of the second light emission control transistors T6_1/T6_2 are connected to the light emitting devices 21/22.
  • the second light-emitting control sub-circuit 141/142 conducts the second electrode of the driving transistor T3 and the corresponding light-emitting device 21/22.
  • the first electrode of the second light-emitting control transistor T6_1/T6_2 is connected to the first electrode of the second light-emitting control transistor T6_1/T6_2.
  • the diodes are turned on, thereby turning on the second electrode of the driving transistor T3 and the corresponding light emitting device 21/22.
  • At least two second reset transistors T7_1 ⁇ T7_2 form a double gate structure, thereby reducing the space occupied by the pixel structure.
  • the two second reset transistors T7_1 ⁇ T7_2 constitute a double-gate transistor
  • the double-gate transistor has two gates, two second reset transistors One pole and one second pole, the two gates of the dual-gate transistor are respectively used as the gates of the two second reset transistors T7_1 ⁇ T7_2
  • the two first poles of the dual-gate transistor are respectively used as the two second reset transistors T7_1 ⁇ T7_2
  • the first pole of T7_2 and the second pole of the dual-gate transistor simultaneously serve as the second pole of the two second reset transistors T7_1/T7_2.
  • FIG. 3 is a schematic diagram of another pixel structure provided by an embodiment of the present disclosure.
  • the difference between FIG. 3 and the pixel structure shown in FIG. 2 is only that: in FIG. 2 , the pixel structure includes two light-emitting devices 21 to 22, two Two reset sub-circuits 151-152, and two second light-emitting control sub-circuits 141-142; and in FIG. 3, the pixel structure includes three light-emitting devices 21-23, three second reset sub-circuits 151-153, and three A second lighting control sub-circuit 141-143.
  • the light emitting devices 21/22/23, the second reset sub-circuits 151/152/153, and the second light-emitting control sub-circuits 141/142/143 may also be set to other numbers, which are not specifically limited herein.
  • two of the second reset transistors T7_1 ⁇ T7_2 can also form a double-gate transistor, and the other second reset transistor T7_3 is a separate transistor.
  • the light emitting colors of the plurality of light emitting devices 21 to 23 in the pixel structure may be different from each other.
  • the light emitting colors of the light emitting devices 21 to 23 in FIG. 3 are red, green and blue, respectively.
  • the operation timing of the pixel structure may be as shown in FIG. 4 .
  • the driving process of the pixel structure includes: a first reset phase t1, a data writing phase t2, a second reset phase t3, and a light-emitting phase t4.
  • the first reset line Reset1 is provided with an active level signal, and the scan line Scan, the second reset line Reset2_1/Reset2_2, the first light-emitting control line EM1 and the second light-emitting control line EM2_1/EM2_2 are provided with an inactive power flat signal.
  • the first reset transistor T2 is turned on, and the voltage signal on the initial voltage line Init is transmitted to the gate of the driving transistor T3, thereby resetting the gate potential of the driving transistor T3.
  • the data writing transistor T4, the compensation transistor T1, the first light-emitting control transistor T5, the second light-emitting control transistors T6_1-T6_3, and the second reset transistors T7_1-T7_3 are all turned off.
  • an active level signal is provided to the scan line Scan, and an inactive power is provided to the first reset line Reset1, the second reset lines Reset2_1-Reset2_3, the first light-emitting control line EM1, and the second light-emitting control lines EM2_1-EM2_3 flat signal.
  • the data writing transistor T4 is turned on, and the voltage signal on the data line Data is written into the first pole of the driving transistor T3; at the same time, the compensation transistor T1 is turned on, so that the gate of the driving transistor T3 is short-circuited with the second pole , a diode structure is formed.
  • the voltage signal on the data line Data passes through the driving transistor T3 and the compensation transistor T1, and flows to the gate of the driving transistor T3, and the gate potential of the driving transistor T3 reaches Vdata+Vth, where Vth is the driving The threshold voltage of the transistor T3, Vdata is the voltage on the data line Data.
  • the second reset lines Reset2_1 to Reset2_3 are all provided with active level signals. Inactive level signals are supplied to the first reset line Reset1, the scan line Scan, the first light emission control line EM1, and the second light emission control lines EM2_1 to EM2_3.
  • the plurality of second light-emitting control transistors T6_1 to T6_3 are all turned on, so as to transmit the voltage signal on the initial signal line Init to the first pole of each light-emitting device 21-23, so that each light-emitting device 21-23 The potential of the first pole is reset.
  • an inactive level signal is provided to the first reset line Reset1, the second reset lines Reset2_1 to Reset2_3, and the scan line Scan, an active level signal is provided to the first light-emitting control line EM1, and a plurality of second light-emitting control lines are provided EM2_1 ⁇ EM2_3 provide effective level signals respectively. It should be noted that the effective level signals provided to the plurality of second light-emitting control lines EM2_1 to EM2_3 are independent of each other.
  • the first light-emitting control transistor T5 is turned on, and each of the second light-emitting control transistors T6_1/T6_2/T6_3 is turned on when the corresponding second light-emitting control line EM2_1/EM2_2/EM2_3 is loaded with an active level, thereby enabling a plurality of light-emitting Devices 21 to 23 all emit light.
  • the gate potential of the driving transistor T3 is maintained at Vdata+Vth.
  • the driving transistor T3 When any one of the second light-emitting control transistors T6_1/T6_2/T6_3 is turned on, the driving transistor T3 outputs a driving current, and when the turn-on time of the second light-emitting control transistors T6_1/T6_2/T6_3 reaches a certain time, the driving current flows through the light-emitting device 21/
  • the drive current I OLED of 22/23 satisfies the following saturation current formula:
  • K is a coefficient related to the characteristics of the driving transistor T3 itself
  • Vgs is the gate-source voltage of the driving transistor T3, that is, the voltage between the gate and the first electrode of the driving transistor T3
  • ELVDD is the voltage provided by the first power supply line VDD. Voltage.
  • the on-time of the second light-emitting control transistors T6_1/T6_2/T6_3 is less than a certain time, the current flowing through the light-emitting devices 21/22/23 is smaller than the above-mentioned I OLED , and is different from the I OLED and the second light-emitting control transistor T6_1/T6_2
  • the on-time is related. Therefore, by controlling the time when the second light-emitting control line EM2_1/EM2_2/EM2_3 is loaded with the active level signal and the above Vdata, the magnitude of the current flowing through the light-emitting devices 21/22/23 can be controlled. That is to say, in the light-emitting stage t4, the active level signal is not continuously provided to each of the second light-emitting control lines EM2_1/EM2_2/EM2_3.
  • the light-emitting colors of the plurality of light-emitting devices 21-23 in the pixel structure may be the same.
  • the working timing of the pixel structure may be as shown in FIG. 5 .
  • the working process of the pixel structure also includes: a first reset phase t1, a data writing phase t2, a second charging phase t3, and a light-emitting phase t4.
  • the first reset line Reset1 is provided with an active level signal, and the scan line Scan, the second reset lines Reset2_1-Reset2_3, the first light-emitting control line EM1 and the second light-emitting control lines EM2_1-EM2_3 are provided with invalid power flat signal.
  • the first reset transistor T2 is turned on, and the voltage signal on the initial signal line Init is transmitted to the gate of the driving transistor T3, thereby resetting the gate potential of the driving transistor T3.
  • the data writing transistor T4, the compensation transistor T1, the first light-emitting control transistor T5, the second light-emitting control transistors T6_1-T6_3, and the second reset transistors T7_1-T7_3 are all turned off.
  • an active level signal is provided to the scan line Scan, and an invalid power is provided to the first reset line Reset1, the second reset lines Reset2_1-Reset2_3, the first light-emitting control line EM1, and the second light-emitting control lines EM2_1-EM2_3 flat signal.
  • the data writing transistor T4 is turned on, and the voltage signal on the data line Data is written into the first pole of the driving transistor T3; at the same time, the compensation transistor T1 is turned on, so that the gate of the driving transistor T3 is short-circuited with the second pole , a diode structure is formed.
  • the voltage signal on the data line Data passes through the driving transistor T3 and the compensation transistor T1, and flows to the gate of the driving transistor T3, and the gate potential of the driving transistor T3 reaches Vdata+Vth, where Vth is the driving The threshold voltage of the transistor T3, Vdata is the voltage on the data line Data.
  • a valid level signal is provided to at least one second reset line Reset2_1, and an invalid power is provided to the first reset line Reset1, the scan line Scan, the first light-emitting control line EM1 and the second light-emitting control lines EM2_1-EM2_3 flat signal.
  • at least the second reset transistor T7_1 is turned on, thereby transmitting the voltage signal on the initial signal line Init to at least the first electrode of the light emitting devices 21 to reset the potential of the first electrode of at least one of the light emitting devices 21 .
  • an inactive level signal is provided to the first reset line Reset1, the second reset lines Reset2_1 to Reset2_3, and the scan line Scan, and an active level is continuously provided to the first light-emitting control line EM1 and one of the second light-emitting control lines EM2_1 Signal.
  • the first light-emitting control transistor T5 is turned on, and one of the second light-emitting control transistors T6_1 is turned on.
  • the gate potential of the driving transistor T3 is maintained at Vdata+Vth.
  • the current output by the driving transistor T3 to the corresponding light emitting device 21 reaches the above-mentioned driving current I OLED .
  • the working process of the pixel structure includes the above four stages, and in the light-emitting stage in three consecutive (i-th to i+2th) display periods, the three second The light-emitting control lines EM2_1-EM2_3 provide effective level signals, so that the three light-emitting devices 21-23 in the pixel structure work alternately in three display periods, so as to prevent a single light-emitting device 21/22/23 from working for a long time and causing display images Branding appears.
  • the display period may be a display stage of one frame of display images, and of course, may also be a display stage of two or other frames of display images.
  • an active level signal is provided to each of the second reset lines Reset2_1 to Reset2_3, but in fact, it is not necessary to supply all of the second reset lines Reset2_1 to Reset2_3 Provides a valid level signal. For example, if an active level signal is provided to the second light-emitting control line EM2_1 to control the light-emitting device 21 to emit light in the light-emitting phase of the i-th display cycle, then in the reset phase t3 of the i-th display cycle, at least the The second reset line Reset2_1 provides an active level signal.
  • the active level signal is provided to the second light-emitting control line EM2_2 to control the light-emitting device 22 to emit light in the light-emitting phase t4 of the i+1 th display period, then in the reset phase t3 of the i+1-th display period, at least the The second reset line Reset2_2 corresponding to the device 22 provides an active level signal.
  • the working sequence shown in FIG. 5 is illustrated by taking the pixel structure in FIG. 3 as an example, and the number of light-emitting devices in the pixel structure can also be other numbers, and only needs to be displayed in consecutive n display periods. In the light-emitting stage, it is sufficient to provide active level signals to the n second light-emitting control lines in turn, so that the n light-emitting devices can light up in turn in n display periods. Wherein, n is the number of light-emitting devices in the pixel structure.
  • the operation sequence of the pixel structure may also be as shown in FIG. 6 .
  • an active level signal is provided to the first reset line Reset1, to the scan line Scan, the second reset lines Reset2_1 to Reset2_3, the first light-emitting control line EM1 and the first light-emitting control line EM1.
  • the two light-emitting control lines EM2_1 to EM2_3 provide inactive level signals, and the first reset transistor T2 is turned on to reset the gate potential of the driving transistor T3.
  • an active level signal is provided to the scan line Scan, and inactive power is provided to the first reset line Reset1, the second reset lines Reset2_1-Reset2_3, the first light-emitting control transistor T5, and the second light-emitting control transistors T6_1-T6_3 flat signal.
  • the gate potential of the drive transistor T3 reaches Vdata+Vth.
  • an active level signal is provided to at least one second reset line Reset2_1/Reset2_2/Reset2_3, and the voltage signal on the initial signal line Init is transmitted to the first pole of the corresponding light-emitting device 21/22/23 to The potential of the first pole of the at least one light emitting device 21/22/23 is reset.
  • One of the second light-emitting control lines EM2_1 connected to the pixel structure in FIG. 3 is used as the first light-emitting control line, and the remaining second light-emitting control lines EM2_2 to EM2_3 are used as alternative light-emitting control lines.
  • the difference between the working process in FIG. 6 and FIG. 5 is that, as shown in FIG.
  • the first reset line Reset1 In the light-emitting stage t4 of the first m display periods, the first reset line Reset1 , the second reset lines Reset2_1 to Reset2_3 , the scan line Scan Both provide inactive level signals, and provide active level signals to the first light emission control line EM1 and the second light emission control line EM2_1 (ie, the first light emission control line).
  • the first light-emitting control transistor T5 is turned on, and the second light-emitting control transistor T6_1 is turned on, thereby providing a driving current for the light-emitting device 21 .
  • the other light-emitting devices 22 and/or 23 can be controlled to emit light in the light-emitting period t4 of the m+1th and subsequent display periods.
  • the luminance attenuation of the light emitting device 21 is compensated.
  • an inactive level signal is provided to the first reset line Reset1, the second reset lines Reset2_1 to Reset2_3, and the scan line Scan, and the first light-emitting control line EM1 is provided with an inactive level signal.
  • the first light-emitting control transistor T5 is turned on
  • the second light-emitting control transistor T6_1 is turned on
  • at least one of the second light-emitting control transistors T6_2 and /T6_3 is turned on, thereby controlling at least one of the light-emitting devices 22 and 23
  • the light emitting device 21 emits light.
  • the duration of supplying the active level signal to the alternative light-emitting control line may be determined according to the brightness required by the light-emitting devices 22/23.
  • an effective level signal is provided to the second reset line corresponding to the light-emitting device to be emitted. , to reset the potential of the first electrode of the light-emitting device to be emitted.
  • the first m display periods may be the first m display periods of cumulative operation of the pixel structure, that is, the first m display periods of cumulative display by the display device, and the size of m may be determined according to the luminance decay curve of the light-emitting device. For example, in a display device, sub-pixels of a first color (eg, blue), sub-pixels of a second color (eg, red), and sub-pixels of a third color (eg, green) may be provided, as shown in FIG. 7 . Schematic diagram of the luminance decay curves of light-emitting devices of different colors.
  • a first color eg, blue
  • sub-pixels of a second color eg, red
  • a third color eg, green
  • the decay speed of the light-emitting device of the first color is greater than the decay speed of the light-emitting device of the second color and the decay speed of the light-emitting device of the second color.
  • the above-mentioned pixel structure can be set in the sub-pixels of the first color, if the difference between the brightness attenuation degree of the light emitting device of the first color and the brightness attenuation degree of other colors reaches a preset value, the light emission of the first color
  • the cumulative working time of the device is time1
  • m is the number of display cycles corresponding to when the cumulative display time of the display device is time1.
  • the above-mentioned pixel structure may also be provided in both the sub-pixels of the first color and the second color.
  • the driving time reaches 500 hours (hr)
  • the light-emitting brightness of the light-emitting devices of the first color and the second color will be significantly attenuated.
  • the cumulative display time of the display device can reach After 500 hours, in the light-emitting stage of the pixel circuit in the sub-pixel of the first color, at least two light-emitting devices of the first color in the pixel circuit are controlled to emit light simultaneously; in the light-emitting stage of the pixel circuit in the sub-pixel of the second color , controlling at least two light-emitting devices of the second color in the pixel circuit to emit light at the same time.
  • the drive current value that can be output by the drive transistor T3 can be increased by adjusting the width to length ratio of the drive transistor T3, so as to meet the requirement of two or more light-emitting devices emitting light simultaneously.
  • the number of light-emitting devices connected to the same pixel circuit is two, and the width-to-length ratio of the driving transistor T3 is between 1/8 and 1/12, for example, 3/30, the driving transistor T3 can output
  • the current value is 200nA; in other examples, the number of light-emitting devices connected to the same pixel circuit is three, and the width to length ratio of the driving transistor is between 1/3 and 1/5, for example, the driving transistor T3
  • the aspect ratio is 5/20, and the output current value of the driving transistor T3 can reach 300nA.
  • the voltage difference between the first power supply line VDD and the second power supply line VSS can be increased to further increase the driving current that the driving transistor T3 can output.
  • the voltage of the first power supply line VDD is between 4V and 5V, For example, it is 4.6V; the voltage of the second power line VSS is between -4V and -6V, for example, -5V.
  • the working process of the pixel structure includes two reset stages (ie, the first reset stage t1 and the second reset stage t3) as an example for description, but in fact, the pixel structure
  • the first reset phase t1 and the second reset phase t3 may be combined, ie, before the data writing phase t2, the first reset line Reset1 and the at least one second reset line Reset2_1/Reset2_2/Reset2_3 are simultaneously provided with active level signals.
  • FIG. 8 is a schematic diagram of the overall structure of the display device provided in the embodiment of the present disclosure.
  • the display device includes a display substrate, a first driving circuit 30 and a second driving circuit 40.
  • the display substrate includes a display area DA and a peripheral area located around the display area DA, and the first driving circuit 30 and the second driving circuit 40 may be disposed in the peripheral area of the display substrate.
  • the display area DA includes a plurality of pixels P arranged in an array, and at least one pixel P is provided with the pixel structure in the above embodiment. Multiple light emitting devices in the same pixel structure can be arranged in the row direction or in the column direction.
  • each pixel P is provided with the pixel structure in the above embodiment, the scan lines Scan connected to the same row of pixel structures are the same, and the first reset lines connected to the same row of pixel structures are the same , the second reset lines connected to the same row of pixel structures are the same, and the first light emission control lines EM1 connected to the same row of pixel structures are the same.
  • the second light-emitting control lines EM2_1 connected to the same row of pixel structures are the same, and the second light-emitting control lines EM2_2 connected to the same row of pixel structures are the same.
  • the data lines connected to the same column of pixel structures are the same.
  • the data lines Data1 to DataM connected to the multi-column pixel structure are connected to the data driving circuit 50 so as to receive the data voltage signals provided by the data driving circuit 50 .
  • the first drive circuit 30 is configured to: in the first reset stage of the pixel circuit, provide an effective level signal to the first reset line connected to the pixel circuit, so that the first reset sub-circuit writes the voltage signal on the initialization signal line The gate of the driving transistor; in the data writing stage of the pixel circuit, an active level signal is provided to the scan line connected to the pixel circuit, so that the data writing sub-circuit writes the voltage signal on the data line into the first gate of the driving transistor and in the second reset stage of the pixel circuit, supplying a valid level signal to at least one second reset line connected to the pixel circuit, so that the corresponding second reset sub-circuit writes the voltage on the initialization signal line into the light-emitting device the first pole.
  • the first driving circuit 30 may specifically include a plurality of cascaded gate driving units.
  • the first driving circuit 30 includes: a first-level gate driving unit S_1 , a second-level gate driving unit S_1 The pole driving unit S_2, the third-level gate driving unit S_3...the N-1-th level gate driving unit S_N-1, the N-th level gate driving unit S_N.
  • the first-level gate driving unit S_1 is connected to the scan line connected to the pixel circuit of the first row, and is used to provide the pixel circuit of the first row with a scan signal in an active level state during the data writing stage of the pixel circuit of the first row; At the same time, the first-stage gate driving circuit S_1 is connected to the first reset line connected to the pixel circuits of the second row, so as to provide the pixel circuits of the second row with an active level state during the first reset stage of the pixel circuits of the second row the first reset signal.
  • the second-level gate driving unit S_2 is connected to the scan line connected to the pixel circuit of the second row, and is used to provide the pixel circuit of the second row with a scan signal in an active level state during the data writing stage of the pixel circuit of the second row.
  • the second-stage gate driving unit S_2 is connected to the second reset line connected to the pixel structure of the first row and the first reset line connected to the pixel circuit of the third row, so that the second reset line of the pixel circuit of the first row is connected.
  • the first reset signal in the active level state is provided for the pixel circuits of the first row .
  • the gate driving unit S_N-1 of the N-1th stage is connected to the scan line connected to the pixel circuit of the N-1th row, so that in the data writing stage of the pixel circuit of the N-1th row, the pixel circuit of the N-1th row is the pixel circuit of the N-1th row.
  • the second reset line connected to the N-1th gate drive unit S_N-1 and the N-2th row of pixel circuits and the first reset line connected to the Nth row of pixel circuits
  • the reset line is connected, so that in the second reset stage of the pixel circuit of the N-2 row, the second reset signal in the active level state is provided for the pixel circuit of the N-2 row; and in the first reset of the pixel circuit of the N-th row In the first stage, the first reset signal in the active level state is provided for the pixel circuit of the Nth row.
  • the Nth-level gate driving unit S_N is connected to the scan line connected to the Nth row of pixel circuits, so as to provide the Nth row of pixel circuits with a scan signal in an active level state during the data writing phase of the Nth row of pixel circuits;
  • the gate driving unit S_N of the Nth stage is connected to the second reset line connected to the pixel circuit of the N-1th row, so that in the second reset stage of the pixel circuit of the N-1th row, the pixel circuit of the N-1th row is the pixel circuit of the N-1th row.
  • a second reset signal is provided in an active level state.
  • the second driving circuit 40 is configured to: in the light-emitting stage of the pixel circuit, provide an active level signal to the first light-emitting control line EM1 connected to the pixel circuit, and to at least one second light-emitting control line EM2_1 connected to the pixel circuit /EM2_2 provides an active level signal, so that the first light-emitting control sub-circuit conducts the first power line and the first electrode of the driving transistor, and at least one second light-emitting control sub-circuit connects the second electrode of the driving transistor with the corresponding light-emitting The device is turned on.
  • the second driving circuit 40 may include a first shift register 41 and a plurality of second shift registers 42_1 to 42_2, and the second shift registers 42_1/42_2 are connected to the second light-emitting control lines of the pixel circuits in the same row One-to-one correspondence between EM2_1/EM2_2.
  • the structure of the second driving circuit 40 will be described below by taking the example of connecting two second light-emitting control lines EM2_1 to EM2_2 in the same row of pixel circuits.
  • the first shift register 41 includes a plurality of cascaded first shift register units G1_1 to G1_N, and each of the first shift register units G1_1 to G1_N is connected to a first light-emitting control line EM1.
  • the first-stage first shift register unit G1_1 is connected to the first light-emitting control line EM1 connected to the first row of pixel circuits
  • the second-stage first shift register unit G1_2 is connected to the second row of pixel circuits
  • the connected first light-emitting control line EM1 is connected, and so on, the Nth-stage first shift register unit G1_N is connected to the first light-emitting control line EM1 connected to the Nth row of pixel circuits.
  • the second shift register 42_1 includes a plurality of cascaded second shift register units G21_1 to G21_N
  • the second shift register 42_2 includes a plurality of cascaded second shift register units G22_1 to G22_N.
  • the first-stage second shift register unit G21_1 and the first-stage second shift register unit G22_1 are respectively connected to the two second light-emitting control lines EM2_1 to EM2_2 connected to the pixel circuits of the first row
  • the register unit G21_2 and the second-stage second shift register unit G22_2 are respectively connected to the two second light-emitting control lines EM2_1 to EM2_2 connected to the pixel circuits of the second row
  • the Nth-stage second shift register unit G21_N and the Nth-stage second shift register unit G22_N are respectively connected to the two second light-emitting control lines EM2_1 to EM2_2 connected to the Nth row of pixel circuit
  • the first drive circuit 30 is specifically configured to, in the first reset stage of the pixel circuit, provide an effective level signal to the first reset line connected to the pixel circuit; and in the second reset phase of the pixel circuit, each second reset line connected to the pixel circuit is provided with an effective level signal, so that the corresponding second reset sub-circuit will reset the initialization signal line The voltage on is written to the first pole of the light emitting device.
  • the second driving circuit 40 is specifically configured to, in the light-emitting stage of the pixel circuit, provide an active level signal to the first light-emitting control line EM1 connected to the pixel circuit, and provide a plurality of second light-emitting control lines EM2_1 ⁇ EM2_2 respectively provide active level signals.
  • a plurality of light emitting devices can be respectively used as a plurality of sub-pixels of a pixel, and since a plurality of light emitting devices in a pixel structure share one pixel circuit, it is beneficial to improve the resolution of the display device.
  • the second driving circuit 40 is specifically configured to provide an active level signal to the first light-emitting control line EM1 connected to the pixel circuit in the light-emitting phase of each display period of the pixel circuit; and to emit light in consecutive n display periods In the stage, the n second light-emitting control lines connected to the pixel circuit are provided with active level signals in turn.
  • n is the number of light-emitting devices in the pixel structure.
  • the control circuit of the display device determines that the display substrate is continuously displaying multiple frames of pictures, the picture in a certain area remains unchanged.
  • the control circuit can send a control signal to the second driving circuit 40, and the second driving circuit 40.
  • the plurality of light-emitting devices in each pixel structure in the region are controlled to emit light in turn in a plurality of consecutive display periods, thereby improving the problem of display burn-in.
  • multiple light-emitting devices connected to the same pixel circuit have the same color.
  • One of the plurality of second light-emitting control lines EM2_1 to EM2_2 connected to the pixel structure is the preferred light-emitting control line, and the other second light-emitting control lines are alternate light-emitting control lines.
  • the second driving circuit 40 is specifically configured to provide an effective level signal to the first light-emitting control line EM1 and the first-select light-emitting control line connected to the pixel circuit during the light-emitting stages of the first m display periods of the pixel circuit; In the light-emitting phase of the display cycle, the active level signal is provided to the first light-emitting control line EM1 connected to the pixel circuit, the preferred light-emitting control line and at least one alternative light-emitting control line; The luminance decay curve of the device is determined.
  • one light-emitting device in the pixel structure is controlled to emit light in each display cycle, and after the cumulative display time of the display device reaches the predetermined time, in each display cycle, the control is At least two light-emitting devices in the pixel structure emit light, which can compensate for the problem that the brightness of the pixel structure decreases due to the long light-emitting time of the light-emitting devices, and prolong the service life of the display device.

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Abstract

一种像素结构及其驱动方法、显示装置，像素结构包括：像素电路和多个发光器件（21~23），像素电路具有多个显示周期，显示周期包括：第一复位阶段（t1）、数据写入阶段（t2）、第二复位阶段（t3）和发光阶段（t4），驱动方法包括：在第二复位阶段（t3），向至少一条第二复位线（Reset2_1~ Reset2_3）提供有效电平信号，以使相应的第二复位子电路（151~153）将初始化信号线（Init）上的电压写入发光器件（21~23）的第一极（S3）；在发光阶段（t4），向第一发光控制线（EM1）提供有效电平信号，并向至少一条第二发光控制线（EM2_1~ EM2_3）提供有效电平信号，以使第一发光控制子电路（13）将第一电源线（VDD）与驱动晶体管（T3）的第一极导通，至少一个第二发光控制子电路（141~143）将驱动晶体管（T3）的第二极与相应的发光器件（21~23）导通（S4）。

Description

像素结构及其驱动方法、显示装置 技术领域
本公开涉及显示技术领域，具体涉及一种像素结构及其驱动方法、显示装置。
背景技术
有源矩阵有机发光二极体面板(Active Matrix Organic Light Emitting Diode，简称：AMOLED)的应用越来越广泛。AMOLED的像素显示器件为有机发光二极管(Organic Light-Emitting Diode,简称OLED)，AMOLED中，通过驱动晶体管在饱和状态下产生驱动电流，来驱动发光器件发光。
发明内容
本公开实施例提出了一种像素结构及其驱动方法、显示装置。
第一方面，本公开实施例提供一种像素结构的驱动方法，所述像素结构包括：像素电路和多个发光器件，所述像素电路包括：驱动晶体管、存储电容、写入补偿子电路、第一复位子电路、第一发光控制子电路、多个第二发光控制子电路和多个第二复位子电路，所述存储电容的两端分别连接所述驱动晶体管的栅极和第一电源线；所述第二发光控制子电路和所述第二复位子电路均与多个所述发光器件一一对应连接；所述多个第二复位子电路分别连接多条第二复位线，所述多个第二发光控制子电路分别连接多条第二发光控制线；
所述像素电路具有多个显示周期，所述显示周期包括：第一复位阶段、数据写入阶段、第二复位阶段和发光阶段，所述驱动方法包括：
在所述第一复位阶段，向第一复位线提供有效电平信号，以使所述第一复位子电路将初始化信号线上的电压信号写入所述驱动晶体管的栅极；
在所述数据写入阶段，向扫描线提供有效电平信号，以使所述 写入补偿子电路将数据线上的电压信号写入所述驱动晶体管的第一极，并将所述驱动晶体管的栅极与第二极导通；
在所述第二复位阶段，向至少一条第二复位线提供有效电平信号，以使相应的所述第二复位子电路将所述初始化信号线上的电压写入所述发光器件的第一极；
在所述发光阶段，向第一发光控制线提供有效电平信号，并向至少一条第二发光控制线提供有效电平信号，以使所述第一发光控制子电路将第一电源线与所述驱动晶体管的第一极导通，至少一个所述第二发光控制子电路将所述驱动晶体管的第二极与相应的发光器件导通。
在一些实施例中，同一个所述像素电路所连接的多个发光器件中的至少两者的颜色不同；
所述向至少一条第二复位线提供有效电平信号，包括：向每条所述第二复位线提供有效电平信号；
所述向至少一条第二发光控制线提供有效电平信号，包括：向多条所述第二发光控制线分别提供有效电平信号。
在一些实施例中，同一个所述像素电路所连接的多个发光器件的颜色相同；
在连续的n个显示周期中的所述发光阶段，轮流向n条所述第二发光控制线提供有效电平信号；其中，n为所述像素结构中的发光器件的数量。
在一些实施例中，同一个所述像素电路所连接的多个发光器件的颜色相同；所述像素电路所连接的多条第二发光控制线的其中一条为首选发光控制线，其余的第二发光控制线为备选发光控制线；
在前m个显示周期的所述发光阶段，向所述第一发光控制线、所述首选发光控制线提供有效电平信号；在第m个之后的显示周期的所述发光阶段，向所述第一发光控制线、所述首选发光控制线和至少一条所述备选发光控制线提供有效电平信号；其中，m根据所述发光器件的亮度衰减曲线确定。
在一些实施例中，所述第一复位子电路包括：第一复位晶体管， 所述第一复位晶体管的栅极连接所述第一复位线，所述第一复位晶体管的第一极连接所述驱动晶体管的栅极，所述第一复位晶体管的第二极连接所述初始化信号线；
在所述第一复位阶段，向第一复位线提供有效电平信号，以使所述第一复位子电路将初始化信号线上的电压信号写入所述驱动晶体管的栅极，具体包括：
在所述第一复位阶段，向所述第一复位线提供有效电平信号，以使所述第一复位线的第一极和第二极导通。
在一些实施例中，所述第二复位子电路包括：第二复位晶体管，所述第二复位晶体管的栅极连接所述第二复位线，所述第二复位晶体管的第一极连接所述发光器件，所述第二复位晶体管的第二极连接所述初始化信号线；
在所述第二复位阶段，向至少一条第二复位线提供有效电平信号，以使相应的所述第二复位子电路将所述初始化信号线上的电压写入所述发光器件的第一极，具体包括：
在所述第二复位阶段，向至少一条第二复位线提供有效电平信号，以使相应的所述第二复位晶体管的第一极和第二极导通。
在一些实施例中，所述第一发光控制子电路包括：第一发光控制晶体管，所述第一发光控制晶体管的栅极连接所述第一发光控制线，所述第一发光控制晶体管的第一极连接所述第一电源线，所述第一发光控制晶体管的第二极连接所述驱动晶体管的第一极；所述第二发光控制子电路包括：第二发光控制晶体管，所述第二发光控制晶体管的栅极连接所述第二发光控制线，所述第二发光控制晶体管的第一极连接所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接所述发光器件；
在所述发光阶段，向第一发光控制线提供有效电平信号，并向至少一条第二发光控制线提供有效电平信号，以使所述第一发光控制子电路将第一电源线与所述驱动晶体管的第一极导通，至少一个所述第二发光控制子电路将所述驱动晶体管的第二极与相应的发光器件导通，具体包括：
在所述发光阶段，向所述第一发光控制线提供有效电平信号，并向至少一条第二发光控制线提供有效电平信号，以使所述第一发光控制晶体管的第一极和第二极导通，至少一个所述第二发光控制晶体管的第一极和第二极导通。
第二方面，本公开实施例还提供一种像素结构，包括：像素电路和多个发光器件，所述像素电路包括：驱动晶体管、存储电容、写入补偿子电路、第一复位子电路、第一发光控制子电路、多个第二发光控制子电路和多个第二复位子电路，所述存储电容的两端分别连接所述驱动晶体管的栅极和第一电源线；所述第二发光控制子电路和所述第二复位子电路均与多个所述发光器件一一对应连接；
所述写入补偿子电路配置为，响应于扫描线的信号的控制，将数据线上的电压信号写入所述驱动晶体管的第一极，并将所述驱动晶体管的栅极与第二极导通；
所述第一复位子电路配置为，响应于第一复位线的信号的控制，将初始化信号线上的电压信号写入所述驱动晶体管的栅极；
所述第二复位子电路配置为，响应于相应的第二复位线的信号的控制，将所述初始化信号线上的电压写入所述第二复位子电路所连接的发光器件的第一极；
所述第一发光控制子电路配置为，响应于第一发光控制线的信号的控制，将所述第一电源线与所述驱动晶体管的第一极导通；
所述第二发光控制子电路配置为，响应于相应的第二发光控制线的信号的控制，将所述驱动晶体管的第二极与所述第二发光控制子电路所连接的发光器件导通。
在一些实施例中，所述第二复位子电路包括：第二复位晶体管，所述第二复位晶体管的栅极连接所述第二复位线，所述第二复位晶体管的第一极连接所述发光器件，所述第二复位晶体管的第二极连接所述初始化信号线；
所述第二发光控制子电路包括：第二发光控制晶体管，所述第二发光控制晶体管的栅极连接所述第二发光控制线，所述第二发光控制晶体管的第一极连接所述驱动晶体管的第二极，所述第二发光控制 晶体管的第二极连接所述发光器件。
在一些实施例中，所述像素结构中的多个所述发光器件中的至少两个的发光颜色不同；或者，
所述像素结构中的多个所述发光器件的发光颜色相同。
在一些实施例中，所述像素结构中的所述发光器件的数量为两个，所述驱动晶体管的宽长比在1/8～1/12之间；或者，
所述像素结构中的所述发光器件的数量为三个，所述驱动晶体管的宽长比在1/3～1/5之间。
第三方面，本公开实施例还提供一种显示装置，包括显示基板、第一驱动电路和第二驱动电路，所述显示基板包括多个像素，至少一个所述像素中设置有权利要求8至11中任意一项所述的像素结构；
所述第一驱动电路配置为，在所述像素电路的第一复位阶段，向所述像素电路所连接的第一复位线提供有效电平信号，以使所述第一复位子电路将初始化信号线上的电压信号写入所述驱动晶体管的栅极；在所述像素电路的数据写入阶段，向所述像素电路所连接的扫描线提供有效电平信号，以使所述数据写入子电路将数据线上的电压信号写入所述驱动晶体管的第一极；以及在所述像素电路的第二复位阶段，向所述像素电路所连接的至少一条第二复位线提供有效电平信号，以使相应的所述第二复位子电路将所述初始化信号线上的电压写入所述发光器件的第一极；
所述第二驱动电路配置为，在所述像素电路的发光阶段，向所述像素电路的所连接的第一发光控制线提供有效电平信号，并向所述像素电路的所连接的至少一条第二发光控制线提供有效电平信号，以使所述第一发光控制子电路将第一电源线与所述驱动晶体管的第一极导通，至少一个所述第二发光控制子电路将所述驱动晶体管的第二极与相应的发光器件导通。
在一些实施例中，同一个所述像素电路所连接的多个发光器件中的至少两者的颜色不同；
所述第一驱动电路具体配置为，在所述第一复位阶段，向所述第一复位线提供有效电平信号；在所述数据写入阶段，向扫描线提供 有效电平信号；以及在所述像素电路的第二复位阶段，向每条第二复位线提供有效电平信号，以使相应的所述第二复位子电路将所述初始化信号线上的电压写入所述发光器件的第一极；
所述第二驱动电路具体配置为，在所述发光阶段，向第一发光控制线提供有效电平信号，并向多条第二发光控制线分别提供有效电平信号。
在一些实施例中，同一个所述像素电路所连接的多个发光器件的颜色相同；
所述第二驱动电路具体配置为，在每个显示周期的发光阶段，向所述像素电路所连接的第一发光控制线提供有效电平信号；以及在连续的n个显示周期中的所述发光阶段，轮流向所述像素电路所连接的n条第二发光控制线提供有效电平信号；其中，n为所述像素结构中的发光器件的数量。
在一些实施例中，同一个所述像素电路所连接的多个发光器件的颜色相同；所述像素结构所连接的多条第二发光控制线的其中一条为首选发光控制线，其余的第二发光控制线为备选发光控制线；
所述第二驱动电路具体配置为，在前m个显示周期的所述发光阶段，向所述第一发光控制线、所述首选发光控制线提供有效电平信号；在第m个之后的显示周期的所述发光阶段，向所述第一发光控制线、所述首选发光控制线和至少一条所述备选发光控制线提供有效电平信号；其中，m根据所述像素电路所连接的多个发光器件的亮度衰减曲线确定。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1A为示例性的一种显示基板的示意图。
图1B为本公开实施例提供的一种像素结构的结构示意图。
图1C为图1B所示的像素结构的驱动方法示意图。
图2为本公开实施例中提供的另一种像素结构的示意图。
图3为本公开实施例提供的另一种像素结构的示意图。
图4为本公开实施例中提供的像素结构的一种工作时序图。
图5为本公开实施例中提供的像素结构的另一种工作时序图。
图6为本公开实施例中提供的像素结构的再一种工作时序图。
图7为不同颜色的发光器件的亮度衰减曲线示意图。
图8为本公开实施例中提供的显示装置的整体架构示意图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
在本公开实施例中，以发光器件为发光二极管(Organic Light Emitting Diode，简称OLED)为例进行描述。发光器件的第一极为阳极，第二极则为阴极。
此外，在本公开实施例中所涉及的各个晶体管可分别独立选自多晶硅薄膜晶体管、非晶硅薄膜晶体管、氧化物薄膜晶体管以及有机薄膜晶体管中的一种。在本公开中涉及到的“第一极”具体是指晶体管的源极，相应的“第二极”具体是指晶体管的漏极。当然，本领域的技术人员应该知晓的是，该“第一极”与“第二极”可进行互换。
另外，晶体管可以划分为N型晶体管和P型晶体管，本公开中的各晶体管可分别独立选自N型晶体管或P型晶体管；在下述实施例中将以显示驱动电路中的各晶体管均为P型晶体管为例进行示例性描述，此时显示驱动电路中的晶体管可采用相同的制备工艺得以同时制备。相应地，有效电平信号为低电平信号，无效电平信号为高电平信号。
图1A为示例性的一种显示基板的示意图，如图1A所示，显示基板的显示区包括阵列排布的多个像素P，多个像素P中的每个包括像素结构，该像素结构包括像素电路和发光器件。显示区周围还设置有驱动电路，驱动电路为像素电路提供扫描信号、复位信号等信号， 像素电路根据接收到的信号为发光器件提供驱动电流。
图1B为本公开实施例提供的一种像素结构的结构示意图，如图1B所示，像素结构包括：像素电路和多个发光器件21～22，像素电路包括：驱动晶体管T3、存储电容Cs、写入补偿子电路11、第一复位子电路12、第一发光控制子电路13、多个第二发光控制子电路141～142和多个第二复位子电路151～152，存储电容Cs的两端分别连接驱动晶体管T3的栅极和第一电源线VDD；第二发光控制子电路141～142和第二复位子电路151～152均与发光器件21～22一一对应连接。例如，第二发光控制子电路141～142和第二复位子电路151～152均与相应的发光器件21～22的第一极连接，发光器件21～22的第二极连接第二电源线VSS。多个第二复位子电路151～152分别连接多条第二复位线Reset2_1～Reset2_2。多个第二发光控制子电路141～142分别连接多条第二发光控制线EM2_1～EM2_2。
写入补偿子电路11配置为，响应于扫描线Scan的信号的控制，并将所述驱动晶体管T3的栅极与第二极导通。
第一复位子电路12配置为，响应于第一复位线Reset1的信号的控制，将初始化信号线Init上的电压信号写入驱动晶体管T3的栅极，从而对驱动晶体管T3的栅极电位进行复位。
第二复位子电路151/152配置为，响应于相应的第二复位线Reset2_1/Reset2_2的信号的控制，将初始化信号线Init上的电压写入第二复位子电路151/152所连接的发光器件21/22的第一极。应当理解的是，不同的第二复位子电路151和152所连接的第二复位线Reset2_1和Reset2_1是彼此独立的。
第一发光控制子电路13配置为，响应于第一发光控制线EM1的信号的控制，将第一电源线VDD与驱动晶体管T3的第一极导通。
第二发光控制子电路141/142配置为，响应于相应的第二发光控制线EM2_1/EM2_2的信号的控制，将驱动晶体管T3的第二极与第二发光控制子电路141/142所连接的发光器件21/22导通。应当理解的是，不同的第二发光控制子电路141和142所连接的第二发光控制线EM2_1和EM2_2是彼此独立的。
在本公开实施例中，像素结构具有多个显示周期，每个显示周期即为显示基板显示一帧图像的时间段。像素结构的每个显示周期可以包括第一复位阶段、数据写入阶段、第二复位阶段、发光阶段。图1C为图1B所示的像素结构的驱动方法示意图。如图1C所示，该驱动方法包括：
在第一复位阶段，向第一复位线Reset1提供有效电平信号，以使第一复位子电路12将初始化信号线Init上的电压信号写入驱动晶体管T3的栅极，从而对驱动晶体管T3的栅极电位进行复位。
在数据写入阶段，向扫描线Scan提供有效电平信号，以使写入补偿子电路11将数据线Data上的电压信号写入驱动晶体管T3的第一极，并将驱动晶体管T3的栅极与第二极导通，从而使存储电容Cs中存储的电压与数据线Data上的电压信号和驱动晶体管T3的阈值电压有关。
在第二复位阶段，向至少一条第二复位线Reset2_1/Reset2_2提供有效电平信号，从而使得相应的第二复位子电路151/152将初始化信号线Init上的电压信号写入发光器件21/22的第一极，从而对发光器件21/22的第一极的电位进行复位。
在发光阶段，向第一发光控制线EM1提供有效电平信号，并向至少一条第二发光控制线EM2_1～EM2_2提供有效电平信号，以使第一发光控制子电路13将第一电源线VDD与驱动晶体管T3的第一极导通，至少一个第二发光控制子电路141/142将驱动晶体管T3的第二极与相应的发光器件21/22导通，从而使得驱动晶体管T3为至少一个发光器件21/22提供驱动电流。
在一些示例中，同一个像素电路所连接的发光器件中的至少两者的颜色不同，例如，发光器件21～22分别为红色发光器件和绿色发光器件；又例如，同一个像素电路同时连接一个红色发光器件、一个绿色发光器件和一个蓝色发光器件；又例如，同一个像素电路同时连接一个红色发光器件、两个绿色发光器件、一个蓝色发光器件。在这种情况下，在第二复位阶段，向每条第二复位线Reset2_1～Reset2_2提供有效电平信号，从而使得每个第二复位子电路151/152对各自对 应的发光器件21/22的第一极的电位进行复位。在发光阶段，向第一发光控制线EM1提供有效电平信号，并分别向多个第二发光控制线EM2_1～EM2_2提供有效电平信号，从而使得驱动晶体管T3为多个发光器件21～22提供驱动电流；其中，驱动晶体管T3能够输出的驱动电流的大小与存储电容Cs所存储的电压有关，即，与数据线Data上的电压信号有关；而当第二发光控制子电路141/142的导通时间足够长时，驱动晶体管T3输出的驱动电流能够全部输出至各个发光器件21/22，而当第二发光控制子电路141/142的导通时间不足时，实际流过发光器件21/22的电流的大小与第二发光控制子电路141/142的导通时间有关，因此，通过控制各条第二发光控制线EM2_1/EM2_2上加载有效电平信号的时间，可以控制流过发光器件21/22的电流大小，进而控制发光器件21/22的发光亮度。此时，同一个像素电路可以同时驱动多个发光器件21～22进行发光，从而有利于实现显示装置的高分辨率。
当然，在像素电路的每个显示周期，也可以只驱动一个发光器件21/22发光。例如，每个像素结构中的多个发光器件21～22的颜色相同，在连续的n个显示周期(即，显示连续的n帧图像时)中的发光阶段，轮流向n条第二发光控制线提供有效电平信号，从而轮流驱动多个发光器件21～22发光，这样，当显示装置的某区域长时间显示相同的图像内容时，可以控制该区域中的像素结构中的发光器件21～22轮流发光，以防止因某个区域中的发光器件21/22长时间发光而导致的显示烙印问题。
另外，由于不同颜色的发光器件的衰减曲线有所差别，因此，显示装置使用一段时间后，不同颜色的发光器件的衰减程度可能出现差异，进而容易产生色偏。而在本公开实施例的像素结构中，像素电路可以驱动多个发光器件21～22，这样，当多个发光器件21～22的发光颜色相同，且均为衰减速度最快的颜色时，可以在显示装置的累计工作时间达到预定时长之前，在每个发光阶段，利用像素电路驱动其中一个发光器件21/22发光；在显示装置的累计工作时间达到预定时长之后，在像素结构的每个发光阶段，利用像素电路驱动至少两个发 光器件21～22同时发光，从而补偿发光器件21/22的亮度衰减。
图2为本公开实施例中提供的另一种像素结构的示意图，其中，图2所示的像素结构为基于图1B所示的像素结构的一种具体化实施方案。如图2所示，在一些实施例中，写入补偿子电路11包括：数据写入晶体管T4和补偿晶体管T1，数据写入晶体管T4的栅极连接扫描线Scan，数据写入晶体管T4的第一极连接数据线Data，数据写入晶体管T4的第二极连接驱动晶体管T3的第一极。补偿晶体管T1的栅极连接扫描线Scan，补偿晶体管T1的第一极连接驱动晶体管T3的第二极，补偿晶体管T1的第二极连接驱动晶体管T3的栅极。
在一些实施例中，第一复位子电路12包括：第一复位晶体管T2，第一复位晶体管T2的栅极连接第一复位线Reset1，第一复位晶体管T2的第一极连接驱动晶体管T3的栅极，第一复位晶体管T2的第二极连接初始化信号线Init。在第一复位阶段，第一复位子电路12将初始化信号线Init上的电压信号写入驱动晶体管T3的栅极具体是指，第一复位晶体管T2的第一极和第二极导通，从而使驱动晶体管T3的栅极与初始化信号线Init导通。
在一些实施例中，第二复位子电路151/152包括：第二复位晶体管T7_1/T7_2，第二复位晶体管T7_1/T7_2的栅极连接第二复位线Reset2_1/Reset2_2，第二复位晶体管T7_1/T7_2的第一极连接发光器件21/22的第一极，第二复位晶体管T7_1/T7_2的第二极连接初始化信号线Init。在第二复位阶段，第二复位子电路151/152将初始化信号线Init上的电压信号写入发光器件21/22的第一极，具体是指，第二复位晶体管T7_1/T7_2的第一极和第二极导通，从而使发光器件21/22的第一极与初始化信号线Init导通。
在一些实施例中，第一发光控制子电路13包括：第一发光控制晶体管T5，第一发光控制晶体管T5的栅极连接第一发光控制线EM1，第一发光控制晶体管T5的第一极连接第一电源线VDD，第一发光控制晶体管T5的第二极连接驱动晶体管T3的第一极。在发光阶段，第一发光控制子电路13将第一电源线VDD与驱动晶体管T3的第一极导通，具体是指，第一发光控制晶体管T5的第一极和第二极导通， 从而使第一电源线VDD与驱动晶体管T3的第一极导通。
在一些实施例中，第二发光控制子电路141/142包括：第二发光控制晶体管T6_1/T6_2，第二发光控制晶体管T6_1/T6_2的栅极连接第二发光控制线EM2_1/EM2_2，第二发光控制晶体管T6_1/T6_2的第一极连接驱动晶体管T3的第二极，第二发光控制晶体管T6_1/T6_2的第二极连接发光器件21/22。在发光阶段，第二发光控制子电路141/142将驱动晶体管T3的第二极与相应的发光器件21/22导通，具体是指，第二发光控制晶体管T6_1/T6_2的第一极与第二极导通，从而将驱动晶体管T3的第二极与相应的发光器件21/22导通。
在一些实施例中，至少两个第二复位晶体管T7_1～T7_2构成双栅结构，从而减少像素结构所占用的空间。例如，对于图2中像素结构包括两个第二复位晶体管T7_1～T7_2的情况，则该两个第二复位晶体管T7_1～T7_2构成双栅晶体管，该双栅晶体管具有两个栅极、两个第一极和一个第二极，双栅晶体管的两个栅极分别作为两个第二复位晶体管T7_1～T7_2的栅极，双栅晶体管的两个第一极分别作为两个第二复位晶体管T7_1～T7_2的第一极，双栅晶体管的第二极同时作为两个第二复位晶体管T7_1/T7_2的第二极。
图3为本公开实施例提供的另一种像素结构的示意图，图3与图2所示的像素结构的区别仅在于：图2中，像素结构包括两个发光器件21～22、两个第二复位子电路151～152、以及两个第二发光控制子电路141～142；而图3中，像素结构包括三个发光器件21～23、三个第二复位子电路151～153、以及三个第二发光控制子电路141～143。需要说明的是，发光器件21/22/23、第二复位子电路151/152/153、第二发光控制子电路141/142/143也可以设置为其他数量，在此不做具体限制。
对于图3中所示的像素结构，也可以使其中两个第二复位晶体管T7_1～T7_2构成双栅晶体管，而另一个第二复位晶体管T7_3为单独的晶体管。
下面以图3中所示的像素结构为例，对本公开实施例中的像素结构的驱动过程进行介绍。
在一些实施例中，像素结构中的多个发光器件21～23的发光颜色可以互不相同，例如，图3中的发光器件21～23的发光颜色分别为红色、绿色和蓝色。这种情况下，像素结构的工作时序可以如图4中所示。其中，像素结构的驱动过程包括：第一复位阶段t1、数据写入阶段t2、第二复位阶段t3、发光阶段t4。
在第一复位阶段t1，向第一复位线Reset1提供有效电平信号，向扫描线Scan、第二复位线Reset2_1/Reset2_2、第一发光控制线EM1和第二发光控制线EM2_1/EM2_2提供无效电平信号。此时，第一复位晶体管T2导通，初始电压线Init上的电压信号传输至驱动晶体管T3的栅极，从而对驱动晶体管T3的栅极电位进行复位。数据写入晶体管T4、补偿晶体管T1、第一发光控制晶体管T5、第二发光控制晶体管T6_1～T6_3、第二复位晶体管T7_1～T7_3均关断。
在数据写入阶段t2，向扫描线Scan提供有效电平信号，向第一复位线Reset1、第二复位线Reset2_1～Reset2_3、第一发光控制线EM1、第二发光控制线EM2_1～EM2_3提供无效电平信号。此时，数据写入晶体管T4导通，数据线Data上的电压信号写入驱动晶体管T3的第一极；同时，补偿晶体管T1导通，从而使驱动晶体管T3的栅极与第二极短接，形成二极管结构，此时，数据线Data上的电压信号经过驱动晶体管T3和补偿晶体管T1，一直流向驱动晶体管T3的栅极，驱动晶体管T3的栅极电位达到Vdata+Vth，其中，Vth为驱动晶体管T3的阈值电压，Vdata为数据线Data上的电压。
在第二复位阶段t3，向第二复位线Reset2_1～Reset2_3均提供有效电平信号。向第一复位线Reset1、扫描线Scan、第一发光控制线EM1和第二发光控制线EM2_1～EM2_3提供无效电平信号。此时，多个第二发光控制晶体管T6_1～T6_3均导通，从而将初始信号线Init上的电压信号传输至每个发光器件21～23的第一极，以对每个发光器件21～23的第一极的电位进行复位。
在发光阶段t4，向第一复位线Reset1、第二复位线Reset2_1～Reset2_3、扫描线Scan提供无效电平信号，向第一发光控制线EM1提供有效电平信号，向多条第二发光控制线EM2_1～EM2_3 分别提供有效电平信号。需要说明的是，向多条第二发光控制线EM2_1～EM2_3提供的有效电平信号是相互独立的。此时，第一发光控制晶体管T5导通，每个第二发光控制晶体管T6_1/T6_2/T6_3在各自对应的第二发光控制线EM2_1/EM2_2/EM2_3加载有效电平时导通，从而使多个发光器件21～23均发光。具体地，在存储电容Cs的电压保持作用下，驱动晶体管T3的栅极电位保持为Vdata+Vth。当任意一个第二发光控制晶体管T6_1/T6_2/T6_3导通时，驱动晶体管T3输出驱动电流，当第二发光控制晶体管T6_1/T6_2/T6_3的导通时间达到一定时间时，流过发光器件21/22/23的驱动电流I OLED满足以下饱和电流公式：
I OLED＝K(Vgs-Vth) 2＝K(Vdata+Vth-ELVDD-Vth) 2
＝K(Vdata-ELVDD) 2
其中，K为与驱动晶体管T3本身特性有关的系数，Vgs为驱动晶体管T3的栅源电压，即，驱动晶体管T3的栅极与第一极之间的电压，ELVDD为第一电源线VDD提供的电压。
当第二发光控制晶体管T6_1/T6_2/T6_3的导通时长小于一定时间时，流过发光器件21/22/23的电流小于上述I OLED，且与I OLED和第二发光控制晶体管T6_1/T6_2的导通时间有关，因此，通过控制第二发光控制线EM2_1/EM2_2/EM2_3加载有效电平信号的时间、和上述Vdata，则可以控制通过流过发光器件21/22/23的电流大小。也就是说，在发光阶段t4，并不是持续向每条第二发光控制线EM2_1/EM2_2/EM2_3提供有效电平信号的。
在另一些实施例中，像素结构中的多个发光器件21～23的发光颜色可以相同。这种情况下，像素结构的工作时序可以如图5中所示。像素结构的工作过程同样包括：第一复位阶段t1、数据写入阶段t2、第二充电阶段t3、发光阶段t4。
在第一复位阶段t1，向第一复位线Reset1提供有效电平信号，向扫描线Scan、第二复位线Reset2_1～Reset2_3、第一发光控制线EM1和第二发光控制线EM2_1～EM2_3提供无效电平信号。此时，第一复位晶体管T2导通，初始信号线Init上的电压信号传输至驱动晶体管 T3的栅极，从而对驱动晶体管T3的栅极电位进行复位。数据写入晶体管T4、补偿晶体管T1、第一发光控制晶体管T5、第二发光控制晶体管T6_1～T6_3、第二复位晶体管T7_1～T7_3均关断。
在数据写入阶段t2，向扫描线Scan提供有效电平信号，向第一复位线Reset1、第二复位线Reset2_1～Reset2_3、第一发光控制线EM1和第二发光控制线EM2_1～EM2_3提供无效电平信号。此时，数据写入晶体管T4导通，数据线Data上的电压信号写入驱动晶体管T3的第一极；同时，补偿晶体管T1导通，从而使驱动晶体管T3的栅极与第二极短接，形成二极管结构，此时，数据线Data上的电压信号经过驱动晶体管T3和补偿晶体管T1，一直流向驱动晶体管T3的栅极，驱动晶体管T3的栅极电位达到Vdata+Vth，其中，Vth为驱动晶体管T3的阈值电压，Vdata为数据线Data上的电压。
在第二复位阶段t3，向至少一条第二复位线Reset2_1提供有效电平信号，向第一复位线Reset1、扫描线Scan、第一发光控制线EM1和第二发光控制线EM2_1～EM2_3提供无效电平信号。此时，至少第二复位晶体管T7_1导通，从而将初始信号线Init上的电压信号至少传输至发光器件21的第一极，以至少对其中一个发光器件21的第一极的电位进行复位。
在发光阶段t4，向第一复位线Reset1、第二复位线Reset2_1～Reset2_3、扫描线Scan提供无效电平信号，向第一发光控制线EM1和其中一条第二发光控制线EM2_1持续提供有效电平信号。此时，第一发光控制晶体管T5导通，其中一个第二发光控制晶体管T6_1导通。在存储电容Cs的电压保持作用下，驱动晶体管T3的栅极电位保持为Vdata+Vth。驱动晶体管T3输出至相应的发光器件21的电流达到上述驱动电流I OLED。
其中，在每个显示周期，像素结构的工作过程均包括上述四个阶段，而在连续的三个(第i个～第i+2个)显示周期中的发光阶段，可以轮流向三条第二发光控制线EM2_1～EM2_3提供有效电平信号，从而使得像素结构中的三个发光器件21～23在三个显示周期轮流工作，以防止单个发光器件21/22/23长时间工作而导致显示画面出现 烙印。其中，显示周期可以为一帧显示画面的显示阶段，当然，也可以为两帧或其他数量帧的显示画面的显示阶段。
需要说明的是，在图5中的第二复位阶段t3，向每个第二复位线Reset2_1～Reset2_3提供有效电平信号，但实际上，不一定要向所有的第二复位线Reset2_1～Reset2_3均提供有效电平信号。例如，若在第i个显示周期的发光阶段向第二发光控制线EM2_1提供有效电平信号来控制发光器件21发光，那么在第i个显示周期的复位阶段t3，至少向发光器件21对应的第二复位线Reset2_1提供有效电平信号。若在第i+1个显示周期的发光阶段t4，向第二发光控制线EM2_2提供有效电平信号来控制发光器件22发光，则在第i+1个显示周期的复位阶段t3，至少向发光器件22对应的第二复位线Reset2_2提供有效电平信号。
还需要说明的是，图5中所示的工作时序是以图3中的像素结构为例进行说明的，像素结构中发光器件的数量也可以为其他数量，只需要在连续的n个显示周期中的发光阶段，轮流向n条第二发光控制线提供有效电平信号，使n个发光器件在n个显示周期轮流发光即可。其中，n为像素结构中的发光器件的数量。
对于像素结构中的多个发光器件21～23的发光颜色相同的情况，像素结构的工作时序还可以如图6中所示。
和图5中的工作时序相同的，在第一复位阶段t1，向第一复位线Reset1提供有效电平信号，向扫描线Scan、第二复位线Reset2_1～Reset2_3、第一发光控制线EM1和第二发光控制线EM2_1～EM2_3提供无效电平信号，第一复位晶体管T2导通，对驱动晶体管T3的栅极电位进行复位。在数据写入阶段t2，向扫描线Scan提供有效电平信号，向第一复位线Reset1、第二复位线Reset2_1～Reset2_3、第一发光控制晶体管T5和第二发光控制晶体管T6_1～T6_3提供无效电平信号。驱动晶体管T3的栅极电位达到Vdata+Vth。在第二复位阶段t3，向至少一条第二复位线Reset2_1/Reset2_2/Reset2_3提供有效电平信号，初始信号线Init上的电压信号传输至相应的发光器件21/22/23的第一极，以对至少一个 发光器件21/22/23的第一极的电位进行复位。
将图3中的像素结构所连接的其中一条第二发光控制线EM2_1作为首选发光控制线，将其余的第二发光控制线EM2_2～EM2_3作为备选发光控制线。图6与图5中的工作过程有所区别的是，如图6所示，在前m个显示周期的发光阶段t4，向第一复位线Reset1、第二复位线Reset2_1～Reset2_3、扫描线Scan均提供无效电平信号，向第一发光控制线EM1和第二发光控制线EM2_1(即首选发光控制线)提供有效电平信号。此时，第一发光控制晶体管T5导通，第二发光控制晶体管T6_1导通，从而为发光器件21提供驱动电流。而由于经过m个显示周期之后，发光器件21的亮度有所衰减，因此，在第m+1个及之后的显示周期的发光阶段t4，可以控制另外的发光器件22和/或23发光，来补偿发光器件21的亮度衰减。具体地，在第m+1个及之后的显示周期的发光阶段t4，向第一复位线Reset1、第二复位线Reset2_1～Reset2_3、扫描线Scan提供无效电平信号，向第一发光控制线EM1、和至少一条备选发光控制线(即EM2_2和EM2_3中的至少一者)提供有效电平信号。此时，第一发光控制晶体管T5导通，第二发光控制晶体管T6_1导通，第二发光控制晶体管T6_2和/T6_3中的至少一者导通，从而控制发光器件22和23中的至少一者以及发光器件21发光。其中，向备选发光控制线提供有效电平信号的持续时间可以根据发光器件22/23所需要的亮度确定。
其中，对于任意一个显示周期，若需要控制某一个或多个发光器件在发光阶段t4发光，则在第二复位阶段t3，向待发光的发光器件所对应的第二复位线提供有效电平信号，以对待发光的发光器件的第一极的电位进行复位。
其中，前m个显示周期可以为像素结构累计工作的前m个显示周期，也即显示装置累计显示的前m个显示周期，m的大小可以根据发光器件的亮度衰减曲线确定。例如，在显示装置中，可以设置有第一颜色(例如，蓝色)的子像素、第二颜色(例如，红色)的子像素和第三颜色(例如，绿色)的子像素，图7为不同颜色的发光器件的亮度衰减曲线示意图，如图7所示，第一颜色的发光器件的衰减速 度大于第二颜色的发光器件的衰减速度和第二颜色的发光器件的衰减速度，这种情况下，可以在第一颜色的子像素中设置上述像素结构，若第一颜色的发光器件的亮度衰减程度与其他颜色的亮度衰减程度之间的差值达到预设值时，第一颜色的发光器件的累计工作时间为time1，则m为显示装置的累计显示时间为time1时所对应的显示周期数量。当然，也可以在第一颜色和第二颜色的子像素中均设置上述像素结构。例如，如图7所示，当驱动时间达到500小时(hr)后，第一颜色和第二颜色的发光器件的发光亮度会明显衰减，对于这种情况，可以在显示装置的累计显示时间达到500小时后，在第一颜色子像素中的像素电路的发光阶段，控制该像素电路中的至少两个第一颜色的发光器件同时发光；在第二颜色的子像素中的像素电路的发光阶段，控制该像素电路中的至少两个第二颜色的发光器件同时发光。
在一些实施例中，可以通过调节驱动晶体管T3的宽长比来提高驱动晶体管T3能够输出的驱动电流值，从而满足两个甚至更多的发光器件同时发光的需求。在一些示例中，同一个像素电路所连接的发光器件的数量为两个，驱动晶体管T3的宽长比在1/8～1/12之间，例如为3/30时，驱动晶体管T3可输出的电流值为200nA；在另一些示例中，同一个像素电路所连接的发光器件的数量为三个，驱动晶体管的宽长比在1/3～1/5之间，例如，驱动晶体管T3的宽长比为5/20，驱动晶体管T3可输出的电流值可以达到300nA。另外，可以增大第一电源线VDD与第二电源线VSS之间的电压差，来进一步提高驱动晶体管T3能够输出的驱动电流，例如，第一电源线VDD的电压在4～5V之间，例如为4.6V；第二电源线VSS的电压在-4V～-6V之间，例如为-5V。
需要说明的是，在上述实施例中，均以像素结构的工作过程包括两个复位阶段(即，第一复位阶段t1和第二复位阶段t3)为例进行说明，而实际上，像素结构的第一复位阶段t1和第二复位阶段t3可以合并，即，在数据写入阶段t2之前，同时向第一复位线Reset1和至少一条第二复位线Reset2_1/Reset2_2/Reset2_3提供有效电平信号。
本公开实施例还提供一种显示装置，图8为本公开实施例中提供的显示装置的整体架构示意图，如图8所示，显示装置包括显示基板、第一驱动电路30和第二驱动电路40。显示基板包括显示区DA和位于该显示区DA周边的周边区，第一驱动电路30和第二驱动电路40可以设置在显示基板的周边区。显示区DA包括阵列排布的多个像素P，至少一个像素P中设置有上述实施例中的像素结构。同一个像素结构中的多个发光器件可以沿行方向排列，也可以沿列方向排列。
在一些实施例中，每个像素P中均设置有上述实施例中的像素结构，同一行像素结构所连接的扫描线Scan为同一条，同一行像素结构所连接的第一复位线为同一条，同一行像素结构所连接的第二复位线为同一条，同一行像素结构所连接的第一发光控制线EM1为同一条。以像素结构中的发光器件的数量为两个为例，则同一行像素结构所连接的第二发光控制线EM2_1为同一条，同一行像素结构所连接的第二发光控制线EM2_2为同一条。同一列像素结构所连接的数据线为同一条。多列像素结构所连接的数据线Data1～DataM与数据驱动电路50连接，从而接收数据驱动电路50所提供的数据电压信号。
第一驱动电路30配置为：在像素电路的第一复位阶段，向像素电路所连接的第一复位线提供有效电平信号，以使第一复位子电路将初始化信号线上的电压信号写入驱动晶体管的栅极；在像素电路的数据写入阶段，向像素电路所连接的扫描线提供有效电平信号，以使数据写入子电路将数据线上的电压信号写入驱动晶体管的第一极；以及在像素电路的第二复位阶段，向像素电路所连接的至少一条第二复位线提供有效电平信号，以使相应的第二复位子电路将初始化信号线上的电压写入发光器件的第一极。
可选地，第一驱动电路30具体可以包括多个级联的栅极驱动单元，例如，如图8所示，第一驱动电路30包括：第一级栅极驱动单元S_1、第二级栅极驱动单元S_2、第三级栅极驱动单元S_3……第N-1级栅极驱动单元S_N-1、第N级栅极驱动单元S_N。第一级栅极驱动单元S_1与第一行像素电路所连接的扫描线连接，用于在第一 行像素电路的数据写入阶段为第一行像素电路提供处于有效电平状态的扫描信号；同时，第一级栅极驱动电路S_1与第二行像素电路所连接的第一复位线连接，从而在第二行像素电路的第一复位阶段，为第二行像素电路提供处于有效电平状态的第一复位信号。第二级栅极驱动单元S_2与第二行像素电路所连接的扫描线连接，用于在第二行像素电路的数据写入阶段，为第二行像素电路提供处于有效电平状态的扫描信号；同时，第二级栅极驱动单元S_2与第一行像素结构所连接的第二复位线和第三行像素电路所连接的第一复位线连接，从而在第一行像素电路的第二复位阶段，为第一行像素电路提供处于有效电平状态的第二复位信号；以及在第三行像素电路的第一复位阶段，为第一行像素电路提供处于有效电平状态的第一复位信号。第N-1级栅极驱动单元S_N-1与第N-1行像素电路所连接的扫描线连接，从而在第N-1行像素电路的数据写入阶段，为第N-1行像素电路提供处于有效电平状态的扫描信号；同时，第N-1级栅极驱动单元S_N-1与第N-2行像素电路所连接的第二复位线和第N行像素电路所连接的第一复位线连接，从而在第N-2行像素电路的第二复位阶段，为第N-2行像素电路提供处于有效电平状态的第二复位信号；并在第N行像素电路的第一复位阶段，为第N行像素电路提供处于有效电平状态的第一复位信号。第N级栅极驱动单元S_N与第N行像素电路所连接的扫描线连接，从而在第N行像素电路的数据写入阶段，为第N行像素电路提供处于有效电平状态的扫描信号；同时，第N级栅极驱动单元S_N与第N-1行像素电路所连接的第二复位线连接，从而在第N-1行像素电路的第二复位阶段，为第N-1行像素电路提供处于有效电平状态的第二复位信号。
第二驱动电路40配置为：在像素电路的发光阶段，向像素电路的所连接的第一发光控制线EM1提供有效电平信号，并向像素电路的所连接的至少一条第二发光控制线EM2_1/EM2_2提供有效电平信号，以使第一发光控制子电路将第一电源线与驱动晶体管的第一极导通，至少一个第二发光控制子电路将驱动晶体管的第二极与相应的发光器件导通。
可选地，第二驱动电路40可以包括第一移位寄存器41和多个第二移位寄存器42_1～42_2，第二移位寄存器42_1/42_2与同一行像素电路所连接的第二发光控制线EM2_1/EM2_2一一对应。下面以同一行像素电路连接两条第二发光控制线EM2_1～EM2_2为例对第二驱动电路40的结构进行介绍。
第一移位寄存器41包括多个级联的第一移位寄存单元G1_1～G1_N，每个第一移位寄存单元G1_1～G1_N连接一条第一发光控制线EM 1。如图8所示，第一级第一移位寄存单元G1_1与第一行像素电路所连接的第一发光控制线EM 1相连，第二级第一移位寄存单元G1_2与第二行像素电路所连接的第一发光控制线EM 1相连，以此类推，第N级第一移位寄存单元G1_N与第N行像素电路所连接的第一发光控制线EM 1相连。第二移位寄存器42_1包括多个级联的第二移位寄存单元G21_1～G21_N，第二移位寄存器42_2包括多个级联的第二移位寄存单元G22_1～G22_N。第一级第二移位寄存单元G21_1和第一级第二移位寄存单元G22_1分别与第一行像素电路所连接的两条第二发光控制线EM2_1～EM2_2连接；第二级第二移位寄存单元G21_2和第二级第二移位寄存单元G22_2分别与第二行像素电路所连接的两条第二发光控制线EM2_1～EM2_2连接；以此类推，第N级第二移位寄存单元G21_N和第N级第二移位寄存单元G22_N分别与第N行像素电路所连接的两条第二发光控制线EM2_1～EM2_2连接。
在一些实施例中，同一个像素电路所连接的多个发光器件中的至少两者的颜色不同。第一驱动电路30具体配置为，在像素电路的第一复位阶段，向像素电路所连接的第一复位线提供有效电平信号；在像素电路的数据写入阶段，向像素电路所连接的扫描线提供有效电平信号；以及在像素电路的第二复位阶段，向像素电路所连接的每条第二复位线提供有效电平信号，以使相应的第二复位子电路将所述初始化信号线上的电压写入所述发光器件的第一极。第二驱动电路40具体配置为，在像素电路的发光阶段，向像素电路所连接的第一发光控制线EM1提供有效电平信号，并向像素电路所连接的多条第二发 光控制线EM2_1～EM2_2分别提供有效电平信号。
这种情况下，多个发光器件可以分别作为像素的多个子像素，而由于像素结构中的多个发光器件共用一个像素电路，因此，有利于提高显示装置的分辨率。
在另一些实施例中，同一个像素电路所连接的多个发光器件的颜色相同。第二驱动电路40具体配置为，在像素电路的每个显示周期的发光阶段，向像素电路所连接的第一发光控制线EM1提供有效电平信号；以及在连续的n个显示周期中的发光阶段，轮流向像素电路所连接的n条第二发光控制线提供有效电平信号。其中，n为所述像素结构中的发光器件的数量。
例如，当显示装置的控制电路判断出显示基板在连续显示多帧画面时，某一区域中的画面保持不变，此时，控制电路可以向第二驱动电路40发送控制信号，第二驱动电路40根据该控制信号控制该区域中的每个像素结构中的多个发光器件在连续的多个显示周期轮流发光，从而改善显示烙印的问题。
在另一些实施例中，同一个像素电路所连接的多个发光器件的颜色相同。像素结构所连接的多条第二发光控制线EM2_1～EM2_2的其中一条为首选发光控制线，其余的第二发光控制线为备选发光控制线。第二驱动电路40具体配置为，在像素电路的前m个显示周期的发光阶段，向像素电路所连接的第一发光控制线EM1、首选发光控制线提供有效电平信号；在第m个之后的显示周期的发光阶段，向像素电路所连接的第一发光控制线EM1、首选发光控制线和至少一条备选发光控制线提供有效电平信号；其中，m根据像素电路所连接的多个发光器件的亮度衰减曲线确定。
也就是说，在显示装置累计显示时长达到预定时长之前，在每个显示周期中控制像素结构中的一个发光器件发光，而在显示装置累计显示时长达到预定时长之后，在每个显示周期，控制像素结构中的至少两个发光器件发光，这样可以补偿发光器件因发光时间较长而导致的像素结构亮度降低的问题，延长显示装置的使用寿命。
像素结构的具体驱动过程已在上文进行介绍，这里不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (15)

  1. 一种像素结构的驱动方法，所述像素结构包括：像素电路和多个发光器件，所述像素电路包括：驱动晶体管、存储电容、写入补偿子电路、第一复位子电路、第一发光控制子电路、多个第二发光控制子电路和多个第二复位子电路，所述存储电容的两端分别连接所述驱动晶体管的栅极和第一电源线；所述第二发光控制子电路和所述第二复位子电路均与多个所述发光器件一一对应连接；所述多个第二复位子电路分别连接多条第二复位线，所述多个第二发光控制子电路分别连接多条第二发光控制线；
    所述像素电路具有多个显示周期，所述显示周期包括：第一复位阶段、数据写入阶段、第二复位阶段和发光阶段，所述驱动方法包括：
    在所述第一复位阶段，向第一复位线提供有效电平信号，以使所述第一复位子电路将初始化信号线上的电压信号写入所述驱动晶体管的栅极；
    在所述数据写入阶段，向扫描线提供有效电平信号，以使所述写入补偿子电路将数据线上的电压信号写入所述驱动晶体管的第一极，并将所述驱动晶体管的栅极与第二极导通；
    在所述第二复位阶段，向至少一条第二复位线提供有效电平信号，以使相应的所述第二复位子电路将所述初始化信号线上的电压写入所述发光器件的第一极；
    在所述发光阶段，向第一发光控制线提供有效电平信号，并向至少一条第二发光控制线提供有效电平信号，以使所述第一发光控制子电路将第一电源线与所述驱动晶体管的第一极导通，至少一个所述第二发光控制子电路将所述驱动晶体管的第二极与相应的发光器件导通。
  2. 根据权利要求1所述的驱动方法，其中，同一个所述像素电路所连接的多个发光器件中的至少两者的颜色不同；
    所述向至少一条第二复位线提供有效电平信号，包括：向每条所述第二复位线提供有效电平信号；
    所述向至少一条第二发光控制线提供有效电平信号，包括：向多条所述第二发光控制线分别提供有效电平信号。
  3. 根据权利要求1所述的驱动方法，其中，同一个所述像素电路所连接的多个发光器件的颜色相同；
    在连续的n个显示周期中的所述发光阶段，轮流向n条所述第二发光控制线提供有效电平信号；其中，n为所述像素结构中的发光器件的数量。
  4. 根据权利要求1所述的驱动方法，其中，同一个所述像素电路所连接的多个发光器件的颜色相同；所述像素结构所连接的多条第二发光控制线的其中一条为首选发光控制线，其余的第二发光控制线为备选发光控制线；
    在前m个显示周期的所述发光阶段，向所述第一发光控制线、所述首选发光控制线提供有效电平信号；在第m个之后的显示周期的所述发光阶段，向所述第一发光控制线、所述首选发光控制线和至少一条所述备选发光控制线提供有效电平信号；其中，m根据所述发光器件的亮度衰减曲线确定。
  5. 根据权利要求1至4中任意一项所述的驱动方法，其中，所述第一复位子电路包括：第一复位晶体管，所述第一复位晶体管的栅极连接所述第一复位线，所述第一复位晶体管的第一极连接所述驱动晶体管的栅极，所述第一复位晶体管的第二极连接所述初始化信号线；
    在所述第一复位阶段，向第一复位线提供有效电平信号，以使所述第一复位子电路将初始化信号线上的电压信号写入所述驱动晶体管的栅极，具体包括：
    在所述第一复位阶段，向所述第一复位线提供有效电平信号，以使所述第一复位线的第一极和第二极导通。
  6. 根据权利要求1至4中任意一项所述的驱动方法，其中，所述第二复位子电路包括：第二复位晶体管，所述第二复位晶体管的栅极连接所述第二复位线，所述第二复位晶体管的第一极连接所述发光器件，所述第二复位晶体管的第二极连接所述初始化信号线；
    在所述第二复位阶段，向至少一条第二复位线提供有效电平信号，以使相应的所述第二复位子电路将所述初始化信号线上的电压写入所述发光器件的第一极，具体包括：
    在所述第二复位阶段，向至少一条第二复位线提供有效电平信号，以使相应的所述第二复位晶体管的第一极和第二极导通。
  7. 根据权利要求1至4中任意一项所述的驱动方法，其中，所述第一发光控制子电路包括：第一发光控制晶体管，所述第一发光控制晶体管的栅极连接所述第一发光控制线，所述第一发光控制晶体管的第一极连接所述第一电源线，所述第一发光控制晶体管的第二极连接所述驱动晶体管的第一极；所述第二发光控制子电路包括：第二发光控制晶体管，所述第二发光控制晶体管的栅极连接所述第二发光控制线，所述第二发光控制晶体管的第一极连接所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接所述发光器件；
    在所述发光阶段，向第一发光控制线提供有效电平信号，并向至少一条第二发光控制线提供有效电平信号，以使所述第一发光控制子电路将第一电源线与所述驱动晶体管的第一极导通，至少一个所述第二发光控制子电路将所述驱动晶体管的第二极与相应的发光器件导通，具体包括：
    在所述发光阶段，向所述第一发光控制线提供有效电平信号，并向至少一条第二发光控制线提供有效电平信号，以使所述第一发光控制晶体管的第一极和第二极导通，至少一个所述第二发光控制晶体管的第一极和第二极导通。
  8. 一种像素结构，包括：像素电路和多个发光器件，所述像素 电路包括：驱动晶体管、存储电容、写入补偿子电路、第一复位子电路、第一发光控制子电路、多个第二发光控制子电路和多个第二复位子电路，所述存储电容的两端分别连接所述驱动晶体管的栅极和第一电源线；所述第二发光控制子电路和所述第二复位子电路均与多个所述发光器件一一对应连接；
    所述写入补偿子电路配置为，响应于扫描线的信号的控制，将数据线上的电压信号写入所述驱动晶体管的第一极，并将所述驱动晶体管的栅极与第二极导通；
    所述第一复位子电路配置为，响应于第一复位线的信号的控制，将初始化信号线上的电压信号写入所述驱动晶体管的栅极；
    所述第二复位子电路配置为，响应于相应的第二复位线的信号的控制，将所述初始化信号线上的电压写入所述第二复位子电路所连接的发光器件的第一极；
    所述第一发光控制子电路配置为，响应于第一发光控制线的信号的控制，将所述第一电源线与所述驱动晶体管的第一极导通；
    所述第二发光控制子电路配置为，响应于相应的第二发光控制线的信号的控制，将所述驱动晶体管的第二极与所述第二发光控制子电路所连接的发光器件导通。
  9. 根据权利要求8所述的像素结构，其中，所述第二复位子电路包括：第二复位晶体管，所述第二复位晶体管的栅极连接所述第二复位线，所述第二复位晶体管的第一极连接所述发光器件，所述第二复位晶体管的第二极连接所述初始化信号线；
    所述第二发光控制子电路包括：第二发光控制晶体管，所述第二发光控制晶体管的栅极连接所述第二发光控制线，所述第二发光控制晶体管的第一极连接所述驱动晶体管的第二极，所述第二发光控制晶体管的第二极连接所述发光器件。
  10. 根据权利要求8或9中任意一项所述的像素结构，其中，所述像素结构中的多个所述发光器件中的至少两个的发光颜色不同； 或者，
    所述像素结构中的多个所述发光器件的发光颜色相同。
  11. 根据权利要求8或9所述的像素结构，其中，所述像素结构中的所述发光器件的数量为两个，所述驱动晶体管的宽长比在1/8～1/12之间；或者，
    所述像素结构中的所述发光器件的数量为三个，所述驱动晶体管的宽长比在1/3～1/5之间。
  12. 一种显示装置，包括显示基板、第一驱动电路和第二驱动电路，所述显示基板包括多个像素，至少一个所述像素中设置有权利要求8至11中任意一项所述的像素结构；
    所述第一驱动电路配置为，在所述像素电路的第一复位阶段，向所述像素电路所连接的第一复位线提供有效电平信号，以使所述第一复位子电路将初始化信号线上的电压信号写入所述驱动晶体管的栅极；在所述像素电路的数据写入阶段，向所述像素电路所连接的扫描线提供有效电平信号，以使所述数据写入子电路将数据线上的电压信号写入所述驱动晶体管的第一极；以及在所述像素电路的第二复位阶段，向所述像素电路所连接的至少一条第二复位线提供有效电平信号，以使相应的所述第二复位子电路将所述初始化信号线上的电压写入所述发光器件的第一极；
    所述第二驱动电路配置为，在所述像素电路的发光阶段，向所述像素电路的所连接的第一发光控制线提供有效电平信号，并向所述像素电路的所连接的至少一条第二发光控制线提供有效电平信号，以使所述第一发光控制子电路将第一电源线与所述驱动晶体管的第一极导通，至少一个所述第二发光控制子电路将所述驱动晶体管的第二极与相应的发光器件导通。
  13. 根据权利要求12所述的显示装置，其中，同一个所述像素电路所连接的多个发光器件中的至少两者的颜色不同；
    所述第一驱动电路具体配置为，在所述第一复位阶段，向所述第一复位线提供有效电平信号；在所述数据写入阶段，向扫描线提供有效电平信号；以及在所述像素电路的第二复位阶段，向每条第二复位线提供有效电平信号，以使相应的所述第二复位子电路将所述初始化信号线上的电压写入所述发光器件的第一极；
    所述第二驱动电路具体配置为，在所述发光阶段，向第一发光控制线提供有效电平信号，并向多条第二发光控制线分别提供有效电平信号。
  14. 根据权利要求12所述的显示装置，其中，同一个所述像素电路所连接的多个发光器件的颜色相同；
    所述第二驱动电路具体配置为，在每个显示周期的发光阶段，向所述像素电路所连接的第一发光控制线提供有效电平信号；以及在连续的n个显示周期中的所述发光阶段，轮流向所述像素电路所连接的n条第二发光控制线提供有效电平信号；其中，n为所述像素结构中的发光器件的数量。
  15. 根据权利要求12所述的显示装置，其中，同一个所述像素电路所连接的多个发光器件的颜色相同；所述像素电路所连接的多条第二发光控制线的其中一条为首选发光控制线，其余的第二发光控制线为备选发光控制线；
    所述第二驱动电路具体配置为，在前m个显示周期的所述发光阶段，向所述第一发光控制线、所述首选发光控制线提供有效电平信号；在第m个之后的显示周期的所述发光阶段，向所述第一发光控制线、所述首选发光控制线和至少一条所述备选发光控制线提供有效电平信号；其中，m根据所述像素电路所连接的多个发光器件的亮度衰减曲线确定。
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