WO2022048224A1 - 金属连线的制备方法 - Google Patents

金属连线的制备方法 Download PDF

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Publication number
WO2022048224A1
WO2022048224A1 PCT/CN2021/098965 CN2021098965W WO2022048224A1 WO 2022048224 A1 WO2022048224 A1 WO 2022048224A1 CN 2021098965 W CN2021098965 W CN 2021098965W WO 2022048224 A1 WO2022048224 A1 WO 2022048224A1
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Prior art keywords
substrate
metal
conductive structure
oxide layer
hydrogen
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PCT/CN2021/098965
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English (en)
French (fr)
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郗宁
潘俊波
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长鑫存储技术有限公司
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Priority to EP21863293.3A priority Critical patent/EP4068340A4/en
Priority to US17/603,497 priority patent/US20230055179A1/en
Publication of WO2022048224A1 publication Critical patent/WO2022048224A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4864—Cleaning, e.g. removing of solder
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer

Definitions

  • the present disclosure relates to the technical field of semiconductor preparation, and in particular, to a preparation method of a metal connection.
  • a plasma process is used in the chip fabrication process. After the substrate is etched by the plasma, there are usually residual charges on the metal connection lines of the substrate. The residual charge will affect the performance of the semiconductor device, and in severe cases, arc discharge will occur during the chip manufacturing process, thereby causing the chip to be scrapped.
  • a main objective of the present disclosure is to provide a method for preparing a metal wire, which can effectively remove residual charges on the surface of a substrate without damaging the surface of the substrate.
  • a method for preparing a metal connection includes: providing a substrate, wherein the substrate includes a metal conductive structure; patterning and etching the substrate to expose the metal conductive structure the surface of the structure; the surface of the substrate is treated with oxygen-containing plasma to remove the electric charge on the surface of the metal conductive structure; the surface of the metal conductive structure is cleaned with hydrogen gas.
  • a metal oxide layer is formed on the surface of the substrate.
  • the hydrogen gas is hydrogen plasma to reduce the metal oxide layer.
  • the temperature at which the hydrogen plasma reduces the metal oxide layer is 15°C to 35°C.
  • the environment in which the substrate is located is evacuated before the metal oxide layer is reduced by the hydrogen plasma.
  • the hydrogen gas is hydrogen gas in a high temperature environment to reduce the metal oxide layer, and the high temperature has a temperature of 500°C to 1100°C.
  • the thickness of the metal oxide layer is less than 1 nm.
  • the temperature of the oxygen-containing plasma for etching the substrate is 15°C to 35°C.
  • the environment in which the substrate is located is evacuated before the surface of the substrate is treated with the oxygen-containing plasma.
  • forming the substrate includes: forming a first insulating layer, the metal conductive structure and a capping layer sequentially stacked on the substrate; forming a hard mask on the capping layer film layer.
  • the present disclosure has at least one of the following advantages and positive effects:
  • oxygen-containing plasma to treat the surface of the substrate can neutralize the charges on the surface of the conductive structure, and cleaning the surface of the conductive structure with hydrogen can completely remove the neutralized charges and other impurities without damaging the surface of the substrate.
  • Fig. 1 is a schematic diagram of residual charge attached to a substrate in the prior art
  • Fig. 2 is the schematic diagram of the substrate after utilizing hydrogen and nitrogen to remove residual charge on the substrate in the prior art
  • FIG. 3 is a schematic diagram of treating a substrate with residual electrical charge using an oxygen-containing plasma according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of forming a metal oxide layer after a substrate surface in an embodiment of the disclosure
  • FIG. 5 is a schematic diagram of using hydrogen to reduce a metal oxide layer according to an embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a substrate after the oxide layer is reduced in an embodiment of the disclosure.
  • FIG. 7 is a schematic diagram of treating a substrate with residual charge using an oxygen-containing plasma according to another embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of forming a metal oxide layer after a substrate surface in another embodiment of the disclosure.
  • FIG. 9 is a schematic diagram of using hydrogen to reduce a metal oxide layer according to another embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a substrate after the oxide layer is reduced according to another embodiment of the disclosure.
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • FIG. 1 shows a schematic diagram of the residual charge on the semiconductor substrate 1 .
  • technicians have tried to prevent the substrate 1 from being oxidized by removing the residual charges by plasma of a mixed gas of hydrogen and nitrogen.
  • this method is easy to damage the surface of the substrate 1, so that defects are formed on the surface of the substrate 1.
  • the present disclosure provides a method for preparing a metal interconnection, which is used for preparing the metal interconnection in a semiconductor.
  • the preparation method of the metal connection includes: forming an insulating layer 12 and a metal conductive structure stacked in sequence on the semiconductor substrate 11, forming a hard mask layer on the metal conductive structure, forming a photoresist layer on the hard mask layer, By etching the photoresist, a pattern is formed, and the pattern is transferred to the hard mask layer. Using the pattern of the hard mask layer, the metal conductive structure is etched through an etching process to form a metal connection, and then the hard mask layer is removed.
  • Another insulating layer 12 is formed on the semiconductor substrate 11 including the metal wirings to insulate the metal wirings from each other.
  • predetermined isolation layers, transistors, source contact plugs, etc. can be formed on the substrate 11, then an insulating layer 12 is formed thereon, and then the insulating layer 12 is etched to form contact holes (not shown in the figure) .
  • an ion implantation process is performed to form a junction region in the semiconductor substrate 11 .
  • a metal barrier layer is formed in the contact hole, and then a conductive layer is formed on the semiconductor substrate 11 including the contact hole to fill the contact hole (not shown in the figure).
  • a metal conductive structure is sequentially formed on the insulating layer 12, wherein the metal conductive structure may include a metal conductive layer and a barrier metal layer.
  • a hard mask layer and a photoresist layer are formed on the metal conductive structure.
  • the photoresist layer is etched through an exposure process and a development process to form a photoresist pattern, and then the hard mask layer is etched through the photoresist pattern as an etching mask.
  • the metal conductive structures are etched using the photoresist pattern and the etched hard mask layer as an etch mask to form metal lines.
  • the hard mask layer is usually formed of an amorphous carbon layer and a silicon oxynitride layer.
  • the metallic conductive structure may be formed of metallic tungsten.
  • the etching process may be a plasma process.
  • the other insulating layer may be formed by a sputtering method, and the other edge layer is preferably formed of a high density plasma (HDP) oxide layer.
  • HDP high density plasma
  • the method for preparing a metal interconnection disclosed in the present disclosure can effectively remove residual impurities and charges 2 on the substrate 1 after the semiconductor device is etched.
  • the method of the present disclosure includes: providing the above-mentioned substrate 1, which contains a metal conductive structure; patterning and etching the substrate 1 to expose the surface of the metal conductive structure; and treating the surface of the substrate 1 with oxygen-containing plasma to remove charges on the surface of the conductive structure 2; Use hydrogen to clean the surface of the metal conductive structure.
  • oxygen-containing plasma to treat the surface of the substrate 1 can neutralize the charges 2 on the surface of the conductive structure, and cleaning the surface of the conductive structure with hydrogen can completely remove the charges 2 and other impurities without damaging the surface of the substrate 1 .
  • FIG. 3 to FIG. 6 are schematic structural diagrams of a substrate 1 , respectively.
  • the substrate 1 includes a substrate 11 , an insulating layer 12 and a metal conductive structure layer 13 .
  • the metal conductive structure layer 13 in this embodiment has not been etched by the hard mask layer, but is only exposed on the substrate 1 . As shown in FIG. 3 , charges are likely to remain on the surface of the exposed metal conductive structure layer 13 .
  • FIG. 3 shows a schematic diagram of treating a substrate 1 with residual electric charge 2 by using an oxygen-containing plasma in the method of the present disclosure
  • FIG. 4 shows using an oxygen-containing plasma to treat a metal conductive
  • FIG. 5 shows a schematic diagram of reducing the metal oxide layer 3 with hydrogen
  • FIG. 6 shows a schematic diagram of the substrate 1 after the metal oxide layer 3 is reduced , a schematic view of the surface of the substrate 1 after removing the residual charge 2 on the surface of the metal conductive structure layer 13 .
  • the method of the present disclosure combined with each schematic diagram is as follows: as shown in FIG. 3 , the surface of the metal conductive structure layer 13 is treated with oxygen-containing plasma. As shown in FIG. 4 , the oxygen-containing plasma utilizes the residual charge 2 to form a metal oxide layer 3 on the surface of the metal conductive structure layer 13 . As shown in FIG. 5 , the surface of the metal conductive structure layer 13 is cleaned with hydrogen gas, that is, the metal oxide layer 3 is reduced in situ to remove the original residual charges.
  • FIG. 7 to FIG. 9 are schematic structural diagrams of a substrate 1, respectively.
  • the substrate 1 includes a substrate 11, an insulating layer 12, and a metal connection 13'.
  • the metal conductive structure layer 13 is etched by using the hard mask layer to form the metal connection lines 13' with patterns. As shown in FIG. 7, electric charges remain on the metal wiring 13' formed after etching.
  • FIG. 7 shows a schematic diagram of treating residual charges 2 on the surface of the metal wiring 13 ′ with oxygen-containing plasma in the method of the present disclosure
  • FIG. 8 shows the residual charge 2 on the metal wiring 13 ′.
  • FIG. 9 shows a schematic diagram of reducing the metal oxide layer 3 with hydrogen gas
  • FIG. 10 is a schematic diagram of the substrate 1 after the metal oxide layer 3 is reduced.
  • the method of the present disclosure combined with the above schematic diagrams is as follows: as shown in FIG. 7 , the surface of the metal connection line 13' is treated with oxygen-containing plasma. As shown in Fig. 8, the oxygen-containing plasma utilizes the residual charge 2 to form a metal oxide layer 3 on the surface of the metal connection 13'. As shown in FIG. 9 , the surface of the metal connection line 13' is cleaned with hydrogen gas, that is, the metal oxide layer 3 is reduced in situ, and the original residual charge 2 is removed.
  • the method of the present disclosure can not only remove the residual charges of the unpatterned metal conductive layer 13 , but also can further remove the residual charges on the surface of the patterned metal wiring 13 ′. .
  • the metal conductive structure layer 13 and the metal connection lines 13' in the above embodiments of the present disclosure may be collectively referred to as a metal conductive structure.
  • the material of the substrate 11 in the above embodiments of the present disclosure may be silicon, silicon carbide, silicon nitride, silicon-on-insulator, silicon-on-insulator, silicon germanium-on-insulator, silicon-germanium-on-insulator, germanium-on-insulator, or the like.
  • the residual impurities may include organic impurities.
  • the organic impurities can be, for example, polymers produced in the plasma etching process, for example, the hard mask layer is etched by plasma, and the hard mask layer is generally silicon oxide, silicon nitride, polysilicon or other materials and combinations thereof. After etching, organic impurities may remain on the substrate 1 .
  • Plasma can also be used to etch the wafer, and the etching gas can be Cl 2 , BCl 3 , CCl 4 , NF 3 , SF 6 , CF 4 , etc. During the etching process, impurities such as organic substances are easily generated and remain after etching. wafer surface.
  • charge 2 will also accumulate, which can be positive ions and electrons.
  • the probability of electrons hitting the substrate 1 is greater than that of positive ions. Due to its high reaction characteristics, electrons are more easily absorbed by the surface of the substrate 1, resulting in The charge 2 accumulates, especially if the substrate 1 exposes the surface of the metal conductive structure.
  • the preparation method of the metal interconnection disclosed in the present disclosure can effectively remove the above-mentioned residual impurities and electric charges 2 and avoid damage to the semiconductor device.
  • the oxygen-containing plasma when the surface of the substrate 1 with the residual electric charge 2 is treated by the oxygen-containing plasma, due to the high activity of the oxygen-containing plasma, it can be treated in a normal temperature environment, such as temperature It is 15°C to 50°C, and may be 20°C, 25°C, 30°C, 40°C, or the like.
  • the oxygen-containing plasma can oxidize the surface of the metal conductive structure, so that a metal oxide layer 3 is formed on the surface of the metal conductive structure of the substrate 1 .
  • the residual charge 2 When oxidizing the surface of the metal conductive structure, the residual charge 2, the plasma and the charge 2 distribution between the metal elements can be used to generate a stable metal oxide, and then the neutralization of the residual charge 2 can be achieved, and the residual charge 2 can be neutralized. into stable metal oxides.
  • the oxygen-containing plasma is provided by the plasma generating device, and the supply amount of the oxygen-containing plasma can be controlled by controlling the plasma generating device.
  • the plasma generating device is a mature prior art in the field and can be purchased from the market, therefore, the structure and working principle of the device are not described in detail in the present disclosure.
  • the thickness of the metal oxide layer 3 can be controlled.
  • the thickness of the metal oxide layer 3 is less than 1 nm, such as 0.5 nm, 0.6 nm, 0.8 nm, etc., which is not limited herein.
  • the purpose of controlling the thickness of the metal oxide layer 3 to be less than 1 nm is to prevent the thickness of the metal oxide layer 3 from being too thick. In subsequent cleaning with hydrogen, it is difficult to completely remove the metal oxide, and it will increase equipment loss and energy consumption. Not good for the environment.
  • the environment where the substrate 1 is located is evacuated, that is, the substrate 1 is subjected to plasma treatment in a vacuum environment to avoid other impurities.
  • the treatment process has an impact, ensuring that all residual charges can be removed2.
  • the use of hydrogen to clean the surface of the conductive structure in the embodiment of the present disclosure is specifically to use hydrogen to reduce the metal oxide layer 3 in the above embodiment in situ.
  • M represents the metal element of the metal conductive structure.
  • the hydrogen gas introduced may be hydrogen plasma.
  • the hydrogen plasma may be provided by a plasma generating device.
  • the amount of hydrogen plasma can be controlled according to the amount of oxygen-containing plasma, and on the basis that the metal oxide layer 3 can be completely reduced, energy consumption and cost are reduced.
  • the metal oxide layer 3 can be quickly reduced to metal, and the temperature during the reduction can be normal temperature, such as 15°C to 50°C, specifically, 20°C, 25°C, 30°C or 40°C, etc., using hydrogen plasma for reduction can reduce losses, and low temperature conditions are easy to achieve, reducing the difficulty of operation.
  • the metal oxide layer 3 is reduced to metal in situ, no damage is caused to the metal conductive structure. Therefore, the process does not damage the surface of the substrate 1 on the basis of removing the residual charges 2 .
  • the environment where the substrate 1 is located is evacuated. That is, plasma cleaning is performed on the substrate 1 in a vacuum environment to prevent other impurities from affecting the cleaning process, so as to ensure that the metal oxide layer 3 can be completely reduced without generating other impurities.
  • the hydrogen gas in the embodiment of the present disclosure may also be hydrogen gas in a high temperature environment, rather than hydrogen plasma.
  • the metal oxide layer 3 can also be reduced in situ with hydrogen.
  • hydrogen gas has strong activity at high temperature, and can rapidly reduce the metal oxide layer 3 .
  • the chemical reaction equation is the same as above, except that the condition is high temperature, which will not be repeated here.
  • the high-temperature temperature may be 500°C to 1100°C, specifically, 600°C, 700°C, 800°C, 900°C, or 1000°C, etc., and those skilled in the art can The temperature is adjusted according to the actual situation, for example, according to the specific thickness of the metal oxide layer 3 .
  • the metal oxide layer 3 is reduced to metal in situ, as shown in FIGS. 8 to 10 , the surface of the metal conductive structure is not damaged, and the surface of the substrate 1 is not damaged.
  • the amount of high-temperature hydrogen can also be controlled according to the oxygen content of the oxygen-containing plasma in the foregoing embodiment, or after a certain amount of hydrogen is introduced, The condition of the surface of the substrate 1 can be checked at any time, and if it is found that there is still metal oxide residue, an appropriate amount of hydrogen can be continuously introduced to continue the reaction.
  • Those skilled in the art can perform operations according to actual conditions, and no special limitation is made here.
  • the introduced hydrogen is pure hydrogen, that is, the introduced gas cannot contain other hydrogen or impurities.
  • the environment in which the substrate 1 is located can be evacuated before the hydrogen is introduced, or pure hydrogen can be filled in the low-temperature environment first, and the air and other impurities in the environment in which the substrate 1 is located can be discharged.
  • the hydrogen atmosphere is present, the temperature is raised again, and hydrogen is continued to pass through for the reaction. In this way, the metal conductive structure can be protected from being damaged, and the stability of the metal connection 13' can be ensured.
  • the entire process of the preparation method for the metal interconnection in the present disclosure may include: forming an insulating layer 12 and a metal conductive structure stacked in sequence on the semiconductor substrate 11 , form a hard mask layer and a photoresist layer on the metal conductive structure; after etching the photoresist, the formed pattern is transferred to the hard mask layer, and the pattern of the hard mask layer is used to etch the metal conductive structure through an etching process to forming metal wiring 13 ′, then removing the hard mask layer, that is, pattern etching the substrate 1 to expose the surface of the metal conductive structure; using oxygen-containing plasma to treat the surface of the substrate 1 to remove the residual electric charge 2 on the surface of the conductive structure, That is, oxygen-containing plasma is used to neutralize the residual charges 2, and a metal oxide layer 3 is formed on the surface of the substrate 1; Another insulating layer is formed on the semiconductor substrate 11 including the metal wirings
  • the surface of the substrate 11 is treated with oxygen-containing plasma to neutralize the charge 2 on the surface of the conductive structure, and the surface of the conductive structure is cleaned with hydrogen gas, which can completely remove the neutralized charge 2 and other impurities, and will not damage the surface of the substrate 1.

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Abstract

一种金属连线的制备方法，包括：提供基底，所述基底中包含有金属导电结构；图形化刻蚀所述基底，露出所述金属导电结构的表面；利用含氧气等离子体处理所述基底的表面，去除所述导电结构的表面的电荷；利用氢气清洁所述导电结构的表面。

Description

金属连线的制备方法
交叉引用
本公开要求于2020年9月3日提交的申请号为202010914670.X、名称为“金属连线的制备方法”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及半导体制备技术领域，尤其涉及一种金属连线的制备方法。
背景技术
芯片制作过程中会使用等离子体的工艺，在等离子体蚀刻基底后，通常会在基底的金属连线上残留电荷。电荷的残留会影响半导体器件的性能，严重的甚至会在芯片制造过程中发生电弧放电，从而造成芯片报废。
发明内容
本公开的一个主要目在于提供一种金属连线的制备方法，能够有效去除基底表面的残留电荷，不会损坏基底表面。
为实现上述目的，根据本公开的一个方面，提供一种金属连线的制备方法，包括：提供基底，所述基底中包含有金属导电结构；图形化刻蚀所述基底，露出所述金属导电结构的表面；利用含氧气等离子体处理所述基底的表面，去除所述金属导电结构的表面的电荷；利用氢气清洁所述金属导电结构的表面。
根据本公开的一示例性实施方式，在利用含氧气等离子体处理所述基底的表面后，在所述基底表面生成一层金属氧化物层。
根据本公开的一示例性实施方式，所述氢气为氢气等离子体，以还原所述金属氧化物层。
根据本公开的一示例性实施方式，所述氢气等离子体还原所述金属氧化物层的温度为15℃～35℃。
根据本公开的一示例性实施方式，在利用所述氢气等离子体还原所述金属氧化物层之前，对所述基底所处的环境抽真空。
根据本公开的一示例性实施方式，所述氢气为高温环境中的氢气，以还原所述金属氧化物层，所述高温的温度为500℃～1100℃。
根据本公开的一示例性实施方式，所述金属氧化物层的厚度小于1nm。
根据本公开的一示例性实施方式，所述含氧气等离子体蚀刻所述基底时的温度为15℃～35℃。
根据本公开的一示例性实施方式，利用含氧气等离子体处理所述基底的表面之前，对所述基底所处的环境抽真空。
根据本公开的一示例性实施方式，所述基底的形成包括：在衬底上形成依序堆叠的一第一绝缘层、所述金属导电结构和覆盖层；在所述覆盖层上形成硬掩膜层。
由上述技术方案可知，本公开具备以下优点和积极效果中的至少之一：
利用含氧气等离子体处理基底表面，能够中和导电结构表面的电荷，通过氢气清洁该导电结构的表面，能够彻底去除中和后电荷及其他杂质，并且不会损坏基底的表面。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1为现有技术中基底上附着残留电荷的示意图；
图2为现有技术中利用氢气和氮气去除基底上残留电荷后的基底的示意图；
图3为本公开的一实施例中利用含氧气等离子体处理具有残留的电荷的基底的示意图；
图4为本公开的一实施例中基底表面后形成金属氧化物层的示意图；
图5为本公开的一实施例中利用氢气还金属原氧化物层时的示意图；
图6为本公开的一实施例中氧化物层被还原后的基底的示意图；
图7为本公开的另一实施例中利用含氧气等离子体处理具有残留的电荷的基底的示意图；
图8为本公开的另一实施例中基底表面后形成金属氧化物层的示意图；
图9为本公开的另一实施例中利用氢气还金属原氧化物层时的示意图；
图10为本公开的另一实施例中氧化物层被还原后的基底的示意图。
附图标记说明：
1、基底；11、衬底；12、绝缘层；13、金属导电结构层；13’、金属连线；2、电荷； 3、金属氧化物层。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
在对本公开的不同示例性实施方式的下面描述中，参照附图进行，附图形成本公开的一部分，并且其中以示例方式显示了可实现本公开的多个方面的不同示例性结构。应理解的是，可以使用部件、结构、示例性装置、***和步骤的其他特定方案，并且可在不偏离本公开范围的情况下进行结构和功能性修改。而且，虽然本说明书中可使用术语“之上”、“之间”、“之内”等来描述本公开的不同示例性特征和元件，但是这些术语用于本文中仅出于方便，例如根据附图中的示例的方向。本说明书中的任何内容都不应理解为需要结构的特定三维方向才落入本公开的范围内。此外，权利要求书中的术语“第一”、“第二”等仅作为标记使用，不是对其对象的数字限制。
研究人员发现在制备半导体金属连线的过程中，基底1上残留有电荷，如图1所示，其示出了半导体基底1上残留有电荷的示意图。为了解决此问题，技术人员曾尝试通过氢气和氮气的混合气体的等离子体去除残留的电荷，以防止基底1被氧化。但是，在去除残留的电荷过程中，发现这种方法容易损坏基底1表面，使基底1表面形成缺陷。
为了能够完全去除残留的电荷，且不损伤基底1，本公开提供一种金属连线的制备方法，用于制备半导体中的金属连线。金属连线的制备方法包括：在半导体衬底11上形成依次堆叠的一绝缘层12和金属导电结构，在金属导电结构上形成硬掩模层，在硬掩膜层上形成光刻胶层，通过对光刻胶进行蚀刻，形成图案，并将图案转移至硬掩膜层，利用硬掩膜层的图案，通过蚀刻工艺蚀刻金属导电结构以形成金属连线，之后去除硬掩模层，在包括金属连线的半导体衬底11上形成另一绝缘层12以使金属连线彼此绝缘。
其中，可以在衬底11上形成有预定的例如隔离层、晶体管、源极接触塞等，之后在其上形成一绝缘层12，然后蚀刻该绝缘层12形成接触孔(图中未示出)。为了减少接触电阻，实施离子注入工艺以在半导体衬底11中形成结区。在接触孔中形成金属阻挡层，然后在包括接触孔的半导体衬底11上形成导电层以填充接触孔(图中未示出)。然后在绝缘层12上再依序形成金属导电结构，其中金属导电结构可以包括金属导电层和阻挡金 属层。随后，在金属导电结构上形成硬掩膜层和光刻胶层。通过曝光工艺和显影工艺来蚀刻光刻胶层以形成光刻胶图案，然后通过光刻胶图案作为蚀刻掩膜来蚀刻硬掩膜层。利用光刻胶图案和蚀刻的硬掩膜层作为蚀刻掩膜来蚀刻金属导电结构，以形成金属线。
其中，硬掩模层通常为非晶碳层和氧氮化物硅层形成。金属导电结构可以由金属钨形成。其中的蚀刻工艺可以是等离子体工艺。
可以通过溅射的方法形成另一绝缘层，并且另一缘层优选由高密度等离子体(HDP)氧化物层形成。
上述的制备方法中，通常会在金属导电结构的表面残留一些杂质(例如一些有机物)以及电荷2，而基于上述制备步骤，并不能清除这些残留的杂质和电荷2。
本公开的金属连线制备方法，在上述的制备方法基础上，能够有效去除半导体器件经过蚀刻后的基底1上的残留杂质及电荷2。
本公开的方法包括：提供上述基底1，基底1中包含有金属导电结构；图形化刻蚀基底1，露出金属导电结构表面；利用含氧气等离子体处理基底1的表面，去除导电结构表面的电荷2；利用氢气清洁金属导电结构的表面。
利用含氧气等离子体处理基底1表面，能够中和导电结构表面的电荷2，通过氢气清洁该导电结构的表面，能够彻底去除电荷2及其他杂质，并且不会损坏基底1的表面。
下面对本公开的金属连线的制备方法进行详细的说明。
在一些实施例中，请参考图3至图6，其分别示出了基底1的结构示意图，该基底1包括衬底11、绝缘层12以及金属导电结构层13。本实施例中的金属导电结构层13尚未通过硬掩膜层蚀刻，仅仅是露出于基底1。如图3所示，在露出的金属导电结构层13的表面容易残留有电荷。
请参考图3至图6，其中，图3示出了本公开的方法中利用含氧气等离子体处理具有残留的电荷2的基底1的示意图，图4示出了利用含氧气等离子体处理金属导电结构层13的表面后形成金属氧化物层3的示意图，图5示出了利用氢气还原金属氧化物层3时的示意图，图6示出了金属氧化物层3被还原后的基底1的示意图，去除金属导电结构层13表面残留电荷2后的基底1的表面示意图。
本公开的方法结合各个示意图为：如图3所示，利用含氧气等离子体处理金属导电结构层13的表面。如图4所示，含氧气等离子体利用残留电荷2在金属导电结构层13表面形成一层金属氧化物层3。如图5所示，利用氢气清洁金属导电结构层13的表面，即将该金属氧化物层3原位还原，去除了原来的残留电荷。
在另一些实施例中，请参考图7至图9，其分别示出了基底1的结构示意图，该基底1包括衬底11、绝缘层12以及金属连线13’。本实施例中利用硬掩膜层对金属导电结构层13蚀刻，形成具有图案的金属连线13’。如图7所示，在蚀刻后形成的金属连线13’上残留有电荷。
请参考图7至图10，其中，图7示出了本公开的方法中利用含氧气等离子体处理金属连线13’表面的残留电荷2的示意图，图8示出了在金属连线13’表面形成金属氧化物层3的示意图，图9示出了利用氢气还原金属氧化物层3时的示意图，图10示出了金属氧化物层3被还原后的基底1的示意图。
本公开的方法结合上述各个示意图为：如图7所示，利用含氧气等离子体处理金属连线13’的表面。如图8所示，含氧气等离子体利用残留电荷2在金属连线13’表面形成一层金属氧化物层3。如图9所示，利用氢气清洁金属连线13’的表面，即将该金属氧化物层3原位还原，去除了原来的残留电荷2。
因此，本公开的方法在制备金属连线13’的过程中，不仅能够去除未图案化的金属导电层13的残留的电荷，也能够进一步去除图案化后的金属连线13’表面的残留电荷。
本公开上述实施例中的金属导电结构层13和金属连线13’可以统称为金属导电结构。
本公开上述实施例中的衬底11的材料可以为硅、碳化硅、氮化硅、绝缘体上硅、绝缘体上层叠硅、绝缘体上层叠锗化硅、绝缘体上层锗化硅或绝缘体上层锗等。
其中，残留杂质可以包含有机物杂质。有机物杂质例如可以是在等离子体蚀刻过程中产生的聚合物，例如利用等离子体蚀刻硬掩膜层，硬掩膜层一般为氧化硅、氮化硅、多晶硅或其他材料及其组合，经过等离子体蚀刻后，会在基底1上残留有机杂质。也可以是利用等离子体对晶片进行蚀刻，蚀刻气体可以为Cl 2、BCl 3、CCl 4、NF 3、SF 6、CF 4等，在该蚀刻过程中，也容易产生有机物等杂质残留在蚀刻后的晶片表面。另外，等离子蚀刻过程中还会累积电荷2，该电荷2可以是正离子与电子，电子撞击基底1的概率大于正离子，由于其具有很高的反应特性，电子更容易被基底1表面吸收，造成电荷2累积，尤其当基底1露出金属导电结构表面的情况下。本公开的金属连线的制备方法，能够有效去除上述残留杂质以及电荷2，避免对半导体器件的损坏。
进一步地，如图3和图7所示，在利用含氧气等离子体处理具有残留的电荷2的基底1表面时，由于含氧气等离子体具有较高的活性，可以在常温环境下处理，例如温度为15℃～50℃，可以为20℃、25℃、30℃或40℃等。如图4和图8所示，含氧气等离子体能够氧化金属导电结构表面，使基底1的金属导电结构表面形成一层金属氧化物层3。在氧化 金属导电结构表面时，可以利用残留的电荷2、等离子体以及金属元素之间的电荷2分配，产生稳定的金属氧化物，进而实现对残留电荷2的中和作用，将残留的电荷2转移至稳定的金属氧化物中。
含氧气等离子体由等离子体产生装置提供，可以通过控制等离子体产生装置来控制含氧气等离子体的供应量。等离子体产生装置为本领域中的成熟的现有技术，可以从市场上购得，因此，本公开对其结构及工作原理不做详细介绍。
进一步地，通过控制氧气等离子体的量，能够控制金属氧化物层3的厚度。在本公开实施例中，金属氧化物层3的厚度为小于1nm，例如0.5nm、0.6nm、0.8nm等，此处不做限定。控制金属氧化物层3的厚度小于1nm，是为了防止金属氧化物层3的厚度过厚，在后续利用氢气进行清洁时，不易彻底清除该金属氧化物，而且会增加设备的损耗以及能耗，不利于环保。
进一步地，为了保证等离子体的有效蚀刻，利用含氧气等离子体处理基底1的表面之前，对基底1所处的环境抽真空，即在真空环境下对基底1进行等离子体处理，避免其他杂质对处理过程产生影响，保证能够去除全部残留的电荷2。
进一步地，如图5和图9所示，本公开实施例中的利用氢气清洁导电结构的表面具体为利用氢气原位还原上述实施例中的金属氧化物层3。其还原的化学方程式可以表示为：M xO y+H 2＝M+H 2O+O 2。其中，M代表金属导电结构的金属元素。通过上述原位还原金属氧化物层3，金属氧化物被还原为金属单质，其他的元素生成水和氧气，而水和氧气能够很容易脱离金属导电结构，从而容易对金属导电结构的表面进行清洁，因此能够彻底清洁金属导电结构。
进一步地，还原金属氧化物层3时，通入的氢气可以是氢气等离子体。
氢气等离子体可以由等离子产生装置提供。并且，可以根据含氧气等离子体的量来控制氢气等离子体的量，在能够彻底还原金属氧化物层3的基础上，节省能耗，降低成本。
进一步地，由于氢气等离子体非常活跃，能够快速地将金属氧化物层3还原为金属，其还原时的温度可以为常温，例如15℃～50℃，具体地，可以为20℃、25℃、30℃或40℃等，利用氢气等离子体进行还原，能够降低损耗，并且低温条件容易实现，降低操作难度。如图6和图10所示，由于金属氧化物层3被原位还原为金属，并未对金属导电结构造成损坏。因此，该过程在去除残留的电荷2的基础上，并未损坏基底1表面。
进一步地，在利用氢气等离子体还原金属氧化物层3之前，对基底1所处的环境抽真空。即在真空环境下对基底1进行等离子体清洁，避免其他杂质对清洁过程产生影响，保 证能够彻底还原金属氧化物层3而不产生其他杂质。
进一步地，如图5和图10所示，本公开实施例的氢气还可以是处于高温环境的氢气，而并非氢气等离子体。利用氢气也可以对金属氧化物层3进行原位还原。并且，氢气在高温时具有较强的活性，能够快速的还原金属氧化物层3。其化学反应方程式同上，只是条件为高温，此处不再赘述。
利用高温的氢气还原金属氧化物层3，此时高温的温度可以为500℃～1100℃，具体地，可以为600℃、700℃、800℃、900℃或1000℃等，本领域技术人员可以根据实际情况，例如根据金属氧化物层3的具体厚度，来调控该温度。同样，由于金属氧化物层3被原位还原为金属，因此，如图8至10所示，金属导电结构的表面并未受到损坏，并未损坏基底1表面。
同样地，由于金属氧化物层3的厚度小于1nm，因此，高温的氢气的量也可以根据前述实施例中的含氧等离子体的中氧含量来控制，或者在通入一定量的氢气后，可以随时检查基底1表面的情况，如果检查到尚有金属氧化物残留，可以继续通入适量的氢气继续反应。本领域技术人员可以根据实际情况进行操作，此处不做特殊限定。
另外，为了避免引入其他杂质或者在反应过程中产生新的杂质，通入的氢气为纯的氢气，即通入的气体中不能含有其他氢气或杂质。例如，可以在通入氢气之前，对基底1所处的环境进行抽真空，或者先在低温环境充入纯的氢气，将基底1所处的环境中的空气及其他杂质排出，检测到为纯的氢气环境时，再升高温度，并继续通入氢气进行反应。如此，能够保护金属导电结构不被破坏，保证金属连线13’的稳定性。
结合本公开的上述实施例中的金属连线的制备方法，本公开的金属连线的制备方法的整个流程可以包括：在半导体衬底11上形成依序堆叠的一绝缘层12和金属导电结构，在金属导电结构上形成硬掩模层以及光刻胶层；通过对光刻胶蚀刻后，形成图案转移至硬掩膜层，利用硬掩膜层的图案，通过蚀刻工艺蚀刻金属导电结构以形成金属连线13’，之后去除硬掩模层，即图形化蚀刻该基底1，露出金属导电结构的表面；利用含氧气等离子体处理基底1的表面，去除导电结构表面的残留的电荷2，即利用含氧气等离子体中和残留的电荷2，并在基底1的表面形成金属氧化物层3；利用氢气清洁导电结构的表面，即利用氢气原位还原金属氧化物层3。在包括金属连线13’的半导体衬底11上形成另一绝缘层以使金属连线13’彼此绝缘。
需要说明的，在利用氢气等离子体或者高温的氢气进行清洁时，除了能够还原金属氧化物层3以去除残留的电荷2外，由于其强的还原性，同时能够去除残留的有机杂质。
综上，本公开的金属连线的制备方法中，利用含氧气等离子体处理基底11表面，能够中和导电结构表面的电荷2，通过氢气清洁该导电结构的表面，能够彻底去除中和后电荷2及其他杂质，并且不会损坏基底1的表面。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书所述的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (10)

  1. 一种金属连线的制备方法，包括：
    提供基底，所述基底中包含有金属导电结构；
    图形化刻蚀所述基底，露出所述金属导电结构的表面；
    利用含氧气等离子体处理所述基底的表面，去除所述金属导电结构的表面的电荷；
    利用氢气清洁所述金属导电结构的表面。
  2. 根据权利要求1所述的金属连线的制备方法，其中，在利用含氧气等离子体处理所述基底的表面后，在所述基底表面生成一层金属氧化物层。
  3. 根据权利要求2所述的金属连线的制备方法，其中，所述氢气为氢气等离子体，以还原所述金属氧化物层。
  4. 根据权利要求3所述的金属连线的制备方法，其中，所述氢气等离子体还原所述金属氧化物层的温度为15℃～50℃。
  5. 根据权利要求3所述的金属连线的制备方法，其中，在利用所述氢气等离子体还原所述金属氧化物层之前，对所述基底所处的环境抽真空。
  6. 根据权利要求2所述的金属连线的制备方法，其中，所述氢气为高温环境中的氢气，以还原所述金属氧化物层，所述高温的温度为500℃～1100℃。
  7. 根据权利要求2所述的金属连线的制备方法，其中，所述金属氧化物层的厚度小于1nm。
  8. 根据权利要求1所述的金属连线的制备方法，其中，所述含氧气等离子体蚀刻所述基底时的温度为15℃～50℃。
  9. 根据权利要求1所述的金属连线的制备方法，其中，利用含氧气等离子体处理所述基底的表面之前，对所述基底所处的环境抽真空。
  10. 根据权利要求1至9中任一项所述的金属连线的制备方法，其中，所述基底的形成包括：
    在衬底上形成依序堆叠的绝缘层和所述金属导电结构；
    在所述金属导电结构上依序形成硬掩膜层和光刻胶层。
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