WO2021258610A1 - 一种阵列基板、显示面板及制作方法 - Google Patents

一种阵列基板、显示面板及制作方法 Download PDF

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Publication number
WO2021258610A1
WO2021258610A1 PCT/CN2020/127838 CN2020127838W WO2021258610A1 WO 2021258610 A1 WO2021258610 A1 WO 2021258610A1 CN 2020127838 W CN2020127838 W CN 2020127838W WO 2021258610 A1 WO2021258610 A1 WO 2021258610A1
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layer
groove
gate insulating
insulating layer
metal layer
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PCT/CN2020/127838
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English (en)
French (fr)
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汪才树
曹志浩
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武汉华星光电技术有限公司
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Publication of WO2021258610A1 publication Critical patent/WO2021258610A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • This application relates to the field of display, in particular to an array substrate, a display panel and a manufacturing method thereof.
  • a dual-wiring design of the gate and the common electrode is often used to balance the voltage of the common electrode. Since the gate and the common electrode are arranged on the same horizontal plane in the dual routing design, when the metal layer is etched to form the gate and the common electrode, it is easy to cause the etching solution to remain between the gate and the common electrode. Since the remaining etching solution cannot be eliminated, the gate and the common electrode line are continuously etched in the subsequent manufacturing process, resulting in the grid and the common electrode line being too thin and easily broken, resulting in poor display of the display panel.
  • the embodiments of the present application provide an array substrate, a display panel, and a manufacturing method, which can solve the problem that the residual etching solution between the gate and the common electrode affects the yield of the display panel in the thin film transistor array substrate with a dual-track design in the prior art. The problem.
  • the present application provides an array substrate, which includes:
  • An active layer formed on the side of the buffer layer away from the substrate;
  • the metal layer is patterned on the active layer to form a gate, the metal layer is patterned in the groove to form a common electrode, and the gate and the common electrode are formed in a horizontal direction. Height difference, the common electrode is insulated from the active layer.
  • the distance between the groove and the edge of the active layer is between 30 nanometers and 50 nanometers.
  • the groove penetrates the gate insulating layer to the surface of the buffer layer.
  • the depth of the groove is one-half to one-third of the gate insulating layer.
  • the shape of the groove includes an inverted trapezoid.
  • the present application provides a manufacturing method of an array substrate for manufacturing the array substrate, and the manufacturing method includes:
  • a metal layer is deposited on the gate insulating layer, and the metal layer is patterned to form a gate and a common electrode.
  • the step of forming a groove on the gate insulating layer after exposing and developing the photoresist includes:
  • the mask being formed with a groove pattern
  • the step of etching the gate insulating layer, and forming a groove in the gate insulating layer in the through hole includes: forming the gate insulating layer by a wet etching method. ⁇ Said groove.
  • the step of depositing a metal layer on the gate insulating layer, and patterning the metal layer to form a gate electrode and a common electrode includes:
  • a metal layer is deposited on the gate insulating layer, the metal layer undergoes a patterning process to form a gate and a common electrode, and the common electrode is formed in the groove.
  • the step of depositing a metal layer on the gate insulating layer, and patterning the metal layer to form a gate electrode and a common electrode includes:
  • a second metal layer is deposited on the gate insulating layer, and the second metal layer is patterned to form a gate.
  • the present application provides a display panel, the display panel includes the array substrate, and the array substrate includes:
  • An active layer formed on the side of the buffer layer away from the substrate;
  • the metal layer is patterned on the active layer to form a gate, the metal layer is patterned in the groove to form a common electrode, and the gate and the common electrode are formed in a horizontal direction. Height difference, the common electrode is insulated from the active layer.
  • the distance between the groove and the edge of the active layer is between 30 nanometers and 50 nanometers.
  • the groove penetrates the gate insulating layer to the surface of the buffer layer.
  • the depth of the groove is one-half to one-third of the gate insulating layer.
  • the shape of the groove includes an inverted trapezoid.
  • the present application provides an array substrate, a display panel and a manufacturing method thereof.
  • the array substrate includes: a substrate, a buffer layer, an active layer, a gate insulating layer, and a metal layer arranged in a stack; wherein the gate insulating layer is formed with In the groove, the metal layer is patterned on the active layer to form a gate, and the metal layer is patterned in the groove to form a common electrode.
  • the gate and the common electrode are formed with a height difference in the horizontal direction. In this application, the height difference formed between the gate and the common electrode alleviates the problem that the etching solution is likely to remain between the gate and the common electrode when the metal layer is etched.
  • FIG. 1 is a schematic diagram of a cross-sectional structure of an array substrate in the prior art
  • FIG. 2 is a schematic diagram of a cross-sectional structure of an array substrate provided by an embodiment of the application.
  • FIG. 3 is a schematic diagram of a first process of a manufacturing method of an array substrate provided by an embodiment of the application.
  • FIG. 4 is a schematic diagram of the second process of the manufacturing method of the array substrate provided by the embodiment of the application.
  • 5 to 8 are schematic structural diagrams of a manufacturing method of an array substrate provided by an embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, "a plurality of" means two or more than two, unless otherwise specifically defined.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected or integrally connected; it can be mechanically connected, it can be electrical connection or it can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • connection should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection. Connected or integrally connected; it can be mechanically connected, it can be electrical connection or it can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • the "above” or “below” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • “above”, “above” and “above” the second feature of the first feature include the first feature being directly above and obliquely above the second feature, or merely indicating that the level of the first feature is higher than that of the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • This application provides an array substrate, a display panel and a preparation method thereof.
  • the display panel includes the array substrate, and the array substrate includes: a laminated substrate and a buffer layer. , The active layer, the gate insulating layer, and the metal layer; wherein the gate insulating layer is formed with a groove, the metal layer is patterned on the active layer to form a gate, and the metal layer is patterned in the groove to form a common electrode.
  • the electrode and the common electrode are formed with a height difference in the horizontal direction. In this application, the height difference formed between the gate and the common electrode alleviates the problem that the etching solution is likely to remain between the gate and the common electrode when the metal layer is etched.
  • the array substrate includes: a substrate 110; a buffer layer 120 formed on the substrate; an active layer 130 formed on the buffer layer 120 away from the substrate On one side of the substrate, the channel region and the doped region are patterned; the first gate insulating layer 140 is formed on the side of the active layer 130 away from the buffer layer 120; the first metal layer is formed on the side of the active layer 130. On a side of the gate insulating layer 140 away from the active layer 130, the gate 150 and the common electrode 160 are patterned.
  • the gate 150 and the common electrode 160 are wet-etched on the same plane by the same metal layer, the gate 150 and the common electrode 160 easily form a semi-enclosed space, causing the etching solution to flow on the gate. Residues occur between the electrode 150 and the common electrode 160, which cannot be eliminated. As a result, in the subsequent manufacturing process, the etching solution continuously etches the gate 150 and the common electrode 160, making the wiring of the gate 150 and the common electrode 160 too thin. It is easy to cause poor display of the display panel.
  • the present application provides an array substrate including: a substrate 110; a buffer layer 120 formed on the substrate 110; and an active layer 130 formed on the substrate 110; The side of the buffer layer 120 away from the substrate 110; the gate insulating layer 140 is formed on the side of the active layer 130 away from the buffer layer 120; the groove T1 is provided in the gate insulating layer The gate 150 is arranged on the side of the gate insulating layer away from the active layer 130; the common electrode 160 is arranged in the groove T1. In this application, a height difference is formed between the gate 150 and the common electrode 160, which alleviates the problem that the etching solution is likely to remain between the gate and the common electrode when the metal layer is etched.
  • the material of the substrate 110 is generally glass; the buffer layer 120 is an inorganic material, which can be one of silicon nitride and silicon oxide; the material of the active layer 130 is a polysilicon layer to prepare the active layer 130 At this time, an amorphous silicon layer is first formed on the buffer layer 130, and then methane and reaction gas are introduced into the reaction chamber to perform high-temperature activation to form active ions and ion groups, and an ion-doped layer is formed on the amorphous silicon layer. The amorphous silicon thin film is then subjected to a crystallization process for the amorphous silicon thin film, and the amorphous silicon thin film is heated to a temperature above 700 degrees to form a polycrystalline silicon layer.
  • the material is an inorganic material, which can be one of silicon nitride and silicon oxide.
  • the groove T1 is formed on the side of the gate insulating layer 140 away from the buffer layer 120.
  • the groove T1 and the active layer 130 are arranged on the same horizontal plane, and the distance from the edge of the active layer 130 It is 30 nanometers to 50 nanometers.
  • the groove T1 penetrates the gate insulating layer 140 to the surface of the buffer layer.
  • the depth of the groove T1 is one-half to one-third of the gate insulating layer 140.
  • the shape of the groove T1 is one of an inverted trapezoid, a triangle, and a semicircle.
  • a magnetron sputtering method is used to prepare a first metal layer on the gate insulating layer 140.
  • the material of the first metal layer can be metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or it can be a combination structure of the foregoing several material films.
  • the first metal layer is etched, and the first metal layer forms a gate on the side of the gate insulating layer 140 away from the active layer 130, and forms a common electrode in the groove T1.
  • a magnetron sputtering method is used to prepare a first metal layer in the groove T1, the first metal layer is etched to form a common electrode 160, and a second metal layer is prepared on the gate insulating layer 140 The second metal layer is etched to form the gate 150.
  • the material of the first metal layer can be molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination structure of the above-mentioned material films;
  • the material of the second metal layer can be molybdenum, aluminum , Aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, etc., can also be a combination of the above-mentioned material films, and the materials of the first metal layer and the second metal layer can be the same or different.
  • the present application provides a manufacturing method of an array substrate for preparing the above-mentioned array substrate, and the method includes:
  • Step S1 Provide a substrate
  • Step S2 sequentially forming a substrate, a buffer layer, an active layer, and a gate insulating layer on the substrate;
  • Step S3 coating a layer of photoresist on the gate insulating layer
  • Step S4 after exposing and developing the photoresist, a groove is formed on the gate insulating layer;
  • Step S5 depositing a metal layer on the gate insulating layer, and the metal layer is patterned to form a gate electrode and a common electrode.
  • the substrate is generally a glass substrate.
  • the buffer layer 120 is an inorganic material, which can be one of silicon nitride and silicon oxide; the material of the active layer 130 is a polysilicon layer.
  • the active layer 130 first An amorphous silicon layer is formed on the buffer layer 130, and then methane and reaction gas are introduced into the reaction chamber, and activated at high temperature to form active ions and ion groups, and an ion-doped amorphous silicon film is formed on the amorphous silicon layer Then, the amorphous silicon film is processed by a crystallization process, and the amorphous silicon film is heated to over 700 degrees to form a polysilicon layer.
  • etching gas is passed into the reaction chamber, and the polysilicon layer is patterned to form a channel region of the active layer. On both sides of the channel region, doped regions of the active layer 130 are formed; the material of the gate insulating layer 140 It is an inorganic material, which can be one of silicon nitride and silicon oxide.
  • the photoresist 210 is coated on the gate insulating layer 140 by a coating method.
  • the photoresist material includes photosensitive resin and photoinitiator.
  • the resin is a high-molecular polymer, generally an alkaline soluble resin, and its molecular chain usually contains a certain amount of acidic groups such as carboxyl groups to ensure that it can interact with Alkaline developer reacts and dissolves; the photoinitiator decomposes to form free radicals after being irradiated by ultraviolet rays, which promotes the opening of monomer and polymer double bonds to cause crosslinking and bridging reactions to form a network, forming a network that is insoluble in alkaline developer Film structure.
  • step S4 includes:
  • Step S401 Provide a mask, the mask is formed with a groove pattern
  • Step S402 Expose and develop the photoresist with the mask, and the photoresist has through holes formed at the positions of the groove patterns;
  • Step S403 etching the gate insulating layer, and forming a groove in the gate insulating layer in the through hole;
  • Step S404 peel off the remaining photoresist.
  • step S401 a mask is provided, the mask is formed with a groove pattern, and an ultraviolet lamp is used to irradiate the photoresist 210. Irradiation, light induced decomposition to form free radicals, which promoted the opening of monomer and polymer double bonds to cause cross-linking and bridging reactions to form a network, forming a film structure that is insoluble in alkaline developer, and in the unexposed groove pattern area Since the resin in the photoresist 210 usually contains a certain amount of acidic groups such as carboxyl groups, during the development process, areas of the photoresist 210 that have not been exposed can react and dissolve with the alkaline developer to form through holes.
  • an ultraviolet lamp is used to irradiate the photoresist 210. Irradiation, light induced decomposition to form free radicals, which promoted the opening of monomer and polymer double bonds to cause cross-linking and bridging reactions to form a network, forming a film structure that is insoluble in alkaline developer
  • step S402 a method of spraying a developer is used to remove the photoresist under the groove pattern to form a through hole. As shown in FIG. 7, the through hole penetrates the photoresist 210 to the surface of the gate insulating layer 140.
  • the developer is generally an alkaline developer, such as potassium hydroxide.
  • a wet etching method is used to etch the gate insulating layer 140 in the through hole to form a groove T1, and the etching solution may be an oxalic acid solution.
  • the groove T1 penetrates the gate insulating layer 140 to the surface of the buffer layer.
  • the depth of the groove T1 is one-half to one-third of the gate insulating layer 140.
  • the shape of the groove T1 is one of an inverted trapezoid, a triangle, and a semicircle.
  • step S404 the array substrate is dried to evaporate the remaining photoresist.
  • a magnetron sputtering method is used to prepare a first metal layer on the gate insulating layer 140.
  • the material of the first metal layer can be metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or it can be a combination structure of the foregoing several material films.
  • the first metal layer is etched to form a gate 150 and a common electrode 160, wherein the first metal layer forms a gate on the side of the gate insulating layer 140 away from the active layer 130, in the groove T1 A common electrode is formed inside.
  • a magnetron sputtering method is used to prepare a first metal layer in the groove T1, the first metal layer is etched to form a common electrode 160, and a second metal layer is prepared on the gate insulating layer 140 The second metal layer is etched to form the gate 150.
  • the material of the first metal layer can be molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination structure of the above-mentioned material films;
  • the material of the second metal layer can be molybdenum, aluminum , Aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, etc., can also be a combination of the above-mentioned material films, and the materials of the first metal layer and the second metal layer can be the same or different.

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Abstract

一种阵列基板、显示面板及其制备方法，所述阵列基板包括：层叠设置的衬底（110）、缓冲层（120）、有源层（130）、栅极绝缘层（140）、金属层；其中，栅极绝缘层（140）形成有凹槽（T1），金属层在有源层（130）上方图案化形成栅极（150），金属层在凹槽（T1）内图案化形成公共电极（160），栅极（150）和公共电极（160）在水平方向上形成有高度差。

Description

一种阵列基板、显示面板及制作方法 技术领域
本申请涉及显示领域，具体涉及一种阵列基板、显示面板及其制作方法。
 背景技术
在大尺寸的低温多晶硅薄膜晶体管的制程中，常常采用栅极和公共电极的双走线设计来平衡公共电极的电压。由于在双走线设计中，栅极和公共电极设置在同一水平面，这样金属层刻蚀形成栅极和公共电极时，容易在栅极和公共电极之间造成刻蚀液残留。由于残留的刻蚀液无法排除，造成栅极和公共电极线在后续制程中持续刻蚀，从而导致栅极和公共电极走线过细容易断线，从而造显示面板显示不良。
因此，现有技术在双走线设计的薄膜晶体管阵列基板中，存在栅极和公共电极之间残留刻蚀液影响显示面板良率的问题。
 技术问题
本申请实施例提供一种阵列基板、显示面板及制作方法，可以解决现有技术在双走线设计的薄膜晶体管阵列基板中，存在栅极和公共电极之间残留刻蚀液影响显示面板良率的问题。
 技术解决方案
本申请提供一种阵列基板，所述阵列基板包括：
衬底；
缓冲层，形成在所述衬底之上；
有源层，形成在所述缓冲层远离所述衬底的一侧；
栅极绝缘层，形成在所述有源层远离所述缓冲层的一侧，图案化形成有凹槽，所述凹槽设置在所述栅极绝缘层远离所述缓冲层的一侧；
金属层，形成在所述栅极绝缘层远离所述缓冲层的一侧，所述金属层的厚度小于所述凹槽的深度；
其中，所述金属层在所述有源层上方图案化形成栅极，所述金属层在所述凹槽内图案化形成公共电极，所述栅极和所述公共电极在水平方向上形成有高度差，所述公共电极与所述有源层之间绝缘。
在本申请提供的阵列基板中，在水平方向上，所述凹槽与所述有源层边缘的距离在30纳米到50纳米之间。
在本申请提供的阵列基板中，所述凹槽贯穿所述栅极绝缘层至所述缓冲层表面。
在本申请提供的阵列基板中，所述凹槽的深度为所述栅极绝缘层的二分之一到三分之一。
在本申请提供的阵列基板中，所述凹槽的形状包括倒梯形。
本申请提供一种阵列基板的制作方法，用于制作所述阵列基板，所述制作方法包括：
提供一基板；
在所述基板上依次形成衬底、缓冲层、有源层、栅极绝缘层；
在所述栅极绝缘层涂布一层光阻；
对所述光阻进行曝光显影后，所述栅极绝缘层上形成有凹槽；
在所述栅极绝缘层上沉积金属层，所述金属层图案化形成栅极和公共电极。
在本申请提供的制作方法中，所述对所述光阻进行曝光显影后，在所述栅极绝缘层上形成有凹槽的步骤包括：
提供一掩膜板，所述掩膜版形成有凹槽图案；
用所述掩膜版对所述光阻进行曝光显影，所述光阻在所述凹槽图案的位置上形成有通孔；
对所述栅极绝缘层进行刻蚀，在所述通孔内，所述栅极绝缘层形成有凹槽；
剥离剩余的光刻胶。
在本申请提供的制作方法中，所述对所述栅极绝缘层进行刻蚀，在所述通孔内，所述栅极绝缘层形成有凹槽的步骤包括：采用湿刻蚀法形成所述凹槽。
在本申请提供的制作方法中，所述在所述栅极绝缘层上沉积金属层，所述金属层图案化形成栅极和公共电极的步骤包括：
在所述栅极绝缘层上沉积金属层，所述金属层经过一次构图工艺形成栅极和公共电极，所述公共电极形成在所述凹槽内。
在本申请提供的制作方法中，所述在所述栅极绝缘层上沉积金属层，所述金属层图案化形成栅极和公共电极的步骤包括：
在所述凹槽内沉积第一金属层，所述第一金属层图案化形成公共电极；
在所述栅极绝缘层上沉积第二金属层，所述第二金属层图案化形成栅极。
本申请提供一种显示面板，所述显示面板包括所述阵列基板，所述阵列基板包括：
衬底；
缓冲层，形成在所述衬底之上；
有源层，形成在所述缓冲层远离所述衬底的一侧；
栅极绝缘层，形成在所述有源层远离所述缓冲层的一侧，图案化形成有凹槽，所述凹槽设置在所述栅极绝缘层远离所述缓冲层的一侧；
金属层，形成在所述栅极绝缘层远离所述缓冲层的一侧，所述金属层的厚度小于所述凹槽的深度；
其中，所述金属层在所述有源层上方图案化形成栅极，所述金属层在所述凹槽内图案化形成公共电极，所述栅极和所述公共电极在水平方向上形成有高度差，所述公共电极与所述有源层之间绝缘。
在本申请提供的显示面板中，在水平方向上，所述凹槽与所述有源层边缘的距离在30纳米到50纳米之间。
在本申请提供的显示面板中，所述凹槽贯穿所述栅极绝缘层至所述缓冲层表面。
在本申请提供的显示面板中，所述凹槽的深度为所述栅极绝缘层的二分之一到三分之一。
在本申请提供的显示面板中，所述凹槽的形状包括倒梯形。
 有益效果
本申请提供一种阵列基板、显示面板及其制作方法，所述阵列基板包括：层叠设置的衬底、缓冲层、有源层、栅极绝缘层、金属层；其中，栅极绝缘层形成有凹槽，金属层在有源层上方图案化形成栅极，金属层在凹槽内图案化形成公共电极，栅极和公共电极在水平方向上形成有高度差。本申请通过栅极和公共电极之间形成有高度差，缓解了金属层在刻蚀时，刻蚀液容易在栅极和公共电极之间残留的问题。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为现有技术的阵列基板的剖面结构示意图；
图2为本申请实施例提供的阵列基板的剖面结构示意图。
图3为本申请实施例提供的阵列基板制作方法的第一种流程示意图。
图4为本申请实施例提供的阵列基板制作方法的第二种流程示意图。
图5至图8为本申请实施例提供的阵列基板制作方法的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
具体的，请参阅图1至图8，本申请提供一种阵列基板、显示面板及其制备方法，所述显示面板包括所述阵列基板，所述阵列基板包括：层叠设置的衬底、缓冲层、有源层、栅极绝缘层、金属层；其中，栅极绝缘层形成有凹槽，金属层在有源层上方图案化形成栅极，金属层在凹槽内图案化形成公共电极，栅极和公共电极在水平方向上形成有高度差。本申请通过栅极和公共电极之间形成有高度差，缓解了金属层在刻蚀时，刻蚀液容易在栅极和公共电极之间残留的问题。
在现有技术中，如图1所示，所述阵列基板包括：衬底110；缓冲层120，形成在所述衬底之上；有源层130，形成在所述缓冲层120远离所述衬底的一侧，图案化形成沟道区和掺杂区；第一栅极绝缘层140，形成在所述有源层130远离所述缓冲层120的一侧；第一金属层形成在所述栅极绝缘层140远离所述有源层130的一侧，图案化形成栅极150和公共电极160。
现有阵列基板制备方法中，由于栅极150和公共电极160由同一金属层在同一平面上湿刻蚀形成，所述栅极150和公共电极160容易形成半封闭空间，造成刻蚀液在栅极150和公共电极160之间发生残留，无法排除，从而导致在后续制程中，刻蚀液对栅极150和公共电极160进行持续刻蚀，使得栅极150和公共电极160的走线过细，容易造成显示面板显示不良。
现有技术在双走线设计的薄膜晶体管中，存在栅极和公共电极之间残留刻蚀液影响显示面板良率的问题。
针对现有问题，如图2所示，本申请提供一种阵列基板，所述阵列基板包括：衬底110；缓冲层120，形成在所述110衬底之上；有源层130，形成在所述缓冲层120远离衬底110的一侧；栅极绝缘层140，形成在所述有源层130远离所述缓冲层120的一侧；凹槽T1，设置在所述栅极绝缘层中；栅极150设置在所述栅极绝缘层远离所述有源层130的一侧；公共电极160，设置在凹槽T1内。本申请通过栅极150和公共电极160之间形成有高度差，缓解了金属层在刻蚀时，刻蚀液容易在栅极和公共电极之间残留的问题。
在一些实施例中，衬底110的材料一般为玻璃；缓冲层120为无机材料，可以为氮化硅、氧化硅中的一种；有源层130的材料为多晶硅层，制备有源层130时，首先在所述缓冲层130上形成非晶硅层，然后向反应腔室通入甲烷和反应气体，进行高温活化形成活性离子和离子团，在非晶硅层上形成掺杂有离子的非晶硅薄膜，然后对非晶硅薄膜进行晶化工艺处理，对非晶硅薄膜进行加热到700度以上，形成多晶硅层。向反应腔通入刻蚀气体，对所述多晶硅层进行图案化处理，形成有源层的沟道区，沟道区的两侧形成有源层130的掺杂区；栅极绝缘层140的材料为无机材料，可以为氮化硅、氧化硅中的一种。
凹槽T1形成在所述栅极绝缘层140远离所述缓冲层120的一侧，所述凹槽T1与所述有源层130设置在同一水平面，且距离所述有源层130边缘的距离为30纳米到50纳米。
在一些实施例中，所述凹槽T1贯穿栅极绝缘层140到所述缓冲层的表面。
在一些实施例中，所述凹槽T1的深度为所述栅极绝缘层140的二分之一到三分之一。
在一些实施例中，所述凹槽T1的形状为倒梯形、三角形、半圆形中的一种。
在一些实施例中，使用磁控溅射方法，在所述栅极绝缘层140上制备第一金属层。第一金属层的材料可以是钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以是上述几种材料薄膜的组合结构。对第一金属层进行刻蚀，所述第一金属层在栅极绝缘层140远离所述有源层130的一侧形成栅极，在凹槽T1内形成公共电极。
在一些实施例中，使用磁控溅射方法，在凹槽T1内制备第一金属层，所述第一金属层经刻蚀后形成公共电极160，在栅极绝缘层140上制备第二金属层，所述第二金属层经刻蚀后形成栅极150。第一金属层的材料可以是钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以是上述几种材料薄膜的组合结构；第二金属层的材料可以是钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以是上述几种材料薄膜的组合结构，第一金属层和第二金属层的材料可以相同，也可以不同。
如图3所示，本申请提供一种阵列基板的制作方法，用于制备上述所述的阵列基板，所述方法包括：
步骤S1：提供一基板；
步骤S2：在所述基板上依次形成衬底、缓冲层、有源层、栅极绝缘层；
步骤S3：在所述栅极绝缘层涂布一层光阻；
步骤S4：对所述光阻进行曝光显影后，所述栅极绝缘层上形成有凹槽；
步骤S5：在所述栅极绝缘层上沉积金属层，所述金属层图案化形成栅极和公共电极。
现结合图5至图8说明，本阵列基板的工作步骤。
在步骤S1中，所述基板一般为玻璃基板。
在步骤S2中，如图5所示，缓冲层120为无机材料，可以为氮化硅、氧化硅中的一种；有源层130的材料为多晶硅层，制备有源层130时，首先在所述缓冲层130上形成非晶硅层，然后向反应腔室通入甲烷和反应气体，进行高温活化形成活性离子和离子团，在非晶硅层上形成掺杂有离子的非晶硅薄膜，然后对非晶硅薄膜进行晶化工艺处理，对非晶硅薄膜进行加热到700度以上，形成多晶硅层。向反应腔通入刻蚀气体，对所述多晶硅层进行图案化处理，形成有源层的沟道区，沟道区的两侧形成有源层130掺杂区；栅极绝缘层140的材料为无机材料，可以为氮化硅、氧化硅中的一种。
在步骤S3中，如图6所示，所述光阻210采用涂布方法涂布在所述栅极绝缘层140之上。所述光阻的材料包括光敏树脂和光引发剂，所述树脂为高分子聚合物，一般为碱性可溶性树脂，其分子链通常含有一定量的羧基等酸性基团，确保在显影过程中能与碱性显影液发生反应溶解；所述光引发剂经紫外线照射后分解形成自由基，促进单体及聚合体双键打开而发生交联架桥反应形成网络，生成了不溶于碱性显影液的膜层结构。
图4是对步骤S4的进一步说明，如图4所示，对于步骤S4包括：
步骤S401：提供一掩膜板，所述掩膜版形成有凹槽图案；
步骤S402：用所述掩膜版对所述光阻进行曝光显影，所述光阻在所述凹槽图案的位置上形成有通孔；
步骤S403：对所述栅极绝缘层进行刻蚀，在所述通孔内，所述栅极绝缘层形成有凹槽；
步骤S404：剥离剩余的光刻胶。
在步骤S401中，提供一掩膜板，所述掩膜版形成有凹槽图案，使用紫外线灯对所述光阻210进行照射，所述光阻210在除凹槽图案的透光区内经紫外线照射，光引分解形成自由基，促进单体及聚合体双键打开而发生交联架桥反应形成网络，生成了不溶于碱性显影液的膜层结构，而在未曝光的凹槽图案区域，由于光阻210中的树脂通常含有一定量的羧基等酸性基团，因此显影过程中，光阻210未曾曝光的区域能与碱性显影液发生反应溶解，形成通孔。
在步骤S402中，采用喷淋显影液的方式，去除所述凹槽图案下的光阻，形成通孔。如图7所示，所述通孔贯穿所述光阻210至所述栅极绝缘层140表面。所述显影液一般为碱性显影液，如氢氧化钾。
如图8所示，在步骤S403中，采用湿刻蚀方法对所述通孔内栅极绝缘层140进行刻蚀形成凹槽T1，所述刻蚀液可以为草酸溶液。
在一些实施例中，所述凹槽T1贯穿栅极绝缘层140到所述缓冲层的表面。
在一些实施例中，所述凹槽T1的深度为所述栅极绝缘层140的二分之一到三分之一。
在一些实施例中，所述凹槽T1的形状为倒梯形、三角形、半圆形中的一种。
在步骤S404中，对所述阵列基板进行烘干，蒸发剩余的光刻胶。
对步骤S5，如图2所示，在一些实施例中，使用磁控溅射方法，在所述栅极绝缘层140上制备第一金属层。第一金属层的材料可以是钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以是上述几种材料薄膜的组合结构。对第一金属层进行刻蚀，形成栅极150和公共电极160，其中，所述第一金属层在栅极绝缘层140远离所述有源层130的一侧形成栅极，在凹槽T1内形成公共电极。
在一些实施例中，使用磁控溅射方法，在凹槽T1内制备第一金属层，所述第一金属层经刻蚀后形成公共电极160，在栅极绝缘层140上制备第二金属层，所述第二金属层经刻蚀后形成栅极150。第一金属层的材料可以是钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以是上述几种材料薄膜的组合结构；第二金属层的材料可以是钼、铝、铝镍合金、钼钨合金、铬、或铜等金属，也可以是上述几种材料薄膜的组合结构，第一金属层和第二金属层的材料可以相同，也可以不同。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种阵列基板、显示面板及制作方法进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (15)

  1. 一种阵列基板，所述阵列基板包括：
    衬底；
    缓冲层，形成在所述衬底之上；
    有源层，形成在所述缓冲层远离所述衬底的一侧；
    栅极绝缘层，形成在所述有源层远离所述缓冲层的一侧，图案化形成有凹槽，所述凹槽设置在所述栅极绝缘层远离所述缓冲层的一侧；
    金属层，形成在所述栅极绝缘层远离所述缓冲层的一侧，所述金属层的厚度小于所述凹槽的深度；
    其中，所述金属层在所述有源层上方图案化形成栅极，所述金属层在所述凹槽内图案化形成公共电极，所述栅极和所述公共电极在水平方向上形成有高度差，所述公共电极与所述有源层之间绝缘。
  2. 如权利要求1所述的阵列基板，其中，在水平方向上，所述凹槽与所述有源层边缘的距离在30纳米到50纳米之间。
  3. 如权利要求1所述的阵列基板，其中，所述凹槽贯穿所述栅极绝缘层至所述缓冲层表面。
  4. 如权利要求1所述的阵列基板，其中，所述凹槽的深度为所述栅极绝缘层的二分之一到三分之一。
  5. 如权利要求1所述的阵列基板，其中，所述凹槽的形状包括倒梯形。
  6. 一种阵列基板的制作方法，用于制作阵列基板，所述制作方法包括：
    提供一基板；
    在所述基板上依次形成衬底、缓冲层、有源层、栅极绝缘层；
    在所述栅极绝缘层涂布一层光阻；
    对所述光阻进行曝光显影后，所述栅极绝缘层上形成有凹槽；
    在所述栅极绝缘层上沉积金属层，所述金属层图案化形成栅极和公共电极。
  7. 如权利要求6所述的制作方法，其中，所述对所述光阻进行曝光显影后，在所述栅极绝缘层上形成有凹槽的步骤包括：
    提供一掩膜板，所述掩膜版形成有凹槽图案；
    用所述掩膜版对所述光阻进行曝光显影，所述光阻在所述凹槽图案的位置上形成有通孔；
    对所述栅极绝缘层进行刻蚀，在所述通孔内，所述栅极绝缘层形成有凹槽；
    剥离剩余的光刻胶。
  8. 如权利要求7所述的制作方法，其中，所述对所述栅极绝缘层进行刻蚀，在所述通孔内，所述栅极绝缘层形成有凹槽的步骤包括：采用湿刻蚀法形成所述凹槽。
  9. 如权利要求6所述的制作方法，所述在所述栅极绝缘层上沉积金属层，所述金属层图案化形成栅极和公共电极的步骤包括：
    在所述栅极绝缘层上沉积金属层，所述金属层经过一次构图工艺形成栅极和公共电极，所述公共电极形成在所述凹槽内。
  10. 如权利要求6所述的制作方法，所述在所述栅极绝缘层上沉积金属层，所述金属层图案化形成栅极和公共电极的步骤包括：
    在所述凹槽内沉积第一金属层，所述第一金属层图案化形成公共电极；
    在所述栅极绝缘层上沉积第二金属层，所述第二金属层图案化形成栅极。
  11. 一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括：
    衬底；
    缓冲层，形成在所述衬底之上；
    有源层，形成在所述缓冲层远离所述衬底的一侧；
    栅极绝缘层，形成在所述有源层远离所述缓冲层的一侧，图案化形成有凹槽，所述凹槽设置在所述栅极绝缘层远离所述缓冲层的一侧；
    金属层，形成在所述栅极绝缘层远离所述缓冲层的一侧，所述金属层的厚度小于所述凹槽的深度；
    其中，所述金属层在所述有源层上方图案化形成栅极，所述金属层在所述凹槽内图案化形成公共电极，所述栅极和所述公共电极在水平方向上形成有高度差，所述公共电极与所述有源层之间绝缘。
  12. 如权利要求11所述的显示面板，其中，在水平方向上，所述凹槽与所述有源层边缘的距离在30纳米到50纳米之间。
  13. 如权利要求11所述的显示面板，其中，所述凹槽贯穿所述栅极绝缘层至所述缓冲层表面。
  14. 如权利要求11所述的显示面板，其中，所述凹槽的深度为所述栅极绝缘层的二分之一到三分之一。
  15. 如权利要求11所述的显示面板，其中，所述凹槽的形状包括倒梯形。
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