WO2021253717A1 - 存储器及其形成方法、控制方法 - Google Patents

存储器及其形成方法、控制方法 Download PDF

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Publication number
WO2021253717A1
WO2021253717A1 PCT/CN2020/128161 CN2020128161W WO2021253717A1 WO 2021253717 A1 WO2021253717 A1 WO 2021253717A1 CN 2020128161 W CN2020128161 W CN 2020128161W WO 2021253717 A1 WO2021253717 A1 WO 2021253717A1
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Prior art keywords
electrically connected
magnetic tunnel
access transistors
target
memory
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PCT/CN2020/128161
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English (en)
French (fr)
Inventor
平尔萱
王晓光
吴保磊
吴玉雷
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长鑫存储技术有限公司
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Priority to EP20925004.2A priority Critical patent/EP3958319B1/en
Priority to US17/310,366 priority patent/US11805701B2/en
Publication of WO2021253717A1 publication Critical patent/WO2021253717A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1655—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods

Definitions

  • the present invention relates to the technical field of semiconductor manufacturing, in particular to a memory and its forming method and control method.
  • Magnetic Random Access Memory is based on the integration of silicon-based complementary oxide semiconductor (CMOS) and magnetic tunnel junction (Megnetic Tuning Junction, MTJ) technology. It is a non-volatile memory with static The high-speed read and write capability of random access memory and the high integration of dynamic random access memory.
  • the magnetic tunnel junction generally includes a fixed layer, a tunneling layer, and a free layer. When the magnetic random access memory is working normally, the magnetization direction of the free layer can be changed, while the magnetization direction of the fixed layer remains unchanged.
  • the resistance of the magnetic random access memory is related to the relative magnetization direction of the free layer and the fixed layer. When the magnetization direction of the free layer changes relative to the magnetization direction of the fixed layer, the resistance value of the magnetic random access memory changes correspondingly, corresponding to different storage information.
  • the present invention provides a memory and a forming method and a control method thereof, which are used to solve the problem that the comprehensive performance of the existing memory needs to be further improved.
  • the present invention provides a memory including:
  • a substrate having a plurality of active regions arranged in an array and a plurality of word lines extending in a first direction, the active regions are inclined at a predetermined angle with respect to the word lines, and the At least one access transistor in the source area;
  • a plurality of bit lines extending along a second direction perpendicular to the first direction
  • a magnetic tunnel junction one end is electrically connected to one of the bit lines, the other end is electrically connected to two of the access transistors at the same time, and the two access transistors that are electrically connected to one of the magnetic tunnel junctions are respectively located in two adjacent ones The active area.
  • it also includes:
  • a conductive contact pad is located above the substrate, one end of the conductive contact pad is electrically connected to the magnetic tunnel junction, and the other end is simultaneously electrically connected to the sources of the two access transistors.
  • the two access transistors electrically connected to one of the magnetic tunnel junctions are respectively located in two adjacent active regions arranged along the second direction; or,
  • the two access transistors electrically connected to one of the magnetic tunnel junctions are respectively located in two adjacent active regions arranged along a third direction, and the third direction is inclined with respect to the first direction The preset angle.
  • each of the active regions has two of the access transistors distributed at opposite ends of the active region;
  • the two access transistors electrically connected to one of the magnetic tunnel junctions are respectively located at the ends of two adjacent active regions close to each other.
  • one of the active regions overlaps two adjacent word lines
  • the two access transistors located in the same active area correspond to the two word lines respectively.
  • it also includes:
  • the source line extends along the first direction, and one of the active regions overlaps one of the source lines;
  • the drains of the two access transistors located in the same active area are electrically connected to the same source line.
  • the source line is curved, and the source line is electrically connected to the access transistor in the active area at a corner.
  • the preset angle is greater than 30° and less than 90°.
  • the present invention also provides a method for forming a memory, which includes the following steps:
  • a substrate is formed, and the substrate has a plurality of active regions arranged in an array and a plurality of word lines extending along a first direction, the active regions are inclined at a predetermined angle with respect to the word lines, the At least one access transistor in the active area;
  • a magnetic tunnel junction is formed on the substrate, one end of the magnetic tunnel junction is electrically connected to two of the access transistors at the same time, and the two access transistors connected to one of the magnetic tunnel junctions are located adjacent to each other. Two of the active areas;
  • a plurality of bit lines extending in a second direction are formed, the other end of the magnetic tunnel junction is electrically connected to the bit lines, and the second direction is perpendicular to the first direction.
  • the specific steps of forming a magnetic tunnel junction on the substrate include:
  • a magnetic tunnel junction is formed above the conductive contact pad, and the magnetic tunnel junction is electrically connected to the conductive contact pad.
  • the two access transistors electrically connected to one of the magnetic tunnel junctions are respectively located in two adjacent active regions arranged along the second direction; or,
  • the two access transistors electrically connected to one of the magnetic tunnel junctions are respectively located in two adjacent active regions arranged along a third direction, and the third direction is inclined with respect to the first direction The preset angle.
  • the specific steps of forming the substrate include:
  • a plurality of active regions arranged in an array, a plurality of word lines extending along a first direction, and two access transistors located in each of the active regions are formed in the semiconductor substrate.
  • the area is inclined at a predetermined angle with respect to the word line, and the two access transistors are distributed at opposite ends of the active area.
  • one of the active regions overlaps two adjacent word lines
  • the two access transistors located in the same active area correspond to the two word lines respectively.
  • a source line extending along the first direction is formed on the substrate, one of the active regions overlaps with one of the source lines, and the two accesses located in the same active region
  • the drains of the transistors are all electrically connected to the same source line.
  • the source line is curved, and the source line is electrically connected to the access transistor in the active area at a corner.
  • the preset angle is greater than 30° and less than 90°.
  • the present invention also provides a method for controlling a memory, the memory including a plurality of source lines extending along the first direction; the method includes the following steps:
  • One end of the target magnetic tunnel junction is electrically connected to a target bit line, and the other end is simultaneously electrically connected to the sources of two target access transistors.
  • the drains of the two target access transistors are connected to two
  • the target source line is electrically connected, and the gates of the two target access transistors are respectively electrically connected to the two target word lines;
  • the word lines other than the target word line transmit a low level to all the source lines to perform a first write operation.
  • Transmit a low level to all the bit lines transmit a high level to two of the target word lines, and simultaneously transmit a low level to the word lines other than the target word line, transmit a high level To the target source line and transmit a low level to the source line other than the target source line, and perform a second write operation.
  • the word lines other than the target word line transmit a low level to all the source lines to perform a read operation.
  • a low level is transmitted to all the bit lines, a low level is transmitted to all the word lines, and a low level is transmitted to all the source lines, and a standby operation is performed.
  • the memory and its forming method and control method provided by the present invention are achieved by setting the active area to be inclined at a predetermined angle with respect to the extension direction of the word line, and simultaneously connecting two adjacent active regions through a magnetic tunnel junction.
  • the access transistors in the area not only ensure the large drive current required for programming the memory, but also increase the storage density of the memory cell and improve the overall performance of the memory, thereby enhancing the product competitiveness of the magnetic memory.
  • Fig. 1 is a schematic diagram of a structure of a memory in a specific embodiment of the present invention
  • FIG. 2 is a schematic structural diagram of a memory including a bit line and a source line in a specific embodiment of the present invention
  • FIG. 3 is another schematic diagram of the structure of the memory in the specific embodiment of the present invention.
  • FIG. 4 is an equivalent circuit diagram of the electrical connection between an access transistor and a magnetic tunnel junction in a specific embodiment of the present invention
  • Fig. 5 is a flowchart of a method for forming a memory in a specific embodiment of the present invention.
  • Fig. 6 is a schematic diagram of control when writing, reading and standby operations are performed on the memory in a specific embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of a memory in a specific embodiment of the present invention
  • Fig. 2 is a schematic structural diagram of a memory including bit lines and source lines in a specific embodiment of the present invention.
  • the memory described in this specific embodiment includes:
  • a substrate having a plurality of active regions 10 arranged in an array and a plurality of word lines WL extending along a first direction D1, the active regions 10 are preset to be inclined with respect to the word lines WL From a perspective, there is at least one access transistor in the active region 10;
  • a plurality of bit lines BL extend along a second direction D2 perpendicular to the first direction D1;
  • a magnetic tunnel junction M one end is electrically connected to one of the bit lines BL, the other end is electrically connected to two of the access transistors at the same time, and the two access transistors electrically connected to one of the magnetic tunnel junctions are located adjacent to each other.
  • the active regions 10 Within two of the active regions 10.
  • the active region 10 is represented by a dotted line.
  • the substrate may be, but is not limited to, a silicon substrate.
  • the plurality of active regions 10 are arranged in an array form inside the substrate, for example, but not limited to a staggered arrangement, so as to increase the arrangement density of the active regions 10.
  • each of the active regions 10 extends along the third direction D3
  • each of the word lines WL extends along the first direction D1
  • the first direction D1 corresponds to the third direction D1.
  • the angle ⁇ between D3 is the preset angle.
  • the preset angle is a non-right angle.
  • the preset angle is greater than 30° and less than 90°, such as 45°-75°, 50°-70°, or 65°-70°. In this specific embodiment, the preset angle is 68.95°.
  • the bit line BL is disposed above the magnetic tunnel junction M, and the bit line BL extends along a second direction D2 perpendicular to the first direction D1.
  • One end of the magnetic tunnel junction M is electrically connected to one of the bit lines BL, and the other end is simultaneously electrically connected to two access transistors located in two adjacent active regions 10 (not shown in the figure).
  • the specific manner of electrical connection between the magnetic tunnel junction M and the access transistor can be direct contact electrical connection, or indirect electrical connection through other electrical components (such as plugs).
  • the specific type of the access transistor can be a transistor of any structure, such as a buried gate structure transistor, a ring gate field effect transistor, or a planar structure transistor.
  • the buried gate structure transistor can be used to reduce the transistor size while ensuring sufficient channel length. Occupies area, thereby increasing storage density.
  • FIG. 4 is an equivalent circuit diagram of the electrical connection between an access transistor and a magnetic tunnel junction in a specific embodiment of the present invention.
  • AT1 represents an access transistor located in one of the active regions 10
  • AT2 represents an adjacent transistor located in the adjacent active area.
  • This specific embodiment provides a new layout of electrical elements in a memory, specifically by setting the active region 10 inclined at a predetermined angle with respect to the extension direction of the word line WL, and by limiting the magnetic
  • the location of the tunnel junction M enables one of the magnetic tunnel junctions M to simultaneously electrically connect the access transistors located in the two adjacent active regions, which not only ensures the drive current required for programming the magnetic tunnel junction M , And at the same time can increase the storage density, thereby improving the overall performance of the memory.
  • the memory further includes:
  • the conductive contact pad 11 is located above the substrate. One end of the conductive contact pad 11 is electrically connected to the magnetic tunnel junction M, and the other end is electrically connected to the sources of the two access transistors.
  • the projection of the conductive contact pad 11 in a direction perpendicular to the substrate may extend from one active region 10 to another active region adjacent to the active region 10. 10, so as to realize the electrical connection between the bottom end of one conductive contact pad 11 and the sources of the two access transistors in two adjacent active regions 10, and the top end of the conductive contact pad 11
  • One of the magnetic tunnel junctions M is electrically connected.
  • the arrangement of the conductive contact pad 11 helps to increase the electrical connection area between the access transistor and the magnetic tunnel junction M, thereby ensuring the connection between the magnetic tunnel junction M and the access transistor. The stability of the electrical connection.
  • the two access transistors electrically connected to one of the magnetic tunnel junctions M are respectively located in the two adjacent active regions 10 arranged along the second direction D2, as shown in FIGS. 1 and As shown in Figure 2.
  • a plurality of the active regions 10 are arranged in parallel along the second direction D2, and two adjacent active regions 10 are arranged in parallel along the second direction D2.
  • the magnetic tunnel junction M is arranged between the source regions 10.
  • one conductive contact pad 11 extending along the first direction D1 is provided between the magnetic tunnel junction M and the active region 10, and the conductive The contact pad 11 extends from one active area 10 to another adjacent active area 10 along a projection perpendicular to the substrate direction.
  • the two access transistors respectively located in the two adjacent active regions 10 arranged along the second direction D2 are electrically connected to one of the magnetic tunnel junctions M through the conductive contact pads 11, A 2T1MTJ (Two-transistor-one-MTJ, 2 transistors and 1 magnetic tunnel junction) structure is formed.
  • a projection of the bit line BL along the direction perpendicular to the substrate and along the second direction D2 is arranged in parallel and overlaps all the magnetic tunnel junctions electrically connected to the bit line BL.
  • the extension direction of the conductive contact pad 11 may deviate from the first direction D1. Those skilled in the art can set it according to actual needs.
  • Fig. 3 is a schematic diagram of another structure of a memory in a specific embodiment of the present invention.
  • Those skilled in the art can also make the two access transistors electrically connected to one magnetic tunnel junction M located in two adjacent active regions 10 arranged along the third direction D3 according to actual needs.
  • the third direction D3 is inclined by the preset angle ⁇ relative to the first direction D1, as shown in FIG. 3.
  • a plurality of the active regions 10 are arranged in parallel, and the active regions 10 are arranged in parallel.
  • a magnetic tunnel junction M is provided between two active regions 10 arranged in parallel along the third direction D3.
  • a conductive contact pad 11 extending along the third direction D3 is provided between the magnetic tunnel junction M and the active region 10, and the conductive The contact pad 11 extends from one active area 10 to another adjacent active area 10 along a projection perpendicular to the substrate direction.
  • the two access transistors respectively located in the two adjacent active regions 10 arranged along the third direction D3 are electrically connected to one magnetic tunnel junction M through the conductive contact pads 11, It is also possible to form a 2T1MTJ structure.
  • the position of the bit line BL needs to be adjusted accordingly so that one of the bit lines BL is perpendicular to the liner.
  • the projection in the bottom direction overlaps all the magnetic tunnel junctions arranged in parallel along the second direction D2 and electrically connected to the bit line BL.
  • each of the active regions 10 has two of the access transistors distributed at opposite ends of the active region 10;
  • the two access transistors electrically connected to one magnetic tunnel junction M are respectively located at the ends of two adjacent active regions 10 close to each other.
  • the access transistors there are two access transistors distributed on opposite ends of the active area 10 along the third direction D3 in one of the active areas 10.
  • the projection of one magnetic tunnel junction M in a direction perpendicular to the substrate is located between two adjacent active regions, so that two magnetic tunnel junctions electrically connected to one magnetic tunnel junction M are located between two adjacent active regions.
  • the access transistors are respectively located at the ends of two adjacent active regions 10 close to each other to simplify the circuit structure of the memory.
  • one of the active regions 10 overlaps two adjacent word lines WL;
  • the two access transistors located in the same active region 10 respectively correspond to the two word lines WL.
  • two adjacent word lines WL pass through the same active region 10, and a part of one of the word lines WL serves as a part of one of the access transistors in the active region 10.
  • the other part of the word line WL serves as the gate of the other access transistor in the active region 10, so that the two access transistors located in the same active region 10
  • the transistors can be controlled by the two word lines WL respectively.
  • the memory further includes:
  • the source line SL extends along the first direction D1, and one of the active regions 10 overlaps one of the source lines SL;
  • the drains of the two access transistors located in the same active region 10 are electrically connected to the same source line SL.
  • the source line SL is curved, and the source line SL is electrically connected to the access transistor in the active region 10 at a corner.
  • FIG. 2 only shows part of the source line SL as an example.
  • the drains of all the access transistors inside the substrate must be connected to the corresponding source lines SL.
  • the pole line SL is electrically connected.
  • the source line SL is set in a curved shape, such as a fold line shape or a wavy line shape, and the source line SL is the same as the one at a corner.
  • the drains of the two access transistors in the active region 10 are electrically connected at the same time. For example, the two access transistors are electrically connected to the same source line SL by sharing the drains.
  • the electrode in the access transistor that is electrically connected to the magnetic tunnel junction M through the conductive contact pad 11 is referred to as the source and is electrically connected to the source line SL.
  • the electrode is called the drain, just for the convenience of distinguishing the two electrodes in the access transistor, so as to more clearly describe the structure of the memory provided by this embodiment, and the protection scope is not limited accordingly.
  • Those skilled in the art can also refer to the electrode electrically connected to the magnetic tunnel junction M through the conductive contact pad 11 in the access transistor as the drain according to actual needs.
  • the electrode electrically connected to the SL is called the source.
  • FIG. 5 is a flowchart of a method for forming a memory in a specific embodiment of the present invention.
  • the structure of the memory formed in this specific embodiment can be seen in FIG. 1 to FIG. 4.
  • the method for forming a memory provided by this embodiment includes the following steps:
  • a substrate is formed.
  • the substrate has a plurality of active regions 10 arranged in an array and a plurality of word lines WL extending along the first direction D1.
  • the active regions 10 are opposite to the word lines.
  • WL is inclined at a predetermined angle ⁇ , and at least one access transistor is provided in the active region 10;
  • a magnetic tunnel junction M is formed on the substrate, one end of the magnetic tunnel junction M is electrically connected to two of the access transistors at the same time, and two of the magnetic tunnel junctions M are electrically connected to each other.
  • the access transistors are respectively located in two adjacent active regions 10;
  • Step S53 forming a plurality of bit lines BL extending along a second direction D2, the other end of the magnetic tunnel junction M is electrically connected to the bit line BL, and the second direction D2 is perpendicular to the first direction D1.
  • the specific steps of forming a magnetic tunnel junction M on the substrate include:
  • a magnetic tunnel junction M is formed above the conductive contact pad 11, and the magnetic tunnel junction M is electrically connected to the conductive contact pad 11.
  • the two access transistors electrically connected to one magnetic tunnel junction M are respectively located in two adjacent active regions 10 arranged along the second direction D2; or,
  • the two access transistors electrically connected to one of the magnetic tunnel junctions M are respectively located in the two adjacent active regions 10 arranged along the third direction D3, and the third direction D3 is relative to the The first direction D1 is inclined by the predetermined angle ⁇ .
  • the specific steps of forming the substrate include:
  • a plurality of active regions 10 arranged in an array in the semiconductor substrate, a plurality of word lines WL extending along the first direction D1, and two access transistors located in each of the active regions 10,
  • the active region 10 is inclined at a predetermined angle ⁇ relative to the word line WL, and two of the access transistors are distributed at opposite ends of the active region 10.
  • one of the active regions 10 overlaps two adjacent word lines WL;
  • the two access transistors located in the same active region 10 respectively correspond to the two word lines WL.
  • the method for forming the memory further includes the following steps:
  • a source line SL extending along the first direction D1 is formed on the substrate, one of the active regions 10 overlaps with one of the source lines SL, and two of the active regions 10 are located in the same active region.
  • the drains of all the access transistors are connected to the same source line SL.
  • the source line SL is curved, and the source line SL is connected to the access transistor in the active region 10 at a corner.
  • the preset angle is greater than 30° and less than 90°.
  • FIG. 6 is a schematic diagram of control when writing, reading and standby operations are performed on the memory in a specific embodiment of the present invention.
  • the structure of the memory described in this specific embodiment can be seen in FIG. 2.
  • the memory includes a plurality of source lines SL extending along the first direction D1; the control method of the memory includes the following steps:
  • One end of the target magnetic tunnel junction is electrically connected to a target bit line, and the other end is simultaneously electrically connected to the sources of two target access transistors.
  • the drains of the two target access transistors are connected to two The target source line is connected, and the gates of the two target access transistors are electrically connected to the two target word lines respectively;
  • the word lines other than the target word line transmit a low level to all the source lines to perform a first write operation.
  • the memory control method further includes the following steps:
  • Transmit a low level to all the bit lines transmit a high level to two of the target word lines, and simultaneously transmit a low level to the word lines other than the target word line, transmit a high level To the target source line and transmit a low level to the source line other than the target source line, and perform a second write operation.
  • the memory control method further includes the following steps:
  • the word lines other than the target word line transmit a low level to all the source lines to perform a read operation.
  • the memory control method further includes the following steps:
  • a low level is transmitted to all the bit lines, a low level is transmitted to all the word lines, and a low level is transmitted to all the source lines, and a standby operation is performed.
  • the following description takes the magnetic tunnel junction M[ij] shown in FIG. 2 as the target magnetic tunnel junction as an example.
  • a high level for example, a bit line boost voltage
  • the low level for example, the ground voltage
  • transmission high Level for example, word line boost voltage
  • a low level lower than the high level for example, the ground voltage or lower than the ground voltage
  • the negative voltage to the word line WL[other] other than the target word line WL[j-1] and WL[j], such as WL[j+1], etc.
  • transmit low level (such as ground Voltage) to all the source lines SL, such as SL[k-1], SL[
  • write 0 write 0
  • BL[i] and BL[other] transmit high power Level (for example, word line boost voltage) to the two target word lines WL[j-1] and WL[j], and simultaneously transmit a low level (for example, ground voltage or a negative voltage lower than the ground voltage) to The word lines WL[others] except the target word lines WL[j-1] and WL[j], such as WL[j+1], etc.; transmit high level (such as source line boost voltage ) To the target source lines SL[k-1] and SL[k], and transmit a low level (for example, a ground voltage) lower than the high level to the target source line SL[k-1] And the source line SL[other] other than SL[k], such as SL[k+1] and so on.
  • a low level such as ground voltage
  • a high level for example, a bit line boost voltage
  • a low level for example, a ground voltage
  • the outer bit line BL[other] such as BL[i-1], BL[i+1], etc.; transmit a high level (such as word line boost voltage) to the target word line WL[j-1 ] And WL[j], and simultaneously transmit a low level (such as a ground voltage or a negative voltage lower than the ground voltage) to the target word lines WL[j-1] and WL[j].
  • Word line WL[others] such as WL[j+1], etc.; transmitting low level (such as ground voltage) to all the source lines SL, such as SL[k-1], SL[k], SL[ k+1] etc.
  • the high level and low level mentioned in this specific embodiment are both relative concepts (that is, the voltage value of the high level is higher than the voltage value of the corresponding low level), and the specific high level is not limited.
  • the voltage value does not limit the specific voltage value of the low level.
  • it does not limit the high voltage applied on different signal lines in this specific embodiment to be equal.
  • the high level on the bit line and the high level on the word line may be different voltages, and there is no limitation on the specific voltage.
  • the high levels of the signal lines at different stages are the same.
  • the high levels applied by the bit line during write 1 and read operations may have different voltage values.
  • the corresponding high-level and low-level values can be set by themselves according to process nodes, speed requirements, reliability requirements, etc.
  • the active area is set to be inclined at a predetermined angle with respect to the extension direction of the word line, and two adjacent ones are connected at the same time through a magnetic tunnel junction.
  • the access transistors in the active area not only ensure the large drive current required for programming the memory, but also increase the storage density of the memory cell and improve the overall performance of the memory, thereby enhancing the product competitiveness of the magnetic memory.

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Abstract

本发明涉及半导体制造技术领域，尤其涉及一种存储器及其形成方法、控制方法。所述存储器包括：衬底，所述衬底内具有呈阵列排布的多个有源区和多条沿第一方向延伸的字线，所述有源区相对于所述字线倾斜预设角度，所述有源区内具有至少一存取晶体管；多条位线，沿与所述第一方向垂直的第二方向延伸；磁性隧道结，一端电连接一条所述位线、另一端同时电连接两个所述存取晶体管，与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于相邻两个所述有源区内。本发明既保证了对存储器进行编程时所需的大驱动电流，同时又提高了存储单元的存储密度，提高了存储器的综合性能，从而增强磁性存储器的产品竞争力。

Description

存储器及其形成方法、控制方法
相关申请引用说明
本申请要求于2020年6月19日递交的中国专利申请号202010564993.0、申请名为“存储器及其形成方法、控制方法”的优先权，其全部内容以引用的形式附录于此。
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种存储器及其形成方法、控制方法。
背景技术
磁性随机存储器(Magnetic Random Access Memory，MARM)是基于硅基互补氧化物半导体(CMOS)与磁性隧道结(Megnetic Tuning Junction，MTJ)技术的集成，是一种非易失性的存储器，它拥有静态随机存储器的高速读写能力、以及动态随机存储器的高集成度。所述磁性隧道结通常包括固定层、隧穿层和自由层。在磁性随机存储器正常工作时，自由层的磁化方向可以改变，而固定层的磁化方向保持不变。磁性随机存储器的电阻与自由层和固定层的相对磁化方向有关。当自由层的磁化方向相对于固定层的磁化方向发生改变时，磁性随机存储器的电阻值相应改变，对应于不同的存储信息。
但是，在现有的磁性随机存储器中，由于存储单元的排布方式以及磁性隧道结与晶体管的连接方式的限制，制约了磁性随机存储器综合性能的进一步提高，从而限制了磁性随机存储器的广泛应用。
因此，如何改善存储器的结构，提升存储器的综合性能，是目前亟待解决的技术问题。
发明内容
本发明提供一种存储器及其形成方法、控制方法，用于解决现有的存储器综合性能有待进一步提高的问题。
为了解决上述问题，本发明提供了一种存储器，包括：
衬底，所述衬底内具有呈阵列排布的多个有源区和多条沿第一方向延伸的字线，所述有源区相对于所述字线倾斜预设角度，所述有源区内具有至少一存 取晶体管；
多条位线，沿与所述第一方向垂直的第二方向延伸；
磁性隧道结，一端电连接一条所述位线、另一端同时电连接两个所述存取晶体管，与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于相邻两个所述有源区内。
可选的，还包括：
导电接触垫，位于所述衬底上方，所述导电接触垫的一端电连接所述磁性隧道结、另一端同时电连接两个所述存取晶体管的源极。
可选的，与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于沿所述第二方向排列且相邻的两个所述有源区内；或者，
与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于沿第三方向排列且相邻的两个所述有源区内，所述第三方向相对于所述第一方向倾斜所述预设角度。
可选的，每一所述有源区内具有分布于所述有源区相对两端的两个所述存取晶体管；
与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于两个相邻的所述有源区相互靠近的端部。
可选的，一个所述有源区与两条相邻的所述字线交叠；
位于同一所述有源区内的两个所述存取晶体管分别与两条所述字线对应。
可选的，还包括：
源极线，沿所述第一方向延伸，且一个所述有源区与一条所述源极线交叠；
位于同一所述有源区内的两个所述存取晶体管的漏极均与同一条所述源极线电连接。
可选的，所述源极线呈弯曲状，且所述源极线在拐角处与所述有源区内的所述存取晶体管电连接。
可选的，所述预设角度大于30°且小于90°。
为了解决上述问题，本发明还提供了一种存储器的形成方法，包括如下步骤：
形成衬底，所述衬底内具有呈阵列排布的多个有源区和多条沿第一方向延伸的字线，所述有源区相对于所述字线倾斜预设角度，所述有源区内具有至少一存取晶体管；
形成磁性隧道结于所述衬底之上，所述磁性隧道结的一端同时电连接两个所述存取晶体管，与一个所述磁性隧道结连接的两个所述存取晶体管分别位于相邻两个所述有源区内；
形成多条沿第二方向延伸的位线，所述磁性隧道结的另一端电连接所述位线，所述第二方向与所述第一方向垂直。
可选的，形成磁性隧道结于所述衬底之上的具体步骤包括：
形成导电接触垫于所述衬底上方，所述导电接触垫同时电连接两个所述存取晶体管的源极；
形成磁性隧道结于所述导电接触垫上方，所述磁性隧道结与所述导电接触垫电连接。
可选的，与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于沿所述第二方向排列且相邻的两个所述有源区内；或者，
与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于沿第三方向排列且相邻的两个所述有源区内，所述第三方向相对于所述第一方向倾斜所述预设角度。
可选的，形成衬底的具体步骤包括：
提供半导体基底；
于所述半导体基底内形成呈阵列排布的多个有源区、多条沿第一方向延伸的字线、以及位于每一个所述有源区内的两个存取晶体管，所述有源区相对于所述字线倾斜预设角度，且两个所述存取晶体管分布于所述有源区的相对两端。
可选的，一个所述有源区与两条相邻的所述字线交叠；
位于同一所述有源区内的两个所述存取晶体管分别与两条所述字线对应。
可选的，还包括如下步骤：
形成沿所述第一方向延伸的源极线于所述衬底上，一个所述有源区与一条 所述源极线交叠，位于同一所述有源区内的两个所述存取晶体管的漏极均与同一条所述源极线电连接。
可选的，所述源极线呈弯曲状，且所述源极线在拐角处与所述有源区内的所述存取晶体管电连接。
可选的，所述预设角度大于30°且小于90°。
为了解决上述问题，本发明还提供了一种存储器的控制方法，所述存储器中包括多条沿所述第一方向延伸的源极线；包括如下步骤：
选择目标磁性隧道结，所述目标磁性隧道结一端电连接一条目标位线、另一端同时电连接两个目标存取晶体管的源极，两个所述目标存取晶体管的漏极分别与两条目标源极线电连接，两个所述目标存取晶体管的栅极分别与两条目标字线电连接；
传输高电平至所述目标位线、并同时传输低电平至除所述目标位线之外的所述位线，传输高电平至所述目标字线、并同时传输低电平至除所述目标字线之外的所述字线，传输低电平至所有的所述源极线，进行第一写入操作。
可选的，还包括如下步骤：
传输低电平至所有的所述位线，传输高电平至两条所述目标字线、并同时传输低电平至除所述目标字线之外的所述字线，传输高电平至所述目标源极线、并传输低电平至除所述目标源极线之外的所述源极线，进行第二写入操作。
可选的，还包括如下步骤：
传输高电平至所述目标位线、并同时传输低电平至除所述目标位线之外的所述位线，传输高电平至所述目标字线、并同时传输低电平至除所述目标字线之外的所述字线，传输低电平至所有的所述源极线，进行读取操作。
可选的，还包括如下步骤：
传输低电平至所有的所述位线、传输低电平至所有的所述字线、并传输低电平至所有的所述源极线，进行待机操作。
本发明提供的存储器及其形成方法、控制方法，通过将有源区设置为相对于字线的延伸方向倾斜预设角度，且通过一个磁性隧道结同时连接位于相邻的两个所述有源区内的存取晶体管，既保证了对存储器进行编程时所需的大驱动 电流，同时又提高了存储单元的存储密度，提高了存储器的综合性能，从而增强磁性存储器的产品竞争力。
附图说明
附图1是本发明具体实施例中存储器的一结构示意图；
附图2是本发明具体实施例中包括位线和源极线的存储器的结构示意图；
附图3是本发明具体实施例中存储器的另一结构示意图；
附图4是本发明具体实施例中存取晶体管与磁性隧道结电连接的等效电路图；
附图5是本发明具体实施例中存储器的形成方法流程图；
附图6是本发明具体实施例中对所述存储器进行写入、读取和待机操作时的控制示意图。
具体实施例
下面结合附图对本发明提供的存储器及其形成方法、控制方法的具体实施例做详细说明。
本具体实施例提供了一种存储器。附图1是本发明具体实施例中存储器的一结构示意图，附图2是本发明具体实施例中包括位线和源极线的存储器的结构示意图。如图1和图2所示，本具体实施例所述的存储器，包括：
衬底，所述衬底内具有呈阵列排布的多个有源区10和多条沿第一方向D1延伸的字线WL，所述有源区10相对于所述字线WL倾斜预设角度，所述有源区10内具有至少一存取晶体管；
多条位线BL，沿与所述第一方向D1垂直的第二方向D2延伸；
磁性隧道结M，一端电连接一条所述位线BL、另一端同时电连接两个所述存取晶体管，与一个所述磁性隧道结M电连接的两个所述存取晶体管分别位于相邻两个所述有源区10内。
在图2中为了清楚表示所述有源区10与所述字线WL、所述位线BL之间的关系，故将所述有源区10以虚线表示。具体来说，所述衬底可以是但不限于硅衬底。多个所述有源区10在所述衬底内部呈阵列形式排布，例如可以是但不限于错位排列，以提高所述有源区10的排布密度。在本具体实施例中， 每个所述有源区10沿第三方向D3延伸，每条所述字线WL沿所述第一方向D1延伸，所述第一方向D1与所述第三方向D3之间的夹角β即为所述预设角度。所述预设角度为非直角，可选的，所述预设角度大于30°且小于90°，例如45°～75°、50°～70°或者65°～70°。在本具体实施例中，所述预设角度为68.95°。所述位线BL设置于所述磁性隧道结M的上方，且所述位线BL沿与所述第一方向D1垂直的第二方向D2延伸。一个所述磁性隧道结M的一端与一条所述位线BL电连接、另一端同时电连接分别位于相邻的两个所述有源区10内的两个存取晶体管(图中未示出)。其中，所述磁性隧道结M与所述存取晶体管电连接的具体方式可以是直接接触电连接，也可以是通过其他电学元件(如插塞)实现的间接电连接，本领域技术人员可以根据实际需要进行选择。所述存取晶体管的具体类型可以是任意结构的晶体管，例如埋栅结构晶体管、环栅场效应晶体管或者平面结构晶体管，利用埋栅结构晶体管可以在保证具有足够沟道长度情况下，减小晶体管的占用面积，从而提高存储密度。
附图4是本发明具体实施例中存取晶体管与磁性隧道结电连接的等效电路图，AT1表示位于一个所述有源区10内的一个存取晶体管、AT2表示位于相邻的所述有源区内的另一个存取晶体管。本具体实施例提供了一种新的存储器中电学元件的布局方式，具体是通过设置相对于所述字线WL的延伸方向倾斜预设角度的所述有源区10，并通过限定所述磁性隧道结M的位置，使得一个所述磁性隧道结M同时电连接位于相邻的两个所述有源区内的存取晶体管，既保证了对磁性隧道结M进行编程时所需的驱动电流，又同时能够提高存储密度，从而改善了存储器的综合性能。
可选的，所述存储器还包括：
导电接触垫11，位于所述衬底上方，所述导电接触垫11的一端电连接所述磁性隧道结M、另一端同时电连接两个所述存取晶体管的源极。
举例来说，所述导电接触垫11沿垂直于所述衬底方向上的投影可以从一个所述有源区10延伸至与该所述有源区10相邻的另一个所述有源区10，从而实现一个所述导电接触垫11的底端与相邻的两个所述有源区10内的两个所述存取晶体管的源极的电连接，所述导电接触垫11的顶端电连接一个所述磁性 隧道结M。所述导电接触垫11的设置，有助于增大所述存取晶体管与所述磁性隧道结M之间的电连接面积，从而确保了所述磁性隧道结M与所述存取晶体管之间电连接的稳定性。
可选的，与一个所述磁性隧道结M电连接的两个所述存取晶体管分别位于沿所述第二方向D2排列且相邻的两个所述有源区10内，如图1和图2所示。
具体来说，如图1和图2所示，多个所述有源区10沿所述第二方向D2平行排列，在相邻的两个沿所述第二方向D2平行排列的所述有源区10之间设置有一个所述磁性隧道结M。在沿垂直于所述衬底的方向上，于所述磁性隧道结M与所述有源区10之间设置有沿所述第一方向D1延伸的一个所述导电接触垫11，所述导电接触垫11沿垂直于所述衬底方向的投影从一个所述有源区10延伸至与其相邻的另一个所述有源区10。通过所述导电接触垫11实现分别位于沿所述第二方向D2排列且相邻的两个所述有源区10内的两个所述存取晶体管与一个所述磁性隧道结M电连接，形成2T1MTJ(Two-transistor-one-MTJ，2个晶体管1个磁性隧道结)结构。在此种排布方式中，为了实现所述位线BL与所述磁性隧道结M的电连接，一条所述位线BL沿垂直于所述衬底方向上的投影与沿所述第二方向D2平行排列且与该条所述位线BL电连接的所有所述磁性隧道结交叠。如图1和图2中所示的排布方式可以减小导电接触垫11与字线WL、位线BL的交叠，减小寄生电容，从而提升性能。需要注意的是，由于有源区的尺寸设置不同，可能导致所述导电接触垫11的延伸方向与第一方向D1有所偏差，本领域技术人可根据实际需求自行设置。
附图3是本发明具体实施例中存储器的另一结构示意图。本领域技术人员还可以根据实际需要，使得与一个所述磁性隧道结M电连接的两个所述存取晶体管分别位于沿第三方向D3排列的且相邻的两个所述有源区10内，所述第三方向D3相对于所述第一方向D1倾斜所述预设角度β，如图3所示。
具体来说，如图3所示，在沿相对于所述第一方向D1倾斜所述预设角度的所述第三方向D3上，多个所述有源区10平行排列，在相邻的两个沿所述第三方向D3平行排列的所述有源区10之间设置有一个所述磁性隧道结M。在沿垂直于所述衬底的方向上，于所述磁性隧道结M与所述有源区10之间设置 有沿所述第三方向D3延伸的一个所述导电接触垫11，所述导电接触垫11沿垂直于所述衬底方向的投影从一个所述有源区10延伸至与其相邻的另一个所述有源区10。通过所述导电接触垫11实现分别位于沿所述第三方向D3排列且相邻的两个所述有源区10内的两个所述存取晶体管与一个所述磁性隧道结M电连接，也可以形成2T1MTJ结构。在此种排布方式中，为了实现所述位线BL与所述磁性隧道结M的电连接，需要相应调所述位线BL的位置，使得一条所述位线BL沿垂直于所述衬底方向上的投影与沿所述第二方向D2平行排列且与该条所述位线BL电连接的所有所述磁性隧道结交叠。
可选的，每一所述有源区10内具有分布于所述有源区10相对两端的两个所述存取晶体管；
与一个所述磁性隧道结M电连接的两个所述存取晶体管分别位于两个相邻的所述有源区10相互靠近的端部。
具体来说，在一个所述有源区10内具有沿所述第三方向D3分布于所述有源区10相对两端的两个所述存取晶体管。一个所述磁性隧道结M在沿垂直于所述衬底的方向上的投影位于相邻的两个所述有源区之间，从而使得与一个所述磁性隧道结M电连接的两个所述存取晶体管分别位于两个相邻的所述有源区10相互靠近的端部，以简化所述存储器的电路结构。
可选的，一个所述有源区10与两条相邻的所述字线WL交叠；
位于同一所述有源区10内的两个所述存取晶体管分别与两条所述字线WL对应。
具体来说，两条相邻的所述字线WL穿过同一个所述有源区10，其中一条所述字线WL的部分作为所述有源区10内的一个所述存取晶体管的栅极，另一条所述字线WL的部分作为所述有源区10内的另一个所述存取晶体管的栅极，使得位于同一个所述有源区10内的两个所述存取晶体管可以由两条所述字线WL分别控制。
可选的，所述存储器还包括：
源极线SL，沿所述第一方向D1延伸，且一个所述有源区10与一条所述源极线SL交叠；
位于同一所述有源区10内的两个所述存取晶体管的漏极均与同一条所述源极线SL电连接。
可选的，所述源极线SL呈弯曲状，且所述源极线SL在拐角处与所述有源区10内的所述存取晶体管电连接。
图2中仅示例性的表示出了部分所述源极线SL，在实际的所述存储器产品中，所述衬底内部的所有所述存取晶体管的漏极均要与对应的所述源极线SL电连接。为了简化所述存储器的电路结构，本具体实施例将所述源极线SL设置成弯曲状，例如折线状或者波浪线状，并使得所述源极线SL在一个拐角处与同一个所述有源区10内的两个所述存取晶体管的漏极同时电连接，例如两个所述存取晶体管通过共用漏极的方式实现与同一条所述源极线SL的电连接。
在本具体实施例中，将所述存取晶体管中通过所述导电接触垫11与所述磁性隧道结M电连接的电极称之为源极、并将与所述源极线SL电连接的电极称之为漏极，只是为了便于区分所述存取晶体管中的两个电极，以更清楚的描述本具体实施例所提供的存储器的结构，并不因此限定保护范围。本领域技术人员也可以根据实际需要，将将所述存取晶体管中通过所述导电接触垫11与所述磁性隧道结M电连接的电极称之为漏极、相应将与所述源极线SL电连接的电极称之为源极。
不仅如此，本具体实施例还提供了一种存储器的形成方法。附图5是本发明具体实施例中存储器的形成方法流程图。本具体实施例形成的所述存储器的结构可参见图1-图4。如图1-图5所示，本具体实施例提供的存储器的形成方法，包括如下步骤：
步骤S51，形成衬底，所述衬底内具有呈阵列排布的多个有源区10和多条沿第一方向D1延伸的字线WL，所述有源区10相对于所述字线WL倾斜预设角度β，所述有源区10内具有至少一存取晶体管；
步骤S52，形成磁性隧道结M于所述衬底之上，所述磁性隧道结M的一端同时电连接两个所述存取晶体管，与一个所述磁性隧道结M电连接的两个所述存取晶体管分别位于相邻两个所述有源区10内；
步骤S53，形成多条沿第二方向D2延伸的位线BL，所述磁性隧道结M的另一端电连接所述位线BL，所述第二方向D2与所述第一方向D1垂直。
可选的，形成磁性隧道结M于所述衬底之上的具体步骤包括：
形成导电接触垫11于所述衬底上方，所述导电接触垫11同时电连接两个所述存取晶体管的源极；
形成磁性隧道结M于所述导电接触垫11上方，所述磁性隧道结M与所述导电接触垫11电连接。
可选的，与一个所述磁性隧道结M电连接的两个所述存取晶体管分别位于沿所述第二方向D2排列且相邻的两个所述有源区10内；或者，
与一个所述磁性隧道结M电连接的两个所述存取晶体管分别位于沿第三方向D3排列且相邻的两个所述有源区10内，所述第三方向D3相对于所述第一方向D1倾斜所述预设角度β。
可选的，形成衬底的具体步骤包括：
提供半导体基底；
于所述半导体基底内形成呈阵列排布的多个有源区10、多条沿第一方向D1延伸的字线WL、以及位于每一个所述有源区10内的两个存取晶体管，所述有源区10相对于所述字线WL倾斜预设角度β，且两个所述存取晶体管分布于所述有源区10的相对两端。
可选的，一个所述有源区10与两条相邻的所述字线WL交叠；
位于同一所述有源区10内的两个所述存取晶体管分别与两条所述字线WL对应。
可选的，所述存储器的形成方法还包括如下步骤：
形成沿所述第一方向D1延伸的源极线SL于所述衬底上，一个所述有源区10与一条所述源极线SL交叠，位于同一所述有源区10内的两个所述存取晶体管的漏极均与同一条所述源极线SL连接。
可选的，所述源极线SL呈弯曲状，且所述源极线SL在拐角处与所述有源区10内的所述存取晶体管连接。
可选的，所述预设角度大于30°且小于90°。
不仅如此，本具体实施例还提供了一种存储器的控制方法。附图6是本发明具体实施例中对所述存储器进行写入、读取和待机操作时的控制示意图。本具体实施例中所述的存储器的结构可参见图2。如图2和图6所示，所述存储器中包括多条沿所述第一方向D1延伸的源极线SL；所述存储器的控制方法，包括如下步骤：
选择目标磁性隧道结，所述目标磁性隧道结一端电连接一条目标位线、另一端同时电连接两个目标存取晶体管的源极，两个所述目标存取晶体管的漏极分别与两条目标源极线连接，两个所述目标存取晶体管的栅极分别与两条目标字线电连接；
传输高电平至所述目标位线、并同时传输低电平至除所述目标位线之外的所述位线，传输高电平至所述目标字线、并同时传输低电平至除所述目标字线之外的所述字线，传输低电平至所有的所述源极线，进行第一写入操作。
可选的，所述存储器的控制方法还包括如下步骤：
传输低电平至所有的所述位线，传输高电平至两条所述目标字线、并同时传输低电平至除所述目标字线之外的所述字线，传输高电平至所述目标源极线、并传输低电平至除所述目标源极线之外的所述源极线，进行第二写入操作。
可选的，所述存储器的控制方法还包括如下步骤：
传输高电平至所述目标位线、并同时传输低电平至除所述目标位线之外的所述位线，传输高电平至所述目标字线、并同时传输低电平至除所述目标字线之外的所述字线，传输低电平至所有的所述源极线，进行读取操作。
可选的，所述存储器的控制方法还包括如下步骤：
传输低电平至所有的所述位线、传输低电平至所有的所述字线、并传输低电平至所有的所述源极线，进行待机操作。
以下以图2中所示的磁性隧道结M[ij]作为目标磁性隧道结为例进行说明。在进行第一写入操作，即写入1(WRITE 1)操作时，传输高电平(例如位线升压电压)至所述目标位线BL[i]、并同时传输低于高电平的低电平(例如接地电压)至除所述目标位线BL[i]之外的所述位线BL[其他]，例如BL[i-1]、BL[i+1]等；传输高电平(例如字线升压电压)至所述目标字线WL[j-1]和WL[j]、 并同时传输低于高电平的低电平(例如接地电压或比接地电压更低的负电压)至除所述目标字线WL[j-1]和WL[j]之外的所述字线WL[其他]，例如WL[j+1]等；传输低电平(例如接地电压)至所有的所述源极线SL，例如SL[k-1]、SL[k]、SL[k+1]等。其中，i、j、k均为大于1的正整数。
在进行第二写入操作，即写入0(WRITE 0)操作时，传输低电平(例如接地电压)至所有的所述位线，包括BL[i]和BL[其他]；传输高电平(例如字线升压电压)至两条所述目标字线WL[j-1]和WL[j]、并同时传输低电平(例如接地电压或比接地电压更低的负电压)至除所述目标字线WL[j-1]和WL[j]之外的所述字线WL[其他]，例如WL[j+1]等；传输高电平(例如源极线升压电压)至所述目标源极线SL[k-1]和SL[k]、并传输低于高电平的低电平(例如接地电压)至除所述目标源极线SL[k-1]和SL[k]之外的所述源极线SL[其他]，例如SL[k+1]等。
在进行读取操作READ时，传输高电平(例如位线升压电压)至所述目标位线BL[i]、并同时传输低电平(例如接地电压)至除所述目标位线之外的所述位线BL[其他]，例如BL[i-1]、BL[i+1]等；传输高电平(例如字线升压电压)至所述目标字线WL[j-1]和WL[j]、并同时传输低电平(例如接地电压或比接地电压更低的负电压)至除所述目标字线WL[j-1]和WL[j]之外的所述字线WL[其他]，例如WL[j+1]等；传输低电平(例如接地电压)至所有的所述源极线SL，例如SL[k-1]、SL[k]、SL[k+1]等。
在进行待机操作OFF时，传输低电平(例如接地电压)至所有的所述位线BL，包括BL[i]和BL[其他]；传输低电平(例如接地电压或比接地电压更低的负电压)至所有的所述字线WL，包括WL[j-1]、WL[j]和WL[其他]；并传输低电平(例如接地电压)至所有的所述源极线SL[k-1]、SL[k]和SL[其他]。
需要注意的是，本具体实施例所称高电平、低电平均为相对的概念(即高电平的电压值高于与其对应的低电平的电压值)，不限定高电平的具体电压值，也不限定低电平的具体电压值。并且也并不限定本具体实施例中不同信号线上施加的高电平均相等，例如所述位线上的高电平与所述字线上的高电平可以为不同电压，也不限定特定信号线在不同阶段的高电平相等，例如所述位线在写 1时和读取操作时所施加的高电平可以为不同电压值。本领域内技术人员应该理解，根据工艺结点、速度要求、可靠性要求等可自行设置相应高电平和低电平的值。
本具体实施例提供的存储器及其形成方法、控制方法，通过将有源区设置为相对于字线的延伸方向倾斜预设角度，且通过一个磁性隧道结同时连接位于相邻的两个所述有源区内的存取晶体管，既保证了对存储器进行编程时所需的大驱动电流，同时又提高了存储单元的存储密度，提高了存储器的综合性能，从而增强磁性存储器的产品竞争力。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (20)

  1. 一种存储器，其特征在于，包括：
    衬底，所述衬底内具有呈阵列排布的多个有源区和多条沿第一方向延伸的字线，所述有源区相对于所述字线倾斜预设角度，所述有源区内具有至少一存取晶体管；
    多条位线，沿与所述第一方向垂直的第二方向延伸；
    磁性隧道结，一端电连接一条所述位线、另一端同时电连接两个所述存取晶体管，与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于相邻两个所述有源区内。
  2. 根据权利要求1所述的存储器，其特征在于，还包括：
    导电接触垫，位于所述衬底上方，所述导电接触垫的一端电连接所述磁性隧道结、另一端同时电连接两个所述存取晶体管的源极。
  3. 根据权利要求1所述的存储器，其特征在于，与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于沿所述第二方向排列且相邻的两个所述有源区内；或者，
    与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于沿第三方向排列且相邻的两个所述有源区内，所述第三方向相对于所述第一方向倾斜所述预设角度。
  4. 根据权利要求3所述的存储器，其特征在于，每一所述有源区内具有分布于所述有源区相对两端的两个所述存取晶体管；
    与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于两个相邻的所述有源区相互靠近的端部。
  5. 根据权利要求4所述的存储器，其特征在于，一个所述有源区与两条相邻的所述字线交叠；
    位于同一所述有源区内的两个所述存取晶体管分别与两条所述字线对应。
  6. 根据权利要求4所述的存储器，其特征在于，还包括：
    源极线，沿所述第一方向延伸，且一个所述有源区与一条所述源极线交叠；
    位于同一所述有源区内的两个所述存取晶体管的漏极均与同一条所述源极 线电连接。
  7. 根据权利要求6所述的存储器，其特征在于，所述源极线呈弯曲状，且所述源极线在拐角处与所述有源区内的所述存取晶体管电连接。
  8. 根据权利要求1所述的存储器，其特征在于，所述预设角度大于30°且小于90°。
  9. 一种存储器的形成方法，其特征在于，包括如下步骤：
    形成衬底，所述衬底内具有呈阵列排布的多个有源区和多条沿第一方向延伸的字线，所述有源区相对于所述字线倾斜预设角度，所述有源区内具有至少一存取晶体管；
    形成磁性隧道结于所述衬底之上，所述磁性隧道结的一端同时电连接两个所述存取晶体管，与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于相邻两个所述有源区内；
    形成多条沿第二方向延伸的位线，所述磁性隧道结的另一端电连接所述位线，所述第二方向与所述第一方向垂直。
  10. 根据权利要求9所述的存储器的形成方法，其特征在于，形成磁性隧道结于所述衬底之上的具体步骤包括：
    形成导电接触垫于所述衬底上方，所述导电接触垫同时电连接两个所述存取晶体管的源极；
    形成磁性隧道结于所述导电接触垫上方，所述磁性隧道结与所述导电接触垫电连接。
  11. 根据权利要求9所述的存储器的形成方法，其特征在于，与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于沿所述第二方向排列且相邻的两个所述有源区内；或者，
    与一个所述磁性隧道结电连接的两个所述存取晶体管分别位于沿第三方向排列且相邻的两个所述有源区内，所述第三方向相对于所述第一方向倾斜所述预设角度。
  12. 根据权利要求11所述的存储器的形成方法，其特征在于，形成衬底的具体 步骤包括：
    提供半导体基底；
    于所述半导体基底内形成呈阵列排布的多个有源区、多条沿第一方向延伸的字线、以及位于每一个所述有源区内的两个存取晶体管，所述有源区相对于所述字线倾斜预设角度，且两个所述存取晶体管分布于所述有源区的相对两端。
  13. 根据权利要求12所述的存储器的形成方法，其特征在于，一个所述有源区与两条相邻的所述字线交叠；
    位于同一所述有源区内的两个所述存取晶体管分别与两条所述字线对应。
  14. 根据权利要求12所述的存储器的形成方法，其特征在于，还包括如下步骤：
    形成沿所述第一方向延伸的源极线于所述衬底上，一个所述有源区与一条所述源极线交叠，位于同一所述有源区内的两个所述存取晶体管的漏极均与同一条所述源极线电连接。
  15. 根据权利要求14所述的存储器的形成方法，其特征在于，所述源极线呈弯曲状，且所述源极线在拐角处与所述有源区内的所述存取晶体管电连接。
  16. 根据权利要求9所述的存储器的形成方法，其特征在于，所述预设角度大于30°且小于90°。
  17. 一种如权利要求1所述的存储器的控制方法，所述存储器中包括多条沿所述第一方向延伸的源极线；其特征在于，包括如下步骤：
    选择目标磁性隧道结，所述目标磁性隧道结一端电连接一条目标位线、另一端同时电连接两个目标存取晶体管的源极，两个所述目标存取晶体管的漏极分别与两条目标源极线电连接，两个所述目标存取晶体管的栅极分别与两条目标字线电连接；
    传输高电平至所述目标位线、并同时传输低电平至除所述目标位线之外的所述位线，传输高电平至所述目标字线、并同时传输低电平至除所述目标字线之外的所述字线，传输低电平至所有的所述源极线，进行第一写入操作。
  18. 根据权利要求17所述的存储器的控制方法，其特征在于，还包括如下步骤：
    传输低电平至所有的所述位线，传输高电平至两条所述目标字线、并同时传输低电平至除所述目标字线之外的所述字线，传输高电平至所述目标源极线、并传输低电平至除所述目标源极线之外的所述源极线，进行第二写入操作。
  19. 根据权利要求17所述的存储器的控制方法，其特征在于，还包括如下步骤：
    传输高电平至所述目标位线、并同时传输低电平至除所述目标位线之外的所述位线，传输高电平至所述目标字线、并同时传输低电平至除所述目标字线之外的所述字线，传输低电平至所有的所述源极线，进行读取操作。
  20. 根据权利要求17所述的存储器的控制方法，其特征在于，还包括如下步骤：
    传输低电平至所有的所述位线、传输低电平至所有的所述字线、并传输低电平至所有的所述源极线，进行待机操作。
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