WO2021248568A1 - 显示面板驱动电路、阵列基板及其制造方法 - Google Patents

显示面板驱动电路、阵列基板及其制造方法 Download PDF

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WO2021248568A1
WO2021248568A1 PCT/CN2020/098262 CN2020098262W WO2021248568A1 WO 2021248568 A1 WO2021248568 A1 WO 2021248568A1 CN 2020098262 W CN2020098262 W CN 2020098262W WO 2021248568 A1 WO2021248568 A1 WO 2021248568A1
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low
layer
thin film
semiconductor
temperature polysilicon
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PCT/CN2020/098262
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English (en)
French (fr)
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张乐
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武汉华星光电半导体显示技术有限公司
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Priority to US17/261,563 priority Critical patent/US11482546B2/en
Publication of WO2021248568A1 publication Critical patent/WO2021248568A1/zh

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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • This application relates to the field of display, and in particular to a display panel drive circuit, an array substrate and a manufacturing method thereof.
  • AMOLED Active-matrix organic light-emitting diode
  • the array substrate used in AMOLED is mainly low-temperature polysilicon (Low Temperature Poly-silicon, LTPS) p-channel metal oxide semiconductor field effect (positive channel MeTLl Oxide Semiconductor, PMOS) array substrate.
  • LTPS Low Temperature Poly-silicon
  • PMOS p-channel metal oxide semiconductor field effect
  • the AMOLED LTPS array substrate sub-pixel drive circuit needs to adopt a pixel compensation circuit to offset the impact of threshold voltage drift.
  • the current mainstream pixel compensation circuit is designed for 7T1C, and the 7T1C circuit is divided into 3 working stages: 1) the initial restoration stage; 2) the circuit compensation stage; 3) the pixel light-emitting stage. Since the pixel light-emitting phase takes a long time, the capacitor potential in the compensation circuit will gradually be distorted due to the long-term leakage effect, causing the pixel to emit light abnormally.
  • TFT-Aging thin film transistor aging
  • the purpose of the present application is to provide a display panel driving circuit, an array substrate, and a manufacturing method that can prevent abnormal pixel light emission caused by the leakage of the thin film transistor without aging.
  • the present application provides a display panel driving circuit, which includes a plurality of transistors including a low leakage current thin film transistor, the low leakage current thin film transistor including a semiconductor layer, the semiconductor layer including a first semiconductor layer and A second semiconductor layer disposed on the first semiconductor layer, one of the first semiconductor layer and the second semiconductor is made of low temperature polysilicon, and the carrier mobility of the other material is lower than the low temperature Carrier mobility of polysilicon.
  • the low-leakage current thin film transistor is arranged at a first position in the pixel compensation circuit to reduce the influence of the leakage current at the first position on the pixel compensation circuit.
  • the material with a carrier mobility lower than that of low-temperature polysilicon includes at least one of metal oxide semiconductor, metal nitride semiconductor, metal oxynitride semiconductor, and amorphous silicon .
  • the material of the first semiconductor layer is low-temperature polysilicon, and the carrier mobility of the material of the second semiconductor layer is lower than the carrier mobility of the low-temperature polysilicon; wherein, the first A semiconductor layer includes a channel region and doped regions respectively located on both sides of the channel region; the orthographic projection of the second semiconductor layer on the channel region is located in the channel region.
  • the first doped region and the second doped region are P-type doped regions.
  • the plurality of transistors further include a low temperature polysilicon thin film transistor, and the low temperature polysilicon thin film transistor and the low leakage current thin film transistor are simultaneously formed on a substrate.
  • the low leakage current thin film transistor and the low temperature polysilicon thin film transistor are both N-type transistors or P-type transistors.
  • the low-temperature polysilicon thin film transistor is disposed at a second position in the pixel driving circuit, and the second position is a position other than the first position in the pixel compensation circuit.
  • the present application provides an array substrate, wherein the array substrate includes the display panel driving circuit as described in any one of the above.
  • the present application provides a manufacturing method of an array substrate, which includes the following steps:
  • a substrate is provided on which a first semiconductor material layer, a second semiconductor material layer, and a photoresist layer are sequentially stacked and formed, wherein one of the first semiconductor material layer and the second semiconductor material layer
  • the material of is low-temperature polysilicon, and the carrier mobility of the other material is less than the carrier mobility of the low-temperature polysilicon;
  • the present application can reduce the TFT leakage current in the display panel driving circuit by using a low leakage current thin film transistor instead of the low temperature polysilicon thin film transistor in the prior art.
  • a low leakage current thin film transistor instead of the low temperature polysilicon thin film transistor in the prior art.
  • abnormal light emission of the pixel caused by the leakage of the TFT is prevented.
  • the aging step is omitted.
  • FIG. 1 is a schematic plan view of an array substrate according to the first embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional view of the array substrate of FIG. 1 along the line A-A.
  • FIG. 3 is an equivalent circuit diagram of a pixel compensation circuit on the array substrate of FIG. 1.
  • the transistors used in all the embodiments of this application can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used here are symmetrical, the source and drain can be interchanged of. In the embodiments of the present application, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the source and the other is called the drain. According to the form in the figure, it is stipulated that the middle end of the switching transistor is the gate, the signal input end is the source, and the output end is the drain.
  • the transistors used in the embodiments of the present application may include P-type transistors and/or N-type transistors. The P-type transistor is turned on when the gate is at a low level, and turned off when the gate is at a high level, and the N-type transistor is at The gate is turned on when the gate is high, and it is turned off when the gate is low.
  • the present application provides an array substrate 1000.
  • the array substrate 1000 can be used for OLED, such as AMOLED.
  • the array substrate 1000 includes a substrate 10 and a display driving circuit 100 provided on the substrate 10.
  • the display driving circuit 100 includes a plurality of transistors.
  • the plurality of transistors includes a low leakage current thin film transistor TP.
  • the low leakage current thin film transistor TL is disposed at the first position P1 in the display driving circuit 100 to reduce the influence of the leakage current at the first position P1 on the display driving circuit 100.
  • the plurality of transistors may also include a low-temperature polysilicon thin film transistor TP.
  • the low-temperature polysilicon thin film transistor TP is disposed at the second position P2 in the display driving circuit 100.
  • the second position P2 is a position other than the first position P1 in the display driving circuit 100.
  • the low leakage current thin film transistor TL and the low temperature polysilicon thin film transistor TP are both N-type transistors or P-type transistors. And, the low leakage current thin film transistor TL and the low temperature polysilicon thin film transistor TP are simultaneously formed on the substrate.
  • the low leakage current thin film transistor TL includes a semiconductor layer 20, a gate insulating layer 30 disposed on the semiconductor layer 20, a first gate 41 disposed on the gate insulating layer 30, and an interlayer disposed on the first gate 41 An insulating layer and source and drain electrodes arranged on the interlayer insulating layer.
  • the semiconductor layer 20 includes a first semiconductor layer 21 and a second semiconductor layer 22 provided on the first semiconductor layer 21.
  • the material of one of the first semiconductor layer 21 and the second semiconductor layer 22 is low-temperature polysilicon, and the carrier mobility of the other material is lower than that of the low-temperature polysilicon.
  • the material having a carrier mobility lower than that of low-temperature polysilicon includes at least one of a metal oxide semiconductor, a metal nitride semiconductor, a metal oxynitride semiconductor, and amorphous silicon.
  • indium gallium zinc oxide indium tin zinc oxide, indium zinc oxide, indium tin oxide, zinc oxide, tin oxide, gallium zinc oxide, zinc oxynitride, tin oxynitride, etc. At least one of.
  • the material of the first semiconductor layer 21 is low-temperature polysilicon.
  • the semiconductor layer of the low-temperature polysilicon thin film transistor in the prior art is only formed of low-temperature polysilicon, which causes electrons to pass through the low-temperature polysilicon regardless of the on-state or off-state of the thin-film transistor.
  • the carrier mobility of the low-temperature polysilicon is relatively low. It is high, which results in high carrier mobility and high concentration of the current in the off state, that is, the leakage current is relatively large.
  • the thin film transistor provided by this embodiment When the thin film transistor provided by this embodiment is in the on state, since the carrier mobility of the first semiconductor layer 21 is higher than that of the second semiconductor layer 22, the first semiconductor layer 21 will attract electrons, so the electrons are removed from Passing through the first semiconductor layer 21, the carrier mobility of the first semiconductor layer 21 is relatively high, so that an on-state current with high carrier mobility and high concentration can be obtained; when the thin film transistor is in the off state, because at this time There are almost no electrons in the first semiconductor layer 21, which becomes a depletion layer, which will repel the electrons. Therefore, electrons will pass through the second semiconductor layer 22, and the carrier mobility of the second semiconductor layer 22 is low, thus obtaining The leakage current with low carrier mobility and low concentration reduces the leakage current.
  • the second semiconductor layer 22 is located above the first semiconductor layer 21. That is, the first semiconductor layer 21 is formed first, and then the second semiconductor layer 22 is formed, so that the low-temperature polysilicon material can be formed on a flat surface without a step difference, which ensures that the first semiconductor layer 21 has good electrical properties.
  • the second semiconductor layer 22 may also be disposed under the first semiconductor layer 21, which is not limited in this embodiment.
  • the first semiconductor layer 21 includes a channel region 21a and doped regions 21b located on both sides of the channel region 21a.
  • the doped region 21b is a P-type doped region.
  • the orthographic projection of the second semiconductor layer 22 on the channel region 21a is located in the channel region 21a.
  • the first gate 41 is arranged corresponding to the channel region 21a. The source and drain are in electrical contact with the doped 21a region.
  • the low-temperature polysilicon thin film transistor TP includes a third semiconductor layer 23, a gate insulating layer 30 disposed on the third semiconductor layer 23, and a second gate 42 disposed on the gate insulating layer 30 and corresponding to the third semiconductor layer 23. And the source electrode and the drain electrode that are in electrical contact with the third semiconductor layer 23. A doped region is also formed on the third semiconductor layer 23.
  • the display driving circuit 100 may include a pixel compensation circuit 100a and an array substrate row driving circuit 100b.
  • the pixel compensation circuit 100a may be a pixel compensation circuit in the prior art such as 4T1C, 5T1C, 7T1C, and so on.
  • the pixel compensation circuit 100a is a 7T1C compensation circuit will be described as an example.
  • the pixel compensation circuit 100a includes a first transistor T1, a second transistor T22, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and Light emitting device D.
  • the gate of the first transistor T1 is electrically connected to the first node a1, the source of the first transistor T1 is electrically connected to the second node a2, and the drain of the first transistor T1 is electrically connected to the third node a3.
  • the gate of the second transistor T22 is electrically connected to the first scan signal, the source of the second transistor T22 is electrically connected to the first node a1, and the drain of the second transistor T22 is electrically connected to the third node a3.
  • the gate of the third transistor T3 is electrically connected to the first scan signal, the source of the third transistor T3 is electrically connected to the data signal DATL, and the drain of the third transistor T3 is electrically connected to the second node a2.
  • the first scan signal is provided by the gate line Gn of the current stage.
  • the data signal is provided by the data line.
  • the gate of the fourth transistor T4 is electrically connected to the second scan signal, the source of the fourth transistor T4 is electrically connected to the low level, and the drain of the fourth transistor T4 is electrically connected to the first node a1.
  • the second scan signal is provided by the upper-level gate line Gn-1.
  • the gate of the fifth transistor T5 is electrically connected to the light-emitting signal EM, the source of the fifth transistor T5 is electrically connected to the third node a3, and the drain of the fifth transistor T5 is electrically connected to the fourth node a4.
  • the gate of the sixth transistor T6 is electrically connected to the light emitting signal EM, the source of the sixth transistor T6 is electrically connected to the first power signal VDD, and the drain of the sixth transistor T6 is electrically connected to the second node a2.
  • the first power signal VDD is provided by the power voltage.
  • the gate of the seventh transistor T7 is electrically connected to the second scan signal, the source of the seventh transistor T7 is electrically connected to the low level Vi, and the drain of the seventh transistor T7 is electrically connected to the fourth node a4.
  • the second scan signal is provided by the upper-level gate line Gn-1.
  • the first terminal of the first capacitor C1 is electrically connected to the first node a1, and the second terminal of the first capacitor is electrically connected to the first power signal.
  • the anode terminal of the light emitting device D is electrically connected to the fourth node a4, and the cathode terminal of the light emitting device D is electrically connected to the second power signal.
  • the second power signal is a ground signal.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a low leakage current thin film transistor TL and a low temperature polysilicon thin film transistor TP.
  • the second thin film transistor T2 and the fourth thin film transistor T4 are highly sensitive to leakage current in the 7T1C structure, the second thin film transistor T2 and the fourth thin film transistor T4 can be configured as low leakage current thin film transistors TL .
  • the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are set as low-temperature polysilicon thin film transistors TP.
  • Using a low-leakage current thin film transistor TL to replace the low-temperature polysilicon thin film transistor TP in the prior art can greatly reduce the TFT leakage current of the LTPS substrate and prevent abnormal light emission of the pixel. And in the preparation process, the aging step is omitted.
  • the array substrate row driving circuit 100b may also include a low leakage current thin film transistor TL.
  • the array substrate row driving circuit 100b uses all low leakage current thin film transistors TL, or some uses low leakage current thin film transistors TL, and some uses ordinary thin film transistors, such as low temperature polysilicon thin film transistors TP.
  • the second embodiment of the present application also provides a manufacturing method of an array substrate for manufacturing the array substrate of the first embodiment of the present application. It includes the following steps:
  • a substrate 10 is provided, and a first semiconductor material layer 2, a second semiconductor material layer 3, and a photoresist layer 200 are sequentially stacked on the substrate 10.
  • Film layers such as a light shielding layer and a buffer layer may be formed on the substrate 10.
  • the material of one of the first semiconductor material layer 2 and the second semiconductor material layer 3 is low-temperature polysilicon, and the carrier mobility of the other material is lower than that of the low-temperature polysilicon.
  • the material having a carrier mobility lower than that of low-temperature polysilicon includes at least one of a metal oxide channel, a metal nitride channel, a metal oxynitride channel, and amorphous silicon. Specifically, including indium gallium zinc oxide, indium tin zinc oxide, indium zinc oxide, indium tin oxide, zinc oxide, tin oxide, gallium zinc oxide, zinc oxynitride, tin oxynitride, etc. At least one of.
  • the first semiconductor material layer 2 is low-temperature polysilicon.
  • S2 Expose and develop the photoresist layer 200 by using the halftone mask 300 to form the first protective layer 201, the second protective layer 202 and the third protective layer 203.
  • the second protection layer 202 is connected to both sides of the first protection layer 201, the thickness of the first protection layer 201 is greater than that of the second protection layer 202, and the third protection layer 203 is spaced apart from the first protection layer 201 and the second protection layer 202.
  • the half-tone mask 300 has an opaque area 301, a semi-transmissive area 302, and a light-transmitting area 303.
  • the opaque area 301 is used to form the first area 201
  • the semi-transmissive area 302 is used to form the second area 202 and the third area 203.
  • the light-transmitting area 303 corresponds to other parts of the photoresist layer 200.
  • S3 Perform the first etching to remove the first semiconductor material layer 2 and the second semiconductor material layer 3 that are not covered by the first protective layer 201, the second protective layer 202, and the third protective layer 203 to obtain the first semiconductor layer twenty one.
  • S5 Perform a second etching to remove the second semiconductor material layer 3 that is not the first protective layer 201, and remove the first protective layer 201 to obtain the second semiconductor layer 22 and the third semiconductor layer 23.
  • the gate insulating layer 30, the first gate 41 and the second gate 42 are laminated and formed on the second semiconductor layer 22 and the third semiconductor layer 23.
  • the first semiconductor layer 21 is doped with the first gate 41 as a shielding layer to form a channel region 21a and doped regions 21b located on both sides of the channel region 21a.
  • the low-temperature polysilicon in the first semiconductor layer 21 is implanted with trivalent elements to form a P-type doped semiconductor with better conductivity.
  • a PN junction is formed at both ends of the first gate 41 to form a TFT.
  • the doped first semiconductor layer 21 and the second semiconductor layer 22 together form the semiconductor layer of the low leakage current thin film transistor TL.
  • the third semiconductor layer 23 is doped with the second gate 42 as a shielding layer.
  • the doped third semiconductor layer 23 serves as the semiconductor layer of the low-temperature polysilicon thin film transistor TP.
  • the thin film transistor in the pixel compensation circuit 100a is a top-gate thin film transistor is exemplified.
  • the first semiconductor layer 21 and the third semiconductor layer 23 may also be doped.
  • the doping method can use the method in the prior art, which will not be repeated here.
  • the manufacturing method of the pixel compensation circuit of this embodiment further includes the step of forming an interlayer insulating layer and source and drain electrodes on the first gate 41 and the second gate 42 to obtain a low leakage current thin film transistor TL and a low temperature polysilicon thin film transistor TP. .
  • the pixel compensation circuit 100a and the array substrate row driving circuit 100b of the array substrate 1000 in the first embodiment of the present application can be manufactured by the above manufacturing method.
  • the manufacturing method of the array substrate of the present application can reduce the leakage current of the TFT in the pixel compensation circuit by using a low leakage current thin film transistor instead of the low temperature polysilicon thin film transistor in the prior art. Thus, abnormal light emission of the pixel caused by the leakage of the TFT is prevented.
  • the pixel compensation circuit and the row drive circuit of the array substrate can both omit the aging step.

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Abstract

本申请提供一种显示面板驱动电路、阵列基板及其制造方法。显示面板驱动电路包括多个晶体管，多个晶体管中包括低漏电流薄膜晶体管，低漏电流薄膜晶体管包括半导体层，半导体层包括第一半导体层和第二半导体层，第一半导体层与第二半导体中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于低温多晶硅。

Description

显示面板驱动电路、阵列基板及其制造方法 技术领域
本申请涉及显示领域，尤其涉及一种显示面板驱动电路、阵列基板及其制造方法。
 背景技术
主动矩阵有机发光二极管（Active-matrix organic light-emitting diode, AMOLED）显示器因其独特的优势，得到快速发展。AMOLED所搭配的阵列基板，主流为低温多晶硅（Low Temperature Poly-silicon，LTPS）p沟道金属氧化物半导体场效应（positive channel MeTLl Oxide Semiconductor，PMOS）阵列基板。LTPS PMOS阵列基板在制作过程中，难以确保所形成的大面积的多晶硅半导体的均一性，而导致阈值电压漂移。
为解决AMOLED LTPS多晶硅均一性差的问题，AMOLED LTPS阵列基板亚像素驱动电路需采用像素补偿电路，以此抵消阈值电压漂移带来的影响。现主流像素补偿电路为7T1C设计，7T1C电路分为3个工作阶段：1）初始还原阶段；2）电路补偿阶段；3）像素发光阶段。由于像素发光阶段时间很长，补偿电路内电容电位会由于长时间漏电作用逐渐失真，造成像素发光异常。LTPS PMOS TFT（Thin Film Transistor，薄膜晶体管）在截止区的翘尾效应加剧了TFT的漏电流，为降低漏电流，现行方案为对TFT栅极和源极加载大偏压，即薄膜晶体管老化（TFT-Aging）。TFT-Aging对主动矩阵（Active-matrix，AA）区以外的如阵列基板行驱动（Gate Driver on Array，GOA）区域TFT无法Aging。
 技术问题
有鉴于此，本申请目的在于提供一种能够防止由于薄膜晶体管漏电导致的像素发光异常且无需进行老化的显示面板驱动电路、阵列基板以及制造方法。
 技术解决方案
本申请提供一种显示面板驱动电路，其包括多个晶体管，所述多个晶体管中包括低漏电流薄膜晶体管，所述低漏电流薄膜晶体管包括半导体层，所述半导体层包括第一半导体层和设置于所述第一半导体层上的第二半导体层，所述第一半导体层与所述第二半导体中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率。
在一种实施方式中，所述低漏电流薄膜晶体管设置在所述像素补偿电路中的第一位置处，以降低所述第一位置处的漏电流对所述像素补偿电路的影响。
在一种实施方式中，所述载流子迁移率小于低温多晶硅的载流子迁移率的材料包括金属氧化物半导体、金属氮化物半导体、金属氮氧化物半导体和非晶硅中的至少一种。
在一种实施方式中，所述第一半导体层的材料为低温多晶硅，所述第二半导体层的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率；其中，所述第一半导体层包括沟道区及分别位于所述沟道区两侧的掺杂区；所述第二半导体层在所述沟道区上的正投影位于所述沟道区内。
在一种实施方式中，所述第一掺杂区和所述第二掺杂区为P型掺杂区。
在一种实施方式中，所述多个晶体管中还包括低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管与所述低漏电流薄膜晶体管同时形成在基板上。
在一种实施方式中，所述低漏电流薄膜晶体管和所述低温多晶硅薄膜晶体管均为N型晶体管或P型晶体管。
在一种实施方式中，所述低温多晶硅薄膜晶体管设置在所述像素驱动电路中的第二位置处，所述第二位置为在所述像素补偿电路中除所述第一位置以外的位置。
本申请提供一种阵列基板，其中，所述阵列基板包括如上任一项所述的显示面板驱动电路。
本申请提供一种阵列基板的制造方法，其中，包括以下步骤：
提供一衬底，在所述衬底上依次层叠形成第一半导体材料层、第二半导体材料层以及光刻胶层，其中所述第一半导体材料层和所述第二半导体材料层中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率；
利用半色调掩模对所述光刻胶层进行曝光，显影，形成第一保护层，第二保护层和第三保护层；所述第二保护层连接于所述第一保护层两侧，所述第一保护层的厚度大于所述第二保护层，所述第三保护层与所述第一保护层和所述第二保护层间隔设置，
进行第一次刻蚀，除去未被所述第一保护层、所述第二保护层和所述第三保护层覆盖的所述第一半导体材料层和所述第二半导体材料层，得到第一半导体层；
灰化并除去所述第二保护层和所述第三保护层，减薄所述第一保护层；
进行第二次刻蚀，除去未被所述第一保护层的所述第二半导体材料层，除去所述第一保护层，得到第二半导体层和第三半导体层。
 有益效果
本申请通过使用低漏电流薄膜晶体管代替现有技术中的低温多晶硅薄膜晶体管，能够降低显示面板驱动电路中的TFT漏电流。从而，防止由于TFT漏电导致的像素发光异常。且在制备过程中，省略老化的步骤。
 附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施方式描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请第一实施方式的阵列基板平面示意图。
图2是图1的阵列基板沿A-A线的剖面示意图。
图3是图1的阵列基板上的像素补偿电路的等价电路图。
图4（a）~图4（h）是本申请第二实施方式的阵列基板的制造方法的流程图。
 本发明的实施方式
下面将结合本申请实施方式中的附图，对本申请中的技术方案进行清楚、完整地描述。显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P 型晶体管和/或N 型晶体管两种，其中，P 型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N 型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参考图1和图2，本申请提供一种阵列基板1000。该阵列基板1000可以用于OLED，例如AMOLED。阵列基板1000包括基板10和设置于基板10上的显示驱动电路100。显示驱动电路100包括多个晶体管。多个晶体管中包括低漏电流薄膜晶体管TP。低漏电流薄膜晶体管TL设置在显示驱动电路100中的第一位置P1处，以降低所述第一位置P1处的漏电流对显示驱动电路100的影响。多个晶体管中还可以包括低温多晶硅薄膜晶体管TP。低温多晶硅薄膜晶体管TP设置在显示驱动电路100中的第二位置P2处。第二位置P2为在显示驱动电路100中除所述第一位置P1以外的位置。低漏电流薄膜晶体管TL和低温多晶硅薄膜晶体管TP均为N型晶体管或P型晶体管。且，低漏电流薄膜晶体管TL和低温多晶硅薄膜晶体管TP同时形成在基板上。
低漏电流薄膜晶体管TL包括半导体层20、设置于半导体层20上的栅极绝缘层30、设置于栅极绝缘层30上的第一栅极41、设置于第一栅极41上的层间绝缘层和设置于层间绝缘层上的源极和漏极。
半导体层20包括第一半导体层21和设置于第一半导体层21上的第二半导体层22。第一半导体层21和第二半导体层22中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于低温多晶硅的载流子迁移率。载流子迁移率小于低温多晶硅的载流子迁移率的材料包括金属氧化物半导体、金属氮化物半导体、金属氮氧化物半导体和非晶硅中的至少一种。具体地，包括铟镓锌氧化物、铟锡锌氧化物、铟锌氧化物、铟锡氧化物、氧化锌、氧化锡、镓锌氧化物、锌的氮氧化物、锡的氮氧化物等中的至少一种。
在本实施方式中，第一半导体层21的材料为低温多晶硅。
现有技术中的低温多晶硅薄膜晶体管的半导体层仅由低温多晶硅形成，这就造成无论薄膜晶体管处于开态还是关态，电子均会从低温多晶硅中通过，由低温多晶硅的载流子迁移率较高，因此导致在关态时电流的载流子迁移率高、浓度高，即漏电流较大。而本实施例所提供的薄膜晶体管的处于开态时，由于第一半导体层21的载流子迁移率高于第二半导体层22，第一半导体层21会对电子产生吸引作用，因此电子从第一半导体层21中通过，第一半导体层21的载流子迁移率较高，从而能够获得载流子迁移率高、浓度高的开态电流；当薄膜晶体管处于关态时，由于此时第一半导体层21 内几乎没有电子，成为耗尽层，会对电子产生排斥作用，因此电子会从第二半导体层22中通过，第二半导体层22的载流子迁移率较低，从而获得载流子迁移率低、浓度低的漏电流，即减小了漏电流。
在本实施方式中，第二半导体层22位于第一半导体层的上方21。即先形成第一半导体层21，再形成第二半导体层22，使得低温多晶硅材料能够形成在一个平坦的表面，不会产生段差，保证了第一半导体层21具有良好的电性能。当然，第二半导体层22也可设置于第一半导体层21的下方，本实施例对此并不限定。
在本实施方式中，第一半导体层21包括：沟道区21a及分别位于沟道区21a两侧的掺杂区21b。掺杂区21b为P型掺杂区。第二半导体层22在沟道区21a上的正投影位于沟道区21a内。第一栅极41与沟道区21a对应设置。源极和漏极与掺杂21a区电接触。
低温多晶硅薄膜晶体管TP包括第三半导体层23和设置于第三半导体层23上的栅极绝缘层30、设置于栅极绝缘层30上并且与第三半导体层23对应设置的第二栅极42以及与第三半导体层23电接触的源极和漏极。第三半导体层23上也形成有掺杂区。
显示驱动电路100可以包括像素补偿电路100a和阵列基板行驱动电路100b。
该像素补偿电路100a可以为4T1C、5T1C、7T1C等现有技术中的像素补偿电路。
以下，举例说明像素补偿电路100a为7T1C补偿电路时的情况。
请参考图3，像素补偿电路100a包括第一晶体管T1、第二晶体管T22、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第一电容C1以及发光器件D。
第一晶体管T1的栅极电性连接于第一节点a1，第一晶体管T1的源极电性连接于第二节点a2，第一晶体管T1的漏极电性连接于第三节点a3。
第二晶体管T22的栅极电性连接于第一扫描信号，第二晶体管T22的源极电性连接于第一节点a1，第二晶体管T22的漏极电性连接于第三节点a3。
第三晶体管T3的栅极电性连接于第一扫描信号，第三晶体管T3的源极电性连接于数据信号DATL，第三晶体管T3的漏极电性连接于第二节点a2。第一扫描信号由本级栅极线Gn提供。数据信号由数据线提供。
第四晶体管T4的栅极电性连接于第二扫描信号，第四晶体管T4的源极电性连接于低电平，第四晶体管T4的漏极电性连接于第一节点a1。第二扫描信号由上一级栅极线Gn-1提供。
第五晶体管T5的栅极电性连接于发光信号EM，第五晶体管T5的源极电性连接于第三节点a3，第五晶体管T5的漏极电性连接于第四节点a4。
第六晶体管T6的栅极电性连接于发光信号EM，第六晶体管T6的源极电性连接于第一电源信号VDD，第六晶体管T6的漏极电性连接于第二节点a2。第一电源信号VDD由电源电压提供。
第七晶体管T7的栅极电性连接于第二扫描信号，第七晶体管T7的源极电性连接于低电平Vi，第七晶体管T7的漏极电性连接于第四节点a4。第二扫描信号由上一级栅极线Gn-1提供。
第一电容C1的第一端电性连接于第一节点a1，第一电容的第二端电性连接于第一电源信号。
发光器件D的阳极端电性连接于第四节点a4，发光器件D的阴极端电性连接于第二电源信号。第二电源信号为接地信号。
第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7中可以包括低漏电流薄膜晶体管TL和低温多晶硅薄膜晶体管TP。在一种实施方式中，由于7T1C结构中，第二薄膜晶体管T2与第四薄膜晶体管T4对漏电流高度敏感，可以将第二薄膜晶体管T2与第四薄膜晶体管T4设为低漏电流薄膜晶体管TL。第一晶体管T1、第三晶体管T3、第五晶体管T5、第六晶体管T6和第七晶体管T7设为低温多晶硅薄膜晶体管TP。使用低漏电流薄膜晶体管TL代替现有技术中的低温多晶硅薄膜晶体管TP能够大大降低LTPS基板TFT漏电流，防止像素发光异常。且在制备过程中，省略老化的步骤。
相似地，阵列基板行驱动电路100b也可以包括低漏电流薄膜晶体管TL。例如，阵列基板行驱动电路100b全部采用低漏电流薄膜晶体管TL，或者一部分采用低漏电流薄膜晶体管TL，一部分采用普通薄膜晶体管，例如低温多晶硅薄膜晶体管TP。
请参考图4（a）至图4（h），本申请第二实施方式还提供一种阵列基板的制造方法，用于制造本申请第一实施方式的阵列基板。其包括以下步骤：
S1:提供一衬底10，在衬底10上依次层叠形成第一半导体材料层2、第二半导体材料层3以及光刻胶层200。
衬底10上可以形成有遮光层、缓冲层等膜层。
其中，第一半导体材料层2和第二半导体材料层3中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于低温多晶硅的载流子迁移率。载流子迁移率小于低温多晶硅的载流子迁移率的材料包括金属氧化物沟道、金属氮化物沟道、金属氮氧化物沟道和非晶硅中的至少一种。具体地，包括铟镓锌氧化物、铟锡锌氧化物、铟锌氧化物、铟锡氧化物、氧化锌、氧化锡、镓锌氧化物、锌的氮氧化物、锡的氮氧化物等中的至少一种。
在本实施方式中，第一半导体材料层2为低温多晶硅。
S2:利用半色调掩模300对光刻胶层200进行曝光，显影，形成第一保护层201，第二保护层202和第三保护层203。第二保护层202连接于第一保护层201两侧，第一保护层201的厚度大于第二保护层202，第三保护层203与第一保护层201和第二保护层202间隔设置。
半色调掩模300具有不透光区301、半透光区302和透光区303。在使用正型光阻的情况下，不透光区301用于形成第一区域201，半透光区302用于形成第二区域202和第三区域203。透光区303对应于光刻胶层200的其他部分。
S3:进行第一次刻蚀，除去未被第一保护层201，第二保护层202和第三保护层203覆盖的第一半导体材料层2和第二半导体材料层3，得到第一半导体层21。
S4:灰化（ash）并除去（strip）第二保护层202和第三保护层203，减薄第一保护层201。
S5:进行第二次刻蚀，除去未被第一保护层201的第二半导体材料层3，除去第一保护层201，得到第二半导体层22和第三半导体层23。
S6:在第二半导体层22和第三半导体层23上层叠形成栅极绝缘层30和第一栅极41以及第二栅极42。以第一栅极41为遮蔽层对第一半导体层21进行掺杂，形成沟道区21a和位于沟道区21a两侧的掺杂区21b。在此步骤中，第一半导体层21中的低温多晶硅被注入三价元素，形成导电率较好的P型掺杂半导体。同时，第一栅极41两端区域PN结形成，形成TFT。掺杂后的第一半导体层21与第二半导体层22共同形成低漏电流薄膜晶体管TL的半导体层。
同时，以第二栅极42为遮蔽层对第三半导体层23进行掺杂。掺杂后的第三半导体层23作为低温多晶硅薄膜晶体管TP的半导体层。
在本实施方式中，举例示出像素补偿电路100a中的薄膜晶体管为顶栅型薄膜晶体管的情况。在底栅型薄膜晶体管中，也可以对第一半导体层21和第三半导体层23进行掺杂。掺杂的方法可以利用现有技术中的方法，在此不再赘述。
本实施方式的像素补偿电路的制造方法还包括在第一栅极41和第二栅极42上形成层间绝缘层和源漏极从而得到低漏电流薄膜晶体管TL和低温多晶硅薄膜晶体管TP的步骤。
通过上述制造方法可以制造本申请第一实施方式中的阵列基板1000的像素补偿电路100a和阵列基板行驱动电路100b造。
本申请的阵列基板的制造方法通过使用低漏电流薄膜晶体管代替现有技术中的低温多晶硅薄膜晶体管，能够降低像素补偿电路中的TFT漏电流。从而，防止由于TFT漏电导致的像素发光异常。在制备过程中，阵列基板上的像素补偿电路和阵列基板行驱动电路均能够省略老化的步骤。
以上对本申请实施方式提供了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (17)

  1. 一种显示面板驱动电路，包括多个晶体管，所述多个晶体管中包括低漏电流薄膜晶体管，所述低漏电流薄膜晶体管包括半导体层，所述半导体层包括第一半导体层和设置于所述第一半导体层上的第二半导体层，所述第一半导体层与所述第二半导体中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率。
  2. 根据权利要求1所述的显示面板驱动电路，其中，所述低漏电流薄膜晶体管设置在所述像素补偿电路中的第一位置处，以降低所述第一位置处的漏电流对所述像素补偿电路的影响。
  3. 根据权利要求1所述的显示面板驱动电路，其中，所述载流子迁移率小于低温多晶硅的载流子迁移率的材料包括金属氧化物半导体、金属氮化物半导体、金属氮氧化物半导体和非晶硅中的至少一种。
  4. 根据权利要求1所述的显示面板驱动电路，其中，所述第一半导体层的材料为低温多晶硅，所述第二半导体层的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率；其中，所述第一半导体层包括沟道区及分别位于所述沟道区两侧的掺杂区；所述第二半导体层在所述沟道区上的正投影位于所述沟道区内。
  5. 根据权利要求4所述的显示面板驱动电路，其中，所述第一掺杂区和所述第二掺杂区为P型掺杂区。
  6. 根据权利要求1所述的显示面板驱动电路，其中，所述多个晶体管中还包括低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管与所述低漏电流薄膜晶体管同时形成在基板上。
  7. 根据权利要求6所述的显示面板驱动电路，其中，所述低漏电流薄膜晶体管和所述低温多晶硅薄膜晶体管均为N型晶体管或P型晶体管。
  8. 根据权利要求6所述的显示面板驱动电路，其中，所述低温多晶硅薄膜晶体管设置在所述像素驱动电路中的第二位置处，所述第二位置为在所述像素补偿电路中除所述第一位置以外的位置。
  9. 一种阵列基板，其中，所述阵列基板包括如权利要求1所述的显示面板驱动电路。
  10. 一种阵列基板的制造方法，包括以下步骤：
    提供一衬底，在所述衬底上依次层叠形成第一半导体材料层、第二半导体材料层以及光刻胶层，其中所述第一半导体材料层和所述第二半导体材料层中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率；
    利用半色调掩模对所述光刻胶层进行曝光，显影，形成第一保护层，第二保护层和第三保护层；所述第二保护层连接于所述第一保护层两侧，所述第一保护层的厚度大于所述第二保护层，所述第三保护层与所述第一保护层和所述第二保护层间隔设置，
    进行第一次刻蚀，除去未被所述第一保护层、所述第二保护层和所述第三保护层覆盖的所述第一半导体材料层和所述第二半导体材料层，得到第一半导体层；
    灰化并除去所述第二保护层和所述第三保护层，减薄所述第一保护层；
    进行第二次刻蚀，除去未被所述第一保护层的所述第二半导体材料层，除去所述第一保护层，得到第二半导体层和第三半导体层。
  11. 根据权利要求10所述的显示面板驱动电路，其中，所述低漏电流薄膜晶体管设置在所述像素补偿电路中的第一位置处，以降低所述第一位置处的漏电流对所述像素补偿电路的影响。
  12. 根据权利要求1所述的阵列基板的制造方法，其中，所述载流子迁移率小于低温多晶硅的载流子迁移率的材料包括金属氧化物半导体、金属氮化物半导体、金属氮氧化物半导体和非晶硅中的至少一种。
  13. 根据权利要求10所述的阵列基板的制造方法，其中，所述第一半导体层的材料为低温多晶硅，所述第二半导体层的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率；其中，所述第一半导体层包括沟道区及分别位于所述沟道区两侧的掺杂区；所述第二半导体层在所述沟道区上的正投影位于所述沟道区内。
  14. 根据权利要求13所述的阵列基板的制造方法，其中，所述第一掺杂区和所述第二掺杂区为P型掺杂区。
  15. 根据权利要求11所述的阵列基板的制造方法，其中，所述多个晶体管中还包括低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管与所述低漏电流薄膜晶体管同时形成在基板上。
  16. 根据权利要求15所述的阵列基板的制造方法，其中，所述低漏电流薄膜晶体管和所述低温多晶硅薄膜晶体管均为N型晶体管或P型晶体管。
  17. 根据权利要求15所述的阵列基板的制造方法，其中，所述低温多晶硅薄膜晶体管设置在所述像素驱动电路中的第二位置处，所述第二位置为在所述像素补偿电路中除所述第一位置以外的位置。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0555570A (ja) * 1991-08-29 1993-03-05 Hitachi Ltd 薄膜半導体装置及びその製造方法
CN101577283A (zh) * 2008-05-06 2009-11-11 三星移动显示器株式会社 薄膜晶体管阵列构件和有机发光显示装置及其制造方法
CN105390551A (zh) * 2015-10-28 2016-03-09 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、阵列基板、显示装置
CN106057826A (zh) * 2016-08-08 2016-10-26 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN107134461A (zh) * 2017-06-28 2017-09-05 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制备方法、oled显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180024817A (ko) * 2016-08-31 2018-03-08 엘지디스플레이 주식회사 멀티 타입의 박막 트랜지스터를 포함하는 유기 발광 표시 장치 및 유기 발광 표시 장치 제조 방법
KR102305442B1 (ko) * 2017-03-30 2021-09-28 삼성디스플레이 주식회사 화소 및 이를 포함하는 유기 발광 표시 장치
US10566401B2 (en) 2017-06-28 2020-02-18 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Thin film transistor array substrate and preparing method therefor, and OLED display device
US10490128B1 (en) * 2018-06-05 2019-11-26 Apple Inc. Electronic devices having low refresh rate display pixels with reduced sensitivity to oxide transistor threshold voltage
KR102517126B1 (ko) * 2018-09-28 2023-04-03 삼성디스플레이 주식회사 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0555570A (ja) * 1991-08-29 1993-03-05 Hitachi Ltd 薄膜半導体装置及びその製造方法
CN101577283A (zh) * 2008-05-06 2009-11-11 三星移动显示器株式会社 薄膜晶体管阵列构件和有机发光显示装置及其制造方法
CN105390551A (zh) * 2015-10-28 2016-03-09 京东方科技集团股份有限公司 薄膜晶体管及其制造方法、阵列基板、显示装置
CN106057826A (zh) * 2016-08-08 2016-10-26 京东方科技集团股份有限公司 一种阵列基板及其制备方法、显示装置
CN107134461A (zh) * 2017-06-28 2017-09-05 深圳市华星光电技术有限公司 薄膜晶体管阵列基板及其制备方法、oled显示装置

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