WO2021196988A1 - 测试电路及半导体测试方法 - Google Patents
测试电路及半导体测试方法 Download PDFInfo
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- WO2021196988A1 WO2021196988A1 PCT/CN2021/079634 CN2021079634W WO2021196988A1 WO 2021196988 A1 WO2021196988 A1 WO 2021196988A1 CN 2021079634 W CN2021079634 W CN 2021079634W WO 2021196988 A1 WO2021196988 A1 WO 2021196988A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/26—Testing of individual semiconductor devices
- G01R31/2642—Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
- G01R31/2858—Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- This application relates to the field of semiconductor technology, in particular to test circuits and semiconductor test methods.
- Electro-migration is one of the main failure mechanisms in semiconductor devices.
- the electro-migration test is an important test to evaluate the performance of semiconductor devices.
- the conventional electro-migration test structure is to load a long metal wire with a constant current. During the test, the larger the current, the shorter the test time, but a larger test current may lead to unreasonable metal life prediction, and a larger test current will burn the metal due to different mechanisms. However, a small current during the test will make the test time longer, and testing one by one will also lead to a longer test time and lower test efficiency.
- test circuit including:
- the test unit has a first end, a second end, a third end, and a fourth end.
- the first end of the test unit of each level is connected to a power cord, and the test unit of each level
- the second end of the test unit is connected to the ground wire
- the third end of the test unit of the first stage is connected to the power line
- the third end of the test unit of the i-th stage is connected to the test unit of the i-1th stage.
- the fourth end is connected; wherein, the M and i are positive integers greater than or equal to 2.
- a semiconductor testing method which includes the following steps:
- the lifetimes of all the electromigration test elements are obtained according to the monitored voltage and current.
- the variation range of the current on the electromigration test element is 1 ⁇ 10 5 A/cm 2 to 1 ⁇ 10 10 A/cm 2 .
- the test circuit can enable the test units of all levels to be tested at the same voltage at the same time.
- the electromigration test element in the test unit performs electromigration test, so that multiple electromigration test elements can be tested at the same time, which greatly shortens the test time.
- the semiconductor test method can be tested at the same voltage at the same time.
- the electromigration test element in the previous test unit is blown, it will automatically turn on the electricity to the next test unit.
- the migration test element is subjected to electromigration test, so that multiple electromigration test elements can be tested in sequence, which greatly shortens the test time.
- Fig. 1 is a circuit diagram of a test circuit provided by an embodiment
- Figures 2 to 4 are test schematic diagrams of the test circuit provided in one embodiment of the application; among them, Figure 2 is a circuit diagram for testing the electromigration test element in the first-level test unit, and Figure 3 is the circuit diagram of the first-level test unit. The circuit diagram when the electromigration test element is blown out, Figure 4 is the circuit diagram when the test element in the second-level test unit is blown out;
- FIG. 5 is a flowchart of a semiconductor testing method provided by another embodiment.
- the present application provides a test circuit including: M-level test units 10, each level of the test unit 10 has a first end, a second end, a third end, and a fourth end,
- the first end of each level of test unit 10 is connected to the power line (that is, the straight line connecting the upper end of each level of test unit 10 in FIG. 1), and the second end of each level of test unit 10 is connected to the ground wire (not (Shown), the third end of the first level test unit 10 is connected to the power cord, and the third end of the i-th level test unit 10 is connected to the fourth end of the i-1th level test unit 10;
- M is greater than A positive integer equal to 2
- i is a positive integer greater than or equal to 2.
- each level of the test unit 10 includes an electromigration test element 101, a switch 102, and a control circuit 103, wherein the first end of the electromigration test element 101 is the first end of the test unit 10 connected to the power line, The second end of the electromigration test element 101 is connected to the first end of the switch 102 and the first end of the control circuit 103, the control end of the switch 102 is the third end of the test unit 10, and the second end of the switch 102 is the test unit 102 The second end of the control circuit 103 is the fourth end of the test unit 10.
- the values of M and i can be set according to actual needs, and are not limited here.
- the electromigration test element 101 can be a metal wire; the length of the electromigration test element 101 can be set according to actual needs, for example, the length of the electromigration test element 101 can be 700 ⁇ m (micrometers) to 2000 ⁇ m; specifically The length of the electromigration test element 101 may be 700 ⁇ m, 1000 ⁇ m, 1500 ⁇ m, or 2000 ⁇ m. It should be noted that, in a specific embodiment, the length of the electromigration test element 101 is not limited to the above-mentioned data.
- the electromigration test element 101 has a first equivalent resistance before the burnout, and the electromigration test element 101 has a second equivalent resistance after the burnout, and the first equivalent resistance is smaller than the second equivalent resistance.
- the ratio of the second equivalent resistance to the first equivalent resistance can be set according to actual needs.
- the ratio of the second equivalent resistance to the first equivalent resistance can be greater than or equal to 100.
- the first The ratio of the second equivalent resistance to the first equivalent resistance can be 100, 150, 200, 250, 300, and so on. It should be noted that, in specific embodiments, the ratio of the second equivalent resistance to the first equivalent resistance is not limited to the above data.
- M is greater than or equal to 2
- the length of the electromigration test element 101 in each level of the test unit 10 is the same, and the width of the electromigration test element 101 in each level of the test unit 10 is the same; That is, the electromigration test elements 101 in each level of the test unit 10 are completely the same.
- multiple identical electromigration test elements 101 can be tested to analyze the consistency of the electromigration test elements 101 and improve the accuracy of the test results.
- M is greater than or equal to 2
- the length of the electromigration test element 101 in each level of test unit 10 is different from each other, and the width of the electromigration test element 101 in each level of test unit 10 is the same ; That is, the electromigration test elements 101 in each level of the test unit 10 are different from each other.
- a plurality of different electromigration test elements 101 with different lengths can be tested sequentially, which significantly shortens the time required for the test of the plurality of electromigration test elements 101, and greatly improves the efficiency of the test.
- M is greater than or equal to 2
- the length of the electromigration test element 101 in each level of test unit 10 is different from each other
- the width of the electromigration test element 101 in each level of test unit 10 is different from each other; That is, the electromigration test elements 101 in each level of the test unit 10 are different from each other.
- M is greater than or equal to 2
- the length of the electromigration test element 101 in each level of test unit 10 is different, and the width of the electromigration test element 101 in each level of test unit 10 is different; That is, the electromigration test elements 101 in the M-level test unit 10 are partly the same and partly different.
- multiple different electromigration test elements 101 can be tested in sequence, which significantly shortens the time required for the test of multiple electromigration test elements 101, and greatly improves the efficiency of the test.
- multiple identical electromigration test elements can be set up. The test element 101 is tested to improve the accuracy of the test structure.
- the electromigration test element 101 may be a metal wire, a polysilicon wire, etc., and the metal wire may be one or more of tungsten, aluminum, and copper.
- the first equivalent resistance value of the electromigration test element 101 before the blow-off is much smaller than the on-resistance value of the switch 102, for example, the first equivalent resistance value is less than one-tenth of the on-resistance value of the switch 102;
- the second equivalent resistance value of the migration test element 101 after blow-off is much greater than the on-resistance value of the switch 102, for example, the second equivalent resistance value is greater than ten times the on-resistance value of the switch 102.
- the switch 102 includes an NMOS tube, and the gate, drain, and source of the NMOS tube correspond to the control terminal, the first terminal, and the second terminal of the switch respectively, that is, the drain of the NMOS tube is the first terminal of the switch 102.
- the terminal is electrically connected to the second terminal of the electromigration test element 101, and the source of the NMOS transistor is grounded at the second terminal of the switch 102.
- control circuit 103 includes an inverter, and the input terminal and output terminal of the inverter correspond to the first terminal and the second terminal of the control circuit 103 respectively, that is, the input terminal of the inverter is the first terminal of the control circuit 103.
- the terminal is electrically connected to the second terminal of the electromigration test element 101, and the output terminal of the inverter is the fourth terminal of the test unit 10, and is electrically connected to the gate of the NMOS transistor in the next-level test unit 10.
- the test principle of the test circuit of the present application is as follows: First, at the beginning of the test, the gate of the NMOS tube in the test unit 10 of the first stage is connected to the test line, and the NMOS tube is turned on at this time , That is, the first-level test unit 10 starts to test the electromigration test element 101 in the first-level test unit 10 for the path; at this time, the gates of the NMOS in the second-level to the M-th test unit 10 are all connected The output terminal of the inverter in the test unit 10 of the previous stage, and the electromigration test element 101 in the second to Mth stages are not blown, and the first terminal of the inverter is high, then the reverse The second terminal of the phaser is at a low level, and the NMOS transistors in the second to M-th test units 10 are all in the off state, that is, the electromigration test element 101 in the second to M-th test units 10 is at this time Did not start the test, as shown in Figure 2.
- the electromigration test element 101 in the first-level test unit 10 is blown, the first terminal of the inverter in the first-level test unit 10 becomes a low level, and the second terminal of the inverter becomes High level, at this time, the NMOS transistor in the second-level test unit 10 is turned on, and the test of the electromigration test element 101 in the second-level test unit 10 is started, as shown in FIG. 3.
- the test circuit of the present application can automatically perform electromigration tests on multiple test units 10 in sequence, which greatly improves the test efficiency.
- this application also provides a semiconductor testing method, which specifically includes the following steps:
- step S11 after the power line in the test circuit shown in FIG. 1 is connected to a power supply device outside the chip, the same test voltage is applied to each electromigration test element 101.
- the first The gate of the NMOS tube in the first-level test unit 10 is connected to the test line.
- the NMOS tube is turned on, that is, the first-level test unit 10 is a channel and starts to test the electromigration test element 101 in the first-level test unit 10 ;
- the gates of the NMOS in the test unit 10 from the second stage to the Mth stage are all connected to the output terminal of the inverter in the test unit 10 of the previous stage, and the electricity in the second stage to the Mth stage
- the migration test element 101 is not blown, the first terminal of the inverter is high, the second terminal of the inverter is low, and the NMOS transistors in the second to M-th test units 10 are all at The off state, that is, the electromigration test element 101 in the second to Mth level test unit 10 does not start testing at this time, as shown in FIG.
- the test circuit of the present application can automatically perform electromigration tests on a plurality of test units 10 in sequence, which greatly improves the test efficiency.
- step S12 the voltage and current of the power supply device are monitored and recorded, and the voltage and current changes corresponding to the breakdown of each electromigration test element 101 are recorded.
- the variation range of the current on the electromigration test element can be 1 ⁇ 10 5 A/cm 2 to 1 ⁇ 10 10 A/cm 2 .
- step S13 the lifetimes of all the electromigration test elements 101 are obtained according to the monitored voltage and current, that is, the lifetime of the electromigration test elements 101 in each level of the test unit 10 is recorded step by step.
- the method of recording the life of each electromigration test element 101 is to start timing when a test voltage is applied to the electromigration test element 101, and the time elapsed until the electromigration test element 101 burns off is the life of the electromigration test element 101.
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Abstract
一种测试电路,包括:M级测试单元,每一级测试单元的第一端均连接到电源线,第二端均连接到地线,第一级测试单元的第三端连接到电源线,第i级测试单元的第三端与第i-1级测试单元的第四端相连接;其中,M和i为大于等于2的正整数。测试电路可以使得各级测试单元同时在同一电压下进行测试,在测试过程中,前一级测试单元中的电迁移测试元件烧断后会自动开启对下一级测试单元中的电迁移测试元件进行电迁移测试,使得多个电迁移测试元件能够同时进行检测,大大缩短了测试时间。
Description
相关申请的交叉引用
本申请要求于2020年4月3日提交中国专利局、申请号为202010259636.3、发明名称为“测试电路及半导体测试方法”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本申请涉及半导体技术领域,特别是涉及测试电路及半导体测试方法。
电迁移(Electro-migration,EM)是半导体器件中主要的失效机理之一,电迁移测试是一种评价半导体器件性能的重要测试,常规电迁移测试结构是用恒定电流加载到长金属线上。在测试时,电流越大,则测试时间越短,但较大的测试电流可能会导致金属寿命预测不合理,且较大的测试电流会由于不同机制使得金属烧毁。然而,测试过程中电流较小会使得测试时间较长,一个一个独立进行测试也会导致测试时间较长,测试效率较低。
发明内容
在本申请的第一方面,提供了一种测试电路,包括:
M级测试单元,所述测试单元具有第一端、第二端、第三端及第四端,每一级所述测试单元的第一端均连接到电源线,每一级所述测试单元的第二端均连接到地线,第一级所述测试单元的第三端连接到所述电源线,第i级所述测试单元的第三端与第i-1级所述测试单元的第四端相连接;其中,所述M和i为大于等于2的正整数。
在本申请的第二方面,提供了一种半导体测试方法,包括以下步骤:
将根据本申请的第一方面的测试电路中的电源线连接到一芯片外部的电源装置;
监测所述电源装置的电压和电流变化;
根据监测的所述电压和所述电流得到所有所述电迁移测试元件的寿命。
在其中一个实施例中,所述电迁移测试元件上的所述电流的变化范围为 1×10
5A/cm
2~1×10
10A/cm
2。
在本申请的技术方案中,测试电路可以使得各级测试单元可以同时在同一电压下进行测试,在测试过程中,前一级测试单元中的电迁移测试元件烧断后会自动开启对下一级测试单元中的电迁移测试元件进行电迁移测试,使得多个电迁移测试元件能够同时进行检测,大大缩短了测试时间。
在本申请的技术方案中,半导体测试方法可以同时在同一电压下进行测试,在测试过程中,前一级测试单元中的电迁移测试元件烧断后会自动开启对下一级测试单元中的电迁移测试元件进行电迁移测试,使得多个电迁移测试元件能够依次进行测试,大大缩短了测试时间。
为了更好地描述和说明本申请的实施例,可参考一幅或多幅附图,但用于描述附图的附加细节或示例不应当被认为是对本申请的发明创造、目前所描述的实施例或优选方式中任何一者的范围的限制。
图1为一个实施例提供的测试电路的电路图;
图2至图4为本申请一个实施例提供测试电路的测试原理图;其中,图2对第一级测试单元中的电迁移测试元件进行测试的电路图,图3为第一级测试单元中的电迁移测试元件烧断时的电路图,图4为第二级测试单元中的测试元件烧断时的电路图;
图5为另一个实施例提供的半导体测试方法的流程图。
为了便于理解本申请,下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是,本申请可以以许多不同的形式来实现,并不限于本文所描述的实施例。相反地,提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义,本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本申请的描述中,需要理解的是,术语“上”、“下”、“竖直”、“水平”、“内”、 “外”等指示的方位或位置关系为基于附图所示的方法或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。
如图1所示,本申请提供了一种测试电路,该测试电路包括:M级测试单元10,每一级测试单元10均具有第一端、第二端、第三端及第四端,每一级测试单元10的第一端均连接到电源线(即图1中每一级测试单元10的上端连接的直线),每一级测试单元10的第二端均连接到地线(未示出),第一级测试单元10的第三端连接到电源线,第i级测试单元10的第三端与第i-1级测试单元10的第四端相连接;其中,M为大于等于2的正整数,i为大于等于2的正整数。
在一个示例中,每一级测试单元10均包括电迁移测试元件101、开关102和控制电路103,其中,电迁移测试元件101的第一端为测试单元10的第一端连接到电源线,电迁移测试元件101的第二端连接到开关102的第一端及控制电路103的第一端,开关102的控制端为测试单元10的第三端,开关102的第二端为测试单元102的第二端,控制电路103的第二端为测试单元10的第四端。
具体的,M及i的取值可以根据实际需要进行设定,此处不做限定。
在一个示例中,电迁移测试元件101可以为金属导线;电迁移测试元件101的长度可以根据实际需要进行设定,例如,电迁移测试元件101的长度可以为700μm(微米)~2000μm;具体的,电迁移测试元件101的长度可以为700μm、1000μm、1500μm或2000μm。需要说明的是,在具体实施例中,电迁移测试元件101的长度并不以上述数据为限。
在一个示例中,电迁移测试元件101烧断之前具有第一等效电阻,电迁移测试元件101烧断之后具有第二等效电阻,第一等效电阻小于第二等效电阻。
在一个示例中,第二等效电阻与第一等效电阻的比值可以根据实际需要进行设定,例如,第二等效电阻与第一等效电阻的比值可以大于等于100,具体的,第二等效电阻与第一等效电阻的比值可以为100、150、200、250或300等等。需要说明的是,在具体实施例中,第二等效电阻与第一等效电阻的比值并不以上述数据为限。
在一个可选的示例中,M大于等于2,且每一级测试单元10中的电迁移测试元件101的长度均相同,每一级测试单元10中的电迁移测试元件101的宽度均相同;即每一级测试单元10中的电迁移测试元件101完全相同。此时,可以对多个相同的电迁移测试元件101进行测试,以分析电迁移测试元件101的一 致性,并提高测试结果的准确性。
在另一个可选的示例中,M大于等于2,且每一级测试单元10中的电迁移测试元件101的长度互不相同,每一级测试单元10中的电迁移测试元件101的宽度相同;即每一级测试单元10中的电迁移测试元件101互不相同。此时,可以对多个具有不同长度的不同的电迁移测试元件101依次进行测试,明显缩短多个电迁移测试元件101测试所需的时间,大大提高测试的效率。
在又一个示例中,M大于等于2,且每一级测试单元10中的电迁移测试元件101的长度互不相同,每一级测试单元10中的电迁移测试元件101的宽度互不相同;即每一级测试单元10中的电迁移测试元件101互不相同。此时,可以对多个具有不同长度及不同宽度的不同的电迁移测试元件101依次进行测试,明显缩短多个电迁移测试元件101测试所需的时间,大大提高测试的效率。
在又一个示例中,M大于等于2,且每一级测试单元10中的电迁移测试元件101的长度不尽相同,每一级测试单元10中的电迁移测试元件101的宽度不尽相同;即M级测试单元10中的电迁移测试元件101有部分相同,部分不同。此时,即可以对多个不同的电迁移测试元件101依次进行测试,明显缩短多个电迁移测试元件101测试所需的时间,大大提高测试的效率;又可以通过设置多个相同的电迁移测试元件101进行测试以提高测试结构的准确性。
在一个示例中,电迁移测试元件101可以为金属线、多晶硅线等,金属线可以为钨、铝、铜中的一种或多种。电迁移测试元件101在烧断之前具有的第一等效电阻值远小于开关102的导通电阻值,例如第一等效电阻值小于开关102的导通电阻值的十分之一;而电迁移测试元件101在烧断之后具有的第二等效电阻值远大于开关102的导通电阻值,例如第二等效电阻值大于开关102的导通电阻值的十倍。
在一个示例中,开关102包括NMOS管,NMOS管的栅极、漏极、源极分别对应所述开关的控制端、第一端、第二端,即NMOS管的漏极为开关102的第一端,与电迁移测试元件101的第二端电连接,NMOS管的源极为开关102的第二端接地。
在一个示例中,控制电路103包括反相器,反相器的输入端、输出端分别对应控制电路103的第一端、第二端,即反相器的输入端为控制电路103的第一端,与电迁移测试元件101的第二端电连接,反相器的输出端为测试单元10的第四端,与下一级测试单元10中的NMOS管的栅极电连接。
请参阅图2至图4,本申请的测试电路的测试原理为:首先,在测试开始时,第一级的测试单元10中的NMOS管的栅极连接到测试线,此时NMOS管导通,即第一级测试单元10为通路开始对第一级测试单元10中的电迁移测试元件101进行测试;由于此时第二级至第M级的测试单元10中的NMOS的栅极均连接上一级的测试单元10中的反相器的输出端,又第二级至第M级中的电迁移测试元件101并未烧断,反相器的第一端为高电平,则反相器的第二端为低电平,第二级至第M级测试单元10中的NMOS管均处于关闭状态,即此时第二级至第M级测试单元10中的电迁移测试元件101并未开始测试,如图2所示。其次,当第一级测试单元10中的电迁移测试元件101烧断以后,第一级测试单元10中的反相器的第一端变成低电平,反相器的第二端变为高电平,此时第二级测试单元10中的NMOS管导通,开始对第二级测试单元10中的电迁移测试元件101进行测试,如图3所示。然后,当第二级测试单元10中的电迁移测试元件101烧断以后,第二级测试单元10中的反相器的第一端变成低电平,反相器的第二端变为高电平,此时第三级测试单元10中的NMOS管导通,开始对第三级测试单元10中的电迁移测试元件101进行测试,如图4所示。依次类推直至对第M级(即测试电路中的最后一级)测试单元10中的电迁移测试元件101测试完毕为止。由上可知,本申请的测试电路可以自动实现对多个测试单元10自动依次进行电迁移测试,大大提高了测试效率。
如图5所示,本申请还提供了一种半导体测试方法,具体包括以下步骤:
S11:将如图1所示的测试电路中的电源线连接到一芯片外部的电源装置;
S12:监测所述电源装置的电压和电流变化;
S13:根据监测的所述电压和所述电流得到所有所述电迁移测试元件的寿命。
测试电路的具体结构请参阅图1至图4及相关文字描述,此处不再累述。
步骤S11中,将如图1所示的测试电路中的电源线连接到一芯片外部的电源装置后,在各电迁移测试元件101上施加相同的测试电压,首先,在测试开始时,第一级的测试单元10中的NMOS管的栅极连接到测试线,此时NMOS管导通,即第一级测试单元10为通路开始对第一级测试单元10中的电迁移测试元件101进行测试;由于此时第二级至第M级的测试单元10中的NMOS的栅极均连接上一级的测试单元10中的反相器的输出端,又第二级至第M级中的电迁移测试元件101并未烧断,反相器的第一端为高电平,则反相器的第二端 为低电平,第二级至第M级测试单元10中的NMOS管均处于关闭状态,即此时第二级至第M级测试单元10中的电迁移测试元件101并未开始测试,如图2所示。其次,当第一级测试单元10中的电迁移测试元件101烧断以后,第一级测试单元10中的反相器的第一端变成低电平,反相器的第二端变为高电平,此时第二级测试单元10中的NMOS管导通,开始对第二级测试单元10中的电迁移测试元件101进行测试,如图3所示。然后,当第二级测试单元10中的电迁移测试元件101烧断以后,第二级测试单元10中的反相器的第一端变成低电平,反相器的第二端变为高电平,此时第三级测试单元10中的NMOS管导通,开始对第三级测试单元10中的电迁移测试元件101进行测试,如图4所示。依次类推直至对第M级(即测试电路中的最后一级)测试单元10中的电迁移测试元件101测试完毕为止。由上可知,本申请的测试电路可以自动实现对多个测试单元10自动依次进行电迁移测试,大大提高了测试效率。
在步骤S12中,监测记录电源装置的电压和电流,会记录对应各电迁移测试元件101被击穿时的电压和电流变化。电迁移测试元件上的电流的变化范围可为1×10
5A/cm
2~1×10
10A/cm
2。
步骤S13中,根据监测的电压和电流得到所有电迁移测试元件101的寿命,即可以为逐级记录每一级测试单元10中的电迁移测试元件101的寿命。记录各电迁移测试元件101的寿命的方法为:在电迁移测试元件101上施加测试电压时开始计时,直至电迁移测试元件101烧断时所经历的时间即为电迁移测试元件101的寿命。
以上实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上实施例仅表达了本申请的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本申请构思的前提下,还可以做出若干变形和改进,这些都属于本申请的保护范围。因此,本申请专利的保护范围应以所附权利要求为准。
Claims (13)
- 一种测试电路,包括:M级测试单元,每一级测试单元均具有第一端、第二端、第三端及第四端,每一级测试单元的第一端均连接到电源线,每一级测试单元的第二端均连接到地线,第一级测试单元的第三端连接到所述电源线,第i级测试单元的第三端与第i-1级测试单元的第四端相连接;其中,所述M和i为大于等于2的正整数。
- 根据权利要求1所述的测试电路,其中,每一级测试单元均包括电迁移测试元件、开关和控制电路,其中,所述电迁移测试元件的第一端为所述测试单元的第一端,所述电迁移测试元件的第二端连接到所述开关的第一端及所述控制电路的第一端,所述开关的控制端为所述测试单元的第三端,所述开关的第二端为所述测试单元的第二端,所述控制电路的第二端为所述测试单元的第四端。
- 根据权利要求2所述的测试电路,其中,所述电迁移测试元件烧断之前具有第一等效电阻,所述电迁移测试元件烧断之后具有第二等效电阻,所述第一等效电阻小于所述第二等效电阻。
- 根据权利要求3所述的测试电路,其中,所述第二等效电阻与所述第一等效电阻的比值大于等于100。
- 根据权利要求2所述的测试电路,其中,所述电迁移测试元件的长度包括10μm~20000μm。
- 根据权利要求2所述的测试电路,其中,每一级测试单元中的所述电迁移测试元件的长度均相同,每一级测试单元中的所述电迁移测试元件的宽度均相同。
- 根据权利要求2所述的测试电路,其中,每一级测试单元中的所述电迁移测试元件的长度互不相同,每一级测试单元中的所述电迁移测试元件的宽度均相同。
- 根据权利要求2所述的测试电路,其中,每一级测试单元中的所述电迁移测试元件的长度互不相同,每一级测试单元中的所述电迁移测试元件的宽度互不相同。
- 根据权利要求2所述的测试电路,其中,所述电迁移测试元件包括金属导线。
- 根据权利要求2所述的测试电路,其中,所述开关包括NMOS管,所述NMOS管栅极、漏极、源极分别对应所述开关的控制端、第一端、第二端。
- 根据权利要求2所述的测试电路,其中,所述控制电路包括反相器,所述反相器的输入端、输出端分别对应所述控制电路的第一端、第二端。
- 一种半导体测试方法,包括以下步骤:将如权利要求2至11中任一项所述的测试电路中的电源线连接到一芯片外部的电源装置;监测所述电源装置的电压和电流变化;根据监测的所述电压和所述电流得到所有所述电迁移测试元件的寿命。
- 根据权利要12所述的半导体测试方法,其中,所述电迁移测试元件上的所述电流的变化范围为1×10 5A/cm 2~1×10 10A/cm 2。
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US20130130415A1 (en) * | 2011-11-18 | 2013-05-23 | Samsung Electronics Co., Ltd. | Methods of testing integrated circuit devices using fuse elements |
CN102590629A (zh) * | 2012-02-10 | 2012-07-18 | 工业和信息化部电子第五研究所 | 一种高精度电迁移预警电路 |
CN104576613A (zh) * | 2013-10-29 | 2015-04-29 | 中芯国际集成电路制造(上海)有限公司 | 电迁移测试方法及结构 |
CN105445636A (zh) * | 2014-09-02 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | 半导体测试电路及被测试件导电性能的检测方法 |
CN204720446U (zh) * | 2015-06-12 | 2015-10-21 | 中芯国际集成电路制造(北京)有限公司 | 电迁移测试结构 |
CN106199195A (zh) * | 2016-07-19 | 2016-12-07 | 牛明慧 | 印刷电路板离子迁移测试*** |
CN106409817A (zh) * | 2016-10-26 | 2017-02-15 | 上海华力微电子有限公司 | Tddb测试结构以及tddb测试方法 |
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US11860217B2 (en) | 2024-01-02 |
US20230058289A1 (en) | 2023-02-23 |
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