WO2021190055A1 - 显示基板及其制备方法、显示面板和显示装置 - Google Patents

显示基板及其制备方法、显示面板和显示装置 Download PDF

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Publication number
WO2021190055A1
WO2021190055A1 PCT/CN2020/141653 CN2020141653W WO2021190055A1 WO 2021190055 A1 WO2021190055 A1 WO 2021190055A1 CN 2020141653 W CN2020141653 W CN 2020141653W WO 2021190055 A1 WO2021190055 A1 WO 2021190055A1
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Prior art keywords
layer
base substrate
conductor layer
metal layer
protective conductor
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PCT/CN2020/141653
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English (en)
French (fr)
Inventor
田春光
李小龙
邹佳滨
文娜
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Publication of WO2021190055A1 publication Critical patent/WO2021190055A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a preparation method of the display substrate, a display panel including the display substrate, and a display device including the display panel.
  • the present disclosure provides a display substrate and a preparation method of the display substrate, a display panel including the display substrate, and a display device including the display panel.
  • a display substrate including a base substrate provided with a display area and a non-display area, and the display substrate in the non-display area further includes:
  • the data line metal layer is arranged on one side of the base substrate
  • the first protective conductor layer is arranged on the side of the data line metal layer away from the base substrate, and the orthographic projection of the first protective conductor layer on the base substrate is in line with the data line metal layer
  • the orthographic projections on the base substrate at least partially overlap;
  • the passivation layer is provided on a side of the first protective conductor layer away from the base substrate, and a first via is provided on the passivation layer;
  • the connecting conductor layer is provided on the side of the passivation layer away from the base substrate, and the connecting conductor layer is connected to the first protective conductor layer through the first via hole so that the data line metal
  • the layer is conductively connected to the connecting conductor layer.
  • the display substrate in the non-display area further includes:
  • the gate metal layer is provided on one side of the base substrate, and the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the data line metal layer on the base substrate do not cross each other Stack
  • the gate insulating layer is disposed on the side of the gate metal layer away from the base substrate, the gate insulating layer is provided with a third via hole, and the data line metal layer is located far from the gate insulating layer. Said one side of the base substrate;
  • the passivation layer is provided on a side of the gate insulating layer away from the base substrate, a second via is provided on the passivation layer, and the connecting conductor layer passes through the second via and the The third via hole is connected to the gate metal layer.
  • the display substrate in the non-display area further includes:
  • the gate metal layer is provided on one side of the base substrate, and the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the data line metal layer on the base substrate do not cross each other Stack
  • the gate insulating layer is disposed on the side of the gate metal layer away from the base substrate, the gate insulating layer is provided with a third via hole, and the data line metal layer is located far from the gate insulating layer. Said one side of the base substrate;
  • the first protective conductor layer extends to a side of the gate insulating layer away from the base substrate, and the first protective conductor layer is connected to the gate metal layer through the third via hole.
  • the display substrate in the non-display area further includes:
  • the gate metal layer is provided on one side of the base substrate, and the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the data line metal layer on the base substrate do not cross each other Stack
  • the gate insulating layer is disposed on the side of the gate metal layer away from the base substrate, the gate insulating layer is provided with a third via hole, and the data line metal layer is located far from the gate insulating layer. Said one side of the base substrate;
  • the second protective conductor layer is provided on a side of the gate insulating layer away from the base substrate, and the second protective conductor layer is connected to the gate metal layer through the third via;
  • the passivation layer is provided on a side of the second protective conductor layer away from the base substrate, a second via is provided on the passivation layer, and the connecting conductor layer passes through the second via It is connected to the second protective conductor layer to make the gate metal layer and the connection conductor layer conductively connected.
  • the first protective conductor layer and the second protective conductor layer are formed of the same layer and the same material, and the first protective conductor layer is connected to the second protective conductor layer As one; or
  • the first protective conductor layer and the second protective conductor layer are formed of the same layer and the same material, and a space is provided between the first protective conductor layer and the second protective conductor layer.
  • the display substrate in the display area includes:
  • the first electrode is provided on one side of the base substrate, and the side of the first electrode away from the base substrate is provided with the passivation layer;
  • the second electrode is provided on the side of the passivation layer away from the base substrate;
  • first electrode and the first protective conductor layer are formed of the same layer and the same material
  • second electrode and the connecting conductor layer are formed of the same layer and the same material
  • the first electrode is a pixel electrode
  • the second electrode is a slit electrode, and is used to form a multi-dimensional electric field with the first electrode.
  • the display substrate in the display area further includes:
  • the gate is provided on one side of the base substrate, and the gate insulating layer is provided on the side of the gate away from the base substrate;
  • the active layer is provided on the side of the gate insulating layer away from the base substrate;
  • the source and drain are provided on the side of the active layer away from the base substrate and on the side of the first electrode close to the base substrate.
  • the source and drain include a source and a drain. Electrode, the source electrode is directly connected to the first electrode;
  • the source and drain electrodes are formed of the same layer and the same material as the data line metal layer; the gate and the gate metal layer are formed of the same layer and the same material.
  • the material of the data line metal layer and the gate metal layer is metallic copper.
  • a method for manufacturing a display substrate including:
  • a first protective conductor layer is formed on the side of the data line metal layer away from the base substrate, and the orthographic projection of the first protective conductor layer on the base substrate is at the same position as the data line metal layer.
  • the orthographic projections on the base substrate at least partially overlap;
  • a connecting conductor layer is formed on the side of the passivation layer away from the base substrate, and the connecting conductor layer is connected to the first protective conductor layer through the first via hole so that the data line metal layer Conductive connection with the connecting conductor layer.
  • the preparation method before forming the data line metal layer, the preparation method further includes:
  • a gate metal layer is formed in the non-display area of the base substrate, and the orthographic projection of the gate metal layer on the base substrate and the orthographic projection of the data line metal layer on the base substrate do not cross each other Stack
  • a gate insulating layer is formed on a side of the gate metal layer away from the base substrate, and the data line metal layer is formed on a side of the gate insulating layer away from the base substrate.
  • the passivation layer is further formed on a side of the gate insulating layer away from the base substrate; while the first via is formed, the A second via is formed on the passivation layer and a third via is formed on the gate insulating layer, so that the connecting conductor layer is connected to the gate metal layer through the second via and the third via.
  • the preparation method further includes:
  • a second protective conductor layer is formed on the side of the gate insulating layer away from the base substrate, and the second protective conductor layer passes through the third via hole and The gate metal layer connection;
  • the passivation layer is also formed on a side of the second protective conductor layer away from the base substrate; while forming the first via hole, a second via hole is formed on the passivation layer, The connecting conductor layer is connected to the second protective conductor layer through the second via hole.
  • the first protective conductor layer and the second protective conductor layer are connected as a whole, or the first protective conductor layer and the second protective conductor layer are arranged between There are compartments.
  • the preparation method further includes:
  • the first protective conductor layer is also formed on a side of the gate insulating layer away from the base substrate, and the first protective conductor layer is connected to the gate metal layer through the third via hole.
  • a first electrode is formed on one side of the display area of the base substrate, and the first electrode is a pixel electrode, And the passivation layer is formed on the side of the first electrode away from the base substrate;
  • a second electrode is formed on the side of the passivation layer of the display area away from the base substrate, and the second electrode is a common electrode.
  • a display panel including the display substrate described in any one of the above.
  • a display device including the display panel described in any one of the above.
  • FIG. 1 is a schematic diagram of the structure of a non-display area of a display substrate in the related art
  • FIG. 2 is a schematic structural diagram of an exemplary embodiment of a non-display area of a display substrate of the present disclosure
  • FIG. 3 is a schematic diagram of the structure in FIG. 2 when the connecting conductor layer and the alignment film have not been formed;
  • FIG. 4 is a schematic structural diagram of another exemplary embodiment of a non-display area of a display substrate of the present disclosure
  • FIG. 5 is a schematic structural diagram of another exemplary embodiment of a non-display area of a display substrate of the present disclosure
  • FIG. 6 is a schematic structural view of still another exemplary embodiment of a non-display area of a display substrate of the present disclosure
  • FIG. 7 is a schematic structural diagram of an exemplary embodiment of a display area of a display substrate of the present disclosure.
  • FIG. 8 is a schematic block diagram of the flow of an exemplary embodiment of a method for preparing a substrate according to the present disclosure.
  • FIG. 1 shows a schematic diagram of the structure of the non-display area of the display substrate in the related art shown in FIG. 1; a gate metal layer 61 is provided on one side of the base substrate 1, and a side of the gate metal layer 61 away from the base substrate 1 is provided
  • the gate insulating layer 7 is provided with a third via 71 on the gate insulating layer 7, a data line metal layer 21 is provided on the side of the gate insulating layer 7 away from the base substrate 1, and the data line metal layer 21 is on the base substrate
  • the orthographic projection on 1 and the orthographic projection of the gate metal layer 61 on the base substrate 1 do not overlap each other.
  • a passivation layer 4 is provided on the side of the data line metal layer 21 and the gate insulating layer 7 away from the base substrate 1, and a first via 41 and a second via are provided on the passivation layer 4.
  • a connecting conductor layer 51 is provided on the side of the passivation layer 4 away from the base substrate 1. The connecting conductor layer 51 is connected to the data line metal layer 21 through the first via 41, and the connecting conductor layer 51 passes through the second via and the first via. The three vias are connected to the gate metal layer 61.
  • the third via 71 on the gate insulating layer 7 in the non-display area and the second via 42 on the passivation layer 4 can be formed by one photolithography process. Therefore, in this process, the gate metal layer 61 There is always the protection of the gate insulating layer 7, which reduces the possibility of oxidation and corrosion of the gate metal layer. Since the data line metal layer 21 is exposed to the air on the surface away from the base substrate 1, the probability of oxidation is significantly increased, and the lotion used when forming other film layers in this process can directly contact the data line metal layer. This increases the risk of the data line metal layer 21 being corroded, resulting in an abnormal increase in the contact resistance between the data line metal layer 21 and the connecting conductor layer 51, which affects the subsequent bridging performance with the gate metal layer 61.
  • a display substrate is provided. Refer to the structural schematic diagrams of an exemplary embodiment of the non-display area of the display substrate of the present disclosure shown in FIGS. 2-6; the display substrate may include a base substrate 1, a data The wire metal layer 21, the first protective conductor layer 31, the passivation layer 4, and the connecting conductor layer 51; the data wire metal layer 21 is provided on one side of the base substrate 1; the first protective conductor layer 31 is provided on the data On the side of the wire metal layer 21 away from the base substrate 1, the orthographic projection of the first protective conductor layer 31 on the base substrate 1 and the orthographic projection of the data wire metal layer 21 on the base substrate 1 at least partially overlap
  • the passivation layer 4 is provided on the side of the first protective conductor layer 31 away from the base substrate 1, the passivation layer 4 is provided with a first via 41; the connecting conductor layer 51 is provided on the On the side of the passivation layer 4 away from the base substrate 1, the connecting conductor layer 51 is connected to the first protective conductor layer 31 through
  • FIG. 2 and FIG. 3 structural schematic diagrams of an exemplary embodiment of the non-display area of the display substrate of the present disclosure.
  • a gate metal layer 61 is provided on the base substrate 1, a gate insulating layer 7 is provided on the side of the gate metal layer 61 away from the base substrate 1, and a gate insulating layer 7 is provided on the gate insulating layer 7.
  • the three vias 71 are provided with a data line metal layer 21 on the side of the gate insulating layer 7 away from the base substrate 1.
  • the orthographic projection of the data line metal layer 21 on the base substrate 1 and the gate metal layer 61 on the base substrate The orthographic projections on 1 do not overlap each other.
  • a first protective conductor layer 31 is provided on the side of the data line metal layer 21 away from the base substrate 1.
  • the orthographic projection of the first protective conductor layer 31 on the base substrate 1 and the data line metal layer 21 on the base substrate 1 overlap at least partially, that is, the first protective conductor layer 31 at least partially covers the area of the data line metal layer 21 exposed by the first via 41. Further, the first protective conductor layer 31 may completely cover the data line metal layer. The area of the layer 21 exposed by the first via 41.
  • a passivation layer 4 is provided on the side of the first protective conductor layer 31 and the gate insulating layer 7 away from the base substrate 1, and a first via 41 and a second via 43 are provided on the passivation layer 4.
  • the second via 42 and the third via 71 are in communication.
  • a connecting conductor layer 51 is provided on the side of the passivation layer 4 away from the base substrate 1.
  • the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41, and the first protective conductor layer 31 can conduct electricity, thereby
  • the connection conductor layer 51 and the data line metal layer 21 can be electrically connected.
  • the connecting conductor layer 51 is connected to the gate metal layer 61 through the second via 42 and the third via 71.
  • the gate insulating layer 7 and the passivation layer 4 can be made of materials with similar properties, and the materials with similar properties can be patterned by etching with the same etching solution, so that only one photolithography can be used.
  • the process forms a second via 42 on the passivation layer 4 and a third via 71 on the gate insulating layer 7. Therefore, before the second via 42 is formed, the surface of the gate metal layer 61 away from the base substrate 1 is covered by the gate insulating layer 7, so there is no need to provide a protective conductor layer to protect the gate metal layer 61, that is, the first protective conductor.
  • the orthographic projection of the layer 31 on the base substrate 1 and the orthographic projection of the gate metal layer 61 on the base substrate 1 do not overlap.
  • the above-mentioned similar properties means that the same etching agent can be used for etching.
  • silicon oxide, silicon nitride, a mixture of silicon oxide and silicon nitride are all materials with similar properties.
  • the material properties for forming the gate insulating layer 7 and the passivation layer 4 are quite different, and cannot be etched by the same etchant, that is, the gate cannot be etched by only one photolithography process.
  • the third via 71 is formed on the insulating layer 7 and the second via 42 is formed on the passivation layer 4. It is necessary to form the third via 71 on the gate insulating layer 7 and then form the second via on the passivation layer 4. Two through holes 44. At this time, the part of the surface of the gate insulating layer 7 away from the base substrate 1 is exposed to the air because the third via 71 has been formed, and may be oxidized and corroded. It is necessary to introduce a protective conductor layer on the gate metal layer 61. Protect it.
  • the following three example embodiments are specific descriptions of the structure of the non-display area of the display substrate in this case.
  • FIG. 4 for a schematic structural view of another exemplary embodiment of the non-display area of the display substrate of the present disclosure.
  • a gate metal layer 61 is provided on the base substrate 1, a gate insulating layer 7 is provided on the side of the gate metal layer 61 away from the base substrate 1, and a gate insulating layer 7 is provided on the gate insulating layer 7.
  • the three vias 71 are provided with a data line metal layer 21 on the side of the gate insulating layer 7 away from the base substrate 1.
  • the orthographic projection of the data line metal layer 21 on the base substrate 1 and the gate metal layer 61 on the base substrate The orthographic projections on 1 do not overlap each other.
  • a first protective conductor layer 31 is provided on the side of the data line metal layer 21 away from the base substrate 1.
  • the orthographic projection of the first protective conductor layer 31 on the base substrate 1 and the data line metal layer 21 on the base substrate 1 The orthographic projection on the base substrate at least partially overlaps, and a first protective conductor layer 31 is also provided on the side of the gate insulating layer 7 away from the base substrate 1, and the orthographic projection of the first protective conductor layer 31 on the base substrate 1 and The orthographic projection of the gate metal layer 61 on the base substrate 1 at least partially overlaps, that is, the first protective conductor layer 31 at least partially covers the area of the gate metal layer 61 exposed by the third via 71, and the first protective conductor layer 31 It is connected to the gate metal layer 61 through the third via 71. Further, the first protective conductor layer 31 may also completely cover the area of the gate metal layer 61 exposed by the third via 71.
  • the data line metal layer 21 and the gate metal layer 61 are connected through the first protective conductor layer 31.
  • a passivation layer 4 is provided on the side of the first protective conductor layer 31 away from the base substrate 1, and a first via 41 is provided on the passivation layer 4.
  • a connecting conductor layer 51 is provided on the side of the passivation layer 4 away from the base substrate 1. The connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41, and the first protective conductor layer 31 can conduct electricity, thereby
  • the data line metal layer 21 and the gate metal layer 61 are electrically connected through the connecting conductor layer 51 and the first protective conductor layer 31.
  • a second via 42 is provided on the passivation layer 4, and the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the second via 42 to realize multiple overlapping modes , Reduce the lap resistance and improve the reliability of the lap.
  • FIG. 6 for a schematic structural view of another exemplary embodiment of the non-display area of the display substrate of the present disclosure.
  • a gate metal layer 61 is provided on the base substrate 1, a gate insulating layer 7 is provided on the side of the gate metal layer 61 away from the base substrate 1, and a gate insulating layer 7 is provided on the gate insulating layer 7.
  • the three vias 71 are provided with a data line metal layer 21 on the side of the gate insulating layer 7 away from the base substrate 1.
  • the orthographic projection of the data line metal layer 21 on the base substrate 1 and the gate metal layer 61 on the base substrate The orthographic projections on 1 do not overlap each other.
  • a first protective conductor layer 31 is provided on the side of the data line metal layer 21 away from the base substrate 1.
  • a second protective conductor layer 32 is provided on the side of the gate insulating layer 7 away from the base substrate 1, and the second protective conductor layer 32 is connected to the gate metal layer 61 through a third via 71, and the second protective conductor layer 32 is The orthographic projection on the base substrate 1 and the orthographic projection of the gate metal layer 61 on the base substrate 1 at least partially overlap, that is, the second protective conductor layer 32 at least partially covers the gate metal layer 61 exposed by the third via 71 Furthermore, the second protective conductor layer 32 may also completely cover the area of the gate metal layer 61 exposed by the third via 71.
  • the first protective conductor layer 31 and the second protective conductor layer 32 are formed by the same patterning process.
  • a passivation layer 4 is provided on the side of the first protective conductor layer 31 and the second protective conductor away from the base substrate 1, and a first via 41 and a second via 42 are provided on the passivation layer 4.
  • a connecting conductor layer 51 is provided on the side of the passivation layer 4 away from the base substrate 1.
  • the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41, and the first protective conductor layer 31 can conduct electricity, thereby
  • the connection conductor layer 51 and the data line metal layer 21 can be electrically connected.
  • the connecting conductor layer 51 is connected to the second protective conductor layer 32 through the second via hole 42, and the second protective conductor layer 32 can conduct electricity, so that the connecting conductor layer 51 and the gate metal layer 61 can be electrically connected.
  • the alignment film 9 is provided on the side of the connecting conductor layer 51 away from the base substrate 1.
  • FIG. 7 for a schematic structural diagram of an exemplary embodiment of the display area of the display substrate of the present disclosure.
  • the display substrate in the display area may include a gate 62, a gate insulating layer 7, an active layer 8, a source electrode 221, a drain electrode 222, a first electrode 33, a passivation layer 4, and a second electrode 52.
  • a gate 62 is provided on one side of the base substrate 1
  • a gate insulating layer 7 is provided on the side of the gate 62 away from the base substrate 1 and the side of the base substrate 1
  • the gate insulating layer 7 is far away from the base substrate 1.
  • An active layer 8 is provided on one side of the base substrate 1
  • a source electrode 221 and a drain electrode 222 are provided on the side of the active layer 8 away from the base substrate 1.
  • the source electrode 221 and the drain electrode 222 are electrically connected to the active layer respectively .
  • a first electrode 33 is provided on the side of the source electrode 221 away from the base substrate 1, the source electrode 221 and the first electrode 33 are directly overlapped, and the drain electrode 222 is electrically connected to the data line (not shown in the figure) to input to the pixel unit Pixel signal.
  • a passivation layer 4 is provided on the side of the first electrode 33 away from the base substrate 1, and a second electrode 52 is provided on the side of the passivation layer 4 away from the base substrate 1.
  • An alignment film 9 is provided on one side of one surface of the substrate 1. It should be noted that the source electrode 221 and the first electrode 33 directly overlap, which means that at least part of the first electrode 33 is formed on the surface of the source electrode 221 away from the base substrate 1.
  • the display substrate is used for a liquid crystal display panel, and the display mode is Advanced Super Dimension Switch (ADS), where the first electrode 33 may be a slit electrode or a plate shape.
  • the second electrode 52 can be a slit electrode.
  • the electric field generated by the edge of the slit electrode in the same plane and the electric field between the slit electrode layer and the plate electrode layer form a multi-dimensional electric field, so that the gap between the slit electrodes in the liquid crystal cell , All oriented liquid crystal molecules directly above the electrode can be rotated to achieve display.
  • the source electrode 221 and the drain electrode 222 are formed of the same layer and the same material as the data line metal layer 21, and the gate 62 and the gate metal layer 61 are formed of the same layer and the same material.
  • the first electrode 33 may be a pixel electrode, and the second electrode 52 may be a common electrode. In order to reduce the space occupied by signal connection, the first electrode 33 and the source electrode 221 may be directly connected, as shown in FIG. 7, for example, The first electrode 33 at least partially covers the surface of the source electrode 221 away from the base substrate 1 to achieve an effective electrical connection between the two, and at the same time can optimize the pixel aperture ratio, thereby improving the transmittance of the display product.
  • the first electrode 33 and the first protective conductor may be formed of the same layer and the same material.
  • the second electrode 52 and the connecting conductor layer 51 may also be formed of the same layer and the same material. It should be noted that the formation of the same layer and the same material mentioned here refers to the formation of patterns by using the same material in the same patterning process. Multiple structures with different functions can be formed through the same patterning process, and various functional requirements of the product can be met without increasing the process flow, which not only saves manpower and material resources, but also improves product performance.
  • the material of the gate 62, the source 221, the drain 222, the data line metal layer 21, and the gate metal layer 61 may be metallic copper.
  • the data line metal layer 21 and the gate metal layer 61 can increase the refresh rate; but because the nature of copper is more active, when exposed to the air Or when it is in direct contact with other etching agents, poor metal corrosion will occur.
  • the first protective conductor layer 31, the gate insulating layer 7, and the second protective conductor layer 32 can protect the metal copper from exposure to the air or direct contact with other etching agents, and prevent the conductor layer 51 from being connected to the data line.
  • the contact resistance between the metal layer 21 and the gate metal layer 61 is abnormally increased, which improves the metal bridge performance.
  • a method for preparing a display substrate is also provided. Referring to the schematic flow diagram of an exemplary embodiment of the method for preparing a display substrate of the present disclosure shown in FIG. 8, the preparation method includes the following steps:
  • Step S10 providing a base substrate 1 with a display area and a non-display area
  • Step S20 forming a data line metal layer 21 on the non-display area of the base substrate 1;
  • a first protective conductor layer 31 is formed on the side of the data line metal layer 21 away from the base substrate 1.
  • the orthographic projection of the first protective conductor layer on the base substrate and the The orthographic projection of the data line metal layer on the base substrate at least partially overlaps;
  • Step S40 forming a passivation layer 4 on the side of the first protective conductor layer 31 away from the base substrate 1, and patterning the passivation layer 4 to form a first via 41;
  • a connecting conductor layer 51 is formed on the side of the passivation layer 4 away from the base substrate 1, and the connecting conductor layer 51 passes through the first via 41 and the first protective conductor layer 31 It is connected to make the data line metal layer 21 and the connecting conductor layer 51 conductively connected.
  • a base substrate 1 is provided, and the base substrate 1 may be a glass substrate.
  • the base substrate 1 is provided with a display area and a non-display area; a display structure is formed in the display area, and a binding structure, various circuits, etc. are formed in the non-display area.
  • a gate material layer is formed on the base substrate 1 through processes such as evaporation or sputtering, and the gate material layer is patterned so that the gate material layer forms a gate 62 in the display area and a gate 62 in the non-display area.
  • Metal layer 61 is formed on the base substrate 1 through processes such as evaporation or sputtering, and the gate material layer is patterned so that the gate material layer forms a gate 62 in the display area and a gate 62 in the non-display area.
  • a gate insulating layer 7 is formed on the side of the gate 62 and the gate metal layer 61 away from the base substrate 1. Among them, if the material for forming the gate insulating layer 7 and the material properties of the passivation layer 4 to be formed later are quite different and cannot be etched by the same etchant, it is necessary to pattern the part of the gate insulating layer 7 in the non-display area Chemical treatment to form a third via 71.
  • An active layer 8 is formed on the side of the gate insulating layer 7 away from the base substrate 1, and a source and drain material layer is formed on the side of the active layer 8 away from the base substrate 1 through evaporation or sputtering processes, and the source
  • the drain material layer is patterned to form a source electrode 221 and a drain electrode 222 in the display area, wherein the source electrode 221 and the drain electrode 222 are electrically connected to the active layer, respectively.
  • a data line metal layer 21 is formed on the side of the gate insulating layer 7 away from the base substrate 1.
  • the data line metal layer 21 and the source electrode 221 and the drain electrode 222 can also be formed of the same layer and the same material, that is, in the display area and the non-display area.
  • the first conductive material layer is formed in all regions, and then the first conductive material layer is patterned once to form the source electrode 221, the drain electrode 222 and the data line metal layer 21 at the same time.
  • a first electrode material layer is formed on the side of the source electrode 221 and the drain electrode 222 away from the base substrate 1, and the first electrode material layer is patterned to form the first electrode 33 in the display area.
  • the source electrode 221 and the first electrode 33 are directly connected, and the drain electrode 222 is electrically connected to a data line (not shown in the figure) to input pixel signals to the pixel unit.
  • a first protective conductor layer 31 is formed on the side of the data line metal layer 21 away from the base substrate 1, or a first protective conductor layer 31 and a second protective conductor are formed on the side of the data line metal layer 21 away from the base substrate 1.
  • Layer 32 is formed on the side of the data line metal layer 21 away from the base substrate 1.
  • first electrode 33, the first protective conductor layer 31, and the second protective conductor layer 32 can also be formed of the same layer and the same material, that is, the first electrode material layer is formed in the display area and the non-display area, and then the first electrode material layer is formed in the display area and the non-display area.
  • An electrode material layer is subjected to a patterning process once to form the first electrode 33 in the display area, and at the same time to form the first protective conductor layer 31 and the second protective conductor layer 32 in the non-display area.
  • the first protective conductor layer 31 is provided only on the side of the data line metal layer 21 away from the base substrate 1, namely The orthographic projection of the first protective conductor layer 31 on the base substrate 1 and the orthographic projection of the data line metal layer 21 on the base substrate 1 at least partially overlap, and the first protective conductor layer 31 at least partially covers the data line metal layer 21
  • the area exposed by the first via 41, further, the first protective conductor layer 31 may also completely cover the area exposed by the first via 41 of the data line metal layer 21.
  • the first protective conductor layer 31 also extends to the area where the gate metal layer 61 is located, that is, the orthographic projection of the first protective conductor layer 31 on the base substrate 1 and the data line metal layer 21 on the base substrate 1 While the orthographic projections at least partially overlap, the orthographic projection of the first protective conductor layer 31 on the base substrate 1 also at least partially overlaps the orthographic projection of the gate metal layer 61 on the base substrate 1.
  • the first protective conductor The layer 31 at least partially covers the area of the data line metal layer 21 exposed by the first via 41, and at least partially covers the area of the gate metal layer 61 exposed by the third via 71. Further, the first protective conductor layer 31 can also completely cover the area of the data line metal layer 21 exposed by the first via 41. Similarly, the first protective conductor layer 31 can also completely cover the third area of the gate metal layer 61. The exposed area of the via 71.
  • first protective conductor layer 31 is provided on the side of the data line metal layer 21 away from the base substrate 1
  • second protective conductor layer 32 is provided on the side of the gate metal layer 61 away from the base substrate 1.
  • the first protective conductor layer 31 and the second protective conductor layer 32 are not connected to each other, that is, a space is provided between the two.
  • the orthographic projection of the first protective conductor layer 31 on the base substrate 1 At least partially overlaps with the orthographic projection of the data line metal layer 21 on the base substrate 1, that is, the first protective conductor layer 31 at least partially covers the area of the data line metal layer 21 exposed by the first via 41, and further, the first A protective conductor layer 31 can also completely cover the area exposed by the first via 41 of the data line metal layer 21; the orthographic projection of the second protective conductor layer 32 on the base substrate 1 and the gate metal layer 61 on the base substrate 1
  • the orthographic projections above overlap at least partially, that is, the second protective conductor layer 32 at least partially covers the area of the gate metal layer 61 exposed by the third via 71.
  • the second protective conductor layer 32 may also completely cover the gate metal layer 61. The area exposed by the third via 71.
  • the passivation layer 4 is formed on the side of the first protective conductor layer 31 away from the base substrate 1, or on the side of the first protective conductor layer 31 and the second protective conductor layer 32 away from the base substrate 1. 4 Perform a patterning process to form the first via 41, or perform a patterning process on the passivation layer 4 to form the first via 41 and the second via 42 respectively.
  • a number of exemplary embodiments corresponding to the structure of the non-display area of the display substrate described above, one is that only one side of the data line metal layer 21 is provided with the first protective conductor layer 31.
  • the other is to provide a first protective conductor layer 31 on one side of the data line metal layer 21 and a second protective conductor layer 32 on one side of the gate metal layer 61.
  • the first via 41 and the second via 42 can be formed on the passivation layer 4.
  • the first via 41 is connected to the first protective conductor layer 31, and the second via 42 is connected to the second protective conductor.
  • the first protective conductor layer 31 also extends to the area where the gate metal layer 61 is located.
  • first via 41 or the second via 42 may be formed on the passivation layer 4.
  • the via 41 or the second via 42 is connected to the first protective conductor layer 31.
  • the first via 41 and the second via 42, and the first via 41 and the second via can also be formed at the same time. 42 are all connected to the first protective conductor layer 31, thereby realizing multiple overlapping modes, reducing the overlapping resistance, and improving the reliability of the overlapping.
  • the material for forming the gate insulating layer 7 is similar to the material for forming the passivation layer 4, while the first via 41 and the second via 42 are formed on the passivation layer 4, A third via hole needs to be formed on the gate insulating layer 7.
  • a second electrode material layer is formed on the side of the passivation layer 4 away from the base substrate 1, and the second electrode material layer is patterned to form a second electrode in the display area and a connecting conductor layer 51 in the non-display area .
  • the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41, and the connecting conductor layer 51 is connected to the gate metal layer 61 through the second via 42 and the third via 71 .
  • the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41.
  • the connecting conductor layer 51 is connected to the first protective conductor layer 31 through the first via 41, and the connecting conductor layer 51 is connected to the second protective conductor layer 32 through the second via 42.
  • the connecting conductor layer 51 may also be connected to the first protective conductor layer 31 through the first via 41 and the second via 42 respectively.
  • the present disclosure also provides a display panel, which includes the above-mentioned display substrate.
  • the specific structure of the display substrate has been described in detail above, so it will not be repeated here.
  • the beneficial effects of the display panel provided by the embodiments of the present disclosure are the same as the beneficial effects of the display substrate provided by the above-mentioned embodiments, and will not be repeated here.
  • the present disclosure also provides a display device, which includes the above-mentioned display panel.
  • the specific type of the display device is not particularly limited.
  • the types of display devices commonly used in the field can be used, such as liquid crystal displays, OLED displays, mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. The personnel can make a corresponding selection according to the specific purpose of the display device, which will not be repeated here.
  • the display device also includes other necessary components and components. Taking the display as an example, specific examples include a housing, a circuit board, a power cord, etc. The specific usage requirements shall be supplemented accordingly, which will not be repeated here.
  • the beneficial effects of the display device provided by the embodiments of the present disclosure are the same as the beneficial effects of the display substrate provided by the above-mentioned embodiments, and will not be repeated here.
  • the terms “a”, “a”, “the” and “said” are used to indicate the presence of one or more elements/components/etc.; the terms “including”, “including” and “have” are used to It means open-ended inclusion and means that in addition to the listed elements/components/etc., there may be other elements/components/etc.; the terms “first”, “second” and “third” “, etc. are only used as markers, not as a restriction on the number of objects.

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Abstract

一种显示基板及其制备方法、显示面板和显示装置。该显示基板包括衬底基板（1），衬底基板设置有显示区和非显示区，在非显示区显示基板还包括数据线金属层（21）、第一保护导体层（31）、钝化层（4）和连接导体层（51）；数据线金属层设于衬底基板的一侧；第一保护导体层设于数据线金属层的远离衬底基板的一侧；钝化层设于第一保护导体层的远离衬底基板的一侧，钝化层上设置有第一过孔（41）；连接导体层设于钝化层的远离衬底基板的一侧，连接导体层通过第一过孔与第一保护导体层连接以使数据线金属层与连接导体层导通连接。通过第一保护导体层可以保护数据线金属层避免暴露于空气中和与其他刻蚀剂直接接触产生氧化、腐蚀不良，改良金属跨接性能。

Description

显示基板及其制备方法、显示面板和显示装置
交叉引用
本公开要求于2020年3月27日提交的申请号为202010229483.8名称为“显示基板及其制备方法、显示面板和显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示基板的制备方法、包括该显示基板的显示面板和包括该显示面板的显示装置。
背景技术
随着科技的发展，人们对显示产品的要求越来越高。目前，在显示基板的***区域，不同层的金属需通过跨接相互连通，但是在该区域数据线金属层和连接导体层的接触电阻存在异常增大的风险，影响金属跨接性能。
发明内容
本公开提供一种显示基板及显示基板的制备方法、包括该显示基板的显示面板和包括该显示面板的显示装置。
本公开的额外方面和优点将部分地在下面的描述中阐述，并且部分地将从描述中变得显然，或者可以通过本公开的实践而习得。
根据本公开的一个方面，提供一种显示基板，包括衬底基板，所述衬底基板设置有显示区和非显示区，在所述非显示区所述显示基板还包括：
数据线金属层，设于所述衬底基板的一侧；
第一保护导体层，设于所述数据线金属层的远离所述衬底基板的一侧，所述第一保护导体层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影至少部分交叠；
钝化层，设于所述第一保护导体层的远离所述衬底基板的一侧，所述钝化层上设置有第一过孔；
连接导体层，设于所述钝化层的远离所述衬底基板的一侧，所述连接导体层通过所述第一过孔与所述第一保护导体层连接以使所述数据线 金属层与所述连接导体层导通连接。
在本公开的一种示例性实施例中，在所述非显示区所述显示基板还包括：
栅金属层，设于所述衬底基板的一侧，所述栅金属层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影互不交叠；
栅绝缘层，设于所述栅金属层的远离所述衬底基板的一侧，所述栅绝缘层上设置有第三过孔，所述数据线金属层位于所述栅绝缘层的远离所述衬底基板的一侧；
所述钝化层设于所述栅绝缘层的远离所述衬底基板的一侧，所述钝化层上设置有第二过孔，所述连接导体层通过所述第二过孔和所述第三过孔与所述栅金属层连接。
在本公开的一种示例性实施例中，在所述非显示区所述显示基板还包括：
栅金属层，设于所述衬底基板的一侧，所述栅金属层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影互不交叠；
栅绝缘层，设于所述栅金属层的远离所述衬底基板的一侧，所述栅绝缘层上设置有第三过孔，所述数据线金属层位于所述栅绝缘层的远离所述衬底基板的一侧；
所述第一保护导体层延伸至所述栅绝缘层的远离所述衬底基板的一侧，且所述第一保护导体层通过所述第三过孔与所述栅金属层连接。
在本公开的一种示例性实施例中，在所述非显示区所述显示基板还包括：
栅金属层，设于所述衬底基板的一侧，所述栅金属层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影互不交叠；
栅绝缘层，设于所述栅金属层的远离所述衬底基板的一侧，所述栅绝缘层上设置有第三过孔，所述数据线金属层位于所述栅绝缘层的远离所述衬底基板的一侧；
第二保护导体层，设于所述栅绝缘层的远离所述衬底基板的一侧，所述第二保护导体层通过所述第三过孔与所述栅金属层连接；
所述钝化层设于所述第二保护导体层的远离所述衬底基板的一侧， 所述钝化层上设置有第二过孔，所述连接导体层通过所述第二过孔与所述第二保护导体层连接以使所述栅金属层与所述连接导体层导通连接。
在本公开的一种示例性实施例中，所述第一保护导体层与所述第二保护导体层同层同材料形成，且所述第一保护导体层与所述第二保护导体层连接为一体；或
所述第一保护导体层与所述第二保护导体层同层同材料形成，且所述第一保护导体层与所述第二保护导体层之间设置有间隔空间。
在本公开的一种示例性实施例中，在所述显示区所述显示基板包括：
第一电极，设于所述衬底基板的一侧，且所述第一电极的远离所述衬底基板的一侧设有所述钝化层；
第二电极，设于所述钝化层的远离所述衬底基板的一侧；
其中，所述第一电极与所述第一保护导体层同层同材料形成，所述第二电极与所述连接导体层同层同材料形成。
在本公开的一种示例性实施例中，所述第一电极为像素电极，所述第二电极为狭缝电极，且用于与所述第一电极形成多维电场。
在本公开的一种示例性实施例中，在所述显示区所述显示基板还包括：
栅极，设于所述衬底基板的一侧，且所述栅极的远离所述衬底基板的一侧设置有所述栅绝缘层；
有源层，设于所述栅绝缘层的远离所述衬底基板的一侧；
源漏极，设于所述有源层的远离所述衬底基板的一侧，且位于所述第一电极的靠近所述衬底基板的一侧，所述源漏极包括源极和漏极，所述源极与所述第一电极直接搭接；
其中，所述源漏极与所述数据线金属层同层同材料形成；所述栅极与所述栅金属层同层同材料形成。
在本公开的一种示例性实施例中，所述数据线金属层和所述栅金属层的材质为金属铜。
根据本公开的一个方面，提供一种显示基板的制备方法，包括：
提供一衬底基板，所述衬底基板设有显示区和非显示区；
在所述衬底基板的非显示区形成数据线金属层；
在所述数据线金属层的远离所述衬底基板的一侧形成第一保护导体 层，所述第一保护导体层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影至少部分交叠；
在所述第一保护导体层的远离所述衬底基板的一侧形成钝化层，并对所述钝化层进行图案化处理形成第一过孔；
在所述钝化层的远离所述衬底基板的一侧形成连接导体层，所述连接导体层通过所述第一过孔与所述第一保护导体层连接以使所述数据线金属层与所述连接导体层导通连接。
在本公开的一种示例性实施例中，在形成数据线金属层之前，所述制备方法还包括：
在所述衬底基板的非显示区形成栅金属层，所述栅金属层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影互不交叠；
在所述栅金属层的远离所述衬底基板的一侧形成栅绝缘层，所述数据线金属层形成于所述栅绝缘层的远离所述衬底基板的一侧。
在本公开的一种示例性实施例中，所述钝化层还形成在所述栅绝缘层的远离所述衬底基板的一侧；在形成所述第一过孔的同时，在所述钝化层上形成第二过孔并在所述栅绝缘层上形成第三过孔，使连接导体层通过第二过孔和第三过孔与栅金属层连接。
在本公开的一种示例性实施例中，形成栅绝缘层之后，所述制备方法还包括：
对所述栅绝缘层进行图案化处理形成第三过孔；
形成所述第一保护导体层的同时，在所述栅绝缘层的远离所述衬底基板的一侧形成第二保护导体层，所述第二保护导体层通过所述第三过孔与所述栅金属层连接；
所述钝化层还形成在所述第二保护导体层的远离所述衬底基板的一侧；在形成所述第一过孔的同时，在所述钝化层上形成第二过孔，使连接导体层通过第二过孔与所述第二保护导体层连接。
在本公开的一种示例性实施例中，所述第一保护导体层与所述第二保护导体层连接为一体，或所述第一保护导体层与所述第二保护导体层之间设置有间隔空间。
在本公开的一种示例性实施例中，形成栅绝缘层之后，所述制备方法还包括：
对所述栅绝缘层进行图案化处理形成第三过孔；
所述第一保护导体层还形成在所述栅绝缘层的远离所述衬底基板的一侧，所述第一保护导体层通过所述第三过孔与所述栅金属层连接。
在本公开的一种示例性实施例中，在形成所述第一保护导体层的同时，在所述衬底基板的显示区的一侧形成第一电极，所述第一电极为像素电极，且在所述第一电极的远离所述衬底基板的一侧形成有所述钝化层；
在形成所述连接导体层的同时，在所述显示区的所述钝化层的远离所述衬底基板的一侧形成第二电极，所述第二电极为公共电极。
根据本公开的一个方面，提供一种显示面板，包括上述任意一项所述的显示基板。
根据本公开的一个方面，提供一种显示装置，包括上述任意一项所述的显示面板。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1是相关技术中显示基板非显示区的结构示意图；
图2是本公开显示基板非显示区一示例实施方式的结构示意图；
图3是图2中还未形成连接导体层和配向膜时的结构示意图；
图4是本公开显示基板非显示区又一示例实施方式的结构示意图；
图5是本公开显示基板非显示区另一示例实施方式的结构示意图；
图6是本公开显示基板非显示区再一示例实施方式的结构示意图；
图7是本公开显示基板显示区一示例实施方式的结构示意图；
图8是本公开显示基板的制备方法的一示例实施方式的流程示意框图。
图中主要元件附图标记说明如下：
1、衬底基板；
21、数据线金属层；221、源极；222、漏极；
31、第一保护导体层；32、第二保护导体层；33、第一电极；
4、钝化层；41、第一过孔；42、第二过孔；
51、连接导体层；52、第二电极；
61、栅金属层；62、栅极；
7、栅绝缘层；71、第三过孔；
8、有源层；9、配向膜。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
参照图1所示的相关技术中显示基板非显示区的结构示意图；在衬底基板1上的一侧设置有栅金属层61，在栅金属层61的远离衬底基板1的一侧设置有栅绝缘层7，在栅绝缘层7上设置有第三过孔71，在栅绝缘层7的远离衬底基板1的一侧设置有数据线金属层21，数据线金属层21在衬底基板1上的正投影与栅金属层61在衬底基板1上的正投影互不交叠。在数据线金属层21和栅绝缘层7的远离衬底基板1的一侧设置有钝化层4，在钝化层4上设置有第一过孔41和第二过孔。在钝化层4的远离衬底基板1的一侧设置有连接导体层51，连接导体层51通过第一过孔41与数据线金属层21连接，连接导体层51通过第二过孔和第三过孔与栅金属层61连接。
在显示基板上形成数据线金属层21后，在形成钝化层4之前还需要形成其他膜层。在此过程中，位于非显示区的栅绝缘层7上的第三过孔71和钝化层4上的第二过孔42可以通过一次光刻工艺形成，因此，此过程中栅金属层61一直有栅绝缘层7的保护，降低了栅金属层出现氧化、腐蚀的可能。而数据线金属层21因为其远离衬底基板1的表面暴露在空气中，发生氧化的几率明显增加，并且在此过程中形成其他膜层时使用的洗液可与数据线金属层直接接触，增加了数据线金属层21被腐蚀的风 险，从而导致数据线金属层21与连接导体层51之间的接触电阻异常增大，影响后续与栅金属层61的跨接性能。
在本公开的一些实施例中，提供了一种显示基板，参照图2～6所示的本公开显示基板非显示区一示例实施方式的结构示意图；该显示基板可以包括衬底基板1、数据线金属层21、第一保护导体层31、钝化层4以及连接导体层51；数据线金属层21设于所述衬底基板1的一侧；第一保护导体层31设于所述数据线金属层21的远离所述衬底基板1的一侧，第一保护导体层31在衬底基板1上的正投影与数据线金属层21在衬底基板1上的正投影至少部分交叠；钝化层4设于所述第一保护导体层31的远离所述衬底基板1的一侧，所述钝化层4上设置有第一过孔41；连接导体层51设于所述钝化层4的远离所述衬底基板1的一侧，所述连接导体层51通过所述第一过孔41与所述第一保护导体层31连接。
下面将结合附图对本公开实施例作进一步地详细描述。
参照图2和图3所示的本公开显示基板非显示区一示例实施方式的结构示意图。
在本示例实施方式中，在衬底基板1上设置有栅金属层61，在栅金属层61的远离衬底基板1的一侧设置有栅绝缘层7，在栅绝缘层7上设置有第三过孔71，在栅绝缘层7的远离衬底基板1的一侧设置有数据线金属层21，数据线金属层21在衬底基板1上的正投影与栅金属层61在衬底基板1上的正投影互不交叠。在数据线金属层21的远离衬底基板1的一侧设置有第一保护导体层31，第一保护导体层31在衬底基板1上的正投影与数据线金属层21在衬底基板1上的正投影至少部分交叠，即第一保护导体层31至少部分覆盖数据线金属层21的被第一过孔41裸露的区域，进一步地，第一保护导体层31可以完全覆盖数据线金属层21的被第一过孔41裸露的区域。在第一保护导体层31和栅绝缘层7的远离衬底基板1的一侧设置有钝化层4，在钝化层4上设置有第一过孔41和第二过孔43。第二过孔42和第三过孔71是相通的。在钝化层4的远离衬底基板1的一侧设置有连接导体层51，连接导体层51通过第一过孔41与第一保护导体层31连接，第一保护导体层31能够导电，从而使连接导体层51与数据线金属层21能够导通连接。连接导体层51通过第二 过孔42和第三过孔71与所述栅金属层61连接。
在本示例的至少一个实施方式中，栅绝缘层7和钝化层4可以采用性质相近的材料，性质相近的材料可以通过同一种刻蚀液刻蚀形成图案，从而，可以仅通过一次光刻工艺在钝化层4上形成第二过孔42且在栅绝缘层7上形成第三过孔71。也因此，在形成此第二过孔42之前栅金属层61远离衬底基板1的表面被栅绝缘层7覆盖，所以无需对栅金属层61设置保护导体层进行保护，也即第一保护导体层31在衬底基板1上的正投影与栅金属层61在衬底基板1上的正投影无交叠。上述性质相近指的是可以通过相同的刻蚀剂进行刻蚀，例如，氧化硅、氮化硅、氧化硅和氮化硅的混合物均为性质相近的材料。
但是，在本公开的其他示例实施方式中，形成栅绝缘层7和钝化层4的材料性质差异较大，无法通过同一刻蚀剂进行刻蚀，也即无法仅通过一次光刻工艺在栅绝缘层7上形成第三过孔71且在钝化层4上形成第二过孔42，而需要在栅绝缘层7上先形成第三过孔71，然后再在钝化层4上形成第二过孔44。此时，栅绝缘层7远离衬底基板1的部分表面因为已形成第三过孔71而暴露在空气中，也存在被氧化、腐蚀的可能，需要在栅金属层61上也引入保护导体层进行保护。下面三个示例实施方式即是这种情况下，对显示基板非显示区的结构进行的具体说明。
参照图4所示的本公开显示基板非显示区又一示例实施方式的结构示意图。
在本示例实施方式中，在衬底基板1上设置有栅金属层61，在栅金属层61的远离衬底基板1的一侧设置有栅绝缘层7，在栅绝缘层7上设置有第三过孔71，在栅绝缘层7的远离衬底基板1的一侧设置有数据线金属层21，数据线金属层21在衬底基板1上的正投影与栅金属层61在衬底基板1上的正投影互不交叠。在数据线金属层21的远离衬底基板1的一侧设置有第一保护导体层31，第一保护导体层31在衬底基板1上的正投影与数据线金属层21在衬底基板1上的正投影至少部分交叠，且在栅绝缘层7的远离衬底基板1的一侧也设置有第一保护导体层31，第一保护导体层31在衬底基板1上的正投影与栅金属层61在衬底基板1上的正投影至少部分交叠，即第一保护导体层31至少部分覆盖栅金属层 61的被第三过孔71裸露的区域，且第一保护导体层31通过第三过孔71与栅金属层61连接。进一步地，第一保护导体层31也可以完全覆盖栅金属层61的被第三过孔71裸露的区域。
通过第一保护导体层31将数据线金属层21和栅金属层61连接。在第一保护导体层31的远离衬底基板1的一侧设置有钝化层4，在钝化层4上设置有第一过孔41。在钝化层4的远离衬底基板1的一侧设置有连接导体层51，连接导体层51通过第一过孔41与第一保护导体层31连接，第一保护导体层31能够导电，从而通过连接导体层51和第一保护导体层31将数据线金属层21和栅金属层61导通连接。
另外需要说明的是，参照图5所示的本公开显示基板非显示区另一示例实施方式的结构示意图。在图3中的示例实施方式的基础上，在钝化层4上设置第二过孔42，连接导体层51通过第二过孔42与第一保护导体层31连接，实现多处搭接模式，减小搭接电阻，提高搭接可靠性。
参照图6所示的本公开显示基板非显示区再一示例实施方式的结构示意图。
在本示例实施方式中，在衬底基板1上设置有栅金属层61，在栅金属层61的远离衬底基板1的一侧设置有栅绝缘层7，在栅绝缘层7上设置有第三过孔71，在栅绝缘层7的远离衬底基板1的一侧设置有数据线金属层21，数据线金属层21在衬底基板1上的正投影与栅金属层61在衬底基板1上的正投影互不交叠。在数据线金属层21的远离衬底基板1的一侧设置有第一保护导体层31，第一保护导体层31在衬底基板1上的正投影与数据线金属层21在衬底基板1上的正投影至少部分交叠。在栅绝缘层7的远离衬底基板1的一侧设置有第二保护导体层32，且第二保护导体层32通过第三过孔71与栅金属层61连接，第二保护导体层32在衬底基板1上的正投影与栅金属层61在衬底基板1上的正投影至少部分交叠，即第二保护导体层32至少部分覆盖栅金属层61的被第三过孔71裸露的区域，进一步地，第二保护导体层32也可以完全覆盖栅金属层61的被第三过孔71裸露的区域。第一保护导体层31和第二保护导体层32通过同一次构图工艺形成。在第一保护导体层31和第二保护导体的远离衬底基板1的一侧设置有钝化层4，在钝化层4上设置有第一过 孔41和第二过孔42。在钝化层4的远离衬底基板1的一侧设置有连接导体层51，连接导体层51通过第一过孔41与第一保护导体层31连接，第一保护导体层31能够导电，从而使连接导体层51与数据线金属层21能够导通连接。连接导体层51通过第二过孔42与第二保护导体层32连接，第二保护导体层32能够导电，从而使连接导体层51与栅金属层61能够导通连接。
在上述多个示例实施方式中，在连接导体层51的远离衬底基板1的一侧设置有配向膜9。
下面对本公开的显示基板的显示区的结构进行详细说明。
参照图7所示的本公开显示基板显示区一示例实施方式的结构示意图。
在本示例实施方式中，在显示区显示基板可以包括栅极62、栅绝缘层7、有源层8、源极221、漏极222、第一电极33、钝化层4以及第二电极52。具体为：在衬底基板1的一侧设置栅极62，在栅极62的远离衬底基板1的一侧和衬底基板1的一侧设置栅绝缘层7，在栅绝缘层7的远离衬底基板1的一侧设置有源层8，在有源层8的远离衬底基板1的一侧设置源极221和漏极222，源极221和漏极222分别与有源层电连接。在源极221的远离衬底基板1的一侧设置第一电极33，源极221和第一电极33直接搭接，漏极222与数据线电连接(图中未示出)向像素单元输入像素信号。在第一电极33的远离衬底基板1的一侧设置钝化层4，在钝化层4的远离衬底基板1的一侧设置有第二电极52，在第二电极52的远离衬底基板1的一面的一侧设置有配向膜9。需要说明的是，所述源极221和第一电极33直接搭接，指的是至少部分第一电极33形成在源极221远离衬底基板1的表面。
在一些实施例中，显示基板用于液晶显示面板，显示模式为高级超维场转换模式(Advanced Super Dimension Switch，简称ADS)，其中，第一电极33可以为狭缝电极，也可以为板状电极，第二电极52可以为狭缝电极，通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场，使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转，从而实现显示。在一些实施例中，源极221和漏极222与数据线金属层21同层同材料形成，栅极62和栅金属 层61同层同材料形成。其中，第一电极33可以为像素电极，第二电极52可以为公共电极，为了减小信号连接所占用的空间，第一电极33与源极221可以直接搭接，例如如图7所示，第一电极33至少部分覆盖源极221远离衬底基板1的表面，以实现二者的有效电连接，同时还可以优化像素开口率，从而提升显示产品的透过率。由于源极221和漏极222与数据线金属层21同层同材料形成，而第一电极33直接形成于源漏极远离衬底基板1的表面，因此，第一电极33与第一保护导体层31和第二保护导体层32可以为同层同材料形成，类似的，第二电极52与连接导体层51也可以同层同材料形成。需要说明的是，此处所述的同层同材料形成指的是通过采用同一材料在同一次构图工艺形成图案。通过同一次构图工艺即可形成不同功能的多个结构，在不增加工艺流程的基础上即可满足产品的各项功能需求，不仅能够节省人力物力，而且能够提高产品性能。
在一些实施例中，栅极62、源极221、漏极222、数据线金属层21和栅金属层61的材质可以为金属铜。采用信号传输性能较好的铜来制作栅极62、源漏极22、数据线金属层21和栅金属层61，能够提高刷新率；但因为铜的性质更活泼，因此当其暴露于空气中或者与其他刻蚀剂直接接触时会发生金属腐蚀的不良。通过第一保护导体层31、栅绝缘层7、第二保护导体层32可以保护金属铜避免暴露于空气中或者与其他刻蚀剂直接接触生金属腐蚀的不良，避免连接导体层51与数据线金属层21和栅金属层61之间的接触电阻异常增加，改良金属跨接性能。
在本公开的一些实施例中，还提供了一种显示基板的制备方法，参照图8所示的本公开显示基板的制备方法的一示例实施方式的流程示意框图，该制备方法包括以下步骤：
步骤S10，提供一衬底基板1，所述衬底基板1设有显示区和非显示区；
步骤S20，在所述衬底基板1的非显示区形成数据线金属层21；
步骤S30，在所述数据线金属层21的远离所述衬底基板1的一侧形成第一保护导体层31，所述第一保护导体层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影至少部分交叠；
步骤S40，在所述第一保护导体层31的远离所述衬底基板1的一侧形成钝化层4，并对所述钝化层4进行图案化处理形成第一过孔41；
步骤S50，在所述钝化层4的远离所述衬底基板1的一侧形成连接导体层51，所述连接导体层51通过所述第一过孔41与所述第一保护导体层31连接以使所述数据线金属层21与所述连接导体层51导通连接。
下面对本公开显示基板的制备方法的各个步骤进行详细说明。
提供一衬底基板1，衬底基板1可以为玻璃基板。衬底基板1设有显示区和非显示区；在显示区形成显示结构，在非显示区形成绑定结构、各种电路等等。
在衬底基板1上通过蒸镀或溅射等工艺形成栅极材料层，并对栅极材料层进行图案化处理，使栅极材料层在显示区形成栅极62，在非显示区形成栅金属层61。
在栅极62和栅金属层61远离衬底基板1的一侧形成栅绝缘层7。其中，若形成栅绝缘层7的材料与后续形成的钝化层4的材料性质差异较大，无法通过同一刻蚀剂进行刻蚀的话，需要对栅绝缘层7位于非显示区的部分进行图案化处理，以形成第三过孔71。
在栅绝缘层7远离衬底基板1的一侧形成有源层8，在有源层8远离衬底基板1的一侧通过蒸镀或溅射等工艺形成源漏极材料层，并对源漏极材料层进行图案化处理以在在显示区形成源极221和漏极222，其中，源极221和漏极222分别与有源层电连接。在栅绝缘层7远离衬底基板1的一侧形成数据线金属层21，当然，数据线金属层21与源极221和漏极222也可以同层同材料形成，即在显示区和非显示区均形成第一导电材料层，然后对第一导电材料层进行一次图案化处理，以同时形成源极221、漏极222和数据线金属层21。
在源极221和漏极222远离衬底基板1的一侧形成第一电极材料层，并对第一电极材料层进行图案化处理，以在显示区形成第一电极33。使源极221和第一电极33直接搭接，漏极222与数据线(图中未示出)电连接以向像素单元输入像素信号。在数据线金属层21远离衬底基板1的一侧形成第一保护导体层31，或者，在数据线金属层21远离衬底基板1的一侧形成第一保护导体层31和第二保护导体层32。需要说明的是， 第一电极33、第一保护导体层31和第二保护导体层32也可以同层同材料形成，即在显示区和非显示区均形成第一电极材料层，然后对第一电极材料层进行一次图案化处理，以在显示区形成第一电极33，同时在非显示区形成第一保护导体层31和第二保护导体层32。
具体来说：对应于上述显示基板的非显示区的结构的多个示例实施方式，一种为仅在数据线金属层21远离衬底基板1的一侧设置有第一保护导体层31，即第一保护导体层31在衬底基板1上的正投影与数据线金属层21在衬底基板1上的正投影至少部分交叠，第一保护导体层31至少部分覆盖数据线金属层21的被第一过孔41裸露的区域，进一步地，第一保护导体层31也可以完全覆盖数据线金属层21的被第一过孔41裸露的区域。
另一种为第一保护导体层31还延伸至栅金属层61所在区域，也即第一保护导体层31在衬底基板1上的正投影与数据线金属层21在衬底基板1上的正投影至少部分交叠的同时，第一保护导体层31在衬底基板1上的正投影还与栅金属层61在衬底基板1上的正投影至少部分交叠，换言之，第一保护导体层31至少部分覆盖数据线金属层21的被第一过孔41裸露的区域，且至少部分覆盖栅金属层61的被第三过孔71裸露的区域。进一步地，第一保护导体层31也可以完全覆盖数据线金属层21的被第一过孔41裸露的区域，类似地，第一保护导体层31还可以完全覆盖栅金属层61的被第三过孔71裸露的区域。
再一种为在数据线金属层21远离衬底基板1的一侧设置有第一保护导体层31，且在栅金属层61远离衬底基板1的一侧设置有第二保护导体层32，第一保护导体层31与第二保护导体层32之间互不连接，即两者之间设置有间隔空间，在该种情况下，第一保护导体层31在衬底基板1上的正投影与数据线金属层21在衬底基板1上的正投影至少部分交叠，即第一保护导体层31至少部分覆盖数据线金属层21的被第一过孔41裸露的区域，进一步地，第一保护导体层31也可以完全覆盖数据线金属层21的被第一过孔41裸露的区域；第二保护导体层32在衬底基板1上的正投影与栅金属层61在衬底基板1上的正投影至少部分交叠，即第二保护导体层32至少部分覆盖栅金属层61的被第三过孔71裸露的区域，另 外，第二保护导体层32也可以完全覆盖栅金属层61的被第三过孔71裸露的区域。
在第一保护导体层31远离衬底基板1的一侧，或者，在第一保护导体层31和第二保护导体层32远离衬底基板1的一侧形成钝化层4，对钝化层4进行图案化处理以形成第一过孔41，或者，对钝化层4进行图案化处理以分别形成第一过孔41和第二过孔42。
具体来说：对应于上述显示基板的非显示区的结构的多个示例实施方式，一种为仅在数据线金属层21的一侧设置有第一保护导体层31。另一种为在数据线金属层21的一侧设置有第一保护导体层31且在栅金属层61的一侧设置有第二保护导体层32。这两种情况下，可以在钝化层4上形成第一过孔41和第二过孔42，第一过孔41连通至第一保护导体层31，第二过孔42连通至第二保护导体层32或栅金属层61。再一种为第一保护导体层31还延伸至栅金属层61所在区域，这种情况下，可以在钝化层4上仅形成第一过孔41或第二过孔42，此时第一过孔41或第二过孔42连通至第一保护导体层31，当然，这种情况下也可以同时形成第一过孔41和第二过孔42，第一过孔41和第二过孔42均连通至第一保护导体层31，从而实现多处搭接模式，减小搭接电阻，提高搭接可靠性。
另外，需要说明的是，在形成栅绝缘层7的材料与形成钝化层4的材料材质相似的情况下，在钝化层4上形成第一过孔41和第二过孔42的同时，需要在栅绝缘层7上形成第三过孔。
在钝化层4远离衬底基板1的一侧形成第二电极材料层，并对第二电极材料层进行图案化处理，以在显示区形成第二电极，在非显示区形成连接导体层51。
具体来说：一种情况为连接导体层51通过第一过孔41与第一保护导体层31连接，且连接导体层51通过第二过孔42和第三过孔71与栅金属层61连接。另一种情况为连接导体层51通过第一过孔41与第一保护导体层31连接。再一种情况为连接导体层51通过第一过孔41与第一保护导体层31连接，且连接导体层51通过第二过孔42与第二保护导体层32连接。此外，连接导体层51也可以分别通过第一过孔41和第二过孔42与第一保护导体层31连接。
进一步的，本公开还提供了一种显示面板，该显示面板包括上述所述的显示基板。显示基板的具体结构上述已经进行了详细说明，因此，此处不再赘述。
与现有技术相比，本公开实施例提供的显示面板的有益效果与上述实施例提供的显示基板的有益效果相同，在此不做赘述。
进一步的，本公开还提供了一种显示装置，该显示装置包上述所述的显示面板。而该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如液晶显示器、OLED显示器、手机等移动装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该显示装置除了显示面板以外，还包括其他必要的部件和组成，以显示器为例，具体例如外壳、电路板、电源线，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
与现有技术相比，本公开实施例提供的显示装置的有益效果与上述实施例提供的显示基板的有益效果相同，在此不做赘述。
上述所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中，如有可能，各实施例中所讨论的特征是可互换的。在上面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而没有所述特定细节中的一个或更多，或者可以采用其它的方法、组件、材料等。在其它情况下，不详细示出或描述公知结构、材料或者操作以避免模糊本公开的各方面。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
本说明书中，用语“一个”、“一”、“该”和“所述”用以表示存在一个或多个要素/组成部分/等；用语“包含”、“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
应可理解的是，本公开不将其应用限制到本说明书提出的部件的详细结构和布置方式。本公开能够具有其他实施方式，并且能够以多种方式实现并且执行。前述变形形式和修改形式落在本公开的范围内。应可理解的是，本说明书公开和限定的本公开延伸到文中和/或附图中提到或明显的两个或两个以上单独特征的所有可替代组合。所有这些不同的组合构成本公开的多个可替代方面。本说明书所述的实施方式说明了已知用于实现本公开的最佳方式，并且将使本领域技术人员能够利用本公开。

Claims (18)

  1. 一种显示基板，包括衬底基板，所述衬底基板设置有显示区和非显示区，其中，在所述非显示区所述显示基板还包括：
    数据线金属层，设于所述衬底基板的一侧；
    第一保护导体层，设于所述数据线金属层的远离所述衬底基板的一侧，所述第一保护导体层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影至少部分交叠；
    钝化层，设于所述第一保护导体层的远离所述衬底基板的一侧，所述钝化层上设置有第一过孔；
    连接导体层，设于所述钝化层的远离所述衬底基板的一侧，所述连接导体层通过所述第一过孔与所述第一保护导体层连接以使所述数据线金属层与所述连接导体层导通连接。
  2. 根据权利要求1所述的显示基板，其中，在所述非显示区所述显示基板还包括：
    栅金属层，设于所述衬底基板的一侧，所述栅金属层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影互不交叠；
    栅绝缘层，设于所述栅金属层的远离所述衬底基板的一侧，所述栅绝缘层上设置有第三过孔，所述数据线金属层位于所述栅绝缘层的远离所述衬底基板的一侧；
    所述钝化层设于所述栅绝缘层的远离所述衬底基板的一侧，所述钝化层上设置有第二过孔，所述连接导体层通过所述第二过孔和所述第三过孔与所述栅金属层连接。
  3. 根据权利要求1所述的显示基板，其中，在所述非显示区所述显示基板还包括：
    栅金属层，设于所述衬底基板的一侧，所述栅金属层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影互不交叠；
    栅绝缘层，设于所述栅金属层的远离所述衬底基板的一侧，所述栅绝缘层上设置有第三过孔，所述数据线金属层位于所述栅绝缘层的远离所述衬底基板的一侧；
    所述第一保护导体层延伸至所述栅绝缘层的远离所述衬底基板的一侧，且所述第一保护导体层通过所述第三过孔与所述栅金属层连接。
  4. 根据权利要求1所述的显示基板，其中，在所述非显示区所述显示基板还包括：
    栅金属层，设于所述衬底基板的一侧，所述栅金属层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影互不交叠；
    栅绝缘层，设于所述栅金属层的远离所述衬底基板的一侧，所述栅绝缘层上设置有第三过孔，所述数据线金属层位于所述栅绝缘层的远离所述衬底基板的一侧；
    第二保护导体层，设于所述栅绝缘层的远离所述衬底基板的一侧，所述第二保护导体层通过所述第三过孔与所述栅金属层连接；
    所述钝化层设于所述第二保护导体层的远离所述衬底基板的一侧，所述钝化层上设置有第二过孔，所述连接导体层通过所述第二过孔与所述第二保护导体层连接以使所述栅金属层与所述连接导体层导通连接。
  5. 根据权利要求4所述的显示基板，其中，所述第一保护导体层与所述第二保护导体层同层同材料形成，且所述第一保护导体层与所述第二保护导体层连接为一体；或
    所述第一保护导体层与所述第二保护导体层同层同材料形成，且所述第一保护导体层与所述第二保护导体层之间设置有间隔空间。
  6. 根据权利要求2～5任意一项所述的显示基板，其中，在所述显示区所述显示基板包括：
    第一电极，设于所述衬底基板的一侧，且所述第一电极的远离所述衬底基板的一侧设有所述钝化层；
    第二电极，设于所述钝化层的远离所述衬底基板的一侧；
    其中，所述第一电极与所述第一保护导体层同层同材料形成，所述第二电极与所述连接导体层同层同材料形成。
  7. 根据权利要求6所述的显示基板，其中，所述第一电极为像素电极，所述第二电极为狭缝电极，且用于与所述第一电极形成多维电场。
  8. 根据权利要求6所述的显示基板，其中，在所述显示区所述显示基板还包括：
    栅极，设于所述衬底基板的一侧，且所述栅极的远离所述衬底基板的一侧设置有所述栅绝缘层；
    有源层，设于所述栅绝缘层的远离所述衬底基板的一侧；
    源漏极，设于所述有源层的远离所述衬底基板的一侧，且位于所述第一电极的靠近所述衬底基板的一侧，所述源漏极包括源极和漏极，所述源极与所述第一电极直接搭接；
    其中，所述源漏极与所述数据线金属层同层同材料形成；所述栅极与所述栅金属层同层同材料形成。
  9. 根据权利要求6所述的显示基板，其中，所述数据线金属层和所述栅金属层的材质为金属铜。
  10. 一种显示基板的制备方法，其中，包括：
    提供一衬底基板，所述衬底基板设有显示区和非显示区；
    在所述衬底基板的非显示区形成数据线金属层；
    在所述数据线金属层的远离所述衬底基板的一侧形成第一保护导体层，所述第一保护导体层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影至少部分交叠；
    在所述第一保护导体层的远离所述衬底基板的一侧形成钝化层，并对所述钝化层进行图案化处理形成第一过孔；
    在所述钝化层的远离所述衬底基板的一侧形成连接导体层，所述连接导体层通过所述第一过孔与所述第一保护导体层连接以使所述数据线金属层与所述连接导体层导通连接。
  11. 根据权利要求10所述的显示基板的制备方法，其中，在形成数据线金属层之前，所述制备方法还包括：
    在所述衬底基板的非显示区形成栅金属层，所述栅金属层在所述衬底基板上的正投影与所述数据线金属层在所述衬底基板上的正投影互不交叠；
    在所述栅金属层的远离所述衬底基板的一侧形成栅绝缘层，所述数据线金属层形成于所述栅绝缘层的远离所述衬底基板的一侧。
  12. 根据权利要求11所述的显示基板的制备方法，其中，所述钝化层还形成在所述栅绝缘层的远离所述衬底基板的一侧；在形成所述第一 过孔的同时，在所述钝化层上形成第二过孔，并在所述栅绝缘层上形成第三过孔，使连接导体层通过第二过孔和第三过孔与栅金属层连接。
  13. 根据权利要求11所述的显示基板的制备方法，其中，形成栅绝缘层之后，所述制备方法还包括：
    对所述栅绝缘层进行图案化处理形成第三过孔；
    形成所述第一保护导体层的同时，在所述栅绝缘层的远离所述衬底基板的一侧形成第二保护导体层，所述第二保护导体层通过所述第三过孔与所述栅金属层连接；
    所述钝化层还形成在所述第二保护导体层的远离所述衬底基板的一侧；在形成所述第一过孔的同时，在所述钝化层上形成第二过孔，使连接导体层通过第二过孔与所述第二保护导体层连接。
  14. 根据权利要求13所述的显示基板的制备方法，其中，所述第一保护导体层与所述第二保护导体层连接为一体，或所述第一保护导体层与所述第二保护导体层之间设置有间隔空间。
  15. 根据权利要求11所述的显示基板的制备方法，其中，形成栅绝缘层之后，所述制备方法还包括：
    对所述栅绝缘层进行图案化处理形成第三过孔；
    所述第一保护导体层还形成在所述栅绝缘层的远离所述衬底基板的一侧，所述第一保护导体层通过所述第三过孔与所述栅金属层连接。
  16. 根据权利要求11～15任意一项所述的显示基板的制备方法，其中，在形成所述第一保护导体层的同时，在所述衬底基板的显示区的一侧形成第一电极，所述第一电极为像素电极，且在所述第一电极的远离所述衬底基板的一侧形成有所述钝化层；
    在形成所述连接导体层的同时，在所述显示区的所述钝化层的远离所述衬底基板的一侧形成第二电极，所述第二电极为公共电极。
  17. 一种显示面板，其中，包括权利要求1～9任意一项所述的显示基板。
  18. 一种显示装置，其中，包括权利要求17所述的显示面板。
PCT/CN2020/141653 2020-03-27 2020-12-30 显示基板及其制备方法、显示面板和显示装置 WO2021190055A1 (zh)

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