WO2021189581A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

Info

Publication number
WO2021189581A1
WO2021189581A1 PCT/CN2020/086106 CN2020086106W WO2021189581A1 WO 2021189581 A1 WO2021189581 A1 WO 2021189581A1 CN 2020086106 W CN2020086106 W CN 2020086106W WO 2021189581 A1 WO2021189581 A1 WO 2021189581A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock signal
line
display panel
electrode
frame area
Prior art date
Application number
PCT/CN2020/086106
Other languages
English (en)
French (fr)
Inventor
高雅楠
金一坤
赵斌
张鑫
赵军
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/770,412 priority Critical patent/US11694646B2/en
Publication of WO2021189581A1 publication Critical patent/WO2021189581A1/zh

Links

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0223—Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes

Definitions

  • the present application relates to the technical field of display panels, and in particular to a display panel and a display device.
  • LCD liquid crystal displays
  • OLED organic light emitting diode displays
  • the LCD display panel is taken as an example, which is mainly composed of a thin film transistor (TFT) array substrate, a color filter (CF) substrate, and a liquid crystal layer (Liquid Crystal Layer) arranged between the two substrates. constitute.
  • TFT thin film transistor
  • CF color filter
  • Liquid Crystal Layer Liquid Crystal Layer
  • the GOA circuit uses multiple TFT tubes.
  • the channel length of each tube, the source/drain etching and the final completion value are critical to the normal operation and stability of the entire circuit. But the source signal of each level of GOA comes from the Busline area of GOA.
  • FIG. 1 it illustrates the GOA signal input structure, which includes: GOA units 61 to 64 arranged on one side of the array substrate, clock signal lines 11 to 14 in the Busline, and electrically connected to clock signal lines 11 to 14 And the connecting lines 31-34 between the corresponding GOA units 61-64; the second electrode 82 arranged on one side of the color filter substrate, the second electrode 82 is a conventional electrode, and the conventional electrode is a common electrode, and the conventional common electrode is The film substrate is set on the entire surface. The second electrode 82 covers the clock signal line and the connecting line.
  • the length/area of the clock signal lines 11-14 and the connecting lines 31-34 connected to the GOA units 61-64 are different, resulting in the clock signal lines 11-14,
  • the connecting wires 31 ⁇ 34 and the second electrode 82 have different capacitance values.
  • the ultra-high resolution products are more sensitive to resistance/capacitance. Time, signal delay) are different, which will cause problems such as horizontal lines in the in-plane display.
  • the embodiments of the present application provide a display panel and a display device to solve the technical problem of horizontal horizontal lines in the in-plane display caused by the different capacitances formed by the clock signal line, the connecting line, and the second electrode in the existing display panel.
  • a display panel includes: a plurality of GOA units arranged along a first direction; a plurality of clock signal lines arranged along a second direction, the plurality of clock signal lines are located on one side of the plurality of GOA units and along the The first direction extends, the second direction is perpendicular to the first direction; a plurality of connecting lines, each of the connecting lines extends in the second direction and is connected to the corresponding clock signal line and the corresponding Between the GOA units; the first electrode, the first electrode is located at one side of the GOA units, the clock signal lines, and the connection lines, the first electrode has an opening , The opening corresponds to at least one of the clock signal lines and/or at least one of the connecting lines.
  • a display panel includes: a first clock signal drive line and a second clock signal drive line; a first GOA unit and a second GOA unit, the first clock signal drive line is connected to the first GOA unit, so The second clock signal driving line is connected to the second GOA unit; a first electrode, the first electrode is provided with an opening, and the area of the opening corresponding to the first clock signal driving line is larger than the opening The area of the portion corresponding to the second clock signal driving line.
  • the application also proposes a display device, which includes a display panel, the display panel includes: a first clock signal drive line and a second clock signal drive line; a first GOA unit and a second GOA unit, the first clock
  • the signal driving line is connected to the first GOA unit
  • the second clock signal driving line is connected to the second GOA unit
  • the first electrode is provided with an opening, and the opening corresponds to the first GOA unit.
  • the area of a part of the clock signal driving line is larger than the area of the part of the opening corresponding to the second clock signal driving line.
  • the beneficial effect of the present application is that by providing an opening on the first electrode, the difference in capacitance formed by the clock signal line, the connecting line and the first electrode is reduced, so as to improve the problem of horizontal horizontal lines in the in-plane display.
  • FIG. 1 is a schematic diagram of the structure of a frame area of a display panel provided by the prior art
  • FIG. 2 is a schematic diagram of the first structure of the frame area of the display panel provided in the first embodiment of the application;
  • FIG. 3 is a schematic diagram of a second structure of the frame area of the display panel provided in the first embodiment of the application;
  • FIG. 4 is a schematic diagram of the first structure of the frame area of the display panel provided in the second embodiment of the application;
  • FIG. 5 is a schematic diagram of the second structure of the frame area of the display panel provided in the second embodiment of the application.
  • FIG. 6 is a schematic diagram of the first structure of the frame area of the display panel provided in the third embodiment of the application.
  • FIG. 7 is a schematic diagram of the second structure of the frame area of the display panel provided in the third embodiment of the application.
  • FIG. 8 is a schematic diagram of a structure of the frame area of the display panel provided in the fourth embodiment of the application.
  • FIG. 9 is a schematic diagram of the first top view structure of the display panel provided by Embodiment 5/Ten of this application.
  • FIG. 10 is a schematic diagram of a second top view structure of the display panel provided by Embodiment 5/Tenth of this application;
  • FIG. 11 is a schematic diagram of a third top view structure of the display panel provided in Embodiment 5/Ten of this application;
  • FIG. 12 is a schematic diagram of the first structure of the frame area of the display panel provided by the sixth/seventh embodiment of the application.
  • FIG. 13 is a schematic diagram of the second structure of the frame area of the display panel provided in Embodiment 6/7 of this application;
  • FIG. 14 is a schematic diagram of a third structure of the frame area of the display panel provided in the sixth/seventh embodiment of the application.
  • FIG. 15 is a schematic diagram of a structure of the frame area of the display panel provided in the eighth embodiment of the application.
  • FIG. 16 is a schematic diagram of a structure of the frame area of the display panel provided in the ninth embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relation.
  • an intermediate medium it can be the internal communication of two components or the interaction of two components relation.
  • the "above” or “below” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • the "above”, “above” and “above” of the first feature on the second feature include the first feature directly above and obliquely above the second feature, or it simply means that the first feature is higher in level than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • the embodiment of the present application provides a display panel, including: a plurality of GOA units arranged along a first direction; Extend along the first direction, the second direction is perpendicular to the first direction; a plurality of connecting lines, each connecting line extends in the second direction and is connected between the corresponding clock signal line and the corresponding GOA unit; the first electrode, the first One electrode is located on one side of the multiple GOA units, multiple clock signal lines, and multiple connection lines.
  • the first electrode has an opening corresponding to the multiple clock signal lines, and the multiple connection lines are located on the side of the multiple clock signal lines. Between the part.
  • the present application reduces the difference in capacitance between the clock signal line, the connection line and the first electrode by providing an opening on the first electrode, and improves the technical problem of horizontal horizontal lines in the in-plane display.
  • the types of display panels include, but are not limited to, liquid crystal display panels, organic light emitting display panels, and quantum dot display panels.
  • the display panel includes: a plurality of GOA units 61 to 64 arranged in a first direction; a plurality of clock signal lines 11 to 14 arranged in a second direction, and the plurality of clock signal lines 11 to 14 are located in the plurality of GOA units 61 to 64 One side extends in the first direction, and the second direction is perpendicular to the first direction; a plurality of connecting lines 31 to 34, each of the connecting lines 31 to 34 extends in the second direction and is connected to the corresponding clock signal lines 11 to 14 and Corresponding GOA units 61 to 64; the first electrode 81, the first electrode 81 is located on one side of the GOA units 61 to 64, the clock signal lines 11 to 14 and the connection lines 31 to 34, the first The electrode 81 has an opening 100, and the opening 100 corresponds to at least one clock signal line 11-14 and/or at least
  • the opening corresponds to at least one clock signal line 11-14 and/or at least one connection line 31-34, which means that the opening 100 corresponds to at least one of the multiple clock signal lines 11-14, or the opening 100 corresponds to the multiple connection lines 31 ⁇ At least one of 34 or the opening 100 corresponds to at least one of the multiple clock signal lines 11-14 and at least one of the multiple connection lines 31-34 at the same time, which is not limited here.
  • the opening 100 may be one opening, two or more sub-openings, which are not limited herein.
  • the opening 100 corresponds to the plurality of clock signal lines 11 to 14 and the portion of the plurality of connection lines 31 to 34 located between the plurality of clock signal lines 11 to 14 as an example.
  • the first electrode 81 is located on one side of the plurality of GOA units 61 to 64, the plurality of clock signal lines 11 to 14 and the plurality of connecting lines 31 to 34, where "one side” refers to the first electrode 81 Located on one side of the plane where the multiple clock signal lines 11-14 (or the plane where the multiple connection lines 31-34 are located, or the plane where the multiple GOA units 61-64 are located), including but not limited to the first electrode being located on the multiple clock signals Above or below the plane where the lines 11-14 (or the plane where the multiple connecting lines 31-34 are located, or the plane where the multiple GOA units 61-64 are located).
  • the opening 100 corresponds to the plurality of clock signal lines 11-14, and the portion of the plurality of connecting lines 31-34 located between the plurality of clock signal lines 11-14, and the opening 100 is far away in the second direction.
  • the opening 100 corresponds to the plurality of clock signal lines 11-14, and the part of the plurality of connecting lines 31-34 located between the plurality of clock signal lines 11-14, and the opening 100 is far away in the second direction.
  • a first electrode 81 is provided on one side of the GOA units 61-64.
  • the method for forming the opening 100 includes: firstly fabricating the first electrode 81 with a full surface, and then forming the opening 100 through processes such as exposure and etching.
  • the material of the first electrode 81 includes but is not limited to ITO.
  • the connecting wires 31 to 34 and the clock signal wires 11 to 14 are conductive metals of different layers and are separated by an insulating layer.
  • the connecting wires 31 to 34 are electrically connected to the corresponding clock signal wires 11 to 14 through the through holes on the insulating layer.
  • the clock signal lines 11 to 14 are made of a first layer of metal
  • the connecting lines 31 to 34 are made of a second layer of metal.
  • the first layer of metal and the second layer of metal are separated by an insulating layer.
  • the metal connecting wires 31 to 34 are electrically connected to the corresponding clock signal wires 11 to 14 of the first layer of metal through the through holes on the insulating layer.
  • the first layer of metal and the second layer of metal can be formed and etched in the same process as the metal layer in the display panel.
  • the first layer of metal can be in the same layer as the scan line
  • the second layer The metal can be in the same layer as the data line, or the first layer of metal can be in the same layer as the scan line or data line, and the second layer of metal can be in the same layer as the common electrode or the pixel electrode, but it is not limited to these examples.
  • the difference in capacitance between the clock signal line, the connection line and the first electrode is reduced, thereby reducing the incoming GOA unit ,
  • the difference of the falling time (signal falling edge time, signal delay) of the in-plane signal to improve the horizontal horizontal line in the in-plane display.
  • the display panel has a first electrode 81, and the first electrode 81 is located on one side of the GOA units 61 to 64, the clock signal lines 11 to 14 and the connection lines 31 to 34.
  • One electrode 81 has an opening 100, and the opening 100 corresponds to a plurality of clock signal lines 11-14, a plurality of connection lines 31-34, and a plurality of GOA units 61-64.
  • the opening 100 by setting the opening 100 to correspond to multiple clock signal lines, multiple connection lines, and multiple GOA units, the difference in capacitance between the clock signal line, the connection line and the first electrode forming capacitance is reduced, thereby reducing
  • the difference in falling time of incoming GOA unit and in-plane signals is used to improve the problem of horizontal horizontal lines in the in-plane display.
  • Embodiment 1 is the same as or similar to Embodiment 1 to Embodiment 2, except that:
  • FIG. 6 among the connecting wire 31 to the connecting wire 34, at least two connecting wires have a gradually decreasing width to reduce the difference in resistance value of the connecting wire 31 to the connecting wire 34.
  • FIG. 7 among the connecting wire 31 to the connecting wire 34, at least two connecting wires have gradually increasing widths to reduce the capacitance difference between the connecting wire 31 to the connecting wire 34 and the first electrode 81 forming a capacitance.
  • the openings 100 in the first embodiment to the second embodiment can be provided at the same time.
  • the double setting of the opening 100 and the width of the connecting line gradually reduces the difference in capacitance between the clock signal line, the connecting line and the first electrode and the resistance between the connecting lines, thereby reducing Minimize the difference in the falling time of incoming GOA unit and in-plane signals to improve the problems of horizontal horizontal lines in the in-plane display.
  • the connection line is designed with a winding compensation part.
  • the GOA units 61-64 are arranged along the first direction
  • the clock signal lines 11-14 are arranged along the second direction
  • the clock signal lines 11-14 are located on one side of the GOA units 61-64 and extend along the first direction.
  • the second direction is perpendicular to the first direction
  • the connecting lines 31-34 extend along the second direction and are connected between the corresponding clock signal lines 11-14 and the corresponding GOA units 61-64.
  • the clock signal lines 11, 12, 13, 14 are located on one side of the GOA units 61-64 and are in turn close to the GOA units 61-64, the connecting line 31 is electrically connected to the clock signal line 11 and the GOA unit 61, and the connecting line 32 is electrically connected Between the clock signal line 12 and the GOA unit 62, the connection line 33 is electrically connected to the clock signal line 13 and the GOA unit 63, the connection line 34 is electrically connected to the clock signal line 14 and the GOA unit 64, and the connection lines 31, 32, 33, 34 has a gradually reduced length, and the connecting wires 31, 32, 33, and 34 are respectively provided with a compensating portion 1 that compensates for the gradually increasing winding length, which can reduce the resistance difference between the connecting wires 31, 32, 33, and 34.
  • the connecting wires 31, 32, 33, and 34 are respectively provided with gradually decreasing compensation winding lengths, which can reduce the clock signal line 11 and the connection line 31, the clock signal line 12 and the connection line 32, and the clock signal line 13 and the connection line.
  • the line 33, the clock signal line 14 and the connection line 34 form a capacitance difference with the first electrode 81 in capacitance value.
  • the limitation on the number of compensation winding parts is: the area of the winding compensation parts of at least two connecting wires gradually increases or decreases in the first direction.
  • the opening 100 in the preferred solution also corresponds to the winding compensation portion 1 of the connecting wires 31 to 34.
  • the opening 100 may not correspond to the winding compensation portion 1 of the connecting wires 31-34.
  • the opening 100 is provided at one of the winding compensation portions 1 of the connecting wires 31-34 in FIG. 8 away from the GOA units 61-64. side.
  • the difference in capacitance between the clock signal line, the connecting wire and the first electrode formed by the capacitance and the difference in resistance between the connecting wires are reduced at the same time, In this way, the difference between the falling time of the incoming GOA unit and the in-plane signal is reduced, so as to improve the problem of horizontal horizontal lines in the in-plane display.
  • the types of display panels may include, but are not limited to, liquid crystal display panels, organic light emitting display panels, and quantum dot display panels.
  • the display panel includes but is not limited to: an array substrate, clock signal lines 11-14, GOA units 61-64, and connecting lines 31-34 are arranged on one side of the array substrate; a color filter substrate, the first electrode 81 is arranged on the color filter substrate On one side, the first electrode 81 is a common electrode.
  • a VA type (vertical alignment type) liquid crystal display panel is taken as an example for description of the special display panel.
  • the display panel may include: an array substrate, clock signal lines 11-14, GOA units 61-64, and connecting lines 31-34 are arranged on one side of the array substrate; a color film substrate, a first electrode 81, and a color resist layer (not shown in the figure) ) Is arranged on one side of the color filter substrate, the first electrode 81 is a common electrode, and the color resist layer includes a red color resist, a green color resist, and a blue color resist.
  • the display panel when the display panel is a liquid crystal display panel, a VA type (vertical alignment type) liquid crystal display panel is taken as an example for description of the special display panel.
  • the LCD panel can be COA (CF on array) type display panel.
  • the display panel may include: an array substrate, clock signal lines 11-14, GOA units 61-64, connecting lines 31-34, and a color resist layer (not shown in the figure) arranged on one side of the array substrate.
  • the resist layer includes a red color resist, a green color resist, and a blue color resist; a color filter substrate, the first electrode 81 is arranged on one side of the color filter substrate, and the first electrode 81 is a common electrode.
  • the display panel of this embodiment is described by taking a VA type (vertical alignment type) liquid crystal display panel as an example.
  • VA type vertical alignment type
  • the liquid crystal display panel includes: an array substrate, clock signal lines 11-14, GOA units 61-64 and connecting lines 31-34 are arranged on one side of the array substrate; a color film substrate, the first electrode 81 is arranged on the color film substrate On one side of the film substrate, the first electrode 81 is a common electrode.
  • the display panel includes a display area and a non-display area surrounding the display area.
  • the non-display area includes a first frame area 91 and a third frame area 93 disposed oppositely, and a second frame area 92 and a fourth frame area 94 disposed oppositely.
  • the second frame area 92 is connected between the first frame area 91 and the third frame area 93
  • the fourth frame area 94 is connected between the first frame area 91 and the third frame area 93.
  • the display panel includes two groups of multiple GOA units 61 to 64, two groups of multiple clock signal lines 11 to 14 and two groups of multiple connecting wires 31 to 34, two groups of multiple GOA units 61 to 64, two A group of multiple clock signal lines 11-14 and two groups of multiple connecting wires 31-34 are arranged on one side of the array substrate and are respectively located in the first frame area 91 and the third frame area 93.
  • the first electrode 81 includes two sets of openings. 100.
  • the first electrode 81 is a common electrode; the display panel includes common electrode conduction units 102 and 104, the array substrate and the color filter substrate are disposed oppositely, the array substrate includes common wiring, and the common electrode conduction unit 102 is located on the array substrate and the color filter.
  • the common electrode conduction unit 104 is located between the array substrate and the color filter substrate and is located in the fourth frame area 94, and the common electrode conduction units 102, 104 are electrically connected to the common electrode And the common wiring, so that the common signal on the array substrate is conducted to the common electrode through the common wiring and the common electrode conduction unit.
  • the setting method of the common electrode conduction unit includes, but is not limited to, conduction through an Au ball in a seal.
  • the common electrode conduction unit 101 may be located between the array substrate and the color filter substrate and in the first frame area 91, and the common electrode conduction unit 103 is located between the array substrate and the color filter substrate and is located in the first frame area.
  • the common electrode conduction units 101 and 103 are electrically connected to the common electrode and the common wiring, so that the common signal on the array substrate is conducted to the common electrode through the common wiring and the common electrode conduction unit.
  • the setting method of the common electrode conduction unit includes, but is not limited to, conduction through an Au ball in a seal.
  • the common electrode conduction unit 101 may be located between the array substrate and the color filter substrate and located in the first frame area 91, and the common electrode conduction unit 102 is located between the array substrate and the color filter substrate and is located in the first frame area.
  • the common electrode conduction unit 103 is located between the array substrate and the color filter substrate and is located in the third frame area 93, and the common electrode conduction unit 104 is located between the array substrate and the color filter substrate and is located on the fourth frame Within district 94.
  • the common electrode conduction units 101, 102, 103, 104 are electrically connected to the common electrode and the common wiring, so that the common signal on the array substrate is conducted to the common electrode through the common wiring and the common electrode conduction unit.
  • the setting method of the common electrode conduction unit includes, but is not limited to, conduction through an Au ball in a seal.
  • a common electrode conduction unit 101 is provided between the array substrate and the color filter substrate and located in the first frame area 91 at the same time, and a common electrode is provided between the array substrate and the color filter substrate and located in the third frame area 93.
  • the conduction unit 103 preferably, at this time, the common electrode conduction units 101 and 103 are correspondingly arranged on the side of the opening 100 away from the GOA units 61 to 64 in the second direction, and the common electrode conduction units 101 and 103 conduct the openings.
  • the common electrode conduction units 101 and 103 are correspondingly provided on the side of the opening 100 close to the GOA units 61-64 in the second direction, and the common electrode conduction units 101 and 103 conduct the opening 100 in the second direction.
  • the opening 100 is close to and away from the common electrodes on both sides of the GOA units 61-64 and the common wiring on the array substrate in the second direction.
  • the opening 100 is provided to reduce the difference in capacitance between the clock signal line, the connecting line and the first electrode forming the capacitance, thereby reducing the difference in falling time of the incoming GOA unit and the in-plane signal, so as to improve the in-plane
  • the display has problems such as horizontal lines.
  • the display panel is a liquid crystal display panel, especially a VA type (vertical alignment type) liquid crystal display panel
  • the common electrode signal is transmitted through the common electrode conduction unit between the array substrate and the color filter substrate.
  • This application also proposes a display panel, which includes: a first clock signal drive line and a second clock signal drive line, wherein when the second electrode covers the first clock signal drive line and the second clock signal drive line, the first The capacitance value of the capacitance formed by the two electrodes and the first clock signal drive line is greater than the capacitance value of the capacitance formed by the second electrode and the second clock signal drive line;
  • the first GOA unit and the second GOA unit, the first clock signal driving line is connected to the first GOA unit, and the second clock signal driving line is connected to the second GOA unit;
  • the first electrode is provided with an opening, and the area of the part of the opening corresponding to the first clock signal driving line is larger than the area of the part of the opening corresponding to the second clock signal driving line.
  • the present application reduces the difference in the capacitance of the capacitor formed by the clock signal line, the connecting line and the first electrode by providing an opening on the first electrode, and improves the technical problem of horizontal horizontal lines in the in-plane display.
  • the types of display panels include, but are not limited to, liquid crystal display panels, organic light emitting display panels, and quantum dot display panels.
  • the display panel includes: a first clock signal drive line 500, the first clock signal drive line 500 includes a first clock signal line 21 and a first connection line 41; a second clock signal drive line 600.
  • the second clock signal driving line 600 includes a second clock signal line 22 and a second connection line 42; a first GOA unit 71 and a second GOA unit 72; a first connection line 41, and the first connection line 41 is electrically connected to Between the first clock signal line 21 and the first GOA unit 71, the second connection line 42 is electrically connected between the second clock signal line 22 and the second GOA unit 72; the first electrode 81 is provided on the first electrode 81
  • the opening 100 includes sub-openings 101 and 102. It should be noted that “first and second" are only used here to facilitate the description of the technical features of the display panel. It does not mean that the display panel only has the first and second clock signal drive lines, GOA units and other structures. The display panel may include Several clock signal drive lines, several GOA units and other structures are not limited here.
  • the second electrode 82 covers the first clock signal driving line 500 and the second clock signal driving line 600, the second electrode 82 and the second electrode 82
  • the capacitance value of the capacitor formed by a clock signal driving line 500 is greater than the capacitance value of the capacitor formed by the second electrode 82 and the second clock signal driving line 600.
  • the first electrode 81 is provided with an opening 100.
  • the opening 100 includes sub-openings 101 and 102.
  • the area of the sub-opening 101 corresponding to the first clock signal driving line 500 is larger than that of the sub-opening 102 corresponding to the second clock signal driving line. 600 area.
  • the sub-opening 101 of the first electrode 81 is set at the corresponding position of the first clock signal driving line 500, and the sub-opening 102 of the first electrode 81 is set at the second clock signal driving line.
  • Line 600 corresponds to the position.
  • the sub-opening 101 of the first electrode 81 may be arranged at the corresponding position of the first clock signal line 21 or/and the first connecting line 41, and the sub-opening 102 of the first electrode 81 may be arranged at the second clock signal line 22 or / And the corresponding position of the second connecting line 42.
  • only the sub-opening 101 may be provided, and the area of the sub-opening 102 is zero.
  • the arrangement form of the sub-openings 101 and 102 is not limited herein.
  • the method for forming the sub-openings 101 and 102 includes: firstly fabricating the first electrode 81 with a full surface, and then forming the sub-openings 101 and 102 through processes such as exposure and etching.
  • the material of the first electrode 81 includes but is not limited to ITO.
  • the first and second connecting wires and the first and second clock signal wires are of different layers of wire metal and are separated by an insulating layer.
  • the first and second connecting wires are electrically connected to the corresponding first and second clock signal wires through the through holes on the insulating layer.
  • the second clock signal line is not limited to ITO.
  • the first clock signal line 21 and the second clock signal line 22 are made of a first layer of metal
  • the first connection line 41 and the second connection line 42 are made of a second layer of metal.
  • the two layers of metal are separated by an insulating layer.
  • the first connecting line 41 and the second connecting line 42 of the second layer of metal are electrically connected to the first clock signal line 21 and the second corresponding to the first metal through the through holes on the insulating layer.
  • Clock signal line 22 In some embodiments, the first layer of metal and the second layer of metal can be formed and etched in the same process as the metal layer in the display panel.
  • the first layer of metal can be in the same layer as the scan line, and the second layer The metal can be in the same layer as the data line, or the first layer of metal can be in the same layer as the scan line or data line, and the second layer of metal can be in the same layer as the common electrode or the pixel electrode, but it is not limited to these examples.
  • the capacitance value of the capacitance formed by the second electrode and the first clock signal drive line is greater than the capacitance value of the capacitance formed by the second electrode and the second clock signal drive line.
  • the area of the first electrode corresponding to the second clock signal driving line is provided with sub-openings.
  • the area of the sub-opening corresponding to the first clock signal driving line is larger than the area of the sub-opening corresponding to the second clock signal driving line, which reduces the first clock.
  • the signal driving line, the second clock signal driving line and the first electrode form the capacitance difference of the capacitance, thereby reducing the difference in the falling time (signal falling edge time, signal delay) of the incoming GOA unit and the in-plane signal to improve the surface Problems such as horizontal lines appear in the internal display.
  • the first GOA unit 71 and the second GOA unit 72 are arranged along the first direction
  • the first clock signal line 21 and the second clock signal line 22 are arranged along the second direction
  • the first clock signal line 21 is located On the side of the second clock signal line 22 away from the first GOA unit 71 and the second GOA unit 72
  • the first connection line 41 and the second connection line 42 extend in a second direction
  • the second direction is perpendicular to the first direction
  • the second A connection line 41 is electrically connected to the first clock signal line 21 and the first GOA unit 71
  • the second connection line 42 is electrically connected to the second clock signal line 22 and the second GOA unit 72. Since the first clock signal line 21 is located on the side of the second clock signal line 22 away from the first GOA unit 71 and the second GOA unit 72, the length of the first connection line 41 is greater than the length of the second connection line 42.
  • the area of the first clock signal driving line 500 is larger than the area of the second clock signal driving line 600.
  • the first clock signal line 21 or/and the first connection line 41 of the first clock signal driving line 500 has a wider width than the second clock signal line 22 or/and the second connection line 42 of the second clock signal driving line 600 Or/and the length, so that the area of the first clock signal driving line 500 is larger than the area of the second clock signal driving line 600.
  • an opening 100 is provided on the first electrode 81.
  • the opening 100 includes sub-openings 101 and 102.
  • the sub-opening 101 corresponds to the first clock signal driving line 500
  • the sub-opening 102 corresponds to the second clock signal driving line 600.
  • the area of the sub-opening 101 is larger than the area of the sub-opening 102.
  • the area of the first clock signal drive line is larger than the area of the second clock signal drive line, so that the capacitance of the capacitance formed by the second electrode and the first clock signal drive line is greater than that of the second electrode and the second clock signal drive line.
  • the capacitance value of the line forming capacitor is provided by setting sub-openings at the location of the first electrode corresponding to the first clock signal drive line and the location of the first electrode corresponding to the second clock signal drive line.
  • the area of the sub-opening corresponding to the first clock signal drive line is larger than The sub-opening corresponds to the area of the second clock signal driving line, which reduces the difference in capacitance between the first clock signal driving line, the second clock signal driving line and the first electrode, thereby reducing the incoming GOA unit and the in-plane The difference of the falling time of the signal to improve the horizontal line and other problems in the in-plane display.
  • the opening 100 corresponds to the first clock signal line 21 and the second clock signal line 22, and the first connection line 41 and the second connection line 42 are located between the first clock signal line 21 and the second clock signal line 22 Part of the time.
  • the opening 100 is provided with a first electrode 81 on the side far away from the first GOA unit 71 and the second GOA unit 72 in the second direction, and the opening 100 is away from the first GOA unit 71 and the second GOA unit 71 in the second direction.
  • the first electrode 81 may not be provided on one side of the GOA unit 72, which is not limited here.
  • the opening 100 corresponds to the first clock signal line 21 and the second clock signal line 22, the first connection line 41 and the second connection line 42, and the first GOA unit 71 and the second GOA unit 72.
  • the clock signal line, The connection line and the first electrode form the capacitance difference of the capacitance, thereby reducing the falling time difference of the signals that are transmitted to the GOA unit and the in-plane, so as to improve the problem of horizontal horizontal lines in the in-plane display.
  • the types of the display panel may include, but are not limited to, a liquid crystal display panel, an organic light emitting display panel, and a quantum dot display panel.
  • the display panel includes but is not limited to: an array substrate, a first clock signal line 21 and a second clock signal line 22, a first connection line 41 and a second connection line 42, and a first GOA unit 71 and a second GOA unit 72 are arranged on One side of the array substrate; color filter substrate, the first electrode 81 is arranged on one side of the color filter substrate, and the first electrode 81 is a common electrode.
  • a VA type (vertical alignment type) liquid crystal display panel is taken as an example for description of the special display panel.
  • the display panel may include an array substrate.
  • the first clock signal line 21 and the second clock signal line 22, the first connection line 41 and the second connection line 42, and the first GOA unit 71 and the second GOA unit 72 are arranged on the array substrate.
  • One side of the color filter substrate, the first electrode 81, the color resist layer (not shown in the figure) are arranged on one side of the color filter substrate, the first electrode 81 is a common electrode, and the color resist layer includes red color resist, green color resist, Blue color resistance.
  • the special display panel is a VA type (vertical alignment type) liquid crystal display panel for illustration.
  • the LCD panel can be COA (CF on array) type display panel.
  • the display panel may include: an array substrate, a first clock signal line 21 and a second clock signal line 22, a first connection line 41 and a second connection line 42, and a first GOA unit 71 and a second GOA
  • the unit 72 and the color resist layer are arranged on one side of the array substrate, the color resist layer includes red color resist, green color resist, and blue color resist; the color film substrate, the first electrode 81 is arranged on one side of the color film substrate On the side, the first electrode 81 is a common electrode.
  • the display panel of this embodiment is described by taking a VA type (vertical alignment type) liquid crystal display panel as an example.
  • VA type vertical alignment type liquid crystal display panel
  • the liquid crystal display panel includes: an array substrate, a first clock signal driving line 500, a second clock signal driving line 600, a first GOA unit 71, and a second GOA unit 72 are arranged on one side of the array substrate;
  • the film substrate, the first electrode 81 is arranged on one side of the color filter substrate, and the first electrode 81 is a common electrode.
  • the display panel includes a display area and a non-display area surrounding the display area.
  • the non-display area includes a first frame area 91 and a third frame area 93 arranged oppositely, and a second frame area 92 and a fourth frame area 94 arranged oppositely.
  • the second frame area 92 is connected between the first frame area 91 and the third frame area 93
  • the fourth frame area 94 is connected between the first frame area 91 and the third frame area 93.
  • the display panel includes two groups of multiple GOA units 71 ⁇ 72, two groups of multiple clock signal driving lines 500 ⁇ 600, two groups of multiple GOA units 71 ⁇ 72, and two groups of multiple clock signal driving lines 500 ⁇ 600 is disposed on the array substrate and located in the first frame area 91 and the third frame area 93 respectively.
  • the first electrode 81 includes two sets of openings 100, the first electrode 81 is a common electrode; the display panel includes a common electrode conduction unit 102, 104.
  • the array substrate and the color filter substrate are arranged oppositely, the array substrate includes a common wiring, the common electrode conduction unit 102 is located between the array substrate and the color filter substrate and is located in the second frame area 92, and the common electrode conduction unit 104 is located in the array Between the substrate and the color filter substrate and located in the fourth frame area 94, the common electrode conduction units 102, 104 are electrically connected to the common electrode and the common wiring, so that the common signal on the array substrate is conducted through the common wiring and the common electrode.
  • the conduction unit is conducted to the common electrode.
  • the setting method of the common electrode conduction unit includes, but is not limited to, conduction through an Au ball in a seal.
  • the common electrode conduction unit 101 may be located between the array substrate and the color filter substrate and in the first frame area 91, and the common electrode conduction unit 103 is located between the array substrate and the color filter substrate and is located in the first frame area.
  • the common electrode conduction units 101 and 103 are electrically connected to the common electrode and the common wiring, so that the common signal on the array substrate is conducted to the common electrode through the common wiring and the common electrode conduction unit.
  • the setting method of the common electrode conduction unit includes, but is not limited to, conduction through an Au ball in a seal.
  • the common electrode conduction unit 101 may be located between the array substrate and the color filter substrate and located in the first frame area 91, and the common electrode conduction unit 102 is located between the array substrate and the color filter substrate and is located in the first frame area.
  • the common electrode conduction unit 103 is located between the array substrate and the color filter substrate and is located in the third frame area 93, and the common electrode conduction unit 104 is located between the array substrate and the color filter substrate and is located on the fourth frame Within district 94.
  • the common electrode conduction units 101, 102, 103, 104 are electrically connected to the common electrode and the common wiring, so that the common signal on the array substrate is conducted to the common electrode through the common wiring and the common electrode conduction unit.
  • the setting method of the common electrode conduction unit includes, but is not limited to, conduction through an Au ball in a seal.
  • a common electrode conduction unit 101 is provided between the array substrate and the color filter substrate and located in the first frame area 91, and a common electrode conduction unit is provided between the array substrate and the color filter substrate and located in the third frame area 93 103.
  • the common electrode conduction units 101 and 103 are correspondingly arranged on the side of the opening 100 away from the GOA units 71 to 72, and the common electrode conduction units 101 and 103 conduct the opening 100 away from the GOA in the second direction.
  • the common electrodes and common wiring on one side of the units 71-72 are correspondingly arranged on the side of the opening 100 close to the GOA units 71 ⁇ 72, and the common electrode conduction units 101 and 103 are close to the GOA unit 71 ⁇ 72 in the second direction.
  • the common electrode on the side 72 and the common wiring; or, the common electrode conduction units 101 and 103 are correspondingly provided on both sides of the opening 100, and the common electrode conduction units 101 and 103 conduct the opening 100 close to and away from each other in the second direction
  • the opening 100 includes a sub-opening 101 and a sub-opening 102
  • a common electrode conduction unit 101 is provided between the array substrate and the color filter substrate and located in the first frame area 91, and is located between the array substrate and the color filter substrate.
  • a common electrode conduction unit 103 is provided in the third frame area 93, so the common electrode conduction units 101 and 103 can also be provided in the non-openings of the first electrode corresponding to the first clock signal driving line 500 and the second clock signal driving line 600.
  • the openings are provided to reduce the capacitance difference between the clock signal line, the connecting line and the first electrode forming the capacitance, thereby reducing the falling time difference between the incoming GOA unit and the in-plane signal, so as to improve the appearance of the in-plane display. Horizontal lines and other issues.
  • the display panel is a liquid crystal display panel, especially a VA type (vertical alignment type) liquid crystal display panel
  • the common electrode signal is transmitted through the common electrode conduction unit between the array substrate and the color filter substrate.
  • the present application also provides a display device, the display device includes the above-mentioned display panel, and the display device includes but is not limited to a mobile phone, a notebook computer, a television, and the like.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

提供一种显示面板，包括：沿第一方向排列的GOA单元（61~64）；沿第二方向排列的时钟信号线（11~14），时钟信号线（11~14）位于GOA单元（61~64）的一侧；连接线（31~34），连接线（31~34）连接于对应的时钟信号线（11~14）和对应的GOA单元（61~64）之间；第一电极（81），第一电极（81）位于GOA单元（61~64）、时钟信号线（11~14）和连接线（31~34）的一侧，第一电极（81）具有开口（100），开口（100）对应于至少一条时钟信号线（11~14）和/或至少一条连接线（31~34）。

Description

显示面板及显示装置 技术领域
本申请涉及显示面板技术领域，尤其涉及一种显示面板及显示装置。
 背景技术
现今显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)已广泛应用于日常生活中，如手机或电视等。LCD的显示面板为例，其主要是由一薄膜晶体管(Thin Film Transistor，TFT)阵列基板、一彩膜 (Color Filter，CF)基板、以及配置于两基板间的液晶层(Liquid Crystal Layer)所构成。随着TFT性能的提升，直接将栅极电路形成于薄膜晶体管阵列技术 (Gate driver on Array，GOA)目前已经普遍应用于显示面板中。
LCD TV产品目前大量使用GOA技术，实现窄边框或无边框设计，特别是在超高清TV（8K分辨率）产品中尤为考量设计。随着影像品质的提升，GOA电路运用了多颗TFT管子，各管子的沟道长度，源/漏极蚀刻完最终完成值攸关整个电路的运作功能正常与稳定性。但每一级GOA源头信号是来自于GOA的总线（Busline）区。如图1所示，其图示了GOA信号输入结构，其中包括：设于阵列基板一侧的GOA单元61~64、Busline中的时钟信号线11~14、电性连接时钟信号线11~14和对应GOA单元61~64之间的连接线31~34；设置于彩膜基板一侧的第二电极82，第二电极82为常规电极，且常规电极为公共电极，常规的公共电极在彩膜基板上整面设置。第二电极82覆盖住时钟信号线和连接线，由于连接各GOA单元61~64的时钟信号线11~14、连接线31~34的长度/面积不同，导致了各时钟信号线11~14、连接线31~34与第二电极82形成电容的电容值不同，超高分辨率产品对电阻/电容敏感性较高，若传入GOA单元61~64、面内信号的falling time（信号下降沿时间、信号延迟）存在差异，会产生面内显示出现水平横线等问题。
 技术问题
本申请实施例提供一种显示面板及显示装置，以解决现有显示面板中由于时钟信号线、连接线与第二电极形成的电容不同导致的面内显示出现水平横线的技术问题。
 技术解决方案
一种显示面板，其包括：沿第一方向排列的多个GOA单元；沿第二方向排列的多条时钟信号线，多条所述时钟信号线位于多个所述GOA单元的一侧并沿所述第一方向延伸，所述第二方向垂直于所述第一方向；多条连接线，每条所述连接线沿所述第二方向延伸并连接于对应的所述时钟信号线和对应的所述GOA单元之间；第一电极，所述第一电极位于多个所述GOA单元、多条所述时钟信号线和多条所述连接线的一侧，所述第一电极具有开口，所述开口对应于至少一条所述时钟信号线和/或至少一条所述连接线。
一种显示面板，其包括：第一时钟信号驱动线和第二时钟信号驱动线；第一GOA单元和第二GOA单元，所述第一时钟信号驱动线连接于所述第一GOA单元，所述第二时钟信号驱动线连接于所述第二GOA单元；第一电极，所述第一电极设有开口，所述开口对应于所述第一时钟信号驱动线的部分的面积大于所述开口对应于所述第二时钟信号驱动线的部分的面积。
本申请还提出了一种显示装置，其包括显示面板，所述显示面板包括：第一时钟信号驱动线和第二时钟信号驱动线；第一GOA单元和第二GOA单元，所述第一时钟信号驱动线连接于所述第一GOA单元，所述第二时钟信号驱动线连接于所述第二GOA单元；第一电极，所述第一电极设有开口，所述开口对应于所述第一时钟信号驱动线的部分的面积大于所述开口对应于所述第二时钟信号驱动线的部分的面积。
 有益效果
本申请的有益效果为：通过在第一电极上设置开口，从而减小时钟信号线、连接线与第一电极形成电容的电容值的差异，以改善面内显示出现水平横线等问题。
 附图说明
图1为现有技术提供的一种显示面板边框区域的结构示意图；
图2为本申请实施例一提供的显示面板边框区域的第一种结构示意图；
图3为本申请实施例一提供的显示面板边框区域的第二种结构示意图；
图4为本申请实施例二提供的显示面板边框区域的第一种结构示意图；
图5为本申请实施例二提供的显示面板边框区域的第二种结构示意图；
图6为本申请实施例三提供的显示面板边框区域的第一种结构示意图；
图7为本申请实施例三提供的显示面板的边框区域的第二种结构示意图；
图8为本申请实施例四提供的显示面板的边框区域的一种结构示意图；
图9为本申请实施例五/十提供的显示面板的第一种俯视结构示意图；
图10为本申请实施例五/十提供的显示面板的第二种俯视结构示意图；
图11为本申请实施例五/十提供的显示面板的第三种俯视结构示意图；
图12为本申请实施例六/七提供的显示面板的边框区域第一种结构示意图；
图13为本申请实施例六/七提供的显示面板的边框区域第二种结构示意图；
图14为本申请实施例六/七提供的显示面板的边框区域第三种结构示意图；
图15为本申请实施例八提供的显示面板的边框区域一种结构示意图；
图16为本申请实施例九提供的显示面板的边框区域一种结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
本申请实施例提供了一种显示面板，包括：沿第一方向排列的多个GOA单元；沿第二方向排列的多条时钟信号线，多条时钟信号线位于多个GOA单元的一侧并沿第一方向延伸，第二方向垂直于第一方向；多条连接线，每条连接线沿第二方向延伸并连接于对应的时钟信号线和对应的GOA单元之间；第一电极，第一电极位于多个GOA单元、多条时钟信号线和多条连接线的一侧，第一电极具有开口，开口对应于多条时钟信号线，以及多条连接线的位于多条时钟信号线的之间部分。
本申请通过在第一电极上设置开口，减小时钟信号线、连接线与第一电极形成电容的电容值差异，改善了面内显示出现水平横线等技术问题。
下面结合附图和实施例对本申请作进一步说明。
实施例一
请参阅图2~图3，显示面板的类型包括但不限于液晶显示面板、有机发光显示面板、量子点显示面板。显示面板包括：沿第一方向排列的多个GOA单元61~64；沿第二方向排列的多条时钟信号线11~14，多条时钟信号线11~14位于多个GOA单元61~64的一侧并沿第一方向延伸，第二方向垂直于第一方向；多条连接线31~34，每条连接线31~34沿第二方向延伸并连接于对应的时钟信号线11~14和对应的GOA单元61~64之间；第一电极81，第一电极81位于多个GOA单元61~64、多条时钟信号线11~14和多条连接线31~34的一侧，第一电极81具有开口100，开口100对应于至少一条时钟信号线11~14和/或至少一条连接线31~34，包括但不限于：开口100对应于多条时钟信号线11~14，以及多条连接线31~34的位于多条时钟信号线11~14之间的部分。开口对应于至少一条时钟信号线11~14和/或至少一条连接线31~34，是指开口100对应多条时钟信号线11~14中的至少一条，或者开口100对应多条连接线31~34中的至少一条，或者开口100同时对应多条时钟信号线11~14中的至少一条和多条连接线31~34中的至少一条，在此不做限定。同时开口100可以为一个开口、两个或者多个子开口，在此不做限定。在后面说明中以开口100对应于多条时钟信号线11~14、以及多条连接线31~34的位于多条时钟信号线11~14之间的部分来举例说明。需要说明的是，第一电极81位于多个GOA单元61~64、多条时钟信号线11~14和多条连接线31~34的一侧，这里的“一侧”是指第一电极81位于多条时钟信号线11~14所在平面（或多条连接线31~34所在平面、或多个GOA单元61~64所在平面）的一侧，包括但不限于第一电极位于多条时钟信号线11~14所在平面（或多条连接线31~34所在平面、或多个GOA单元61~64所在平面）的上方或者下方。
在图2中，开口100对应于多条时钟信号线11~14，以及多条连接线31~34的位于多条时钟信号线11~14之间的部分，同时开口100在第二方向上远离GOA单元61~64的一侧没有设置第一电极81。在图3中，开口100对应于多条时钟信号线11~14，以及多条连接线31~34的位于多条时钟信号线11~14之间的部分，同时开口100在第二方向上远离GOA单元61~64的一侧设置有第一电极81。
开口100的形成方法包括：先制作整面性的第一电极81，然后通过曝光、刻蚀等工艺形成开口100。第一电极81的制作材料包括但不限于ITO。其中连接线31~34与时钟信号线11~14为不同层导线金属且之间被绝缘层间隔，连接线31~34通过绝缘层上的通孔电性连接对应的时钟信号线11~14。在一些实施例中，时钟信号线11~14用第一层金属制作，连接线31~34用第二层金属制作，第一层金属与第二层金属之间通过绝缘层间隔，第二层金属的连接线31~34通过绝缘层上的通孔电性连接对应的第一层金属的时钟信号线11~14。在一些实施例中，第一层金属、第二层金属可以为与显示面板面内的金属层同工序形成并刻蚀而成，例如：第一层金属可以与扫描线同层、第二层金属可以与数据线同层，或者第一层金属可以与扫描线或者数据线同层、第二层金属可以与公共电极或者像素电极同层，但不限于这些举例。
本实施例中，通过设置开口对应于至少一条时钟信号线和/或至少一条连接线，减小了时钟信号线、连接线与第一电极形成电容的电容值差异，从而减小传入GOA单元、面内信号的falling time（信号下降沿时间、信号延迟）差异，以改善面内显示出现水平横线等问题。
实施例二
本实施例与实施例一相同或相似，不同之处在于：
请参阅图4~图5，显示面板具有第一电极81，第一电极81位于多个GOA单元61~64、多条时钟信号线11~14和多条连接线31~34的一侧，第一电极81具有开口100，开口100对应于多条时钟信号线11~14、多条连接线31~34和多个GOA单元61~64。
本实施例中，通过设置开口100对应于多个时钟信号线、多条连接线和多个GOA单元，减小了时钟信号线、连接线与第一电极形成电容的电容值差异，从而减小传入GOA单元、面内信号的falling time差异，以改善面内显示出现水平横线等问题。
实施例三
本实施例与实施例一~实施例二相同或相似，不同之处在于：
请参阅图6~图7。在图6中，连接线31至连接线34之中，至少两条连接线具有逐渐减小的宽度，以减小连接线31至连接线34的电阻值差异。在图7中，连接线31至连接线34之中，至少两条连接线具有逐渐增加的宽度，以减小连接线31至连接线34与第一电极81形成电容的电容值差异。
进一步的，在本实施中，可以同时设置实施例一~实施例二中的开口100。
在本实施例中，通过开口100与连接线宽度渐变的双重设置，同时减小了时钟信号线、连接线与第一电极形成电容的电容值差异和连接线之间的电阻值差异，从而减小传入GOA单元、面内的信号falling time的差异，以改善面内显示出现水平横线等问题。
实施例四
本实施例与实施例一~实施例三相同或相似，不同之处在于：
请参阅图8，进一步的，为了补偿由于时钟信号线、连接线的长度不同导致的电阻值差异，连接线进行了绕线补偿部的设计。在图8中， GOA单元61~64沿第一方向排列的，时钟信号线11~14沿第二方向排列，时钟信号线11~14位于GOA单元61~64的一侧并沿第一方向延伸，第二方向垂直于第一方向，连接线31~34沿第二方向延伸并连接于对应的时钟信号线11~14和对应的GOA单元61~64之间。时钟信号线11、12、13、14位于GOA单元61~64的一侧并依次靠近GOA单元61~64，连接线31电性连接于时钟信号线11与GOA单元61，连接线32电性连接于时钟信号线12与GOA单元62，连接线33电性连接于时钟信号线13与GOA单元63，连接线34电性连接于时钟信号线14与GOA单元64，连接线31、32、33、34具有逐渐减小的长度，连接线31、32、33、34分别设置补偿绕线长度逐渐增加的补偿部1，可以减小连接线31、32、33、34之间的电阻值差异。进一步的，连接线31、32、33、34分别设置逐渐减小的补偿绕线长度，可以减小时钟信号线11和连接线31、时钟信号线12和连接线32、时钟信号线13和连接线33、时钟信号线14和连接线34之间与第一电极81形成电容的电容值差异。在本实施例中对补偿绕线部数量的限定是：至少两条连接线的绕线补偿部的面积在第一方向上逐渐增加或逐渐减小。
在图8中示意了优选方案中的开口100同时对应了连接线31~34的绕线补偿部1。在一些实施例中，开口100可以不对应连接线31~34的绕线补偿部1，例如开口100设置在图8中连接线31~34的绕线补偿部1远离GOA单元61~64的一侧。
在本实施例中，通过开口与连接线的补偿绕线部的双重设置，同时减小了时钟信号线、连接线与第一电极形成电容的电容值差异和连接线之间的电阻值差异，从而减小传入GOA单元、面内的信号falling time的差异，以改善面内显示出现水平横线等问题。
在实施例一~实施例四中，显示面板的类型可以包括但不限于液晶显示面板、有机发光显示面板、量子点显示面板。显示面板包括但不限于：阵列基板，时钟信号线11~14、GOA单元61~64和连接线31~34设置于阵列基板的一侧；彩膜基板，第一电极81设置于彩膜基板的一侧，第一电极81为公共电极。
在实施例一~实施例四中，当显示面板为液晶显示面板时，特别的显示面板以VA型（垂直配向型）液晶显示面板举例进行说明。显示面板可以包括：阵列基板，时钟信号线11~14、GOA单元61~64和连接线31~34设置于阵列基板的一侧；彩膜基板，第一电极81、色阻层（图未示意）设置于彩膜基板的一侧，第一电极81为公共电极，色阻层包括红色色阻、绿色色阻、蓝色色阻。
在实施例一~实施例四中，当显示面板为液晶显示面板时，特别的显示面板以VA型（垂直配向型）液晶显示面板举例进行说明。此时液晶显示面板可以为COA（CF on array）型显示面板，显示面板可以包括：阵列基板，时钟信号线11~14、GOA单元61~64、连接线31~34、色阻层（图未示意）设置于阵列基板的一侧，色阻层包括红色色阻、绿色色阻、蓝色色阻；彩膜基板，第一电极81设置于彩膜基板的一侧，第一电极81为公共电极。
实施例五
请参阅图9~图11，基于实施例一~实施例四，本实施例的显示面板以VA型（垂直配向型）液晶显示面板举例进行说明。
在此实施例中液晶显示面板包括：阵列基板，时钟信号线11~14、GOA单元61~64和连接线31~34设置于阵列基板的一侧；彩膜基板，第一电极81设置于彩膜基板的一侧，第一电极81为公共电极。显示面板包括显示区和围绕显示区的非显示区，非显示区包括相对设置的第一边框区91和第三边框区93，以及相对设置的第二边框区92和第四边框区94，第二边框区92连接于第一边框区91和第三边框区93之间，第四边框区94连接于第一边框区91和第三边框区93之间。
在图9中，显示面板包括两组多个GOA单元61~64、两组多条时钟信号线11~14和两组多条连接线31~34，两组多个GOA单元61~64、两组多条时钟信号线11~14和两组多条连接线31~34设置在阵列基板的一侧并分别位于第一边框区91和第三边框区93内，第一电极81包括两组开口100，第一电极81为公共电极；显示面板包括公共电极导通单元102、104，阵列基板与彩膜基板相对设置，阵列基板包括公共走线，公共电极导通单元102位于阵列基板和彩膜基板之间并位于第二边框区92内，公共电极导通单元104位于阵列基板和彩膜基板之间并位于第四边框区94内，公共电极导通单元102、104电性连接于公共电极与公共走线，以便阵列基板上的公共信号通过公共走线、公共电极导通单元导通至公共电极上。公共电极导通单元的设置方法包括但不限于：通过框胶（seal）内金球（Au ball）导通。
在图10中，还可以设置公共电极导通单元101位于阵列基板和彩膜基板之间并位于第一边框区91内，公共电极导通单元103位于阵列基板和彩膜基板之间并位于第三边框区93内，公共电极导通单元101、103电性连接于公共电极与公共走线，以便阵列基板上的公共信号通过公共走线、公共电极导通单元导通至公共电极上。公共电极导通单元的设置方法包括但不限于：通过框胶（seal）内金球（Au ball）导通。
在图11中，还可以设置公共电极导通单元101位于阵列基板和彩膜基板之间并位于第一边框区91内，公共电极导通单元102位于阵列基板和彩膜基板之间并位于第二边框区92内，公共电极导通单元103位于阵列基板和彩膜基板之间并位于第三边框区93内，公共电极导通单元104位于阵列基板和彩膜基板之间并位于第四边框区94内。公共电极导通单元101、102、103、104电性连接于公共电极与公共走线，以便阵列基板上的公共信号通过公共走线、公共电极导通单元导通至公共电极上。公共电极导通单元的设置方法包括但不限于：通过框胶（seal）内金球（Au ball）导通。
当两组多个GOA单元61~64、两组多条时钟信号线11~14和两组多条连接线31~34设置在阵列基板上并分别位于第一边框区91和第三边框区93内，同时在阵列基板和彩膜基板之间并位于第一边框区91内设置有公共电极导通单元101、在阵列基板和彩膜基板之间并位于第三边框区93内设置有公共电极导通单元103，优选的，此时公共电极导通单元101、103对应的设于开口100在第二方向上远离GOA单元61~64的一侧，公共电极导通单元101、103导通开口100在第二方向上远离GOA单元61~64一侧的公共电极与阵列基板上的公共走线。但不限于：公共电极导通单元101、103对应的设于开口100在第二方向上靠近GOA单元61~64的一侧，公共电极导通单元101、103导通开口100在第二方向上靠近GOA单元61~64一侧的公共电极与阵列基板上的公共走线；或者，公共电极导通单元101、103对应的设于开口100的两侧，公共电极导通单元101、103导通开口100在第二方向上靠近和远离GOA单元61~64两侧的公共电极与阵列基板上的公共走线。
本实施例中，通过开口100设置减小了时钟信号线、连接线与第一电极形成电容的电容值差异，从而减小传入GOA单元、面内信号的falling time的差异，以改善面内显示出现水平横线等问题。同时提供了当显示面板为液晶显示面板，特别是VA型（垂直配向型）液晶显示面板时，公共电极信号通过阵列基板和彩膜基板之间的公共电极导通单元进行传递的方式。
本申请还提出了一种显示面板，其包括：第一时钟信号驱动线和第二时钟信号驱动线，其中，当第二电极覆盖第一时钟信号驱动线和第二时钟信号驱动线时，第二电极与第一时钟信号驱动线形成电容的电容值大于第二电极与第二时钟信号驱动线形成电容的电容值；
第一GOA单元和第二GOA单元，第一时钟信号驱动线连接于第一GOA单元，第二时钟信号驱动线连接于第二GOA单元；
第一电极，第一电极设有开口，开口对应于第一时钟信号驱动线的部分的面积大于开口对应于第二时钟信号驱动线的部分的面积。
本申请通过在第一电极上设置开口，减小时钟信号线、连接线与第一电极形成电容的电容值的差异，改善了面内显示出现水平横线等技术问题。
实施例六
请参阅图12~图14，显示面板的类型包括但不限于液晶显示面板、有机发光显示面板、量子点显示面板。在图12、图13、图14中，显示面板包括：第一时钟信号驱动线500，第一时钟信号驱动线500包括第一时钟信号线21和第一连接线41；第二时钟信号驱动线600，第二时钟信号驱动线600包括第二时钟信号线22和第二连接线42；第一GOA单元71和第二GOA单元72；第一连接线41，第一连接线41电性连接于第一时钟信号线21和第一GOA单元71之间，第二连接线42电性连接于第二时钟信号线22和第二GOA单元72之间；第一电极81，第一电极81上设置开口100，开口100包括子开口101、102。需要说明的是“第一、第二”在这里仅为方便描述显示面板的技术特征，并不是指显示面板仅仅具有第一、第二条时钟信号驱动线、GOA单元等结构，显示面板可以包括若干个时钟信号驱动线、若干个GOA单元等结构，在此不做限定。
结合图1举例说明，当第二电极82（第二电极82为常规电极，常规电极整面设置）覆盖第一时钟信号驱动线500和第二时钟信号驱动线600时，第二电极82与第一时钟信号驱动线500形成电容的电容值大于第二电极82与第二时钟信号驱动线600形成电容的电容值。
在本实施例中，第一电极81上设置开口100，开口100包括子开口101、102，子开口101对应于第一时钟信号驱动线500的面积大于子开口102对应于第二时钟信号驱动线600的面积。
在图12、图13、图14中，一些实施例中第一电极81的子开口101设置在第一时钟信号驱动线500对应位置，第一电极81的子开口102设置在第二时钟信号驱动线600对应位置。一些实施例中第一电极81的子开口101可以设置在第一时钟信号线21或/和第一连接线41对应位置，第一电极81的子开口102可以设置在第二时钟信号线22或/和第二连接线42对应位置。在一些实施例中，可以只是设置子开口101，子开口102的面积为零。只要满足子开口101对应于第一时钟信号驱动线500的面积大于子开口102对应于第二时钟信号驱动线600的面积，子开口101、102设置形式在此不做限定。
子开口101、102的形成方法包括：先制作整面性的第一电极81，然后通过曝光、刻蚀等工艺形成子开口101、102。第一电极81的制作材料包括但不限于ITO。其中第一、二连接线与第一、第二时钟信号线为不同层导线金属且之间被绝缘层间隔，第一、二连接线通过绝缘层上的通孔电性连接对应的第一、第二时钟信号线。在一些实施例中，第一时钟信号线21和第二时钟信号线22用第一层金属制作，第一连接线41和第二连接线42用第二层金属制作，第一层金属与第二层金属之间通过绝缘层间隔，第二层金属的第一连接线41和第二连接线42通过绝缘层上的通孔电性连接对应第一金属的第一时钟信号线21和第二时钟信号线22。在一些实施例中，第一层金属、第二层金属可以为与显示面板面内的金属层同工序形成并刻蚀而成，例如：第一层金属可以与扫描线同层、第二层金属可以与数据线同层，或者第一层金属可以与扫描线或者数据线同层、第二层金属可以与公共电极或者像素电极同层，但不限于这些举例。
在本实施例中，第二电极与第一时钟信号驱动线形成电容的电容值大于第二电极与第二时钟信号驱动线形成电容的电容值，通过在第一电极对应第一时钟信号驱动线部位、第一电极对应第二时钟信号驱动线部位分别设置子开口，子开口对应于第一时钟信号驱动线的面积大于子开口对应于第二时钟信号驱动线的面积，减小了第一时钟信号驱动线、第二时钟信号驱动线与第一电极形成电容的电容值差异，从而减小传入GOA单元、面内信号的falling time（信号下降沿时间、信号延迟）的差异，以改善面内显示出现水平横线等问题。
实施例七
本实施例与实施例六相同或相似，不同之处在于：
请参阅图12~14，第一GOA单元71和第二GOA单元72沿第一方向排列，第一时钟信号线21和第二时钟信号线22沿第二方向排列且第一时钟信号线21位于第二时钟信号线22的远离第一GOA单元71和第二GOA单元72的一侧，第一连接线41和第二连接线42沿第二方向延伸，第二方向垂直于第一方向，第一连接线41电性连接第一时钟信号线21和第一GOA单元71，第二连接线42电性连接第二时钟信号线22和第二GOA单元72。由于第一时钟信号线21位于第二时钟信号线22的远离第一GOA单元71和第二GOA单元72的一侧，因此第一连接线41的长度大于第二连接线42的长度。
本实施例中第一时钟信号驱动线500的面积大于第二时钟信号驱动线600的面积。第一时钟信号驱动线500的第一时钟信号线21或/和第一连接线41具有比第二时钟信号驱动线600的第二时钟信号线22或/和第二连接线42更宽的宽度或/和长度，使得第一时钟信号驱动线500的面积大于第二时钟信号驱动线600的面积。结合图1举例说明，当第二电极82覆盖第一时钟信号驱动线500和第二时钟信号驱动线600时，由于第一时钟信号驱动线500的面积大于第二时钟信号驱动线600的面积，使得第二电极82与第一时钟信号驱动线500形成电容的电容值大于第二电极82与第二时钟信号驱动线600形成电容的电容值。
在本实施例中，第一电极81上设置开口100，开口100包括子开口101、102，子开口101对应于第一时钟信号驱动线500，子开口102对应于第二时钟信号驱动线600，子开口101的面积大于子开口102的面积。
在本实施例中，第一时钟信号驱动线的面积大于第二时钟信号驱动线的面积，使得第二电极与第一时钟信号驱动线形成电容的电容值大于第二电极与第二时钟信号驱动线形成电容的电容值，通过在第一电极对应第一时钟信号驱动线部位、第一电极对应第二时钟信号驱动线部位分别设置子开口，子开口对应于第一时钟信号驱动线的面积大于子开口对应于第二时钟信号驱动线的面积，减小了第一时钟信号驱动线、第二时钟信号驱动线与第一电极形成电容的电容值差异，从而减小传入GOA单元、面内的信号falling time的差异，以改善面内显示出现水平横线等问题。
实施例八
本实施例与实施例六~实施例七相同或相似，不同之处在于：
请参阅图15，开口100对应于第一时钟信号线21和第二时钟信号线22、以及第一连接线41和第二连接线42位于第一时钟信号线21和第二时钟信号线22之间的部分。在图15中，开口100在第二方向上远离第一GOA单元71、第二GOA单元72的一侧设置有第一电极81，开口100在第二方向上远离第一GOA单元71、第二GOA单元72的一侧还可以不设置有第一电极81，在此不做限定。
本实施例中，通过设置开口对应于第一时钟信号线和第二时钟信号线、以及第一连接线和第二连接线位于第一时钟信号线和第二时钟信号线之间的部分，减小了时钟信号线、连接线与第一电极形成电容的电容值差异，从而减小传入GOA单元、面内信号的falling time的差异，以改善面内显示出现水平横线等问题。
实施例九
本实施例与实施例六~实施例八相同或相似，不同之处在于：
请参阅图16，开口100对应于第一时钟信号线21和第二时钟信号线22、第一连接线41和第二连接线42、以及第一GOA单元71和第二GOA单元72。
本实施例中，通过设置开口对应于第一时钟信号线和第二时钟信号线、第一连接线和第二连接线、以及第一GOA单元和第二GOA单元，减小了时钟信号线、连接线与第一电极形成电容的电容值差异，从而减小传入GOA单元、面内的信号的falling time差异，以改善面内显示出现水平横线等问题。
在实施例六~实施例九中，显示面板的类型可以包括但不限于液晶显示面板、有机发光显示面板、量子点显示面板。显示面板包括但不限于：阵列基板，第一时钟信号线21和第二时钟信号线22、第一连接线41和第二连接线42、以及第一GOA单元71和第二GOA单元72设置于阵列基板的一侧；彩膜基板，第一电极81设置于彩膜基板的一侧，第一电极81为公共电极。
在实施例六~实施例九中，当显示面板为液晶显示面板时，特别的显示面板以VA型（垂直配向型）液晶显示面板举例进行说明。显示面板可以包括：阵列基板，第一时钟信号线21和第二时钟信号线22、第一连接线41和第二连接线42、以及第一GOA单元71和第二GOA单元72设置于阵列基板的一侧；彩膜基板，第一电极81、色阻层（图未示意）设置于彩膜基板的一侧，第一电极81为公共电极，色阻层包括红色色阻、绿色色阻、蓝色色阻。
在实施例六~实施例九中，当显示面板为液晶显示面板时，特别的显示面板为VA型（垂直配向型）液晶显示面板举例进行说明。此时液晶显示面板可以为COA（CF on array）型显示面板，显示面板可以包括：阵列基板，第一时钟信号线21和第二时钟信号线22、第一连接线41和第二连接线42、以及第一GOA单元71和第二GOA单元72、色阻层（图未示意）设置于阵列基板的一侧，色阻层包括红色色阻、绿色色阻、蓝色色阻；彩膜基板，第一电极81设置于彩膜基板的一侧，第一电极81为公共电极。
实施例十
请参阅图9~图11，基于实施例六~实施例九，本实施例的显示面板以VA型（垂直配向型）液晶显示面板举例进行说明。
在此实施例中液晶显示面板包括：阵列基板，第一时钟信号驱动线500、第二时钟信号驱动线600、第一GOA单元71、以及第二GOA单元72设置于阵列基板的一侧；彩膜基板，第一电极81设置于彩膜基板的一侧，第一电极81为公共电极。显示面板包括显示区和围绕显示区的非显示区，非显示区包括相对设置的第一边框区91和第三边框区93，以及相对设置的第二边框区92和第四边框区94，第二边框区92连接于第一边框区91和第三边框区93之间，第四边框区94连接于第一边框区91和第三边框区93之间。
在图9中，显示面板包括两组多个GOA单元71~72、两组多条时钟信号驱动线500~600，两组多个GOA单元71~72、两组多条时钟信号驱动线500~600设置在阵列基板上并分别位于第一边框区91和第三边框区93内，第一电极81包括两组开口100，第一电极81为公共电极；显示面板包括公共电极导通单元102、104，阵列基板与彩膜基板相对设置，阵列基板包括公共走线，公共电极导通单元102位于阵列基板和彩膜基板之间并位于第二边框区92内，公共电极导通单元104位于阵列基板和彩膜基板之间并位于第四边框区94内，公共电极导通单元102、104电性连接于公共电极与公共走线，以便阵列基板上的公共信号通过公共走线、公共电极导通单元导通至公共电极上。公共电极导通单元的设置方法包括但不限于：通过框胶（seal）内金球（Au ball）导通。
在图10中，还可以设置公共电极导通单元101位于阵列基板和彩膜基板之间并位于第一边框区91内，公共电极导通单元103位于阵列基板和彩膜基板之间并位于第三边框区93内，公共电极导通单元101、103电性连接于公共电极与公共走线，以便阵列基板上的公共信号通过公共走线、公共电极导通单元导通至公共电极上。公共电极导通单元的设置方法包括但不限于：通过框胶（seal）内金球（Au ball）导通。
在图11中，还可以设置公共电极导通单元101位于阵列基板和彩膜基板之间并位于第一边框区91内，公共电极导通单元102位于阵列基板和彩膜基板之间并位于第二边框区92内，公共电极导通单元103位于阵列基板和彩膜基板之间并位于第三边框区93内，公共电极导通单元104位于阵列基板和彩膜基板之间并位于第四边框区94内。公共电极导通单元101、102、103、104电性连接于公共电极与公共走线，以便阵列基板上的公共信号通过公共走线、公共电极导通单元导通至公共电极上。公共电极导通单元的设置方法包括但不限于：通过框胶（seal）内金球（Au ball）导通。
在一些实施例中，当两组多个GOA单元71~72、两组多条时钟信号驱动线500~600设置在阵列基板上并分别位于第一边框区91和第三边框区93内，同时在阵列基板和彩膜基板之间并位于第一边框区91内设置有公共电极导通单元101、在阵列基板和彩膜基板之间并位于第三边框区93内设置有公共电极导通单元103，优选的，此时公共电极导通单元101、103对应的设于开口100远离GOA单元71~72的一侧，公共电极导通单元101、103导通开口100在第二方向上远离GOA单元71~72一侧的公共电极与公共走线。但不限于：公共电极导通单元101、103对应的设于开口100靠近GOA单元71~72的一侧，公共电极导通单元101、103导通开口100在第二方向上靠近GOA单元71~72一侧的公共电极与公共走线；或者，公共电极导通单元101、103对应的设于开口100两侧，公共电极导通单元101、103导通开口100在第二方向上靠近和远离GOA单元71~72两侧的公共电极与阵列基板上的公共走线。
在一些实施例中，当两组多个GOA单元71~72、两组多条时钟信号驱动线500~600设置在阵列基板上并分别位于第一边框区91和第三边框区93内，同时开口100包括子开口101、子开口102时，若在阵列基板和彩膜基板之间并位于第一边框区91内有设置公共电极导通单元101、在阵列基板和彩膜基板之间并位于第三边框区93内有设置公共电极导通单元103，那么共电极导通单元101、103也可以设置在第一电极对应第一时钟信号驱动线500和第二时钟信号驱动线600的非开口区。
本实施例中，通过设置开口减小了时钟信号线、连接线与第一电极形成电容的电容值差异，从而减小传入GOA单元、面内信号的falling time差异，以改善面内显示出现水平横线等问题。同时提供了当显示面板为液晶显示面板，特别是VA型（垂直配向型）液晶显示面板时，公共电极信号通过阵列基板和彩膜基板之间的公共电极导通单元进行传递的方式。
基于上述实施例，本申请还提供了一种显示装置，显示装置包括上述显示面板，显示装置包括但不限于手机、笔记本电脑、电视机等。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (18)

  1. 一种显示面板，其包括：
    沿第一方向排列的多个GOA单元；
    沿第二方向排列的多条时钟信号线，多条所述时钟信号线位于多个所述GOA单元的一侧并沿所述第一方向延伸，所述第二方向垂直于所述第一方向；
    多条连接线，每条所述连接线沿所述第二方向延伸并连接于对应的所述时钟信号线和对应的所述GOA单元之间；
    第一电极，所述第一电极位于多个所述GOA单元、多条所述时钟信号线和多条所述连接线的一侧，所述第一电极具有开口，所述开口对应于至少一条所述时钟信号线和/或至少一条所述连接线。
  2. 根据权利要求1所述的显示面板，其中，
    所述开口对应于多条所述时钟信号线、多条所述连接线和多个所述GOA单元。
  3. 根据权利要求1所述的显示面板，其中，
    至少两条所述连接线的宽度在第一方向上逐渐增加或逐渐减小，和/或至少两条所述连接线的绕线补偿部的面积在第一方向上逐渐增加或逐渐减小。
  4. 根据权利要求2所述的显示面板，其中，
    至少两条所述连接线的宽度在第一方向上逐渐增加或逐渐减小，和/或至少两条所述连接线的绕线补偿部的面积在第一方向上逐渐增加或逐渐减小。
  5. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    阵列基板，所述时钟信号线、所述GOA单元和所述连接线设置于阵列基板的一侧；
    彩膜基板，所述第一电极设置于所述彩膜基板的一侧，所述第一电极为公共电极。
  6. 根据权利要求2所述的显示面板，其中，所述显示面板还包括：
    阵列基板，所述时钟信号线、所述GOA单元和所述连接线设置于阵列基板的一侧；
    彩膜基板，所述第一电极设置于所述彩膜基板的一侧，所述第一电极为公共电极。
  7. 根据权利要求5所述的显示面板，其中，
    所述显示面板包括显示区和围绕显示区的非显示区，所述非显示区包括相对设置的第一边框区和第三边框区，以及相对设置的第二边框区和第四边框区，所述第二边框区连接于所述第一边框区和所述第三边框区之间，所述第四边框区连接于所述第一边框区和所述第三边框区之间；
    所述显示面板包括两组所述多个GOA单元、两组所述多条时钟信号线和两组所述多条连接线，两组所述多个GOA单元、两组所述多条时钟信号线和两组所述多条连接线设置在所述阵列基板上并分别位于所述第一边框区和所述第三边框区内，所述第一电极包括两组所述开口；
    所述显示面板包括公共电极导通单元，所述阵列基板与所述彩膜基板相对设置，所述阵列基板包括公共走线，所述公共电极导通单元位于所述阵列基板和所述彩膜基板之间并位于所述第二边框区以及所述第四边框区内，所述公共电极导通单元电性连接于所述公共电极与所述公共走线。
  8. 根据权利要求6所述的显示面板，其中，
    所述显示面板包括显示区和围绕显示区的非显示区，所述非显示区包括相对设置的第一边框区和第三边框区，以及相对设置的第二边框区和第四边框区，所述第二边框区连接于所述第一边框区和所述第三边框区之间，所述第四边框区连接于所述第一边框区和所述第三边框区之间；
    所述显示面板包括两组所述多个GOA单元、两组所述多条时钟信号线和两组所述多条连接线，两组所述多个GOA单元、两组所述多条时钟信号线和两组所述多条连接线设置在所述阵列基板上并分别位于所述第一边框区和所述第三边框区内，所述第一电极包括两组所述开口；
    所述显示面板包括公共电极导通单元，所述阵列基板与所述彩膜基板相对设置，所述阵列基板包括公共走线，所述公共电极导通单元位于所述阵列基板和所述彩膜基板之间并位于所述第二边框区以及所述第四边框区内，所述公共电极导通单元电性连接于所述公共电极与所述公共走线。
  9. 一种显示面板，其包括：
    第一时钟信号驱动线和第二时钟信号驱动线；
    第一GOA单元和第二GOA单元，所述第一时钟信号驱动线连接于所述第一GOA单元，所述第二时钟信号驱动线连接于所述第二GOA单元；
    第一电极，所述第一电极设有开口，所述开口对应于所述第一时钟信号驱动线的部分的面积大于所述开口对应于所述第二时钟信号驱动线的部分的面积。
  10. 根据权利要求9所述的显示面板，其中，
    所述第一时钟信号驱动线的面积大于所述第二时钟信号驱动线的面积。
  11. 根据权利要求10所述的显示面板，其中，
    所述第一时钟信号驱动线包括第一时钟信号线和第一连接线，所述第二时钟信号驱动线包括第二时钟信号线和第二连接线；第一连接线电性连接于第一时钟信号线与第一GOA单元，第二连接线电性连接于第二时钟信号线与第二GOA单元；
    其中，所述第一GOA单元和所述第二GOA单元沿第一方向排列，所述第一时钟信号线和所述第二时钟信号线沿第二方向排列且所述第一时钟信号线位于所述第二时钟信号线的远离所述第一GOA单元和所述第二GOA单元的一侧，所述第一连接线和所述第二连接线沿所述第二方向延伸，所述第二方向垂直于所述第一方向，所述第一连接线的长度大于所述第二连接线的长度；
    所述开口对应于所述第一时钟信号线、所述第二时钟信号线，以及所述第一连接线和所述第二连接线的位于所述第一时钟信号线和所述第二时钟信号线之间的部分。
  12. 根据权利要求11所述的显示面板，其中，
    所述开口对应于所述第一时钟信号线和所述第二时钟信号线、所述第一连接线和所述第二连接线，以及所述第一GOA单元和所述第二GOA单元。
  13. 根据权利要求9所述的显示面板，其包括：
    阵列基板，所述第一时钟信号驱动线和所述第二时钟信号驱动线设置在阵列基板的非显示区；
    彩膜基板，所述第一电极设置于所述彩膜基板的一侧，所述第一电极为公共电极。
  14. 一种显示装置，其包括显示面板，所述显示面板包括：
    第一时钟信号驱动线和第二时钟信号驱动线；
    第一GOA单元和第二GOA单元，所述第一时钟信号驱动线连接于所述第一GOA单元，所述第二时钟信号驱动线连接于所述第二GOA单元；
    第一电极，所述第一电极设有开口，所述开口对应于所述第一时钟信号驱动线的部分的面积大于所述开口对应于所述第二时钟信号驱动线的部分的面积。
  15. 根据权利要求14所述的显示装置，其中，所述第一时钟信号驱动线的面积大于所述第二时钟信号驱动线的面积。
  16. 根据权利要求15所述的显示装置，其中，所述第一时钟信号驱动线包括第一时钟信号线和第一连接线，所述第二时钟信号驱动线包括第二时钟信号线和第二连接线；第一连接线电性连接于第一时钟信号线与第一GOA单元，第二连接线电性连接于第二时钟信号线与第二GOA单元；
    其中，所述第一GOA单元和所述第二GOA单元沿第一方向排列，所述第一时钟信号线和所述第二时钟信号线沿第二方向排列且所述第一时钟信号线位于所述第二时钟信号线的远离所述第一GOA单元和所述第二GOA单元的一侧，所述第一连接线和所述第二连接线沿所述第二方向延伸，所述第二方向垂直于所述第一方向，所述第一连接线的长度大于所述第二连接线的长度；
    所述开口对应于所述第一时钟信号线、所述第二时钟信号线，以及所述第一连接线和所述第二连接线的位于所述第一时钟信号线和所述第二时钟信号线之间的部分。
  17. 根据权利要求16所述的显示装置，其中，所述开口对应于所述第一时钟信号线和所述第二时钟信号线、所述第一连接线和所述第二连接线，以及所述第一GOA单元和所述第二GOA单元。
  18. 根据权利要求14所述的显示装置，其中，所述显示面板包括：
    阵列基板，所述第一时钟信号驱动线和所述第二时钟信号驱动线设置在阵列基板的非显示区；
    彩膜基板，所述第一电极设置于所述彩膜基板的一侧，所述第一电极为公共电极。
PCT/CN2020/086106 2020-03-22 2020-04-22 显示面板及显示装置 WO2021189581A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/770,412 US11694646B2 (en) 2020-03-22 2020-04-22 Display panel having opening in first electrode and display device thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010204838.8 2020-03-22
CN202010204838.8A CN111090202B (zh) 2020-03-22 2020-03-22 显示面板及显示装置

Publications (1)

Publication Number Publication Date
WO2021189581A1 true WO2021189581A1 (zh) 2021-09-30

Family

ID=70400566

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/086106 WO2021189581A1 (zh) 2020-03-22 2020-04-22 显示面板及显示装置

Country Status (3)

Country Link
US (1) US11694646B2 (zh)
CN (1) CN111090202B (zh)
WO (1) WO2021189581A1 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111584500A (zh) * 2020-04-27 2020-08-25 深圳市华星光电半导体显示技术有限公司 一种显示面板
CN111583882A (zh) * 2020-05-21 2020-08-25 深圳市华星光电半导体显示技术有限公司 阵列基板以及显示面板
CN111679520A (zh) * 2020-06-01 2020-09-18 深圳市华星光电半导体显示技术有限公司 显示面板及显示装置
CN115210802A (zh) * 2020-10-30 2022-10-18 京东方科技集团股份有限公司 显示基板及显示装置
CN112433415A (zh) * 2020-12-02 2021-03-02 深圳市华星光电半导体显示技术有限公司 阵列基板、显示面板及电子设备
CN113325637A (zh) 2021-05-31 2021-08-31 Tcl华星光电技术有限公司 显示面板
CN113419366B (zh) * 2021-06-17 2022-10-04 深圳市华星光电半导体显示技术有限公司 一种时钟信号线路、栅极驱动电路及显示面板
CN114141198B (zh) * 2021-12-07 2023-04-21 合肥京东方卓印科技有限公司 扫描驱动电路及其维修方法、显示装置
CN114446255B (zh) * 2022-01-20 2023-02-28 Tcl华星光电技术有限公司 显示面板及显示装置
CN114695389A (zh) * 2022-03-18 2022-07-01 Tcl华星光电技术有限公司 显示面板及显示装置
WO2023230876A1 (zh) * 2022-05-31 2023-12-07 京东方科技集团股份有限公司 触控显示面板、显示装置及其制备方法
CN115202114B (zh) * 2022-07-14 2023-11-28 惠州华星光电显示有限公司 阵列基板及显示面板
CN115616817B (zh) * 2022-10-11 2024-05-14 苏州华星光电技术有限公司 显示面板和电子装置
CN115657378B (zh) * 2022-12-27 2023-04-14 惠科股份有限公司 显示面板及显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103472606A (zh) * 2013-09-27 2013-12-25 京东方科技集团股份有限公司 一种液晶显示面板及显示装置
CN103745707A (zh) * 2013-12-31 2014-04-23 深圳市华星光电技术有限公司 补偿栅极驱动电路信号线阻值的方法及应用该方法的液晶显示面板
US20170287432A1 (en) * 2016-03-29 2017-10-05 Samsung Display Co., Ltd. Display device
CN107978293A (zh) * 2018-01-03 2018-05-01 惠科股份有限公司 一种曲面显示面板及曲面显示面板的制作方法
CN109119039A (zh) * 2018-09-13 2019-01-01 惠科股份有限公司 一种显示面板和显示装置
CN109523963A (zh) * 2018-11-21 2019-03-26 惠科股份有限公司 一种显示装置的驱动电路和显示装置
CN110888277A (zh) * 2018-09-07 2020-03-17 三星显示有限公司 显示设备

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100846464B1 (ko) 2002-05-28 2008-07-17 삼성전자주식회사 비정질실리콘 박막 트랜지스터-액정표시장치 및 그 제조방법
KR100849771B1 (ko) * 2002-05-30 2008-07-31 샤프 가부시키가이샤 액정 표시 장치용 기판 및 그것을 구비한 액정 표시 장치및 그 제조 방법
CN100423275C (zh) * 2006-10-27 2008-10-01 北京京东方光电科技有限公司 Tft lcd阵列基板***走线结构及其制造方法
SG11201406630YA (en) * 2012-04-20 2015-01-29 Sharp Kk Display device
CN104810002B (zh) 2015-05-19 2017-12-05 武汉华星光电技术有限公司 一种显示装置
KR102436255B1 (ko) * 2015-12-30 2022-08-26 삼성디스플레이 주식회사 표시 장치
KR102585124B1 (ko) * 2016-04-20 2023-10-05 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
CN108806573B (zh) * 2017-04-27 2021-11-23 乐金显示有限公司 显示装置
KR20200119954A (ko) * 2019-04-10 2020-10-21 삼성디스플레이 주식회사 게이트 구동부 및 이를 포함하는 표시 장치
KR102670900B1 (ko) * 2019-08-27 2024-05-30 삼성디스플레이 주식회사 표시 장치

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103472606A (zh) * 2013-09-27 2013-12-25 京东方科技集团股份有限公司 一种液晶显示面板及显示装置
CN103745707A (zh) * 2013-12-31 2014-04-23 深圳市华星光电技术有限公司 补偿栅极驱动电路信号线阻值的方法及应用该方法的液晶显示面板
US20170287432A1 (en) * 2016-03-29 2017-10-05 Samsung Display Co., Ltd. Display device
CN107978293A (zh) * 2018-01-03 2018-05-01 惠科股份有限公司 一种曲面显示面板及曲面显示面板的制作方法
CN110888277A (zh) * 2018-09-07 2020-03-17 三星显示有限公司 显示设备
CN109119039A (zh) * 2018-09-13 2019-01-01 惠科股份有限公司 一种显示面板和显示装置
CN109523963A (zh) * 2018-11-21 2019-03-26 惠科股份有限公司 一种显示装置的驱动电路和显示装置

Also Published As

Publication number Publication date
CN111090202B (zh) 2020-09-01
CN111090202A (zh) 2020-05-01
US20220114980A1 (en) 2022-04-14
US11694646B2 (en) 2023-07-04

Similar Documents

Publication Publication Date Title
WO2021189581A1 (zh) 显示面板及显示装置
WO2019223607A1 (zh) 液晶显示基板及显示装置
US10192893B2 (en) Array substrate and display device
WO2016086539A1 (zh) 液晶面板及其制作方法
WO2021208643A1 (zh) 显示面板及显示装置
US9791733B2 (en) Array substrate, manufacture method thereof, and display device
WO2013086746A1 (zh) 液晶显示面板以及其制造方式
WO2022193337A1 (zh) 阵列基板及显示面板
US9335587B2 (en) Liquid crystal cell and method for manufacturing the same
US20230097478A1 (en) Array substrate, method for fabricating same, and display panel
JP2012242497A (ja) 液晶表示装置
WO2022156131A1 (zh) 阵列基板、阵列基板的制作方法以及显示面板
US11372297B2 (en) Display panel
KR101307555B1 (ko) 평판 표시장치 제조 방법
WO2020124896A1 (zh) 液晶显示面板
TW201411851A (zh) 顯示面板及顯示裝置
WO2023088168A1 (zh) 阵列基板、显示面板及其制作方法
WO2021232556A1 (zh) 显示面板及电子装置
WO2018205524A1 (zh) 一种阵列基板及其制作方法、显示装置
US10985193B2 (en) Display panel
JP2012098329A (ja) 液晶表示装置
WO2021082213A1 (zh) 液晶显示面板及液晶显示装置
WO2021174975A1 (zh) 一种显示面板及装置
WO2021189573A1 (zh) 阵列基板及显示面板
WO2020237731A1 (zh) 阵列基板及其制作方法与显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20926549

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20926549

Country of ref document: EP

Kind code of ref document: A1