WO2021184166A1 - 电子设备、芯片封装结构及其制作方法 - Google Patents
电子设备、芯片封装结构及其制作方法 Download PDFInfo
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- WO2021184166A1 WO2021184166A1 PCT/CN2020/079518 CN2020079518W WO2021184166A1 WO 2021184166 A1 WO2021184166 A1 WO 2021184166A1 CN 2020079518 W CN2020079518 W CN 2020079518W WO 2021184166 A1 WO2021184166 A1 WO 2021184166A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- This application relates to the field of integrated circuit packaging technology, and in particular to an electronic device, a chip packaging structure and a manufacturing method thereof.
- Flip chip is not only a chip interconnection technology, but also an ideal chip bonding technology. It has now become a packaging form often used in the field of high-end devices and high-density packaging. With the widespread application of flip-chips, the power density of the chips is also increasing, and a packaging structure formed by stacking multiple chips has also appeared, which puts forward higher requirements for the heat dissipation of the chips.
- the existing flip-chip packaging structure mainly includes electrical connectors such as chips and copper pillars and a substrate.
- the electrical connectors are located between the chip and the substrate, and the two ends are electrically connected to the chip and the substrate, so as to realize the connection between the chip and the substrate.
- the gaps of the package structure formed by the chip, electrical connectors and the substrate are filled with underfill (UF) to reduce the gap between the substrate and the chip caused by the mismatch of thermal expansion coefficients.
- UF underfill
- the existing underfill has limited heat dissipation performance, which severely restricts the integration and power consumption of the chip, and when the underfill with higher thermal conductivity is used, it will cause leakage of electrical connections, affecting the chip and substrate.
- the present application provides an electronic device, a chip packaging structure and a manufacturing method thereof. While ensuring the heat dissipation efficiency of the chip packaging structure, it prevents the electrical connections in the chip packaging structure from leaking to the outside, and ensures the transfer of the chip and the substrate. Stability of electrical conduction between connecting plates.
- an embodiment of the present application provides a chip packaging structure, including: a first chip, an adapter board, and at least one electrical connector between the first chip and the adapter board, the electrical connection Two ends of the component are respectively electrically connected to the first chip and the adapter board;
- It also includes: a high thermal conductivity medium located between the first chip and the adapter board and surrounding the outer periphery of the electrical connector, one end of the high thermal conductivity medium is in contact with the first chip, and the high thermal conductivity An insulating layer is arranged between the thermally conductive medium and the electrical connector, and the insulating layer is used to separate the high thermally conductive medium from the electrical connector.
- the heat on the first chip and the electrical connector can be effective
- the heat is diffused to the high thermal conductivity medium, and the heat is released to the external environment through the high thermal conductivity medium, which effectively improves the heat dissipation efficiency of the first chip and the electrical connectors, thereby improving the integration and power consumption of the chip.
- the high thermal conductivity medium and the electrical connector are separated by an insulating layer to prevent the current on the electrical connector from spreading to the high thermal conductivity medium and cause leakage, thus not only ensuring the connection between the first chip and the transfer board Conduction stability, and will not cause electrical signal interference to components outside the chip package structure.
- the insulating layer is wrapped on at least part of the side wall of the electrical connector, and the high thermal conductivity medium is wrapped on the surface of the insulating layer away from the electrical connector
- the high thermal conductivity medium is wrapped on the surface of the insulating layer away from the electrical connector
- the high thermal conductivity medium filled between two adjacent connectors can simultaneously dissipate the electrical connectors on both sides, thereby effectively improving the heat dissipation efficiency of the high thermal conductivity medium to each electrical connector.
- the high thermal conductivity medium filled between the adjacent electrical connectors also supports the two electrical connectors and the first chip, so that the electrical connectors can be more stably supported on the first chip and the adapter board. In this way, the conduction between the first chip and the adapter board is ensured.
- the high thermal conductivity medium located between two adjacent electrical connectors and any one of the electrical connectors are separated by an insulating layer, so that the adjacent electrical connectors will not be affected by the conductivity of the high thermal conductivity medium.
- the occurrence of a short circuit further ensures the normal conduction of each electrical connector to the electrical signal.
- the first end of the insulating layer extends to an end of the electrical connection member close to the first chip, and the second end of the insulating layer extends to the end of the There is a preset spacing between the adapter plates. In this way, while ensuring the coverage area of the insulating layer on the surface of the electrical connector, the part of the electrical connector close to the end of the adapter board is exposed, so that the electrical connector is welded on the adapter board. The end can be effectively wetted and spread, so as to further ensure the welding stability between the electrical connector and the adapter plate.
- the distance between the end of the high thermal conductivity medium facing the adapter plate and the adapter plate is greater than or equal to the second end of the insulating layer and the adapter plate.
- the distance between the plates, in other words, the end of the high thermal conductivity medium close to the adapter plate can extend to be flush with the second end of the insulating layer, or it can be higher than the second end of the insulating layer.
- the high thermal conductivity medium on the outer periphery of the insulating layer has a heat dissipation effect on the electrical connector and the first chip, it effectively prevents the high thermal conductivity medium from extending out of the second end of the insulating layer and contacting the electrical connector on the side of the insulating layer. This further prevents the electrical connector from leaking, and when the high thermal conductivity medium is filled in the space between the adjacent electrical connectors, it also avoids the short circuit between the adjacent electrical connectors due to the current conduction of the high thermal conductivity medium. .
- the chip packaging structure further includes an underfill, and the thermal conductivity of the underfill is smaller than the thermal conductivity of the high thermal conductivity medium;
- the underfill is filled between the insulating layer and the adapter plate and between the high thermal conductivity medium and the adapter plate.
- the bottom of the insulating layer and the high thermal conductivity medium is supported, thereby reducing thermal expansion
- the stress between the transfer board and the first chip caused by the mismatch of the coefficients improves the welding reliability between the electrical connector and the transfer board and the structural stability of the insulating layer and the high thermal conductivity medium.
- the thermal conductivity is small, so it will not have electrical conductivity, so it will not cause leakage or short circuit of the electrical connection.
- the electrical connector is any one of micro bumps or controllable collapse bumps.
- the electrical connector includes: a copper pillar and a tin bump electrically connected to the copper pillar, one end of the copper pillar is electrically connected to the first chip,
- the tin bumps are arranged between the copper pillar and the transfer board and are electrically connected to the transfer board; the second end of the insulating layer extends to the end of the copper pillar close to the transfer board; Part of the underfill material extends to contact the outer side surface of the tin bump.
- the diffusion process of the tin bumps during soldering with the interposer board is prevented from being hindered by the insulating layer and affecting the tin bumps and the interposer.
- the soldering stability of the transfer board is provided.
- the structural stability of the tin bumps in the packaged chip structure is further improved, thereby further ensuring the solder bumps and the transfer Reliability of the electrical connection of the board.
- the high thermal conductivity medium includes one or more of the following materials: solder, silver paste, graphene, and alumina particles. All of the above materials can improve the heat dissipation efficiency of the first chip and the electrical connector in the chip packaging structure.
- the high thermal conductivity medium is formed by stacking nanowires or nanoparticles; and the gaps between the nanowires or the nanoparticles are filled with an oxidizing medium to enhance The bonding strength between the individual nanowires or between the nanoparticles, thereby enhancing the structural stability of the high thermal conductivity medium formed by the nanowires or nanoparticle stacks, thereby ensuring the thermal conductivity of the nano thermal conductivity medium, and improving its impact on the first chip. And the structural support effect of each electrical connector.
- the insulating layer is a copper oxide layer; or, the insulating layer is a tin oxide layer; or, the insulating layer is a dry film or passivation made of an insulating material Floor.
- the insulating layer is a tin oxide layer, and a barrier layer is provided between the tin oxide layer and the outer sidewall of the electrical connector.
- the tin oxide insulating layer is made by first immersing tin on the surface of the electrical connector, and then oxidizing it to tin oxide.
- a barrier layer is provided on the surface of the electrical connector to prevent tin from getting into the electrical connector.
- the metal such as copper, over-reacts to generate intermetallic compounds that are unfavorable to the mechanical structure and electrical properties of the electrical connector, thereby further ensuring the structural stability of the electrical connector and the stable conduction between the first chip and the adapter board.
- the barrier layer is a film layer made of Ni, Ti, W, and TaN.
- the film layer made of Ni, Ti, W, and TaN can achieve the barrier between tin and the metal compound in the electrical connector, so as to ensure the smooth growth of tin oxide.
- a mounting hole is opened on the adapter plate, a ground connection point or a power connection point is provided in the mounting hole, and at least part of the second end of the high thermal conductivity medium It is in contact with the ground connection point or the power connection point.
- a metal pad is provided on the adapter board, one end of the metal pad extends into the mounting hole and is connected to the ground connection point or the power supply Point contact, the other end of the metal pad is in contact with the high thermal conductivity medium.
- the interposer board is a second chip; or, the interposer board is a substrate. That is to say, the chip packaging structure can be mounted on the circuit board and other components through the second chip or substrate to realize the conduction between the first chip and the circuit board and other components.
- an embodiment of the present application provides an electronic device, including any one of the above-mentioned chip packaging structures.
- the chip packaging structure has a good heat dissipation effect
- a highly integrated chip packaging structure can be provided in the electronic device. This way, while enhancing the function of the electronic device, the chip packaging structure is reduced in size.
- the occupied size of the electronic device will not only provide effective space for the installation of other components in the electronic device, but also reduce the size of the entire electronic device and optimize the experience effect of the electronic device. At the same time, the stability of the signal transmission in the electronic equipment is also ensured, and the normal operation of the electronic equipment is ensured.
- an embodiment of the present application provides a manufacturing method of a chip packaging structure, the method including:
- At least one electrical connector is prepared on one side of the first chip, and the electrical connector is electrically connected to the first chip;
- a high thermal conductivity medium is provided on the side of the first chip with the electrical connection member, the high thermal conductivity medium is arranged around the outer periphery of the electrical connection member, and the insulating layer connects the high thermal conductivity medium and the Separate electrical connections;
- An adapter board is provided, and the adapter board is electrically connected with an end of the electrical connector away from the first chip to form a chip packaging structure.
- the heat on the first chip and the electrical connector can be effectively diffused to the high thermal conductivity medium, and then The high thermal conductivity medium releases heat to the external environment, which effectively improves the heat dissipation efficiency of the first chip and the electrical connectors, thereby providing a good heat dissipation basis for improving the integration and power consumption of the chip.
- the high thermal conductivity medium and the electrical connector are separated by an insulating layer to prevent the current on the electrical connector from spreading to the high thermal conductivity medium and cause leakage, thus not only ensuring the connection between the first chip and the transfer board Conduction stability, and will not cause electrical signal interference to components outside the chip package structure.
- the outer periphery of the electrical connector is filled with a high thermal conductivity medium, which makes the filling process of the high thermal conductivity medium simpler and faster, and can ensure the uniformity of the filling at the same time , Reduce the difficulty of process production, effectively improve the production efficiency and product quality.
- an embodiment of the present application provides a manufacturing method of a chip packaging structure, and the method includes:
- At least one electrical connector is prepared on one side of the first chip, and the electrical connector is electrically connected to the first chip;
- An adapter board is provided, and the adapter board is electrically connected to an end of the electrical connector away from the first chip;
- the heat on the first chip and the electrical connector can be effectively diffused to the high thermal conductivity medium, and then The high thermal conductivity medium releases heat to the external environment, which effectively improves the heat dissipation efficiency of the first chip and the electrical connectors, thereby providing a good heat dissipation basis for improving the integration and power consumption of the chip.
- the high thermal conductivity medium and the electrical connector are separated by an insulating layer to prevent the current on the electrical connector from spreading to the high thermal conductivity medium and cause leakage, thus not only ensuring the connection between the first chip and the transfer board Conduction stability, and will not cause electrical signal interference to components outside the chip package structure.
- the fourth aspect of the embodiments of the present application may first weld the adapter plate to the end of the electrical connector away from the first chip, and then fill the high thermal conductivity medium, that is, the present application There is no high requirement on the process sequence, as long as the final chip packaging structure can meet the requirements.
- the forming an insulating layer on the outer sidewall of the electrical connector includes:
- the outer sidewall of the electrical connection member is oxidized to form an oxide layer on the outer sidewall of the electrical connection member, and the oxide layer serves as the insulating layer.
- the forming an insulating layer on the outer sidewall of the electrical connector includes:
- the tin layer is oxidized to form a tin oxide layer, and the tin oxide layer serves as the insulating layer.
- the tin oxide layer is used as the insulating layer to improve the insulating performance of the insulating layer, and to ensure that the electrical connectors will not leak or short-circuit.
- the method before immersing the outer side wall of the electrical connector with tin, the method further includes:
- the dipping the outer side wall of the electrical connection member with tin to form a tin layer on the outer side wall of the electrical connection member includes:
- the barrier layer on the outer side wall of the electrical connection member is immersed in tin, and the tin layer is formed on the barrier layer.
- a barrier layer is formed before tin immersion on the outer side wall of the electrical connector, and tin immersion is performed on the barrier layer to avoid the rapid combination of tin and copper and other metals on the surface of the electrical connector to generate a mechanical structure for the electrical connector and Intermetallic compounds with unfavorable electrical properties.
- the forming an insulating layer on the outer sidewall of the electrical connection member includes: pasting an insulating dry film or An insulating passivation layer, the insulating dry film or the insulating passivation layer is used as the insulating layer to simplify the manufacturing process of the insulating layer.
- the high thermal conductivity medium is a nano material; the high thermal conductivity medium is arranged behind the outer periphery of the electrical connector, and further includes: The gaps between the materials are filled with an oxidizing medium.
- thermal conductivity of the thermal conductive medium also improves its structural support effect on the first chip and each electrical connector.
- preparing at least one electrical connector on one side of the first chip includes:
- At least one copper pillar is prepared on one side of the first chip
- An end of the copper pillar facing the adapter board forms a tin bump electrically connected to the copper pillar;
- the electrical connection between the adapter board and the end of the electrical connector away from the first chip includes:
- the transfer board is electrically connected to an end of the tin bump facing away from the first chip.
- the third aspect or the fourth aspect there is a gap between the end of the insulating layer facing the adapter plate and the adapter plate, and the high thermal conductivity medium faces the adapter plate
- the distance between one end of and the adapter board is greater than or equal to the distance from the insulating layer to the adapter board;
- the method further includes:
- the end of the insulating layer facing the adapter board and the adapter board are spaced apart so that the part of the electrical connector near the adapter board is exposed, ensuring that the end of the electrical connector near the adapter board is in contact with the adapter board. During welding, wetting and stretching can be carried out smoothly, thereby further ensuring the stability of the electrical connection between the electrical connector and the adapter plate.
- the end of the high thermal conductivity medium close to the adapter plate can extend to be flush with the second end of the insulating layer, or higher than the second end of the insulating layer, so that the high thermal conductivity medium surrounding the outer circumference of the insulating layer While the heat dissipation effect on the electrical connector and the first chip, it effectively prevents the high thermal conductivity medium from extending out of the second end of the insulating layer and contacting the electrical connector on the side of the insulating layer, thereby further preventing leakage of the electrical connector And when the high thermal conductivity medium is filled in the space between the adjacent electrical connectors, it also avoids the short circuit between the adjacent electrical connectors due to the current conduction of the high thermal conductivity medium.
- the underfill between the insulating layer and the transfer plate and between the high thermal conductivity medium and the transfer plate With a higher thermal conductivity and a small thermal conductivity medium, the bottom of the insulating layer and the high thermal conductivity medium is supported, thereby reducing thermal expansion
- the stress between the transfer board and the first chip caused by the mismatch of the coefficients improves the welding reliability between the electrical connector and the transfer board and the structural stability of the insulating layer and the high thermal conductivity medium.
- the thermal conductivity is small, so it will not have electrical conductivity, so it will not cause leakage or short circuit of the electrical connection.
- the method before the adapter board is electrically connected to an end of the electrical connector away from the first chip, the method further includes:
- a metal pad is formed on the side of the interposer board facing the first chip, one end of the metal pad is electrically connected to the ground connection point or the power connection point on the interposer board, and the metal pad The other end is used to contact the high thermal conductivity medium when the adapter plate is connected to the electrical connector.
- FIG. 1a is a schematic diagram of a first structure of a chip packaging structure provided by an embodiment of this application;
- FIG. 1b is a schematic diagram of the second structure of the chip packaging structure provided by an embodiment of the application.
- FIG. 2 is a schematic diagram of a third structure of the chip packaging structure provided by Embodiment 1 of the application;
- FIG. 3 is a schematic diagram of a fourth structure of a chip packaging structure provided by an embodiment of the application.
- FIG. 4 is a schematic diagram of a fifth structure of the chip packaging structure provided by an embodiment of the application.
- FIG. 5a is a schematic structural diagram of a first chip in the first manufacturing method of the chip packaging structure provided by Embodiment 1 of the application;
- FIG. 5a is a schematic structural diagram of a first chip in the first manufacturing method of the chip packaging structure provided by Embodiment 1 of the application;
- FIG. 5b is a schematic structural diagram of manufacturing electrical connectors on the surface of the first chip in the first manufacturing method of the chip packaging structure provided in the first embodiment of the application;
- FIG. 5c is a schematic structural diagram of forming an insulating layer on the outer sidewall of the electrical connector in the first manufacturing method of the chip packaging structure provided in the first embodiment of the application;
- FIG. 5d is a schematic structural diagram of the first method of manufacturing the chip packaging structure provided by the first embodiment of the application after the adapter board is electrically connected to the end of the electrical connector away from the first chip;
- FIG. 5e is a schematic structural diagram of filling the outer periphery of the electrical connector with a high thermal conductivity medium in the first manufacturing method of the chip packaging structure provided in the first embodiment of the application;
- FIG. 6a is a schematic structural diagram of a first chip in a second manufacturing method of a chip packaging structure provided by Embodiment 1 of the application;
- FIG. 6a is a schematic structural diagram of a first chip in a second manufacturing method of a chip packaging structure provided by Embodiment 1 of the application;
- FIG. 6b is a schematic structural diagram of fabricating electrical connectors on the surface of the first chip in the second method for fabricating the chip packaging structure provided by Embodiment 1 of the application;
- FIG. 6b is a schematic structural diagram of fabricating electrical connectors on the surface of the first chip in the second method for fabricating the chip packaging structure provided by Embodiment 1 of the application;
- FIG. 6c is a schematic structural diagram of forming an insulating layer on the outer sidewall of the electrical connector in the second manufacturing method of the chip package structure provided in the first embodiment of the application;
- FIG. 6d is a schematic structural diagram of filling the outer periphery of the electrical connector with a high thermal conductivity medium in the second manufacturing method of the chip packaging structure provided in the first embodiment of the application;
- 6e is a schematic structural diagram of the second manufacturing method of the chip packaging structure provided in the first embodiment of the application after the adapter board is electrically connected to the end of the electrical connector away from the first chip;
- FIG. 7 is a schematic diagram of a sixth structure of a chip packaging structure provided by an embodiment of the application.
- FIG. 8 is a schematic diagram of a seventh structure of a chip packaging structure provided by an embodiment of the application.
- FIG. 9 is a schematic diagram of the eighth structure of the chip packaging structure provided by an embodiment of the application.
- the chip is the most core part of electronic equipment, which has the function of logic processing and control of the normal operation of the whole machine.
- the chip In electronic equipment, the chip is mainly fixed on the circuit board in the form of chip packaging structure to achieve stability. The purpose of controlling the stable conduction between the chip inside the chip packaging structure and the external circuit board.
- Flip chip (Flip Chip) is not only a chip interconnection technology, but also an ideal chip bonding technology. It has now become a packaging form often used in the field of high-end devices and high-density packaging.
- the integration of chips in the flip-chip packaging structure needs to be further improved, that is, the connection points on the chip in the flip-chip packaging structure, that is, the number of pins or stacks of chips need to increase. It is satisfied that the electronic device has more abundant functions without increasing the structure size, and at the same time, the power consumption of the flip-chip package structure also increases. In order to meet the requirements of high integration and high power consumption of the flip-chip packaging structure, it is necessary to make the heat dissipation efficiency of the chip packaging structure better.
- the flip-chip package structure mainly includes electrical connectors such as chips and copper pillars, and a substrate.
- the electrical connectors are located between the chip and the substrate, and both ends are electrically connected to the chip and the substrate to realize the chip and the substrate.
- the electrical signals are connected between, and the electrical connection points on the substrate are electrically connected to the circuit board, so as to realize the conduction between the chip and the circuit board in the flip-chip package structure.
- the gaps in the package structure formed by the chip, the electrical connection and the substrate are filled with underfill (UF) to reduce the stress between the substrate and the chip caused by the mismatch of the thermal expansion coefficient, thereby improving the electrical connection The reliability of the electrical connection with the substrate.
- UF underfill
- the underfill can be composed of epoxy resin and silicon dioxide, and its heat dissipation performance is low, and cannot meet the high integration and high power consumption chip packaging structure. Therefore, it will affect the integration and power consumption density of the chip in the chip packaging structure. This causes serious constraints, and thus cannot increase the function of the electronic device on the basis of saving the internal space of the electronic device.
- fillers with higher heat dissipation performance are used to fill the gaps of the chip packaging structure to improve the heat dissipation effect of the chip.
- the present application provides an electronic device, a chip packaging structure and a manufacturing method thereof, by providing a high thermal conductivity medium on the outer circumference of the electrical connector, and providing an insulating layer between the high thermal conductivity medium and the outer side wall of the electrical connector to While ensuring the heat dissipation effect of the chip, the leakage of electrical connections is prevented, thereby ensuring the stability of signal conduction between the chip and the transfer board such as the substrate.
- the following takes different scenarios as examples to introduce the specific structure of the chip packaging structure.
- FIG. 1a is a schematic diagram of the first structure of a chip packaging structure provided by an embodiment of the application
- FIG. 1b is a schematic diagram of a second structure of the chip packaging structure provided by an embodiment of the application
- FIG. 2 is a schematic diagram of the first embodiment of the application
- FIG. 3 is a fourth structural schematic diagram of a chip packaging structure provided by an embodiment of this application
- FIG. 4 is a fifth structural schematic diagram of a chip packaging structure provided by an embodiment of this application.
- the present application provides a chip packaging structure, including a first chip 10, an adapter board 20, and at least one electrical connector 30 between the first chip 10 and the adapter board 20. Two ends of the connecting member 30 are electrically connected to the first chip 10 and the adapter board 20 respectively, so as to realize the conduction of electrical signals between the first chip 10 and the adapter board 20.
- the first chip 10 may be any chip structure in the prior art, and the embodiment of the present application does not limit the specific type or structure of the first chip 10, as long as it can implement certain logic processing or control functions.
- the interposer board 20 of the embodiment of the present application specifically functions to realize the conduction between the first chip 10 and the external circuit board, and to carry the first chip 10, and the package structure formed by the first chip 10 is stable.
- the interposer 20 may be a substrate (Substrate), a redistribution layer (RDL), a silicon substrate (also referred to as an interposer in English), etc. in a common sense.
- the chip packaging structure of the present application is fixed on the circuit board of the electronic device through the adapter board 20, and the electrical connection points (metal pads) on the adapter board 20 are corresponding to the electrical connection points (metal pads) on the circuit board.
- the electrical connection realizes the conduction between the first chip 10 and the external circuit board, thereby ensuring that the external circuit board provides a stable current to the first chip 10, and at the same time realizing signal transmission between the first chip 10 and the external circuit board.
- the adapter board 20 may also be one or more chips.
- the first chip described in the embodiment of the present invention may be a die, or may be a package structure formed by encapsulating one or more dies together.
- the substrate provides the pins of the first chip 10 to be rearranged in a larger plane range, so as to realize the functions of multiple pins and rearrangement of the pin positions.
- the first chip 10 can be accurately connected to the connection points corresponding to the external circuit board, that is, the substrate serves to amplify the connection points of the first chip 10
- the size makes the connection between the first chip 10 and the external circuit board more accurate and faster.
- the adapter board 20 is a chip, in order to distinguish it from the above-mentioned first chip 10, the chip used to carry the first chip 10 is called a second chip, and the second chip implements the first chip 10 and the external circuit board.
- the conduction of the chip package structure and the external external circuit board are realized at the same time.
- the distribution position and number of the connection points of the second chip can be consistent with the substrate to ensure that the second chip can well realize the electrical connection with the corresponding electrical connector 20 and the external circuit board.
- the embodiment of the present application further includes a high thermal conductivity medium 40 located between the first chip 10 and the adapter board 20, the high thermal conductivity medium 40 is surrounded by the outer periphery of the electrical connector 30, and the high thermal conductivity medium 40
- One end of the first chip 10 is in contact with the first chip 10, specifically with the surface of the first chip 10 facing the adapter board 20, so that the heat on the first chip 10 is effectively conducted to the high thermal conductivity medium 40, and then the high thermal conductivity medium 40 quickly transfers heat to the outside, so as to realize the effective heat dissipation of the first chip 10 by the high thermal conductivity medium 40.
- the high thermal conductivity medium 40 is also located on the outer periphery of the electrical connector 30, so as to achieve an effective effect on the electrical connector 30. Heat dissipation.
- the high thermal conductivity medium 40 also functions to support the first chip 10 and the electrical connector 30, so as to reduce the degree of deformation of the first chip 10 and the electrical connector 30, thereby making the first chip 10 and the electrical The connection of the connector 30 is more stable.
- the thermal conductivity of the high thermal conductivity medium 40 is higher than the thermal conductivity of the underfill (UF) filled in the gap of the chip packaging structure in the related art, so as to improve the heat dissipation efficiency of the first chip 10 and the electrical connector 30 , So as to meet the heat dissipation requirements of a chip package structure with high integration and high power consumption.
- the high thermal conductivity medium 40 may include, but is not limited to, any one or more of the following materials: solder, silver paste (epoxy), graphene.
- the high thermal conductivity medium 40 of the present application may be silver paste coated or printed on the outer periphery of the electrical connector 30 to achieve effective heat dissipation of the first chip 10 and the electrical connector 30.
- the high thermal conductivity medium 40 may be a mixed material composed of silver paste and solder that is coated or printed on the outer periphery of the electrical connector 30. It should be noted that the aforementioned solder, silver paste (epoxy), graphene and other materials are not nanomaterials.
- the high thermal conductivity medium 40 may be formed by nanomaterials such as nanowires (NW) or nanoparticle stacks.
- the composition of the nanowires or nanoparticles may be metal materials (such as Au, Ag, Ge), semiconductor materials (such as Si), metal alloy materials (such as Fe-Co), metal oxide materials (such as LiNiO 2 , CdO ), etc., this embodiment specifically does not limit the composition of the nanowire or nanoparticle.
- the high thermal conductivity medium 40 is composed of nanowires
- a plurality of nanowires are entangled with each other to form a structure similar to a ball of wool, and the winding method of the nanowires can be random winding. Or, follow certain rules for winding.
- FIG. 1a shows another winding method when the high thermal conductivity medium 40 is composed of nanowires.
- each nanowire of the nanowire structure goes from the first chip 10 to the adapter plate 20 Extending in the direction, a plurality of nanowires are sequentially stacked in a direction parallel to the first chip 10 until the thickness of the high thermal conductivity medium 40 is actually required to complete the filling of the nanowire structure.
- the thickness of the high thermal conductivity medium 40 refers to the distance between the two sides of the high thermal conductivity medium 40 parallel to the extending direction of the first chip 10, as shown in d in FIG. 1a.
- the high thermal conductivity medium 40 is composed of nanoparticles
- a plurality of nanoparticles can be stacked from the surface of the insulating layer 50 to a direction away from the insulating layer 50 until it reaches the required thickness of the high thermal conductivity medium 40, or a plurality of nanometers can be Starting from the first chip 10 toward the surface of the transfer board 20, it is stacked in the direction of the transfer board 20 until it reaches the height required by the high thermal conductivity medium 40.
- the height of the high thermal conductivity medium 40 specifically refers to the distance between the two ends of the high thermal conductivity medium 40 in a direction perpendicular to the first chip 10, as shown in e in FIG. 1a.
- an oxidizing medium can be filled between the nanowires or the gaps between the nano-particles of the high thermally conductive medium 40 to enhance the relationship between the nanowires or nano-particles.
- the bonding strength between the nanomaterials enhances the structural stability of the high thermal conductivity medium 40 formed of nanomaterials, thereby ensuring the thermal conductivity of the nano thermal conductivity medium, and also improves the structural support effect of the first chip 10 and the electrical connector 30.
- the high thermal conductivity medium 40 is composed of a plurality of nanowires and an oxidizing medium arranged between the plurality of nanowires, or the high thermal conductivity medium 40 is composed of a plurality of nano particles and a plurality of nano particles. Between the oxidizing medium composition.
- the other constituent elements except oxygen in the oxidizing medium can be consistent with the main constituent elements of the nanomaterials, so that the bonding strength between the oxidizing medium and the nanomaterials can be enhanced, thereby enhancing The bonding strength between nanowires or nanoparticles.
- the oxidizing medium is silver oxide
- the oxidizing medium is titanium oxide
- the oxidizing medium is silicon dioxide .
- constituent elements except oxygen in the oxidizing medium can be consistent with the main constituent elements of the nanomaterial, which can further ensure the thermal conductivity of the final high thermal conductivity medium 40.
- the structure of the embodiment of the present invention further includes an insulating layer 50.
- the insulating layer 50 wraps the side surface of the electrical connector 30 and is used to isolate the high thermal conductivity medium 40 from the electrical connector 30.
- the insulating layer 50 is wrapped on a part of the side wall of the electrical connector 30, and the high thermal conductivity medium 40 is wrapped on the surface of the insulating layer 50 facing away from the electrical connector 30, that is, the outer surface of the insulating layer 50.
- This arrangement avoids the leakage of the electric current on the electrical connector 30 to the high thermal conductivity medium 40, thereby not only ensuring the stability of the conduction between the first chip 10 and the adapter board 20, but also avoiding damage to the chip. Components outside the package structure cause electrical signal interference.
- the number of the electrical connector 30 can be one or more.
- a high thermal conductivity medium 40 is provided around the electrical connector 30, and an insulating layer 50 is provided between the high thermal conductivity medium 40 and the electrical connector 30 to prevent the electrical connector 30
- the current on the 20 diffuses to the high thermal conductivity medium 40 and affects the electrical transmission stability of the electrical connector 20.
- the multiple electrical connectors 30 are arranged in a matrix on the bottom of the first chip 10, and the spaces between adjacent electrical connectors 30 are filled with a high thermal conductivity medium 40.
- the high thermal conductivity medium 40 filled between two adjacent connectors 30 can provide heat dissipation to the electrical connectors 30 on both sides at the same time, thereby effectively improving the heat dissipation efficiency of the high thermal conductivity medium 40 to each electrical connector 30.
- the high thermal conductivity medium 40 filled between the adjacent electrical connectors 30 also supports the two electrical connectors 30 and the first chip 10, so that the electrical connector 30 can be more stably supported on the first chip 10. Between the first chip 10 and the adapter board 20, the conduction between the first chip 10 and the adapter board 20 is ensured.
- a material with high thermal conductivity will have electrical conductivity. Therefore, in order to achieve effective heat dissipation of the first chip 10 while avoiding direct contact with the electrical connector 30 with the high thermal conductivity medium 40 with a certain electrical conductivity, this embodiment An insulating layer 50 is provided between the high thermal conductivity medium 40 located between two adjacent electrical connectors 30 and any one of the electrical connectors 30, that is, the high thermal conductivity medium 40 is connected to each electrical connector 30 through the insulating layer 50.
- each electrical connector 30 will not be short-circuited due to the conductivity of the high thermal conductivity medium 40, and further ensure that each electrical connector 30 is normally conductive to its corresponding electrical signal, and at the same time can ensure
- the high thermal conductivity medium 40 effectively dissipates the heat of the first chip 10.
- one end of the high thermal conductivity medium 40 extends to contact the inner surface of the first chip 10 (that is, the surface facing the adapter plate 20), for example, one end of the high thermal conductivity medium 40 extends to the electrical connector 30 close to One end of the first chip 10 and the first end of the insulating layer 50 also extend to an end of the electrical connector 30 close to the first chip 10 to prevent the high thermal conductivity medium 40 from directly contacting the sidewall of the electrical connector 30.
- first end of the insulating layer 50 refers to the end of the insulating layer 50 close to the first chip 10
- the second end of the insulating layer 50 refers to the end of the insulating layer 50 close to the adapter board 20.
- the electrical connector 30 may be a micro bump or a Controlled Collapse Chip Connection (referred to as "Bump").
- Bump Controlled Collapse Chip Connection
- C4 as shown in Figure 1b, where the controllable collapse chip interconnect structure is also called a controllable collapse bump.
- the electrical connection member 30 may be a micro bump or a controllable collapse bump.
- the structure and composition of the micro bumps and the controllable collapse bumps in this application can directly refer to the content recorded in the prior art.
- the electrical connector 30 may also be a structure formed by a copper pillar (Cu Pillar, CuP) 31 and a tin bump 32 disposed at one end of the copper pillar 31, wherein the copper pillar 31 passes through The tin bump 32 is electrically connected to the adapter board 20.
- a copper pillar Cu Pillar, CuP
- a tin bump 32 disposed at one end of the copper pillar 31, wherein the copper pillar 31 passes through
- the tin bump 32 is electrically connected to the adapter board 20.
- Any of the above types of electrical connectors 30 are fixed on the adapter plate 20 by welding. Those skilled in the art should understand that the welding process needs to ensure that the end of the electrical connector such as micro bumps or controllable collapse bumps, which is close to the adapter plate 20, needs to have a certain degree of melting and fluidity at high temperatures. In the process, only one end of the electrical connector 30 close to the adapter plate 20 can be wetted and spread on the surface of the adapter plate 20 under the action of
- the second end of the insulating layer 50 in the embodiment of the present application extends to a predetermined distance a from the adapter board 20, as shown in FIGS. 1a and 1b.
- the side wall of one end of the electrical connector 30 close to the adapter board 20 is exposed, and the insulating layer 50 does not cover the side wall of one end of the electrical connector 30 close to the adapter board 20.
- the end of the electrical connector 30 can effectively be wetted and spread in the horizontal direction, thereby further ensuring the welding between the electrical connector 30 and the adapter plate 20 Stability.
- the end of the high thermal conductivity medium 40 facing the adapter plate 20 will not exceed the insulating layer 50 facing the adapter plate 20.
- One end, for example, the high thermal conductivity medium 40 will not contact the side wall of the exposed end of the electrical connector 30.
- the specific value of the preset distance a can be determined according to actual welding requirements, which is not limited in the embodiment of the present application.
- the electrical connector 30 includes the copper pillar 31 and the tin bump 32 provided at one end of the copper pillar 30 as an example to describe the arrangement of the insulating layer 50.
- one end of the copper pillar 31 of the electrical connector 30 is electrically connected to the first chip 10
- the tin bump 32 is connected to the end of the copper pillar 31 close to the adapter board 20.
- the tin bump 32 is located on the copper
- the pillar 31 is electrically connected to the adapter board 20 and with the adapter board 20, so as to achieve electrical conduction between the first chip 10 and the adapter board 20.
- the tin bump 32 is a solder bump made of tin, that is, a tin solder bump, so as to ensure that the copper pillar 30 and the tin bump 32 are both electrical conductors. Because the copper pillar 31 itself cannot be connected to the adapter board 30 by welding, a tin bump 32 made of tin is provided at the bottom end of the copper pillar 31 to weld the tin bump 32 to the adapter board 30. On the board 20, the connection and conduction between the copper pillar 32 and the adapter board 20 are realized.
- solder bumps 32 must first be properly wetted and spread on the adapter board 20 under the action of high temperature, so that the solder bumps can be spread.
- 32 is welded to the adapter board 20 stably. Therefore, as shown in FIG.
- the outer sidewalls of the copper pillars 31 are completely covered, but the tin bumps 32 may not be covered by the insulating layer 50, so that the tin bumps 32 under the copper pillars 31 are completely exposed at the insulating layer 50 to prevent the insulating layer 50 from bumping the tin.
- the wetting spread of point 32 is hindered.
- the second end of the insulating layer 50 may also extend to a part of the outer surface of the tin bump 32.
- the outer surface of the tin bump 32 near the end of the copper pillar 31 may cover the insulating layer 50.
- the outer surface of the tin bump 32 is partially covered by 50.
- the second end of the insulating layer 50 may also have a space b between the end of the copper pillar 31 close to the adapter plate 20.
- the insulating layer 50 may also Cover a part of the copper pillar 31 in the axial direction. The embodiment of the present application does not limit the coverage area of the insulating layer 50 on the copper pillar 31, as long as the high thermal conductivity medium 40 and the copper pillar 31 can be effectively isolated.
- the end of the high thermal conductivity medium 40 close to the adapter plate 20 can extend to the second end of the insulating layer 50 (that is, the end of the insulating layer facing the adapter plate 20)
- the distance c between the end of the high thermal conductivity medium 40 close to the adapter plate 20 and the adapter plate 20 is equal to the distance a between the second end of the insulating layer 50 and the adapter plate 20, thus increasing While increasing the filling amount of the high thermal conductivity medium 40, it also prevents the high thermal conductivity medium 40 from protruding out of the second end of the insulating layer 50 and directly contacting the surface of the electrical connector 30, thereby not only increasing the height
- the heat-conducting medium 40 has a heat dissipation efficiency for the first chip 10 and the electrical connector 30, and ensures that the electrical connector 30 will not leak electricity or a short circuit between adjacent electrical connectors 30 due to the high thermal conductivity medium 40.
- a refers to the distance between the second end of the insulating layer 50 and the adapter plate 20
- c refers to the end of the high thermal conductivity medium 40 close to the adapter plate 20 and the adapter plate 20. the distance between.
- the height One end of the thermally conductive medium 40 may extend to be flush with the second end of the insulating layer 50 to increase the filling area and filling amount of the high thermally conductive medium 40, so that more heat can be transferred on the first chip 10 and the electrical connector 30 Into the high thermal conductivity medium 40 and dissipate to the outside along with the high thermal conductivity medium 40, and will not cause leakage and short circuit of the electrical connector 30.
- the support strength of the high thermal conductivity medium 40 to the copper pillar 31 and the first chip 10 is also enhanced.
- the end of the high thermal conductivity medium 40 close to the adapter plate 20 may be higher than the second end of the insulating layer 50.
- the distance between the connecting plates 20 is greater than the distance between the second end of the insulating layer 50 and the adapter plate 20 to further ensure that the high thermal conductivity medium 40 does not directly contact the surface of the electrical connector 30.
- one end of the high thermal conductivity medium 40 may extend to a certain distance from the end of the copper pillar 31 near the adapter board 20. In order to ensure that the insulating layer 50 effectively isolates the high thermal conductivity medium 40 and the copper pillar 31.
- the distance between the end of the high thermal conductivity medium 40 close to the adapter plate 20 and the second end of the insulating layer 50 can be adjusted according to actual heat dissipation requirements.
- the insulating layer 50 in the embodiment of the present application may be a copper oxide layer or a tin oxide layer.
- the insulating layer 50 may also be a dry film or a passivation layer made of an insulating material, where the insulating material may be a polymer such as polyvinyl chloride, styrene butadiene rubber, polyamide, etc. This embodiment does not limit the composition of the insulating material.
- the formation process of the insulating layer 50 can be as follows: the copper pillar 31 is oxidized on the surface of the copper pillar 31 by means of high temperature or humidification to form a copper oxide layer, and the copper oxide layer serves as Insulation layer 50.
- the tin oxide layer as an insulating layer is manufactured by first immersing tin on the surface of the electrical connection member 30 and then oxidizing it to tin oxide, thereby forming a tin oxide layer on the surface of the electrical connection member 30 and acting as an insulating layer.
- the direct immersion of tin on the electrical connector 30 will inevitably cause the tin to react with the metal compound in the electrical connector 30, such as CuP on the surface of the copper pillar 31, to form CuSn, which will affect the mechanical structure of the electrical connector 30 and the The electrical performance of the electrical connector 30 is affected. Therefore, referring to FIG.
- the present application provides a barrier layer 60 between the outer sidewall of the electrical connector 30 and the tin oxide layer (ie, the insulating layer 50) to prevent tin from excessively reacting with the metal in the electrical connector 30, such as copper.
- An intermetallic compound that is unfavorable to the mechanical structure and electrical performance of the electrical connector 30 is generated, thereby further ensuring the structural stability of the electrical connector 30 and the stable conduction between the first chip 10 and the adapter board 20.
- the barrier layer 60 may be a film layer made of Ni (nickel), Ti (titanium), W (tungsten), and TaN (tantalum nitride). The film layer made of Ni, Ti, W, and TaN can effectively block tin and the metal compound in the electrical connector 30, thereby ensuring the smooth growth of tin oxide.
- the embodiment of the present application also provides a manufacturing method of a chip packaging structure, and the manufacturing method may specifically include the following steps.
- FIG. 5a is a schematic diagram of the structure of the first chip in the first method of manufacturing the chip package structure provided in the first embodiment of the application
- FIG. 5b is the first method of manufacturing the chip package structure provided in the first embodiment of the application.
- Figure 5c is a schematic diagram of the structure of forming an insulating layer on the outer sidewall of the electrical connector in the first manufacturing method of the chip packaging structure provided in the first embodiment of the application;
- Figure 5d is In the first manufacturing method of the chip packaging structure provided in the first embodiment of the application, a schematic diagram of the structure after the adapter board is electrically connected to the end of the electrical connector away from the first chip;
- FIG. 5a is a schematic diagram of the structure of the first chip in the first method of manufacturing the chip package structure provided in the first embodiment of the application
- FIG. 5b is the first method of manufacturing the chip package structure provided in the first embodiment of the application.
- Figure 5c is a schematic diagram of the structure of forming an insulating layer on the outer sidewall of the electrical connector in
- the first manufacturing method of the chip packaging structure provided by the embodiment of the present application is specifically as follows:
- a first chip 10 is provided, wherein the first chip 10 can directly adopt the existing chip structure, or a silicon wafer for making the chip 10 can be obtained first, and then a dicing device can be used for the silicon wafer The dicing is performed to form the required first chip 10.
- the first chip 10 may be a wafer, and the wafer may be cut to form the required chips when the packaging is completed.
- the first chip 10 is first placed on the preparation platform, and then the electrical connector 30 is deposited on the upper surface of the first chip 10 until the electrical connector 30 reaches the required height.
- the electrical connector 30 is deposited on the upper surface of the first chip 10 upward, that is, in the direction of the arrow d in FIG. 5b, the deposition process of the electrical connector 30 is made more stable and controllable.
- one or more electrical connectors 30 may be deposited on the upper surface of the first chip 10.
- the multiple electrical connectors 30 are arranged at intervals in a direction parallel to the first chip 10.
- S102 may include:
- At least one copper pillar 31 is deposited on the upper surface of the first chip 10 along the direction of arrow a.
- tin is sputtered on the top of the copper pillar 31 to form a tin bump 32. It can be understood that the tin bump 32 is electrically connected to the top end of the copper pillar 31.
- An insulating layer 50 is formed on the outer sidewall of the electrical connection member 30, and the insulating layer 50 covers at least a part of the outer sidewall of the electrical connection member 30.
- an insulating layer 50 is formed on the outer sidewall of the electrical connector 30.
- the insulating layer 50 can be formed on the outer sidewall of the electrical connector 30 by oxidation, sputtering or printing.
- forming the insulating layer 50 on the outer sidewall of the electrical connector 30 may include:
- the outer sidewall of the electrical connection member 30 is oxidized by a method such as high temperature or moisture to form an oxide layer on the outer sidewall of the electrical connection member 30, and the oxide layer is used as the insulating layer 50.
- the electrical connector 30 includes a copper pillar 31 and a tin bump 32 provided at one end of the copper pillar 31, the CuP on the surface of the copper pillar 31 is oxidized to form a copper oxide layer, and the copper oxide layer is used as an insulating layer 50. It can be seen that the insulating layer 50 can cover all or part of the sidewall of the copper pillar 31.
- the process of forming the insulating layer 50 on the outer side wall of the electrical connection member 30 may also include: pasting an insulating dry film or an insulating passivation layer on the outer side wall of the electrical connection member 30 to pass the insulating dry film or the insulating passivation layer.
- the chemical layer serves as an insulating layer.
- the insulating dry film or insulating passivation layer can be made of polyvinyl chloride, styrene butadiene rubber, polyamide and other polymer materials.
- the process of forming the insulating layer 50 on the outer sidewall of the electrical connector 30 may specifically also include:
- the tin layer is oxidized to form a tin oxide layer, and the tin oxide layer is used as the insulating layer 50.
- the surface of the copper pillar 31 is first immersed in tin, and then it is oxidized into SnOx, or tin oxide, and used as the insulating layer 50 .
- the intermetallic compound formed by the reaction between the tin and the metal on the surface of the electrical connector 30, such as copper, will adversely affect the mechanical structure and electrical properties of the electrical connector 30.
- the process of forming the insulating layer 50 on the outer side wall of the electrical connector 30 may also specifically include:
- a barrier layer 60 is formed on the outer sidewall of the electrical connection member 30 through an electroplating or sputtering process (see FIG. 4);
- the tin layer is oxidized to form a tin oxide layer, and the tin oxide layer is used as the insulating layer 50.
- the barrier layer 60 is sputtered on the CuP surface of the copper pillar 31, and then the barrier layer 60 is immersed in tin, and finally the tin is oxidized into SnOx or tin oxide, which serves as the insulating layer 50, thereby preventing the CuSn from growing too fast , To ensure the structural stability and electrical performance of the electrical connector 30.
- S104 Provide an adapter board 20, and electrically connect the adapter board 20 and the end of the electrical connector 30 away from the first chip 10, so that the first chip 10 and the adapter board 20 are connected through the electrical connector 30.
- the adapter board 20 is connected to one end of the electrical connector 31, for example, the adapter board 20 and the tin bump 32 can be welded and connected.
- the adapter board 20 can be a substrate or a second chip. It should be understood that the substrate or the second chip may directly adopt the substrate or the second chip in the prior art.
- the electrical connector 30 includes a copper pillar 31 and a tin bump 32 disposed at one end of the copper pillar 31, the transfer board 20 is electrically connected to an end of the tin bump 32 that faces away from the first chip 10.
- the high thermal conductivity medium 40 can be coated or printed upward in the direction of arrow d starting from the upper surface of the first chip 10, that is, the surface facing the adapter board 20, until the high thermal conductivity medium 40 reaches the first part of the insulating layer 50.
- the two ends, namely, the end close to the adapter plate 20 or the top end of the high thermal conductivity medium 40 and the second end of the insulating layer 50 may be spaced apart.
- the high thermal conductivity medium 40 is arranged around the outer circumference of the electrical connector 30, and one end of the high thermal conductivity medium 40 is in contact with the first chip 10, and the insulating layer 50 separates the high thermal conductivity medium 40 from the electrical connector 30 to prevent electrical The connection piece 30 is leaking or the adjacent point connection piece 30 is short-circuited.
- the high thermal conductivity medium 40 is a nanomaterial formed by stacking nanowires or nano particles
- the gaps of the nanomaterial can be filled continuously. Oxidize the medium to enhance the bonding force between the nanowires or nanoparticles in the nanomaterial, thereby improving the structural strength of the high thermal conductivity medium 40 formed by stacking the nanomaterials.
- FIG. 6a is a schematic structural diagram of the first chip in the second manufacturing method of the chip packaging structure provided in the first embodiment of the application
- FIG. 6b is the first chip in the second manufacturing method of the chip packaging structure provided in the first embodiment of the application
- Figure 6c is a schematic diagram of the structure of forming an insulating layer on the outer sidewall of the electrical connector in the second method of manufacturing the chip packaging structure provided in the first embodiment of the application
- Figure 6d is a schematic diagram of the electrical connector In the second manufacturing method of the chip package structure provided in the first embodiment of the application, a schematic structural view of filling the outer periphery of the electrical connector with a high thermal conductivity medium
- FIG. 6e is the second manufacturing method of the chip package structure provided in the first embodiment of the application The schematic diagram of the structure after the adapter board is electrically connected to the end of the electrical connector away from the first chip.
- the manufacturing process and sequence of S101 to S103 in the second preparation method provided in this embodiment are completely consistent with the above-mentioned first preparation method, and the specific manufacturing process of S101 to S103 can be directly referred to the above The content of the first preparation method.
- the difference from the above-mentioned first preparation method is that S104 and S105 of the second preparation method provided in this embodiment are respectively:
- the high thermal conductivity medium 40 is arranged around the outer periphery of the electrical connector 30 on which the insulating layer 50 is formed, and the insulating layer 50 separates the high thermal conductivity medium 40 from the electrical connector 30.
- An adapter board 20 is provided, and the adapter board 20 is electrically connected to an end of the electrical connector 30 away from the first chip 10 to form a chip packaging structure.
- the first preparation method and the second preparation method of the above-mentioned chip packaging structure are only after the insulating layer 50 is completed, the high thermal conductivity medium 40 and the fixed adapter plate 20 are replaced. order.
- the electrical connectors 30 and the high thermal conductivity medium 40 are directly fabricated on the first chip 10.
- silicon wafers can also be directly provided, and the electrical connectors 30, the insulating layer 50 and the high thermal conductivity medium 40 are made on the silicon wafers, and the high thermal conductivity medium 40 is filled to the outer periphery of the electrical connectors 30 After that, the silicon wafer is cut into the first chip 10.
- the high thermal conductivity medium 40 may be before the adapter plate 20 is fixed, or after the adapter plate 20 is fixed, in other words, the silicon wafer can be cut when the adapter plate 20 is fixed to the electrical connector 30. Before one end of the silicon wafer, the high thermal conductivity medium 40 is filled into the outer periphery of the electrical connector 30. The dicing of the silicon wafer may also be performed at the end of all the manufacturing steps.
- the silicon wafer can also be directly provided, and then after the electrical connectors 30 and the insulating layer 50 are completed, the silicon wafer is cut before the high thermal conductivity medium 40 is filled, and then the silicon wafer is formed by cutting.
- the gap between the first chip 10 and the electrical connector 30 is filled with a high thermal conductivity medium 40.
- the cutting of the silicon wafer can be performed after the adapter plate 20 is fixed to one end of the electrical connector 30 and before the high thermal conductivity medium 40 is filled on the outer circumference of the electrical connector 30, or it can be performed on the high thermal conductivity medium.
- the silicon wafer is cut first, so that the subsequent filling of the high thermal conductivity medium 40 and the fixing of the adapter plate 20 are performed on the first chip 10.
- FIG. 7 is a schematic diagram of the sixth structure of the chip packaging structure provided by an embodiment of the application.
- the chip packaging structure of the present application further includes an underfill 70 whose thermal conductivity is less than that of the high thermal conductivity medium 40.
- the thermal conductivity of the underfill 70 is generally lower than 3W/mK or even 1W/mK.
- the underfill material 70 of the present application is filled between the insulating layer 50 and the adapter plate 20 and between the high thermal conductivity medium 40 and the adapter plate 20, so that the underfill material 70 can affect the bottom of the insulating layer 50 and the high thermal conductivity medium 40. Play a supporting role, thereby reducing the stress between the adapter plate 20 and the first chip 10 caused by the mismatch of the thermal expansion coefficient, avoiding the breakage of the pad between the electrical connector 30 and the adapter plate 20, and improving the electrical The welding reliability between the connecting member 30 and the adapter plate 20 and the structural stability of the insulating layer 50 and the high thermal conductivity medium 60. At the same time, since the thermal conductivity of the underfill 70 is small, it will not have electrical conductivity, and therefore will not cause leakage or short circuit of the electrical connector 30.
- the electrical connector 30 includes a copper pillar 31 and a tin bump 32 provided at one end of the copper pillar 31, a part of the underfill 70 extends to contact the outer surface of the tin bump 32 to further improve the tin bump in the packaged chip structure.
- the structural stability of the dot 32 further ensures the reliability of the electrical connection between the solder bump 32 and the adapter board 20.
- the underfill 70 may directly use the filler of the existing chip packaging structure, for example, the underfill may be composed of epoxy resin and silicon dioxide.
- the underfill 70 has the ability to climb upwards, so that the underfill 70 can climb to the outer surface of the high thermal conductivity medium 40, thereby strengthening the high thermal conductivity medium 40
- the structural stability of the high thermal conductivity medium 40 has a tendency to converge toward the center of the package structure, thereby ensuring the structural support of the high thermal conductivity medium 40 on the first chip 10 and the electrical connectors 30, making the entire chip package structure more stable.
- the underfill 70 can climb from the side of the interposer board 20 toward the first chip 10 to 2/3 of the high thermal conductivity medium 40 relative to the interposer board 20.
- the filling of the underfill 70 needs to be performed after the adapter plate 20 is electrically connected to the end of the electrical connector 30 away from the first chip 10 and the high thermal conductivity medium 40 is filled on the outer periphery of the electrical connector 30.
- the manufacturing method of the fifth structure of the chip packaging structure can be directly performed on the basis of the first manufacturing method or the second manufacturing method of the above-mentioned chip packaging structure. Specifically, the following steps are performed before the chip packaging structure is formed: An underfill 70 is filled in the space between the insulating layer 50 and the transfer board 20 and the space between the high thermal conductivity medium 40 and the transfer board 20, wherein the underfill 70 is in contact with the outer surface of the tin bump 32.
- a mounting hole (not shown in the figure) is provided on the substrate or the second chip of the adapter board 20, and a ground connection point (also called VSS, ground pin) or a power connection point is provided in the mounting hole (Also known as VDD, ground pin), where the ground connection point VSS extends out of the side of the mounting hole away from the first chip 10, that is, extends out of the adapter board 20 and is used to connect to the ground line to protect the adapter board 20.
- the safety of electricity also protrudes from the side of the mounting hole away from the first chip 10, that is, protrudes out of the adapter board 20, and is used to connect with an external power source, so as to provide electrical signals for the chip package structure.
- the embodiment of the present application can be based on any of the above chip packaging structures, and the high thermal conductivity medium 40 is directed toward the end of the adapter board 20 and the ground on the adapter board 20.
- the connection point or the power connection point is contacted to conduct the heat of the ground connection point or the power connection point to the high thermal conductivity medium 40, and then the heat is dissipated to the outside through the heat conduction medium 40, thereby ensuring the ground connection point or power connection of the adapter board 20 The electrical performance of the point.
- FIG. 8 is a schematic diagram of the seventh structure of the chip packaging structure provided by an embodiment of the application.
- a metal pad 80 may be provided at the end of the ground connection point or the power connection point facing the first chip 10, and the high thermal conductivity medium 40 may face one end of the adapter board 20 It can be in contact with the metal pad 80 so that the heat of the ground connection point or the power connection point is conducted to the high thermal conductivity medium 40 through the metal pad 80.
- the metal pad 80 may be a copper pad or a tin pad or other metal pads with high thermal conductivity.
- the difference between the manufacturing method of the sixth structure of the chip packaging structure of the present application and any of the above-mentioned manufacturing methods of the chip packaging structure is that the manufacturing method of the sixth structure is used between the adapter plate 20 and the electrical connector 30 Before the end of the first chip 10 is electrically connected, the method further includes:
- a metal pad 80 is formed on the side of the interposer board 20 facing the first chip 10, one end of the metal pad 80 is electrically connected to the ground connection point or power connection point on the interposer board 20, and the other end of the metal pad 80 is at The adapter plate 20 is in contact with the high thermal conductivity medium 40 when it is connected to the electrical connector 30.
- the seventh structure of the chip packaging structure shown in FIG. 8 is only an improvement made on the basis of the sixth structure of the chip packaging structure, that is, FIG. 7, but the chip packaging structure of the embodiment of the present application cannot be excluded
- the seventh structure can also be an improvement on the above other structures.
- One end of the medium 40 close to the adapter board 20 is in contact with the metal pad 80, so that the heat on the ground connection point or power connection point of the adapter board 20 is transferred to the high thermal conductivity medium 40 through the metal pad 80, so as to realize the connection to the adapter board. 20 ground connection point or power connection point for effective heat dissipation.
- the metal pad 80 may extend to contact with the end of the high thermal conductivity medium 40 close to the adapter plate 20, instead of extending the end of the high thermal conductivity medium 40 close to the adapter plate 20.
- the portion of the high thermal conductivity medium 40 close to the end of the adapter plate 20 may also be extended to form the extension portion 41 mentioned below, and the extension portion 41 is in contact with the metal pad 80.
- FIG. 9 is a schematic diagram of the eighth structure of the chip packaging structure provided by an embodiment of the application.
- the eighth structure of the chip packaging structure is to place the high thermal conductivity medium 40 close to the adapter board 20 A part of the area at one end extends in the direction close to the adapter plate 20 to form an extension 41.
- One end of the extension 41 extends to the ground connection point or the power connection point and directly contacts the ground connection point or the power connection point to reduce
- the heat conduction resistance between the small high thermal conductivity medium 40 and the ground connection point or the power connection point in the adapter plate 20 can quickly and effectively transfer the heat at the ground connection point or the power connection point to the high thermal conductivity medium 40, and follow the height
- the heat-conducting medium 40 is transferred to the external environment to further ensure the working performance of the adapter plate 40.
- neither the extension 41 or the metal pad 80 of the end of the high thermal conductivity medium 40 close to the adapter plate 20 can contact the outer surface of the electrical connector 30 to prevent leakage and short circuit.
- the end of the high thermal conductivity medium 40 close to the adapter plate 20 is in contact with the ground connection point or the power connection point on the adapter plate 20 through the metal pad 80 or the extension 41 At this time, it is also necessary to ensure that the outer sidewall of the metal pad 80 or the extension portion 41 does not contact the tin bump 32.
- the embodiment of the present application does not elaborate on the case where the metal pad 80 or the outer side wall of the extension 41 is provided on the basis of the chip package structure of other structure, as long as it is ensured that the outer side wall of the metal pad 80 or the extension 41 is not connected to the electrical connector 30
- the outer side wall of the device can be directly contacted.
- the embodiment of the present application also provides a circuit board, which includes a chip packaging structure in any of the above scenarios.
- An embodiment of the present application also provides an electronic device, which includes any one of the chip packaging structures in any of the above scenarios.
- the chip packaging structure has a good heat dissipation effect
- a highly integrated chip packaging structure can be provided in the electronic device. This way, while enhancing the function of the electronic device, the chip packaging structure is reduced in size.
- the occupied size of the electronic device will not only provide effective space for the installation of other components in the electronic device, but also reduce the size of the entire electronic device and optimize the experience effect of the electronic device. At the same time, the stability of the signal transmission in the electronic equipment is also ensured, and the normal operation of the electronic equipment is ensured.
- the electronic devices may include, but are not limited to, mobile phones, tablet computers, notebook computers, ultra-mobile personal computers (UMPC), handheld computers, walkie-talkies, netbooks, POS machines, personal digital assistants (PDAs for short), wearable devices, virtual reality devices and other mobile or fixed terminals with chip packaging structures.
- UMPC ultra-mobile personal computers
- PDA personal digital assistants
- connection should be understood in a broad sense, for example, it may be a fixed connection or Indirect connection through an intermediate medium can be the internal communication between two elements or the interaction between two elements.
- connection should be understood in a broad sense, for example, it may be a fixed connection or Indirect connection through an intermediate medium can be the internal communication between two elements or the interaction between two elements.
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Abstract
一种电子设备、芯片封装结构及其制作方法;其中,芯片封装结构包括第一芯片(10)、转接板(20)以及位于第一芯片(10)和转接板(20)之间的至少一个电连接件(30),电连接件(30)的两端分别与第一芯片(10)和转接板(20)电连接;还包括:位于第一芯片(10)和转接板(20)之间且围设在电连接件(30)外周的高导热介质(40),高导热介质(40)的一端与第一芯片(10)接触,以实现对第一芯片(10)以及电连接件(30)的有效散热,从而可提高芯片封装结构的集成度,高导热介质(40)与电连接件(30)之间设置绝缘层(50),绝缘层(50)用于将高导热介质(40)与所述电连接件(30)隔开,以避免电连接件(30)上的电流扩散至高导热介质(40)上而造成漏电的情况,从而不仅确保了第一芯片(10)与转接板(30)之间的导通稳定性,而且不会对芯片封装结构外部的元器件造成电信号的干扰。
Description
本申请涉及集成电路封装技术领域,特别涉及一种电子设备、芯片封装结构及其制作方法。
倒装芯片(Flip Chip)既是一种芯片互联技术,又是一种理想的芯片粘接技术,现已成为高端器件及高密度封装领域中经常采用的封装形式。随着倒装芯片的广泛应用,芯片的功耗密度也越来越大,同时也出现了多个芯片堆叠形成的封装结构,这对芯片的散热提出了更高的要求。
现有的倒装芯片封装结构主要包括芯片、铜柱等电连接件以及基板,其中,电连接件位于芯片与基板之间,且两端分别与芯片与基板电连接,以实现芯片与基板之间电信号的导通,同时,在芯片、电连接件以及基板形成的封装结构的空隙中填充有底填料(under fill,UF),以减小由于热膨胀系数不匹配而引起的基板与芯片之间的应力,从而提高电连接件与基板之间的电连接的可靠性。
然而,现有的底填料的散热性能有限,严重制约了芯片的集成度和功耗,并且当采用导热性能较高的底填料时,会造成电连接件发生漏电等情况,影响芯片与基板之间的导通稳定性。
发明内容
本申请提供了一种电子设备、芯片封装结构及其制作方法,在保证芯片封装结构的散热效率的同时,防止了芯片封装结构中的电连接件向外漏电的情况,确保芯片与基板等转接板之间的电导通稳定性。
第一方面,本申请实施例提供一种芯片封装结构,包括:第一芯片、转接板以及位于所述第一芯片和所述转接板之间的至少一个电连接件,所述电连接件的两端分别与所述第一芯片和所述转接板电连接;
还包括:位于所述第一芯片和所述转接板之间且围设在所述电连接件外周的高导热介质,所述高导热介质的一端与所述第一芯片接触,所述高导热介质与所述电连接件之间设置绝缘层,所述绝缘层用于将所述高导热介质与所述电连接件隔开。
通过在第一芯片和转接板之间的电连接件的外周设置高导热介质,并且将该高导热介质的一端与第一芯片接触,以使第一芯片以及电连接件上的热量能够有效的扩散至该高导热介质上,进而通过该高导热介质将热量释放至外部环境,有效提高了第一芯片以及电连接件的散热效率,从而为提高芯片的集成度和功耗提供了很好的散热基础。同时,高导热介质与电连接件之间通过绝缘层隔开,以避免电连接件上的电流扩 散至高导热介质上而造成漏电的情况,从而不仅确保了第一芯片与转接板之间的导通稳定性,而且不会对芯片封装结构外部的元器件造成电信号的干扰。
在第一方面的一种可能的实现方式中,所述绝缘层包裹在所述电连接件的至少部分侧壁上,所述高导热介质包裹在所述绝缘层背离所述电连接件的表面上,这样,不仅通过高导热介质实现对第一芯片的有效散热,而且也避免了该高导热介质直接与电连接件接触而导致电连接件漏电的情况发生。
在第一方面的一种可能的实现方式中,所述电连接件为多个,多个所述电连接件间隔设置;且相邻所述电连接件之间的间隔中填充有所述高导热介质。这样,一方面,填充在相邻两个连接件之间的高导热介质能够同时对两侧的电连接件进行散热,从而有效提高了高导热介质对每个电连接件的散热效率,另一方面,填充在相邻电连接件之间的高导热介质对两个电连接件以及第一芯片也起到支撑的作用,从而使得电连接件能够更加稳定地支撑在第一芯片与转接板之间,进而确保了第一芯片与转接板之间的导通。同时,位于相邻两个电连接件之间的高导热介质与其中任意一个电连接件之间均通过绝缘层隔开,使得相邻的电连接件之间不会因高导热介质的导电性而发生短路,进一步保证每个电连接件对电信号的正常导通。
在第一方面的一种可能的实现方式中,所述绝缘层的第一端延伸至所述电连接件靠近所述第一芯片的一端,所述绝缘层的第二端延伸至与所述转接板之间具有预设间距。这样,在保证绝缘层在电连接件表面的覆盖面积的同时,通过将电连接件靠近转接板的一端的部分裸露在外,以使电连接件焊接在转接板上时该电连接件的末端能够有效地进行润湿铺展,从而进一步确保该电连接件与转接板之间的焊接稳固性。
在第一方面的一种可能的实现方式中,所述高导热介质朝向所述转接板的一端与所述转接板的距离大于或者等于所述绝缘层的第二端与所述转接板之间的距离,换句话说,高导热介质靠近转接板的一端可以延伸至与绝缘层的第二端齐平,也可以高于该绝缘层的第二端,这样,在保证围设在绝缘层外周的高导热介质对电连接件以及第一芯片的散热效果的同时,有效的避免了该高导热介质延伸出绝缘层的第二端而与绝缘层一侧的电连接件接触,从而进一步防止了电连接件漏电,且当高导热介质填充在相邻电连接件之间的间隔中时,也避免了相邻电连接件之间因高导热介质的电流传导而发生短路的情况。
在第一方面的一种可能的实现方式中,所述芯片封装结构还包括底填料,所述底填料的导热系数小于所述高导热介质的导热系数;
所述底填料填充在所述绝缘层与所述转接板之间以及填充在所述高导热介质与所述转接板之间。
通过在绝缘层与转接板之间以及高导热介质与转接板之间填充导热系数较高导热介质小的底填料,以实现对绝缘层和高导热介质底部的支撑,从而减小由于热膨胀系数不匹配而引起的转接板与第一芯片之间的应力,提高电连接件与转接板之间的焊接可靠性以及绝缘层和高导热介质的结构稳定性,同时,因底填料的导热系数较小,因而不会具有导电性能,因此不会造成电连接件发生漏电或者短路的情况。
在第一方面的一种可能的实现方式中,所述电连接件为微凸点或可控坍塌凸点中的任意一种。
在第一方面的一种可能的实现方式中,所述电连接件包括:铜柱以及与所述铜柱电连接的锡凸点,所述铜柱的一端与所述第一芯片电连接,所述锡凸点设置在所述铜柱与所述转接板之间且与所述转接板电连接;所述绝缘层的第二端延伸至所述铜柱靠近转接板的一端;部分所述底填料延伸至与所述锡凸点的外侧面接触。通过将用于连接铜柱与转接板的锡凸点暴露在绝缘层的外部,以防止该锡凸点在与转接板焊接时的扩散过程会受到绝缘层的阻碍而影响锡凸点与转接板的焊接稳定性,另外,通过将部分底填料填充在锡凸点的外侧壁,以进一步提高封装后的芯片结构中锡凸点的结构稳定性,从而进一步确保锡凸点与转接板的电连接可靠性。
在第一方面的一种可能的实现方式中,所述高导热介质包括以下一种或者多种材料:焊料、银浆、石墨烯、氧化铝颗粒。以上材料均能够提高芯片封装结构中第一芯片与电连接件的散热效率。
在第一方面的一种可能的实现方式中,所述高导热介质由纳米线或纳米颗粒堆叠形成;且所述纳米线之间或所述纳米颗粒之间的空隙内填充有氧化介质,以增强各个纳米线之间或者纳米颗粒之间的结合力度,从而增强纳米线或纳米颗粒堆叠形成的高导热介质的结构稳定性,进而保证纳米导热介质的导热性能,同时也提高了其对第一芯片以及各个电连接件的结构支撑效果。
在第一方面的一种可能的实现方式中,所述绝缘层为氧化铜层;或者,所述绝缘层为氧化锡层;或者,所述绝缘层为绝缘材料制成的干膜或钝化层。
在第一方面的一种可能的实现方式中,所述绝缘层为氧化锡层,且所述氧化锡层与所述电连接件的外侧壁之间设置阻挡层。通常,该氧化锡绝缘层的制作过程是先在电连接件的表面浸锡,然后将其氧化为氧化锡,本申请通过在电连接件的表面设置阻挡层,以防止锡与电连接件中的金属例如铜过度反应生成对电连接件的机械结构以及电性能不利的金属间化合物,从而进一步确保电连接件的结构稳定性以及对第一芯片与转接板的稳定导通。
在第一方面的一种可能的实现方式中,所述阻挡层为Ni,Ti,W,TaN制成的膜层。通过Ni,Ti,W,TaN制成的膜层能够实现对锡与电连接件中的金属化合物的阻隔,从而保证氧化锡的顺利生长。
在第一方面的一种可能的实现方式中,所述转接板上开设有安装孔,所述安装孔内设置有接地连接点或电源连接点,所述高导热介质的第二端的至少部分与所述接地连接点或电源连接点接触。通过将高导热介质的第二端与转接板上的接地连接点或者电源连接点接触,以实现对接地连接点或者电源连接点的有效散热,从而改善转接板的其他连接点的电学性能。
在第一方面的一种可能的实现方式中,所述转接板上设置有金属焊盘,所述金属焊盘的一端伸入至所述安装孔内并与所述接地连接点或电源连接点接触,所述金属焊盘的另一端与所述高导热介质接触。
在第一方面的一种可能的实现方式中,所述转接板为第二芯片;或者,所述转接板为基板。也即是说,芯片封装结构可通过第二芯片或者基板装载在电路板等元器件上,实现第一芯片与电路板等元器件的导通。
第二方面,本申请实施例提供一种电子设备,包括上述任一所述的芯片封装结构。
通过在电子设备中设置上述芯片封装结构,因芯片封装结构的散热效果佳,从而可在电子设备内设置集成度高的芯片封装结构,这样在增强电子设备功能的同时,缩小了芯片封装结构在电子设备内的占用尺寸,不仅会给电子设备中其他元器件的安装提供有效的空间,而且也可缩小整个电子设备的尺寸,优化电子设备的体验效果。与此同时,也保证了电子设备中信号传输的稳定性,确保电子设备的正常工作。
第三方面,本申请实施例提供一种芯片封装结构的制作方法,所述方法包括:
提供第一芯片;
在所述第一芯片的一面上制备至少一个电连接件,且所述电连接件与所述第一芯片电连接;
在所述电连接件的外侧壁上形成绝缘层,所述绝缘层至少覆盖所述电连接件的部分外侧壁;
在所述第一芯片具有所述电连接件的一面上设置高导热介质,所述高导热介质围设在所述电连接件的外周,且所述绝缘层将所述高导热介质和所述电连接件隔开;
提供转接板,所述转接板与所述电连接件背离所述第一芯片的一端电连接,形成芯片封装结构。
通过在电连接件的周围设置高导热介质,并且将该高导热介质的一端与第一芯片接触,以使第一芯片以及电连接件上的热量能够有效的扩散至该高导热介质上,进而通过该高导热介质将热量释放至外部环境,有效提高了第一芯片以及电连接件的散热效率,从而为提高芯片的集成度和功耗提供了很好的散热基础。同时,高导热介质与电连接件之间通过绝缘层隔开,以避免电连接件上的电流扩散至高导热介质上而造成漏电的情况,从而不仅确保了第一芯片与转接板之间的导通稳定性,而且不会对芯片封装结构外部的元器件造成电信号的干扰。另外,该芯片封装结构的制作工序中,在焊接转接板之前,先在电连接件的外周填充高导热介质,使得高导热介质的填充过程更加简单快捷,且能够在保证填充均匀性的同时,降低了工艺制作难度,有效提高了制作效率以及产品质量。
第四方面,本申请实施例提供一种芯片封装结构的制作方法,所述方法包括:
提供第一芯片;
在所述第一芯片的一面上制备至少一个电连接件,且所述电连接件与所述第一芯片电连接;
在所述电连接件的外侧壁上形成绝缘层,所述绝缘层至少覆盖所述电连接件的部分外侧壁;
提供转接板,所述转接板与所述电连接件背离所述第一芯片的一端电连接;
通过在电连接件的周围设置高导热介质,并且将该高导热介质的一端与第一芯片接触,以使第一芯片以及电连接件上的热量能够有效的扩散至该高导热介质上,进而通过该高导热介质将热量释放至外部环境,有效提高了第一芯片以及电连接件的散热效率,从而为提高芯片的集成度和功耗提供了很好的散热基础。同时,高导热介质与电连接件之间通过绝缘层隔开,以避免电连接件上的电流扩散至高导热介质上而造成漏电的情况,从而不仅确保了第一芯片与转接板之间的导通稳定性,而且不会对芯片封装结构外部的元器件造成电信号的干扰。另外,相对于第三方面提供的制作方法, 本申请实施例的第四方面可以先将转接板焊接在电连接件背离第一芯片的一端后,再进行高导热介质的填充,即本申请对工艺制作顺序没有过高的要求,只要最终制成能够符合要求的芯片封装结构即可。
在第三方面或者第四方面的一种可能的实现方式中,所述在所述电连接件的外侧壁上形成绝缘层,包括:
对所述电连接件的外侧壁进行氧化,以在所述电连接件的外侧壁上形成氧化层,所述氧化层作为所述绝缘层。
通过直接对电连接件的表面进行氧化而形成防止电连接件上的电流扩散的绝缘层,在确保电连接件不会漏电或者短路的同时,也简化了绝缘层的制作工序,提高了芯片封装结构的制作效率。
在第三方面或者第四方面的一种可能的实现方式中,所述在所述电连接件的外侧壁上形成绝缘层,包括:
将所述电连接件的外侧壁浸锡,以在所述电连接件的外侧壁上形成锡层;
将所述锡层进行氧化,形成氧化锡层,所述氧化锡层作为所述绝缘层。
以氧化锡层作为绝缘层,提高了绝缘层的绝缘性能,保证电连接件不会发生漏电或者短路的情况。
在第三方面或者第四方面的一种可能的实现方式中,所述将所述电连接件的外侧壁浸锡之前,还包括:
在所述电连接件的外侧壁上通过电镀或溅射工艺形成阻挡层;
所述将所述电连接件的外侧壁浸锡,以在所述电连接件的外侧壁上形成锡层,包括:
对所述电连接件外侧壁上的所述阻挡层进行浸锡,在所述阻挡层上形成所述锡层。
通过在电连接件的外侧壁上浸锡之前先形成阻挡层,在该阻挡层上进行浸锡,以避免锡与电连接件表面的铜等金属快速结合而生成对电连接件的机械结构以及电性能不利的金属间化合物。
在第三方面或者第四方面的一种可能的实现方式中,所述在所述电连接件的外侧壁上形成绝缘层,包括:在所述电连接件的外侧壁上粘贴绝缘干膜或绝缘钝化层,所述绝缘干膜或所述绝缘钝化层作为所述绝缘层,以简化绝缘层的制作工序。
在第三方面或者第四方面的一种可能的实现方式中,所述高导热介质为纳米材料;所述高导热介质围设在所述电连接件的外周之后,还包括:在所述纳米材料之间的空隙中填充氧化介质。
通过在纳米材料之间的空隙中填充氧化介质,以增强各个纳米线之间或者纳米颗粒之间的结合力度,从而增强纳米线或纳米颗粒堆叠形成的高导热介质的结构稳定性,进而保证纳米导热介质的导热性能,同时也提高了其对第一芯片以及各个电连接件的结构支撑效果。
在第三方面或者第四方面的一种可能的实现方式中,在所述第一芯片的一面上制备至少一个电连接件,包括:
在所述第一芯片的一面上制备至少一个铜柱;
所述铜柱朝向转接板的一端形成与所述铜柱电连接的锡凸点;
所述转接板与所述电连接件背离所述第一芯片的一端电连接,包括:
所述转接板与所述锡凸点背离所述第一芯片的一端电连接。
通过在第一芯片的一面上设置导电性能以及机械强度较高的铜柱,以实现对第一芯片与转接板之间的电信号的稳定传输,同时保证芯片封装结构的稳固性,并且,通过在铜柱的一端设置锡凸点,以实现与转接板的稳定焊接。
在第三方面或者第四方面的一种可能的实现方式中,所述绝缘层朝向所述转接板的一端与所述转接板之间存在间隔,且所述高导热介质朝向转接板的一端与所述转接板之间的距离大于或等于所述绝缘层到所述转接板的距离;
所述形成芯片封装结构之前,还包括:
在所述绝缘层与所述转接板之间的间隔以及所述高导热介质与所述转接板之间的间隔内中填充底填料,且所述底填料与所述锡凸点的外侧面接触。
通过将绝缘层朝向转接板的一端与转接板之间间隔设置,以使电连接件靠近转接板的一端的部分裸露在外,确保电连接件靠近转接板的一端在与转接板焊接时能够顺利的进行润湿延展,从而进一步确保该电连接件与转接板之间的电连接稳固性。同时,高导热介质靠近转接板的一端可以延伸至与绝缘层的第二端齐平,也可以高于该绝缘层的第二端,这样,在保证围设在绝缘层外周的高导热介质对电连接件以及第一芯片的散热效果的同时,有效的避免了该高导热介质延伸出绝缘层的第二端而与绝缘层一侧的电连接件接触,从而进一步防止了电连接件漏电,且当高导热介质填充在相邻电连接件之间的间隔中时,也避免了相邻电连接件之间因高导热介质的电流传导而发生短路的情况。通过在绝缘层与转接板之间以及高导热介质与转接板之间填充导热系数较高导热介质小的底填料,以实现对绝缘层和高导热介质底部的支撑,从而减小由于热膨胀系数不匹配而引起的转接板与第一芯片之间的应力,提高电连接件与转接板之间的焊接可靠性以及绝缘层和高导热介质的结构稳定性,同时,因底填料的导热系数较小,因而不会具有导电性能,因此不会造成电连接件发生漏电或者短路的情况。通过将部分底填料填充在锡凸点的外侧壁,以进一步提高封装后的芯片结构中锡凸点的结构稳定性,从而进一步确保锡凸点与转接板的电连接可靠性。
在第三方面或者第四方面的一种可能的实现方式中,所述转接板与所述电连接件背离所述第一芯片的一端电连接之前,还包括:
在所述转接板朝向所述第一芯片的一面上形成金属焊盘,所述金属焊盘的一端与所述转接板上的接地连接点或电源连接点电连接,所述金属焊盘的另一端用于在所述转接板与所述电连接件连接时与所述高导热介质接触。
图1a为本申请一实施例提供的芯片封装结构的第一种结构示意图;
图1b为本申请一实施例提供的芯片封装结构的第二种结构示意图;
图2为本申请实施例一提供的芯片封装结构的第三种结构示意图;
图3为本申请一实施例提供的芯片封装结构的第四种结构示意图;
图4为本申请一实施例提供的芯片封装结构的第五种结构示意图;
图5a为本申请实施例一提供的芯片封装结构的第一种制作方法中第一芯片的结构示意图;
图5b为本申请实施例一提供的芯片封装结构的第一种制作方法中在第一芯片的表面制作出电连接件的结构示意图;
图5c为本申请实施例一提供的芯片封装结构的第一种制作方法中在电连接件的外侧壁形成绝缘层的结构示意图;
图5d为本申请实施例一提供的芯片封装结构的第一种制作方法中将转接板与电连接件背离第一芯片的一端电连接后的结构示意图;
图5e为本申请实施例一提供的芯片封装结构的第一种制作方法中在电连接件的外周填充高导热介质的结构示意图;
图6a为本申请实施例一提供的芯片封装结构的第二种制作方法中第一芯片的结构示意图;
图6b为本申请实施例一提供的芯片封装结构的第二种制作方法中在第一芯片的表面制作出电连接件的结构示意图;
图6c为本申请实施例一提供的芯片封装结构的第二种制作方法中在电连接件的外侧壁形成绝缘层的结构示意图;
图6d为本申请实施例一提供的芯片封装结构的第二种制作方法中在电连接件的外周填充高导热介质的结构示意图;
图6e为本申请实施例一提供的芯片封装结构的第二种制作方法中将转接板与电连接件背离第一芯片的一端电连接后的结构示意图;
图7为本申请一实施例提供的芯片封装结构的第六种结构示意图;
图8为本申请一实施例提供的芯片封装结构的第七种结构示意图;
图9为本申请一实施例提供的芯片封装结构的第八种结构示意图。
附图标记说明:
10-第一芯片;20-转接板;30-电连接件;31-铜柱;32-锡凸点;40-高导热介质;41-延伸部;50-绝缘层;60-阻挡层;70-底填料;80-金属焊盘。
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释,而非旨在限定本申请。
众所周知,芯片对于电子设备而言是最为核心的部分,具有逻辑处理与控制整机正常运行的作用,在电子设备中,该芯片主要以芯片封装结构的形式固定在电路板上,以起到稳定控制芯片封装结构内部的芯片与外部电路板稳定导通的目的。倒装芯片(Flip Chip)既是一种芯片互联技术,又是一种理想的芯片粘接技术,现已成为高端器件及高密度封装领域中经常采用的封装形式。
随着科技的发展以及人类日益增长的需求,倒装芯片封装结构中芯片的集成度需进一步提升,即倒装芯片封装结构中芯片上的连接点即引脚或者芯片的堆叠数量需增多,以满足电子设备在不增大结构尺寸的同时具有更为丰富的功能,与此同时,该倒 装芯片封装结构的功耗也就随之增大。为了满足倒装芯片封装结构的高集成度和高功耗的要求,便需使芯片封装结构的散热效率更佳。
相关技术中,倒装芯片封装结构主要包括芯片、铜柱等电连接件以及基板,其中,电连接件位于芯片与基板之间,且两端分别与芯片与基板电连接,以实现芯片与基板之间电信号的导通,基板上的电连接点与电路板电连接,从而实现倒装芯片封装结构中芯片与电路板的导通。在芯片、电连接件以及基板形成的封装结构的空隙中填充有底填料(under fill,UF),以减小由于热膨胀系数不匹配而引起的基板与芯片之间的应力,从而提高电连接件与基板之间的电连接的可靠性。
一般地,底填料可由环氧树脂和二氧化硅组成,其散热性能较低,无法满足高集成度和高功耗的芯片封装结构,因此会对芯片封装结构中芯片的集成度和功耗密度造成严重制约,从而无法在节约电子设备内部空间的基础上,增大电子设备的功能。为了解决上述问题,相关技术中采用散热性能较高的填料填充在芯片封装结构的空隙中,以提升对芯片的散热效果。
本领域技术人员应当理解的是,通常具有高导热系数的材料会带有一定的导电性。这样,将高导热系数的材料填充在芯片封装结构中铜柱等电连接件的外周时,会使电连接件上的部分或者全部电流扩散至该具有高导热系数的材料内,造成芯片封装结构漏电的情况,从而影响芯片与基板之间的导通稳定性。
基于此,本申请提供一种电子设备、芯片封装结构及其制作方法,通过在电连接件的外周设置高导热介质,并且在高导热介质与电连接件的外侧壁之间设置绝缘层,以在保证芯片的散热效果的同时,防止了电连接件出现漏电的情况,从而确保了芯片与基板等转接板之间的信号导通稳定性。以下分别以不同的场景为例,对芯片封装结构的具体结构进行介绍。
场景一
图1a为本申请一实施例提供的芯片封装结构的第一种结构示意图;图1b为本申请一实施例提供的芯片封装结构的第二种结构示意图;图2为本申请实施例一提供的芯片封装结构的第三种结构示意图;图3为本申请一实施例提供的芯片封装结构的第四种结构示意图;图4为本申请一实施例提供的芯片封装结构的第五种结构示意图。参照图1a至图4所示,本申请提供一种芯片封装结构,包括第一芯片10、转接板20以及位于第一芯片10和转接板20之间的至少一个电连接件30,电连接件30的两端分别与第一芯片10和转接板20电连接,以实现第一芯片10与转接板20之间电信号的导通。
其中,第一芯片10可以是现有技术中的任意一种芯片结构,本申请实施例不对该第一芯片10的具体类型或者结构进行限制,只要能够实现一定逻辑处理或者控制功能即可。
需要说明的是,本申请实施例的转接板20具体是起到实现第一芯片10与外部电路板之间的导通以及承载第一芯片10并将该第一芯片10形成的封装结构稳固在外部电路板上的作用。该转接板20可以是通常意义上的基板(Substrate),重布线层(Redistribution Layer,RDL),硅基板(英文又称为interposer)等。
本申请的芯片封装结构通过转接板20固定在电子设备的电路板上,且该转接板20上的电连接点(金属焊盘)与电路板上对应的电连接点(金属焊盘)电连接,实现第一芯片10与外部电路板的导通,从而保证外部电路板对第一芯片10提供稳定的电流,同时也实现第一芯片10与外部电路板之间的信号传递。
在某些场景下,两个或两个以上的芯片会上下叠加并封装在一起,相邻的两个芯片之间一样可以通过电连接件30进行信号传输。因此,在可能的实施例中,转接板20也可以是一块或多块芯片。需要注意的是,本发明实施例中所述的第一芯片可以是裸片(Die),也可以是由一个或多个裸片封装在一起形成的一种封装结构。
当转接板20为基板时,该基板为第一芯片10的引脚提供在更大的平面范围内进行重排布,以实现多引脚化以及引脚位置重新排布的作用。另外,因基板上的连接点尺寸较大,因此能够将第一芯片10准确的接在外部电路板对应的连接点上,也即是说,该基板起到放大第一芯片10的连接点的尺寸的作用,使得第一芯片10与外部电路板的对接更加准确快捷。当该转接板20为芯片时,为了与上述第一芯片10进行区分,将用于承载该第一芯片10的芯片称为第二芯片,该第二芯片实现第一芯片10与外部电路板的导通,同时实现该芯片封装结构与外部外部电路板的固定。其中,该第二芯片的连接点分布位置及数量等可以与基板一致,以保证第二芯片能够很好地实现与对应的电连接件20以及外部电路板的电连接。
参照图1a所示,本申请实施例还包括位于第一芯片10和转接板20之间的高导热介质40,该高导热介质40围设在电连接件30的外周,且高导热介质40的一端与第一芯片10接触,具体与该第一芯片10朝向转接板20的一侧表面接触,以使第一芯片10上的热量有效地传导至高导热介质40上,继而该高导热介质40将热量快速传递至外部,从而实现该高导热介质40对第一芯片10的有效散热,同时该高导热介质40也位于电连接件30的外周,从而也能够实现对电连接件30的有效散热。
可以理解的是,该高导热介质40也起到支撑第一芯片10以及电连接件30的作用,以减小第一芯片10以及电连接件30的变形程度,进而使得第一芯片10与电连接件30的连接更加稳固。
需要说明的是,高导热介质40的导热系数高于相关技术中填充在芯片封装结构的空隙中的底填料(UF)的导热系数,以提高对第一芯片10以及电连接件30的散热效率,从而满足高集成度及高功耗的芯片封装结构的散热需求。
该高导热介质40可以包括但不限于以下任意一种或多种材料:焊料、银浆(epoxy)、石墨烯。例如,本申请的高导热介质40可以是通过涂覆或者印刷在电连接件30的外周的银浆,以实现对第一芯片10以及电连接件30的有效散热。再例如,该高导热介质40可以是通过涂覆或者印刷在电连接件30的外周的银浆和焊料组成的混合材料。需要说明的是,上述提到的焊料、银浆(epoxy)、石墨烯等材料并非纳米材料。
作为一种可能的实现方式,该高导热介质40可由纳米材料例如纳米线(Nanowire,NW)或者纳米颗粒堆叠形成。其中,该纳米线或者纳米颗粒的组成可以是金属材料(例如Au、Ag、Ge)、半导体材料(例如Si)、金属合金材料(例如Fe-Co)、金属氧化物材料(例如LiNiO
2、CdO)等,本实施例具体不对该纳米线或者纳米颗粒的组成成分进行限制。
当高导热介质40由纳米线组成时,多条纳米线互相缠绕,形成类似毛线团的结构,纳米线的缠绕方式可以是无规则的缠绕。或者,遵循一定的规则缠绕。
图1a所示的则是在高导热介质40由纳米线组成时的另一种缠绕方式,如图1a所示,该纳米线结构的每条纳米线从第一芯片10朝转接板20的方向延伸,多条纳米线沿平行于第一芯片10的方向依次叠层设置,直至达到高导热介质40实际所需的厚度,完成纳米线结构的填充。其中,高导热介质40的厚度是指该高导热介质40沿平行于第一芯片10的延伸方向的两侧表面之间的距离,参照图1a中的d所示。
当高导热介质40由纳米颗粒组成时,多个纳米颗粒可从绝缘层50的表面往远离绝缘层50的方向开始堆叠,直至达到高导热介质40所需的厚度即可,或者多个纳米可以从第一芯片10朝向转接板20的表面开始往转接板20的方向堆叠,直至达到高导热介质40所需的高度即可。需要说明的是,该高导热介质40的高度具体是指该高导热介质40沿垂直于第一芯片10的方向的两端之间的距离,参照图1a中的e所示。
实际应用中,纳米线或者纳米颗粒在堆叠过程中会因堆叠力度、材料本身的结构特性等原因而在各个纳米线之间或者纳米颗粒之间产生空隙,从而导致纳米线或者纳米颗粒堆叠形成的高导热介质40中具有大量空隙,而该空隙会直接影响高导热介质40的结构强度以及导热性能。
基于此,作为该导热介质40的另一种可能的实现方式,可以在该高导热介质40的纳米线之间或者纳米颗粒之间的空隙中填充氧化介质,以增强各个纳米线或者纳米颗粒之间的结合力度,从而增强纳米材料形成的高导热介质40的结构稳定性,进而保证纳米导热介质的导热性能,同时也提高了其对第一芯片10以及电连接件30的结构支撑效果。可以理解的是,该示例中,高导热介质40由多个纳米线以及设置在多个纳米线之间的氧化介质组成,或者,高导热介质40由多个纳米颗粒以及设置在多个纳米颗粒之间的氧化介质组成。
为了提高氧化介质与纳米材料的相容性,该氧化介质中除氧外的其他组成元素可以与纳米材料的主要组成元素一致,这样便可增强氧化介质与纳米材料之间的结合力度,进而增强纳米线或者纳米颗粒之间的结合力度。例如,当纳米线为银纳米线时,该氧化介质为氧化银;当纳米线为钛纳米线时,该氧化介质为氧化钛;当纳米线为Si纳米线时,该氧化介质为二氧化硅。
另外,该氧化介质中除氧外的其他组成元素可以与纳米材料的主要组成元素一致,也能够进一步保证最终的高导热介质40的导热性能。
继续参照图1a所示,本发明实施例的结构中还包括绝缘层50。该绝缘层50包裹电连接件30的侧部表面,用于将高导热介质40和电连接件30隔离。例如,该绝缘层50包裹在电连接件30的部分侧壁上,高导热介质40包裹在绝缘层50背离电连接件30的表面即绝缘层50的外侧表面。如此设置,避免了电连接件30上的电流扩散至高导热介质40上而造成漏电的情况,从而不仅确保了第一芯片10与转接板20之间的导通稳定性,而且不会对芯片封装结构外部的元器件造成电信号的干扰。
实际应用中,该电连接件30的数量可以是一个,也可以是多个。当电连接件30的数量为1个时,在该电连接件30的外周围设高导热介质40,同时在高导热介质40与电连接件30之间设置绝缘层50,以防止电连接件20上的电流扩散至高导热介质40 上而影响该电连接件20的电传输稳定性。当电连接件30为多个时,多个电连接件30在第一芯片10的底部成矩阵排列,在相邻电连接件30之间的间隔中填充有高导热介质40,这样,一方面,填充在相邻两个连接件30之间的高导热介质40能够同时对两侧的电连接件30提供散热,从而有效提高了高导热介质40对每个电连接件30的散热效率,另一方面,填充在相邻电连接件30之间的高导热介质40对两个电连接件30以及第一芯片10也起到支撑的作用,从而使得电连接件30能够更加稳定地支撑在第一芯片10与转接板20之间,进而确保了第一芯片10与转接板20之间的导通。
通常,具有高导热性能的材料会具有导电性,因此,为了在实现对第一芯片10的有效散热的同时,避免具有一定导电性能的高导热介质40直接与电连接件30接触,本实施例在位于相邻两个电连接件30之间的高导热介质40与其中任意一个电连接件30之间设置绝缘层50,即通过该绝缘层50将高导热介质40与每一个电连接件30隔开,使得相邻的电连接件30之间不会因高导热介质40的导电性而发生短路,进一步保证每个电连接件30对各自对应的电信号的正常导通,同时又能够保证高导热介质40对第一芯片10的有效散热。
可以理解的是,因高导热介质40的一端延伸至与第一芯片10的内表面(即朝向转接板20的表面)接触,例如,该高导热介质40的一端延伸至电连接件30靠近第一芯片10的一端,则绝缘层50的第一端也延伸至电连接件30靠近第一芯片10的一端,以避免高导热介质40与电连接件30的侧壁直接接触。
需要说明的是,绝缘层50的第一端是指该绝缘层50靠近第一芯片10的一端,绝缘层50的第二端是指该绝缘层50靠近转接板20的一端。
实际应用中,为实现第一芯片10与转接板20之间的电性导通,电连接件30可以是微凸点(Bump)或者可控坍塌芯片互连结构(Controlled Collapse Chip Connection,简称C4),如图1b所示,其中,该可控坍塌芯片互连结构又称可控坍塌凸点。其中,图1b中,电连接件30可以是微凸点,也可以是可控坍塌凸点。本申请中的微凸点和可控坍塌凸点的结构和组成成分可直接参照现有技术中记载的内容。
参照图1a所示,在一些示例中,该电连接件30还可以为铜柱(Cu Pillar,CuP)31以及设置在铜柱31一端的锡凸点32形成的结构,其中,铜柱31通过锡凸点32电连接在转接板20上。以上任意一种类型的电连接件30均是通过焊接的方式固定在转接板20上的。而本领域技术人员应当理解的是,焊接过程需保证微凸点或者可控坍塌凸点等电连接件靠近转接板20的一端需在高温下具有一定的熔融性以及流动性,这样在焊接的过程中,电连接件30靠近转接板20的一端才能够在高温的作用下在转接板20的表面润湿铺展,并在冷却后稳定地焊接在该转接板20上。
基于此,本申请实施例的绝缘层50的第二端延伸至与转接板20之间具有预设间距a,如图1a和图1b所示。例如,电连接件30靠近转接板20的一端侧壁裸露,绝缘层50未覆盖在电连接件30靠近转接板20的一端侧壁。这样电连接件30焊接在转接板20上时,该电连接件30的末端能够有效地进行水平方向上的润湿铺展,从而进一步确保该电连接件30与转接板20之间的焊接稳固性。需要说明的是,当绝缘层50未覆盖在电连接件30靠近转接板20的一端侧壁时,高导热介质40朝向转接板20的一端不会超过绝缘层50朝向转接板20的一端,例如,高导热介质40不会与电连接件 30裸露的一端侧壁接触。
可以理解的是,该预设间距a的具体数值可根据实际焊接需求进行确定,本申请实施例对此不做限制。
本申请实施例中,以电连接件30包括铜柱31以及设置在铜柱30一端的锡凸点32为例,对绝缘层50的设置方式进行说明。参照图1a所示,电连接件30的铜柱31的一端与第一芯片10电连接,锡凸点32连接在铜柱31靠近转接板20的一端,例如,该锡凸点32位于铜柱31与转接板20之间且与转接板20电连接,从而实现第一芯片10与转接板20之间的电导通。其中,该锡凸点32为锡制成的焊接锡凸点即锡焊锡凸点,以确保铜柱30与锡凸点32均为电导体。因铜柱31本身不能够通过焊接的方式连接在转接板30上,因此在该铜柱31的底端设置锡制成的锡凸点32,以通过将该锡凸点32焊接在转接板20上,实现铜柱32与转接板20之间的连接与导通。
可以理解的是,该锡凸点32与转接板20焊接的过程中,首先要在高温作用下使锡凸点32在转接板20上进行适当润湿铺展,才能够将该锡凸点32稳定的焊接在转接板20上,因此,如图1a所示,本申请实施例的绝缘层50的第二端可延伸至铜柱31靠近转接板20的一端,例如,绝缘层50将铜柱31的外侧壁完全覆盖,但是锡凸点32可以未被绝缘层50覆盖,这样铜柱31下方的锡凸点32在绝缘层50处完全暴露,以防止该绝缘层50对锡凸点32的润湿铺展进行阻碍。
当然,在其他一些示例中,绝缘层50的第二端也可以延伸到锡凸点32的部分外侧面,例如,锡凸点32靠近铜柱31的一端外侧面可以覆盖绝缘层50,绝缘层50部分覆盖锡凸点32的外侧面。
在一种可能的实现方式中,如图3所示,该绝缘层50的第二端还可与铜柱31靠近转接板20的一端之间具有间隔b,例如,该绝缘层50还可以覆盖铜柱31沿轴线方向的部分区域。本申请实施例不对绝缘层50在铜柱31上的覆盖面积进行限制,只要能够保证对高导热介质40与铜柱31进行有效隔离即可。
如图1a和图4所示,高导热介质40设置时,高导热介质40靠近转接板20的一端可以延伸至与绝缘层50的第二端(即绝缘层朝向转接板20的一端)齐平,例如,该高导热介质40靠近转接板20的一端与转接板20之间的距离c等于绝缘层50的第二端与转接板20之间的距离a,这样,在增大该高导热介质40的填充量的同时,又防止了该高导热介质40伸出绝缘层50的第二端而与电连接件30的表面直接接触的情况发生,从而不仅增大了该高导热介质40对第一芯片10以及电连接件30的散热效率,而且确保了电连接件30不会因高导热介质40而发生漏电或者相邻电连接件30之间短路的情况。需要说明的是,参照图1a所示,a为指绝缘层50的第二端与转接板20之间的距离,c是指高导热介质40靠近转接板20的一端与转接板20之间的距离。
依然以电连接件30包括铜柱31和连接在铜柱31一端的锡凸点32为例进行说明,当绝缘层50的第二端延伸至铜柱31靠近转接板20的一端时,高导热介质40的一端可以延伸至与绝缘层50的第二端齐平,以增大高导热介质40的填充面积及填充量,使得第一芯片10以及电连接件30上更多的热量能够传递至高导热介质40内,并随该高导热介质40散出至外部,且不会造成电连接件30漏电以及短路的情况。另外,也增强了高导热介质40对铜柱31以及第一芯片10的支撑强度。
在一些示例中,高导热介质40靠近转接板20的一端还可高于绝缘层50的第二端,例如,如图2所示,该高导热介质40靠近转接板20的一端与转接板20之间的距离大于绝缘层50的第二端与转接板20之间的距离,以进一步确保该高导热介质40不会直接接触到电连接件30的表面。例如,当绝缘层50的第二端延伸至铜柱31靠近转接板20的一端时,高导热介质40的一端可以延伸至与铜柱31靠近转接板20的一端之间具有一定间距,以保证绝缘层50对高导热介质40与铜柱31之间的有效隔离。
应当理解,高导热介质40靠近转接板20的一端与绝缘层50的第二端之间的距离可根据实际的散热需求进行调整。
本申请实施例中的绝缘层50可以为氧化铜层或氧化锡层。在一些示例中,该绝缘层50还可以是由绝缘材料制成的干膜(dry film)或者钝化层,其中,该绝缘材料可以是聚氯乙烯、丁苯橡胶、聚酰胺等聚合物,本实施例不对绝缘材料的成分进行限制。
其中,绝缘层50为氧化铜层时,绝缘层50的形成过程可以为:将铜柱31通过高温或加湿气的方式,在铜柱31表面氧化形成一层氧化铜层,该氧化铜层作为绝缘层50。
其中,氧化锡层作为绝缘层的制作过程是先在电连接件30的表面浸锡,然后将其氧化为氧化锡,从而在该电连接件30的表面形成氧化锡层,并作为绝缘层。其中,在该电连接件30上直接浸锡,不可避免地会使得锡与电连接件30中的金属化合物例如铜柱31表面的CuP发生反应形成CuSn,对电连接件30的机械结构以及该电连接件30的电性能造成影响。因此,参照图4所示,本申请在电连接件30的外侧壁与氧化锡层(即绝缘层50)之间设置阻挡层60,以防止锡与电连接件30中的金属例如铜过度反应生成对电连接件30的机械结构以及电性能不利的金属间化合物,从而进一步确保电连接件30的结构稳定性以及对第一芯片10与转接板20的稳定导通。其中,该阻挡层60可以是Ni(镍),Ti(钛),W(钨),TaN(氮化钽)制成的膜层。通过Ni,Ti,W,TaN制成的膜层能够实现对锡与电连接件30中金属化合物的有效阻隔,从而保证氧化锡的顺利生长。
本申请实施例还提供一种芯片封装结构的制作方法,该制备方法具体可包括以下步骤。
图5a为本申请实施例一提供的芯片封装结构的第一种制作方法中第一芯片的结构示意图;图5b为本申请实施例一提供的芯片封装结构的第一种制作方法中在第一芯片的表面制作出电连接件的结构示意图;图5c为本申请实施例一提供的芯片封装结构的第一种制作方法中在电连接件的外侧壁形成绝缘层的结构示意图;图5d为本申请实施例一提供的芯片封装结构的第一种制作方法中将转接板与电连接件背离第一芯片的一端电连接后的结构示意图;图5e为本申请实施例一提供的芯片封装结构的第一种制作方法中在电连接件的外周填充高导热介质的结构示意图。参照图本申请实施例提供的芯片封装结构的第一种制备方法,具体如下:
S101、提供第一芯片10。
参照图5a所示,提供第一芯片10,其中,该第一芯片10可直接采用现有的芯片结构,也可以先获取一块用于制作芯片10的硅晶片,然后采用切割设备对该硅晶片进行切割,以形成所需第一芯片10。或者,第一芯片10可以为晶圆(wafer),该晶圆 可以在封装完成时进行切割形成所需的芯片。
S102、在第一芯片10的一面上制备至少一个电连接件30,且电连接件30与第一芯片10电连接。
参照图5b所示,先将第一芯片10放置在制备平台上,然后在该第一芯片10的上表面开始沉积电连接件30,直至该电连接件30达到所需高度。通过在第一芯片10的上表面开始往上即图5b中箭头d的方向沉积电连接件30,使得电连接件30的沉积过程更加稳定可控。
其中,可以在第一芯片10的上表面沉积一个或者多个电连接件30,当电连接件30为多个时,多个电连接件30沿平行于第一芯片10的方向间隔设置。
当电连接件30包括铜柱31以及设置在铜柱31一端的锡凸点32时,S102可以包括:
先在第一芯片10的上表面沿箭头a的方向沉积至少一个铜柱31,当铜柱31达到一定高度时,在铜柱31的顶端溅射锡,以形成锡凸点32。可以理解,该锡凸点32与铜柱31的顶端电连接。
S103、在电连接件30的外侧壁上形成绝缘层50,该绝缘层50至少覆盖电连接件30的部分外侧壁。
参照图5c所示,在电连接件30的外侧壁上形成绝缘层50,该绝缘层50可以通过氧化、溅射或印刷等方式形成在电连接件30的外侧壁上。
例如,电连接件30的外侧壁上形成绝缘层50可以包括:
通过高温或者湿气等方法对电连接件30的外侧壁进行氧化,以在电连接件30的外侧壁上形成氧化层,将氧化层作为绝缘层50。例如,当电连接件30包括铜柱31以及设置在铜柱31一端的锡凸点32时,对该铜柱31的表面的CuP进行氧化,形成氧化铜层,将该氧化铜层作为绝缘层50。可以看出,该绝缘层50可覆盖铜柱31的全部或者部分侧壁。
在一些示例中,在电连接件30的外侧壁上形成绝缘层50的过程也可包括:在电连接件30的外侧壁上粘贴绝缘干膜或绝缘钝化层,将绝缘干膜或绝缘钝化层作为绝缘层。其中,该绝缘干膜或者绝缘钝化层可采用聚氯乙烯、丁苯橡胶、聚酰胺等聚合物材料制成。
在一种可能的实现方式中,在电连接件30的外侧壁上形成绝缘层50的过程具体也可包括:
a1)、将电连接件30的外侧壁浸锡,以在电连接件30的外侧壁上形成锡层;
b1)、将锡层进行氧化,形成氧化锡层,将该氧化锡层作为绝缘层50。
继续以电连接件30包括铜柱31以及设置在铜柱31一端的锡凸点32为例,首先在铜柱31的表面浸锡,然后将其氧化成SnOx即氧化锡,并作为绝缘层50。
为了防止在电连接件30的表面浸锡时,该锡与电连接件30表面的金属例如铜发生反应生成的金属间化合物对电连接件30的机械结构以及电性能造成不利的影响,上述在电连接件30的外侧壁上形成绝缘层50的过程还可具体包括:
a2)、在电连接件30的外侧壁上通过电镀或溅射工艺形成阻挡层60(参见图4所示);
b2)、对电连接件30外侧壁的阻挡层60进行浸锡,以在阻挡层60的外侧壁形成 锡层;
c)、将锡层进行氧化,形成氧化锡层,将该氧化锡层作为绝缘层50。
例如,首先在铜柱31的CuP表面上溅射阻挡层60,然后对该阻挡层60进行浸锡,最后将锡氧化成SnOx即氧化锡,并作为绝缘层50,从而防止了CuSn过快生长,保证电连接件30的结构稳定性以及电学性能。
S104、提供转接板20,将转接板20与电连接件30背离第一芯片10的一端电连接,以使第一芯片10与转接板20通过该电连接件30实现导通。
参照图5d所示,将转接板20与电连接件31的一端连接,例如,可以将转接板20与锡凸点32的焊接连接。其中,该转接板20可以基板,也可以是第二芯片。应当理解,该基板或者第二芯片可以直接采用现有技术中的基板或者第二芯片。
可以理解的是,当电连接件30包括铜柱31以及设置在铜柱31一端的锡凸点32时,该转接板20与锡凸点32背离第一芯片10的一端电连接。
S105、在第一芯片10和转接板20之间填充高导热介质40,形成芯片封装结构。
参照图5e所示,可从第一芯片10的上表面即朝向转接板20的表面开始沿箭头d的方向向上涂覆或者印刷高导热介质40,直至高导热介质40到达绝缘层50的第二端即靠近转接板20的一端或者高导热介质40的顶端与绝缘层50的第二端之间具有间隔即可。
其中,高导热介质40围设在电连接件30的外周,且该高导热介质40的一端与第一芯片10接触,绝缘层50将高导热介质40和电连接件30隔开,以防止电连接件30漏电或者相邻点连接件30短路。
应当理解的是,当高导热介质40为纳米线或者纳米颗粒堆叠形成的纳米材料时,在将高导热介质40围设在电连接件30的外周之后,还可继续在纳米材料的空隙中填充氧化介质,以增强纳米材料中纳米线或者纳米颗粒之间的结合力,从而提高纳米材料堆叠形成的高导热介质40的结构强度。
图6a为本申请实施例一提供的芯片封装结构的第二种制作方法中第一芯片的结构示意图;图6b为本申请实施例一提供的芯片封装结构的第二种制作方法中在第一芯片的表面制作出电连接件的结构示意图;图6c为本申请实施例一提供的芯片封装结构的第二种制作方法中在电连接件的外侧壁形成绝缘层的结构示意图;图6d为本申请实施例一提供的芯片封装结构的第二种制作方法中在电连接件的外周填充高导热介质的结构示意图;图6e为本申请实施例一提供的芯片封装结构的第二种制作方法中将转接板与电连接件背离第一芯片的一端电连接后的结构示意图。
参照图6a~图6e所示,本实施例提供的第二种制备方法中的S101~S103的制作过程以及顺序与上述第一种制备方法完全一致,S101~S103的具体制作过程可直接参照上述第一种制备方法的内容。与上述第一种制备方法不同的是,本实施例提供的第二种制备方法的S104和S105分别为:
S104、在第一芯片10具有电连接件30的一面上设置高导热介质40,
如图6d所示,该高导热介质40围设在形成有绝缘层50的电连接件30的外周,且绝缘层50将高导热介质40和电连接件30隔开。
S105、提供转接板20,转接板20与电连接件30背离第一芯片10的一端电连接, 形成芯片封装结构。
如图6e所示,可以理解的是,上述芯片封装结构的第一种制备方法与第二种制备方法仅是在绝缘层50制作完成后,调换了高导热介质40和固定转接板20的顺序。
需要说明的是,芯片封装结构的上述第一种制备方法与第二种制备方法中均是直接在第一芯片10上进行电连接件30以及高导热介质40等结构的制作。
在其他一些制备方法的示例中,还可以直接提供硅晶片,在硅晶片上进行电连接件30、绝缘层50以及高导热介质40的制作,在高导热介质40填充至电连接件30的外周后,再将硅晶片切割成第一芯片10。其中,该高导热介质40可以是在固定转接板20之前,也可以是在固定转接板20之后,换句话说,该硅晶片的切割可以是在转接板20固定在电连接件30的一端之前,高导热介质40填充至电连接件30的外周之后进行的,该硅晶片的切割也可以是在所有的制作步骤的最后进行。
当然,在另外一些制备方法的示例中,还可以直接提供硅晶片,然后在电连接件30和绝缘层50等制作完成后,在高导热介质40填充之前对硅晶片进行切割,继而在切割形成的第一芯片10与电连接件30之间的空隙中填充高导热介质40。可以理解的是,该硅晶片的切割可以是在转接板20固定在电连接件30的一端之后,高导热介质40填充至电连接件30的外周之前进行的,也可以是在高导热介质40以及转接板20均未设置时,先切割硅晶片,以使后续的高导热介质40的填充以及转接板20的固定均是在第一芯片10上进行。
场景二
图7为本申请一实施例提供的芯片封装结构的第六种结构示意图。
参照图7所示,在场景一的基础上,本申请的芯片封装结构还包括底填料70,该底填料70的导热系数小于高导热介质40的导热系数。该底填料70的导热系数一般低于3W/mK甚至1W/mK。
本申请的底填料70填充在绝缘层50与转接板20之间以及填充在高导热介质40与转接板20之间,以使该底填料70能够对绝缘层50和高导热介质40底部起到支撑的作用,从而减小由于热膨胀系数不匹配而引起的转接板20与第一芯片10之间的应力,避免电连接件30与转接板20之间的焊盘断裂,提高电连接件30与转接板20之间的焊接可靠性以及绝缘层50和高导热介质60的结构稳定性。同时,因底填料70的导热系数较小,因而不会具有导电性能,因此不会造成电连接件30发生漏电或者短路的情况。
当电连接件30包括铜柱31以及设置在铜柱31一端的锡凸点32时,部分底填料70延伸至与锡凸点32的外侧面接触,以进一步提高封装后的芯片结构中锡凸点32的结构稳定性,从而进一步确保锡凸点32与转接板20的电连接可靠性。
其中,该底填料70可以直接采用现有的芯片封装结构的填料,例如该底填料可以由环氧树脂和二氧化硅组成。
实际应用中,因底填料70的材料特殊性,该底填料70会具有往上攀爬的性能,使得该底填料70可攀爬至高导热介质40的外侧表面,从而起到加强高导热介质40的结构稳固性,使得该高导热介质40具有向封装结构中心收拢的趋势,进而也保证高 导热介质40对第一芯片10以及电连接件30的结构支撑作用,使得整个芯片封装结构更加稳固。在一些示例中,该底填料70可从转接板20朝向第一芯片10的一侧攀爬至高导热介质40相对于转接板20的2/3处。
可以理解的是,该底填料70的填充需在转接板20电连接在电连接件30背离第一芯片10的一端上以及高导热介质40填充在电连接件30的外周后进行的。
具体地,该芯片封装结构的第五种结构的制作方法可直接在上述芯片封装结构的第一种制作方法或者第二种制作方法的基础上进行,具体在形成芯片封装结构之前进行如下步骤:在绝缘层50与转接板20之间的间隔以及高导热介质40与转接板20之间的间隔内中填充底填料70,其中,该底填料70与锡凸点32的外侧面接触。
场景三
实际应用中,作为转接板20的基板或者第二芯片上开设有安装孔(图中未示出),该安装孔内设置有接地连接点(亦称VSS、接地引脚)或电源连接点(亦称VDD、接地引脚),其中,该接地连接点VSS伸出安装孔背离第一芯片10的一侧即伸出转接板20的外侧并用于与接地线,以保护转接板20的用电安全。电源连接点同样伸出安装孔背离第一芯片10的一侧即伸出转接板20的外侧并用于与外部电源连接,以为芯片封装结构提供电信号。
为了实现对接地连接点或电源连接点的散热,本申请实施例可在以上任意一种芯片封装结构的基础上,将高导热介质40朝向转接板20的一端与转接板20上的接地连接点或者电源连接点接触,以将接地连接点或者电源连接点的热量传导至高导热介质40中,继而通过该导热介质40散热至外部,从而保证该转接板20的接地连接点或者电源连接点的电学性能。
图8为本申请一实施例提供的芯片封装结构的第七种结构示意图。参照图8所示,作为芯片封装结构的第七种结构,可以在接地连接点或者电源连接点朝向第一芯片10的一端设置金属焊盘80,该高导热介质40朝向转接板20的一端可与该金属焊盘80接触,以使接地连接点或者电源连接点的热量通过金属焊盘80传导至高导热介质40上。
其中,金属焊盘80可为铜焊盘或者锡焊盘或者其他导热性能较高的金属焊盘。
本申请的芯片封装结构的第六种结构的制作方法与上述提到的芯片封装结构的任意一种制备方法的区别在于,该第六种结构的制作方法在转接板20与电连接件30背离第一芯片10的一端电连接之前,还包括:
在转接板20朝向第一芯片10的一面上形成金属焊盘80,金属焊盘80的一端与转接板20上的接地连接点或电源连接点电连接,金属焊盘80的另一端在转接板20与电连接件30连接时与高导热介质40接触。
应当理解的是,图8示出的芯片封装结构的第七种结构仅是在芯片封装结构的第六种结构即图7的基础上做的改进,但不能排除本申请实施例的芯片封装结构的第七种结构也可以是在以上其他几种结构上做的改进。例如,在上述提到的芯片封装结构的第一种结构即图1a的基础上,在转接板20的接地连接点或电源连接点朝向第一芯片10的一端设置金属焊盘80,高导热介质40靠近转接板20的一端与金属焊盘80接 触,以使转接板20的接地连接点或电源连接点上的热量通过金属焊盘80传递至高导热介质40上,实现对转接板20的接地连接点或电源连接点的有效散热。
参照图8所示,在一些示例中,该金属焊盘80可延伸至与高导热介质40靠近转接板20的一端接触,而不对高导热介质40靠近转接板20的一端进行延伸。当然,在其他示例中,也可对高导热介质40靠近转接板20的一端的部分进行延伸,以形成下文即将提到的延伸部41,该延伸部41与金属焊盘80接触。
图9为本申请一实施例提供的芯片封装结构的第八种结构示意图。参照图9所示,为提高高导热介质40对转接板20上的接地连接点或者电源连接点的散热效率,芯片封装结构的第八种结构是将高导热介质40靠近转接板20的一端的部分区域往靠近转接板20的方向延伸,形成延伸部41,该延伸部41的一端延伸至接地连接点或者电源连接点处,并与接地连接点或者电源连接点直接接触,以减小高导热介质40与转接板20内接地连接点或者电源连接点之间的热传导阻力,从而能够将接地连接点或者电源连接点处的热量快速有效地传递至高导热介质40上,并随高导热介质40传递至外部环境,进一步保证转接板40的工作性能。
需要说明的是,高导热介质40靠近转接板20的一端的延伸部41或者金属焊盘80均不能与电连接件30的外表面接触,以防止漏电以及短路的情况发生。
例如,如图8和图9所示,当绝缘层50的第二端延伸至与铜柱31靠近转接板20的一端齐平,且在绝缘层50的第二端与转接板20之间以及高导热介质40靠近转接板20的一端与转接板20之间填充有底填料70时,该高导热介质40一端的延伸部41或者金属焊盘80均不会与锡凸点32以及任意一个铜柱31的外侧壁直接接触。
当在图1a所示的第一种结构的基础上,高导热介质40靠近转接板20的一端通过金属焊盘80或者延伸部41与转接板20上的接地连接点或者电源连接点接触时,也需保证金属焊盘80或者延伸部41的外侧壁不与锡凸点32接触。
本申请实施例不对在其他结构的芯片封装结构基础上设置金属焊盘80或者延伸部41的外侧壁的情况进行赘述,只要确保金属焊盘80或者延伸部41的外侧壁不与电连接件30的外侧壁直接接触即可。
本申请实施例还提供一种电路板,该电路板包括以上任意场景下的一种芯片封装结构。
本申请实施例还提供一种电子设备,该电子设备包括以上任意场景下的其中任意一种芯片封装结构。
通过在电子设备中设置上述芯片封装结构,因芯片封装结构的散热效果佳,从而可在电子设备内设置集成度高的芯片封装结构,这样在增强电子设备功能的同时,缩小了芯片封装结构在电子设备内的占用尺寸,不仅会给电子设备中其他元器件的安装提供有效的空间,而且也可缩小整个电子设备的尺寸,优化电子设备的体验效果。与此同时,也保证了电子设备中信号传输的稳定性,确保电子设备的正常工作。
需要说明的是,本申请实施例提供的电子设备可以包括但不限于为手机、平板电脑、笔记本电脑、超级移动个人计算机(ultra-mobile personal computer,简称:UMPC)、手持计算机、对讲机、上网本、POS机、个人数字助理(personal digital assistant,简称:PDA)、可穿戴设备、虚拟现实设备等具有芯片封装结构的移动或固定终端。
在本申请实施例的描述中,需要说明的是,除非另有明确的规定和限定,术语“安装”、“相连”、“连接”应作广义理解,例如,可以是固定连接,也可以是通过中间媒介间接相连,可以是两个元件内部的连通或者两个元件的相互作用关系。对于本领域的普通技术人员而言,可以根据具体情况理解上述术语在本申请实施例中的具体含义。
本申请实施例的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象,而不必用于描述特定的顺序或先后次序。
Claims (27)
- 一种芯片封装结构,其特征在于,包括:第一芯片、转接板以及位于所述第一芯片和所述转接板之间的至少一个电连接件,所述电连接件的两端分别与所述第一芯片和所述转接板电连接;还包括:位于所述第一芯片和所述转接板之间且围设在所述电连接件外周的高导热介质,所述高导热介质的一端与所述第一芯片接触,所述高导热介质与所述电连接件之间设置绝缘层,所述绝缘层用于将所述高导热介质与所述电连接件隔开。
- 根据权利要求1所述的芯片封装结构,其特征在于,所述绝缘层包裹在所述电连接件的至少部分侧壁上,所述高导热介质包裹在所述绝缘层背离所述电连接件的表面上。
- 根据权利要求1所述的芯片封装结构,其特征在于,所述电连接件为多个,多个所述电连接件间隔设置,且相邻所述电连接件之间的间隔中填充有所述高导热介质。
- 根据权利要求1-3任一项所述的芯片封装结构,其特征在于,所述绝缘层的第一端延伸至所述电连接件靠近所述第一芯片的一端,所述绝缘层的第二端延伸至与所述转接板之间具有预设间距。
- 根据权利要求1-4任一项所述的芯片封装结构,其特征在于,所述高导热介质靠近所述转接板的一端与所述转接板的距离大于或者等于所述绝缘层的第二端与所述转接板之间的距离。
- 根据权利要求1-5任一项所述的芯片封装结构,其特征在于,所述芯片封装结构还包括底填料,所述底填料的导热系数小于所述高导热介质的导热系数;所述底填料填充在所述绝缘层与所述转接板之间以及填充在所述高导热介质与所述转接板之间。
- 根据权利要求1-6任一项所述的芯片封装结构,其特征在于,所述电连接件为微凸点或可控坍塌凸点中的任意一种。
- 根据权利要求6所述的芯片封装结构,其特征在于,所述电连接件包括:铜柱以及与所述铜柱连接的锡凸点,所述铜柱的一端与所述第一芯片电连接,所述锡凸点设置在所述铜柱与所述转接板之间且与所述转接板电连接;所述绝缘层的第二端延伸至所述铜柱靠近转接板的一端;部分所述底填料延伸至与所述锡凸点的外侧面接触。
- 根据权利要求1-8任一项所述的芯片封装结构,其特征在于,所述高导热介质包括以下一种或者多种材料:焊料、银浆、石墨烯。
- 根据权利要求1-8任一项所述的芯片封装结构,其特征在于,所述高导热介质由纳米线或纳米颗粒堆叠形成;且所述纳米线之间或所述纳米颗粒之间的空隙内填充有氧化介质。
- 根据权利要求1-10任一项所述的芯片封装结构,其特征在于,所述绝缘层为氧化铜层;或者,所述绝缘层为氧化锡层;或者,所述绝缘层为绝缘材料制成的干膜或钝化层。
- 根据权利要求11所述的芯片封装结构,其特征在于,所述绝缘层为氧化锡层,且所述氧化锡层与所述电连接件的外侧壁之间设置阻挡层。
- 根据权利要求12所述的芯片封装结构,其特征在于,所述阻挡层为Ni,Ti,W,TaN制成的膜层。
- 根据权利要求1-13任一项所述的芯片封装结构,其特征在于,所述转接板上开设有安装孔,所述安装孔内设置有接地连接点或电源连接点,所述高导热介质的第二端的至少部分与所述接地连接点或电源连接点接触。
- 根据权利要求14所述的芯片封装结构,其特征在于,所述转接板上设置有金属焊盘,所述金属焊盘的一端伸入至所述安装孔内并与所述接地连接点或电源连接点接触,所述金属焊盘的另一端与所述高导热介质接触。
- 根据权利要求1-15任一项所述的芯片封装结构,其特征在于,所述转接板为第二芯片;或者,所述转接板为基板。
- 一种电子设备,其特征在于,包括如权利要求1-16任一项所述的芯片封装结构。
- 一种芯片封装结构的制作方法,其特征在于,所述方法包括:提供第一芯片;在所述第一芯片的一面上制备至少一个电连接件,且所述电连接件与所述第一芯片电连接;在所述电连接件的外侧壁上形成绝缘层,所述绝缘层至少覆盖所述电连接件的部分外侧壁;在所述第一芯片具有所述电连接件的一面上设置高导热介质,所述高导热介质围设在所述电连接件的外周,且所述绝缘层将所述高导热介质和所述电连接件隔开;提供转接板,所述转接板与所述电连接件背离所述第一芯片的一端电连接,形成芯片封装结构。
- 一种芯片封装结构的制作方法,其特征在于,所述方法包括:提供第一芯片;在所述第一芯片的一面上制备至少一个电连接件,且所述电连接件与所述第一芯片电连接;在所述电连接件的外侧壁上形成绝缘层,所述绝缘层至少覆盖所述电连接件的部分外侧壁;提供转接板,所述转接板与所述电连接件背离所述第一芯片的一端电连接;在所述第一芯片和所述转接板之间填充高导热介质,形成芯片封装结构,其中,所述高导热介质围设在电连接件的外周,且所述高导热介质的一端与所述第一芯片接触,所述绝缘层将所述高导热介质和所述电连接件隔开。
- 根据权利要求18或19所述的制作方法,其特征在于,所述在所述电连接件的外侧壁上形成绝缘层,包括:对所述电连接件的外侧壁进行氧化,以在所述电连接件的外侧壁上形成氧化层, 所述氧化层作为所述绝缘层。
- 根据权利要求18或19所述的制作方法,其特征在于,所述在所述电连接件的外侧壁上形成绝缘层,包括:将所述电连接件的外侧壁浸锡,以在所述电连接件的外侧壁上形成锡层;将所述锡层进行氧化,形成氧化锡层,所述氧化锡层作为所述绝缘层。
- 根据权利要求21所述的制作方法,其特征在于,所述将所述电连接件的外侧壁浸锡之前,还包括:在所述电连接件的外侧壁上通过电镀或溅射工艺形成阻挡层;所述将所述电连接件的外侧壁浸锡,以在所述电连接件的外侧壁上形成锡层,包括:对所述电连接件外侧壁上的所述阻挡层进行浸锡,在所述阻挡层上形成所述锡层。
- 根据权利要求18或19所述的制作方法,其特征在于,所述在所述电连接件的外侧壁上形成绝缘层,包括:在所述电连接件的外侧壁上粘贴绝缘干膜或绝缘钝化层,所述绝缘干膜或所述绝缘钝化层作为所述绝缘层。
- 根据权利要求18-23任一项所述的制作方法,其特征在于,所述高导热介质为纳米材料;所述高导热介质围设在所述电连接件的外周之后,还包括:在所述纳米材料之间的空隙中填充氧化介质。
- 根据权利要求18-24任一项所述的制作方法,其特征在于,在所述第一芯片的一面上制备至少一个电连接件,包括:在所述第一芯片的一面上制备至少一个铜柱;所述铜柱朝向转接板的一端形成与所述铜柱电连接的锡凸点;所述转接板与所述电连接件背离所述第一芯片的一端电连接,包括:所述转接板与所述锡凸点背离所述第一芯片的一端电连接。
- 根据权利要求25所述的制作方法,其特征在于,所述绝缘层朝向所述转接板的一端与所述转接板之间存在间隔,且所述高导热介质朝向转接板的一端与所述转接板之间的距离大于或等于所述绝缘层到所述转接板的距离;所述形成芯片封装结构之前,还包括:在所述绝缘层与所述转接板之间的间隔以及所述高导热介质与所述转接板之间的间隔内中填充底填料,且所述底填料与所述锡凸点的外侧面接触。
- 根据权利要求18-26任一项所述的制作方法,其特征在于,所述转接板与所述电连接件背离所述第一芯片的一端电连接之前,还包括:在所述转接板朝向所述第一芯片的一面上形成金属焊盘,所述金属焊盘的一端与所述转接板上的接地连接点或电源连接点电连接,所述金属焊盘的另一端用于在所述转接板与所述电连接件连接时与所述高导热介质接触。
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