WO2021147502A1 - Method for global time synchronization by combining data packet and short pulse - Google Patents

Method for global time synchronization by combining data packet and short pulse Download PDF

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Publication number
WO2021147502A1
WO2021147502A1 PCT/CN2020/131024 CN2020131024W WO2021147502A1 WO 2021147502 A1 WO2021147502 A1 WO 2021147502A1 CN 2020131024 W CN2020131024 W CN 2020131024W WO 2021147502 A1 WO2021147502 A1 WO 2021147502A1
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clock count
slave device
master device
clock
count value
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PCT/CN2020/131024
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French (fr)
Chinese (zh)
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王非
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南京深视光点科技有限公司
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

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  • the present invention relates to a global time synchronization (global time synchronization) technology, in particular to an implementation method that allows a master device to send a clock counting data packet (Data Packet, or data packet) combined with a short pulse (pulse), so that the master device reduces
  • the clock sent to the subsystem to be synchronized counts the number of data packets, thereby reducing the amount of data sent, a global clock synchronization method that combines data packets and short pulses.
  • the global clock can ensure the synchronization of the coordinated work between the hardware devices (chip modules or circuit boards) in the system.
  • the data communication between the devices needs to complete the synchronization of the global beat by sending and receiving data packets.
  • the data packet sending device usually timestamps the data packet (Timestamp), so that each data packet sending device must have its own counter (Timer) .
  • timestamp the data packet sending device
  • timer the data packet sending device
  • Timestamps are not related, and at the same time, when each device receives data packets sent by different senders, the timestamps are also not related, which can easily cause confusion in the sending and receiving of data packets.
  • the clock synchronization algorithm is usually used to synchronize the counters of each cooperative device, so that the master device publishes data packets (including the clock count data generated by the master device counter after counting) at intervals, and the slave device then Obtain the clock count data in the data packet, adjust the clock count of the slave device through an algorithm, so that the clock count value of the count clock of each device is approximately the same at the same time, or the error of the clock count value is within an acceptable range.
  • the packet contains the complete clock count data of the master device, so more data transmission will be generated between the master device and the slave device, and the data communication power consumption will also be relatively large.
  • the timing of sending the clock count value of the master device to the slave device can be completely controlled by the master device, so that the time interval between the two clock count data packets sent by the master device to the slave device is exactly the same, so when the slave device is the first
  • the data in the data packet can be used to initialize the clock of the slave device and start counting. After that, wait until the second time the slave device receives the clock counting data packet from the master device.
  • the slave device does not need to obtain the clock count value of the master device from the data packet. It only needs to add the clock count value received for the first time to the time interval of the two data packet transmissions to get the clock count value of the master device.
  • the slave device By reducing the number of data transmissions in this way to reduce the power consumption of data communication, as long as the master device sends two clock counting data packets at a fixed time that both the master and the slave device know, then the second clock counting data packet starts , The slave device does not need to track the clock count value in the data packet, but only cares about the accurate sending time of the clock count data packet.
  • the clock counting data packet can be replaced with a short pulse that can accurately indicate the clock counting time sent by the master device.
  • the subsequent master device clock count data packet can be replaced by short pulses, and the clock count value in the data packet can be replaced by the slave
  • the equipment calculates by itself.
  • the master device clock counts 22000 ⁇ S and sends a short pulse P'to the slave device, and at this time, if the slave device is subjected to an electrostatic shock (Electrostatic Discharge, ESD, also called electrostatic discharge), Then all the register values will be cleared or confused, and the short pulse P'sent by the master device has not been received. Then, when the clock count of the master device is 23000 ⁇ S, the slave device will receive the data sent by the master device to the slave device.
  • ESD Electrostatic Discharge
  • the aforementioned method will synchronize the slave device to the wrong master device clock, causing the error between the master device and the slave device to be unable to be reduced. This is not the situation that the designer wants to see. Therefore, in order to achieve global clock synchronization ,Propose a global clock synchronization method combining data packets and short pulses that can reduce the amount of data sent in the clock synchronization algorithm, thereby reducing the power consumption of data communication, and can automatically restore the clock count value when an electrostatic shock occurs , It becomes the problem to be solved by the present invention.
  • the present invention proposes a global clock synchronization method combining data packets and short pulses, which mainly includes the following steps:
  • a counter of the master device performs a counting operation based on a clock count cycle, and the master device sends a clock count data packet containing a master device clock count value to at least one slave device;
  • the slave device After the slave device receives the clock count data packet sent by the master device, based on the clock count data packet, it initializes a slave device clock count value of the slave device and starts the counting operation;
  • the master device sends a short pulse to the slave device every time a first time interval has elapsed, so that after the slave device receives the short pulse, it updates the clock count value of the slave device according to the first time interval;
  • the master device sends the clock count data packet to the slave device every second time interval, so that the slave device counts the master device clock count value of the data packet according to the clock, and synchronizes the master device clock count value with the slave device clock count value.
  • the second time interval is greater than the first time interval;
  • the clock count value temporarily stored in the slave device is reset to zero, so that the slave device receives the short pulse sent by the master device every time the first time interval has passed.
  • the master device sends a clock count data packet every second time interval, let the slave device count the data packet according to the received clock and temporarily store its counter in the slave device
  • the clock count value is set as the clock count value of the master device to achieve the purpose of automatically recovering the clock count value of the slave device and the master device.
  • the master device When the master device has an abnormality such as an electrostatic shock, which causes the clock count of the master device to be cleared, the master device initializes, and then the master device and the slave device execute steps (1) to (4) again.
  • an abnormality such as an electrostatic shock
  • the present invention can reduce the number of clock count data packets sent to each slave device (subsystem) to be synchronized by the master device, thereby reducing the global clock synchronization method.
  • the amount of data that needs to be sent in the clock synchronization method saves the effect of data communication power consumption.
  • the present invention can still automatically restore the clock count value of the master device or the slave device when an electrostatic shock or other abnormality occurs.
  • Figure 1 is a schematic diagram of replacing data packets with short pulses in the conventional global clock synchronization algorithm.
  • Figure 2 is a schematic diagram of an abnormality occurring after the data packet is replaced with a short pulse in the global clock synchronization algorithm.
  • Figure 3 is a system architecture diagram of the present invention.
  • Figure 4 is a flow chart of the implementation of the present invention.
  • Figure 5 is a schematic diagram (1) of the implementation of the present invention.
  • Figure 6 is a schematic diagram (2) of the implementation of the present invention.
  • Fig. 7 is another embodiment of the present invention.
  • the S10 master device sends the first clock count packet
  • the S30 master device sends short pulses after the first time interval
  • the S40 master device sends a clock count data packet after the second time interval
  • FIG. 3 is a system architecture diagram of the present invention.
  • the present invention proposes a global clock synchronization method combining data packets and short pulses, which is mainly implemented by a digital hardware system 10, and is based on hardware (ie, through the PCB circuit The counter T between multiple chips connected by a board or a special data line is synchronized, and the synchronization error is generally small), rather than based on software (that is, the clock count value between multiple connected servers or computers is performed through the network.
  • the digital hardware system 10 mainly includes a master device 101 and at least one slave device (102, 102', 102"), where the master device 101 and each slave device (102, 102', 102") ") Each has a counter T, which is used for performing counting tasks and comparing counting data.
  • the master device 101 and the slave device (102, 102', 102") can be chips on the same circuit board, or different circuit boards with chips mounted on the same circuit board connected by data lines.
  • the master device 101 and the slave device (102 , 102', 102”) can be connected through a data line, and the aforementioned data line can be a differential line or a single-ended line, when the master device 101 regularly sends the clock count data packet of the master device 101 to all through the data line
  • the slave devices (102, 102', 102") and each slave device (102, 102', 102") receive the clock counting data packet of the master device 101, the counter T can be further triggered to count.
  • the slave device (102, 102', 102") can adjust the slave device (102, 102', 102") by comparing the clock count data packet data of the master device 101, so that the slave device (102, 102', 102") The error between the clock count data of the master device 101 and the clock count data of the master device 101 is within a very small error range.
  • the counter T of the slave device (102, 102', 102") can lock the counter T of the master device 101.
  • the device (102, 102', 102") can transmit this lock signal through the data line that sends the clock counting data packet, or it can establish a special lock data line and send it to the master device 101, or the slave device (102, 102', 102")
  • the lock information may not be sent to the master device 101 to simplify the global clock synchronization procedure.
  • the master device 101 can periodically send the complete clock count value to the slave device (102, 102', 102") through the data line in the form of a data packet,
  • the data line can only be a dedicated data line dedicated to global clock synchronization. It cannot be a general data line for communication between devices. If a dedicated data line dedicated to global clock synchronization is used, the master device 101 and the slave device (102, 102, When other data is transmitted between 102' and 102”), the transmission of other data will not affect the time that the master device 101 accurately sends the clock count.
  • the global clock synchronization method S combining data packets and short pulses proposed by the present invention is executed in the digital hardware system 10, and the following steps can be performed:
  • the master device 101 sends the Nth clock counting data packet (step S10): After a master device 101 is initialized, a counter T of the master device 101 performs a counting operation based on a clock counting cycle, and the master device 101 will include a master device 101. A clock count data packet D1 of the device clock count value (the Nth master device clock count data packet as shown in the figure) is sent to at least one slave device (102, 102', 102").
  • the slave device (102, 102', 102") starts counting the clock after receiving the clock counting data packet (step S20): following step S10, the slave device (102, 102', 102") receives the data sent by the master device 101 After the clock count data packet D1, based on the master clock count value in the clock count data packet D1, initialize a slave device clock count value of the slave device (102, 102', 102"), and start counting with its counter T.
  • the master device 101 sends a short pulse after the first time interval I1 (step S30): following step S20, the master device 101 elapses every time the first time interval I1 (for example, 1000 ⁇ S shown in FIG. 5, that is, 1 mS (millisecond), but It is not limited to this value) Send a short pulse P to the slave device (102, 102', 102"), so that the slave device (102, 102', 102”) receives the short pulse P according to the first time interval I1 Update the clock count value of the slave device.
  • the first time interval I1 for example, 1000 ⁇ S shown in FIG. 5, that is, 1 mS (millisecond), but It is not limited to this value
  • the master device 101 sends a clock count data packet after the second time interval I2 (step S40): Following step S30, the master device 101 elapses every second time interval I2 (for example, 10000 ⁇ S as shown in FIG. 5, that is, 10mS, but not Not limited to this value), another clock counting data packet D2 (the N+1th master clock counting data packet shown in Figure 5) can be sent to the slave device (102, 102', 102"), so that the slave The devices (102, 102', 102") synchronize the clock count value of the master device with the clock count value of the slave device according to the master device clock count value of the clock count data packet D2, wherein the second time interval I2 is greater than the first time interval I1.
  • the master device 101 elapses every second time interval I2 (for example, 10000 ⁇ S as shown in FIG. 5, that is, 10mS, but not Not limited to this value)
  • another clock counting data packet D2 (the N+1th master clock counting data packet shown in Figure 5) can be sent
  • step S30 the clock of the slave device (102, 102', 102") will be temporarily stored
  • the count value is reset to zero, and then when step S30 (the master device 101 sends a short pulse after the first time interval I1) is executed, the slave device (102, 102', 102") is continuously allowed to calculate the wrong clock count value (as shown in the figure)
  • the clock count value of the slave device shown in 6 is 6000 ⁇ S)
  • step S40 is executed again, the clock count value of the slave device temporarily stored by the slave device (102, 102', 102") is synchronized with the clock count value of the master device.
  • the slave device (102, 102', 102") can load the clock count data packet D2 sent by the master device 101 received in step S40 (The N+1th master device clock count packet shown in Figure 6) the master device clock count value (30000 ⁇ S), and set the slave device clock of the counter T of the slave device (102, 102', 102")
  • the count value is 30000 ⁇ S, which can correct the previously incorrectly calculated clock count value (6000 ⁇ S), ensuring that the slave device (102, 102', 102") can frequently adjust its own clock count, reducing the number of slave devices (102, 102') , 102") and the clock count error between the master device 101.
  • the master device 101 when the first time interval I1 and the second time interval I2 overlap, the master device 101 only needs to perform step S40 to synchronize the clock count value of the master device and the clock count value of the slave device in this step.
  • the time for the master device 101 to send the clock count value can be the rising edge of the short pulse P (rising edge, also called the rising edge), or the falling edge of the short pulse P (falling edge). , Can also be called falling edge)
  • step S30 is another embodiment of the present invention.
  • the present embodiment is basically the same as the technology of FIGS. 4-6.
  • the main difference lies in the steps During the execution of S20, step S30 or step S40, if the main device 101 is restarted due to an electrostatic shock or other abnormality, the main device 101 may re-execute step S10 in this embodiment to initialize and count based on the new main device clock Value, resend the clock count data packet D_NEW to the slave device (102, 102', 102") to continue to step S20, and let the slave device (102, 102', 102”) receive the new clock count data packet D_NEW After that, the master clock count value previously received from the master device 101 can be discarded, and a new master clock count can be imported and initialized and recounted to start a new global clock synchronization.
  • the present invention can not only replace the conventional and well-known global clock synchronization method for sending clock count data packets of the master device in specific applications, but also impact the static electricity that the master device 101 and the slave device (102, 102', 102") encounter Various abnormal events can be automatically recovered and reported as early as possible.
  • it is unnecessary to send clock count data packets every time, which can reduce the global clock synchronization master device 101 and slave device (102, 102', 102"), thereby reducing the communication power consumption required for clock synchronization of the digital hardware system 10.

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Abstract

Provided is an algorithm for hardware global time synchronization by combining a short pulse and a data packet, which algorithm can reduce a data transmission amount. Mainly by means of a master device sending a short pulse to a slave device every time a first time interval (for example, 1 mS) elapses, such that the slave device adjusts a clock count value thereof according to the first time interval, and the master device sending a clock count data packet to the slave device every time a second time interval (for example, 10 mS) elapses, such that the slave device loads a clock count value of the master device from the clock count data packet, such that global time synchronization is completed. In addition, in the present invention, when a static shock or another abnormality occurs in the master device or the slave device, a clock count value thereof can still be automatically recovered. After the present invention is implemented according thereto, a data transmission amount between a master device and a slave device during global time synchronization can be reduced since a clock count data packet does not need to be sent every time, such that communication power consumption required by time synchronization of a digital hardware system can be reduced.

Description

结合数据包和短脉冲的全局时钟同步方法Global clock synchronization method combining data packet and short pulse 技术领域Technical field
本发明涉及全局时钟同步(global time synchronization)技术，尤指一种让主设备发送时钟计数数据包(Data Packet，或称数据包)和短脉冲(pulse)相结合的实施方法，使得主设备减少发送给需同步的子***的时钟计数数据包的次数，从而减少资料发送量的结合数据包和短脉冲的全局时钟同步方法。The present invention relates to a global time synchronization (global time synchronization) technology, in particular to an implementation method that allows a master device to send a clock counting data packet (Data Packet, or data packet) combined with a short pulse (pulse), so that the master device reduces The clock sent to the subsystem to be synchronized counts the number of data packets, thereby reducing the amount of data sent, a global clock synchronization method that combines data packets and short pulses.
背景技术Background technique
全局时钟可确保***中各硬件设备(晶芯片模组或电路板)之间协同工作的同步。当多个硬件设备协同工作时，设备之间的数据通信需要通过发送和接收数据包来完成全局节拍的同步。为了方便同步不同类型数据包和分辨同类型资料数据包的先后顺序，数据包发送设备通常会将数据包打上时间戳(Timestamp)，使得每个数据包发送设备都要有各自的计数器(Timer)。当多个设备协同工作时，通常每个设备需要同时发送数据包及接收数据包，由于每个设备使用自己专属的计数器，使得每个设备发送的数据包的时间戳和接收到的数据包的时间戳没有关联性，同时每个设备收到不同发送端发送的数据包时间戳也没有关联性，很容易造成数据包发送和接收的混乱。The global clock can ensure the synchronization of the coordinated work between the hardware devices (chip modules or circuit boards) in the system. When multiple hardware devices work together, the data communication between the devices needs to complete the synchronization of the global beat by sending and receiving data packets. In order to facilitate the synchronization of different types of data packets and distinguish the sequence of data packets of the same type, the data packet sending device usually timestamps the data packet (Timestamp), so that each data packet sending device must have its own counter (Timer) . When multiple devices work together, usually each device needs to send and receive data packets at the same time. Because each device uses its own counter, the timestamp of the data packet sent by each device and the time stamp of the received data packet are Timestamps are not related, and at the same time, when each device receives data packets sent by different senders, the timestamps are also not related, which can easily cause confusion in the sending and receiving of data packets.
因此，在实际应用中通常通过时钟同步算法同步各协同工作设备的计数器，让主设备每隔一段间隔时间就发布数据包(其包含主设备计数器经过计数所产生的时钟计数数据)，从设备再获取数据包中时钟计数数据，通过算法调整从设备的时钟计数，使得各设备计数时钟的时钟计数值在同一时间大致相同，或者时钟计数值的误差在一个可以接受的范围内，然而，由于数据包包含完整的主设备时钟计数数据，故主设备与从设备之间会产生较多的数据发送量，数据通讯功耗也会 比较大。Therefore, in practical applications, the clock synchronization algorithm is usually used to synchronize the counters of each cooperative device, so that the master device publishes data packets (including the clock count data generated by the master device counter after counting) at intervals, and the slave device then Obtain the clock count data in the data packet, adjust the clock count of the slave device through an algorithm, so that the clock count value of the count clock of each device is approximately the same at the same time, or the error of the clock count value is within an acceptable range. However, due to the data The packet contains the complete clock count data of the master device, so more data transmission will be generated between the master device and the slave device, and the data communication power consumption will also be relatively large.
对此，主设备的时钟计数值发送给从设备的时机可完全由主设备控制，从而可让主设备发送给从设备的2次时钟计数数据包的时间间隔完全相同，故当从设备第1次收到主设备发来的时钟计数数据包后，可用数据包中的数据初始化从设备的时钟并开始计数，其后，等到第2次从设备收到主设备发来的时钟计数数据包后，从设备不必从数据包中获取出主设备的时钟计数值，只需要将第1次收到的时钟计数值，加上2次数据包发送的时间间隔就可以得到主设备的时钟计数值，通过这样减少数据发送次数来降低数据通讯功耗的作法，只要主设备发送2次时钟计数数据包的间隔是主设备和从设备都知道的一个固定时间，那么从第2个时钟计数数据包开始，从设备就可以不必追踪数据包中的时钟计数值，而只用关心时钟计数数据包的准确发送时间就可以。In this regard, the timing of sending the clock count value of the master device to the slave device can be completely controlled by the master device, so that the time interval between the two clock count data packets sent by the master device to the slave device is exactly the same, so when the slave device is the first After receiving the clock counting data packet from the master device for the second time, the data in the data packet can be used to initialize the clock of the slave device and start counting. After that, wait until the second time the slave device receives the clock counting data packet from the master device. , The slave device does not need to obtain the clock count value of the master device from the data packet. It only needs to add the clock count value received for the first time to the time interval of the two data packet transmissions to get the clock count value of the master device. By reducing the number of data transmissions in this way to reduce the power consumption of data communication, as long as the master device sends two clock counting data packets at a fixed time that both the master and the slave device know, then the second clock counting data packet starts , The slave device does not need to track the clock count value in the data packet, but only cares about the accurate sending time of the clock count data packet.
所以有发明人提出从第2个时钟计数数据包开始，时钟计数数据包可被替换为能够准确表示出主设备发送时钟计数时间的短脉冲，如图1所示，在从设备收到主设备时钟计数值于第21000μS(微秒)时发送的第N个时钟计数数据包D1’后，后面的主设备时钟计数数据包可以全部被短脉冲所取代，数据包中的时钟计数值可以由从设备自行计算得出。Therefore, some inventors proposed that starting from the second clock counting data packet, the clock counting data packet can be replaced with a short pulse that can accurately indicate the clock counting time sent by the master device. As shown in Figure 1, when the slave device receives the master device After the clock count value is the Nth clock count data packet D1' sent at the 21000μS (microsecond), the subsequent master device clock count data packet can be replaced by short pulses, and the clock count value in the data packet can be replaced by the slave The equipment calculates by itself.
请继续参阅图2，若当主设备时钟计数为22000μS，并发送了一个短脉冲P’给从设备，而此时从设备如果受到了一次静电冲击(Electrostatic Discharge,ESD，也可称静电放电)，则所有寄存器值将被清零或发生混乱，同时也没有收到主设备发送的短脉冲P’，其后在主设备时钟计数为23000μS时，从设备虽然会收到主设备发给从设备的短脉冲，但因为上次的静电冲击，已遗失之前保存的主设备时钟计数(21000μS)，故从设备此时会计算出错误的主设备时钟计数(0+1000＝1000μS)，而且因为主设备后来只发送短脉冲，再也没有发送过完整的时钟计数数据包，故从设备在收到后来的短脉冲时，也只会不断计算出错误的时钟计数，例如主设备时钟计数为24000μS时， 从设备此时计算出的主设备时钟计数为1000+1000＝2000μS，而再也没有机会纠正这个错误。Please continue to refer to Figure 2. If the master device clock counts 22000μS and sends a short pulse P'to the slave device, and at this time, if the slave device is subjected to an electrostatic shock (Electrostatic Discharge, ESD, also called electrostatic discharge), Then all the register values will be cleared or confused, and the short pulse P'sent by the master device has not been received. Then, when the clock count of the master device is 23000μS, the slave device will receive the data sent by the master device to the slave device. Short pulse, but because of the last electrostatic shock, the previously saved master device clock count (21000μS) has been lost, so the slave device will calculate the wrong master device clock count (0+1000=1000μS) at this time, and because the master device later Only short pulses are sent, and a complete clock count data packet has never been sent. Therefore, when the slave device receives subsequent short pulses, it will only continuously calculate the wrong clock count. For example, when the clock count of the master device is 24000μS, the slave The clock count of the master device calculated by the device at this time is 1000+1000=2000μS, and there is no chance to correct this error again.
换句话说，前述作法将使从设备同步在错误的主设备时钟之上，造成主设备与从设备误差无法缩小，而这并不是设计者所希望看到的状况，因此，为了达成全局时钟同步，提出一种即可减少在时钟同步演算法中产生的资料发送量，从而降低数据通讯功耗，又可以在发生静电冲击时自动恢复时钟计数值的结合数据包和短脉冲的全局时钟同步方法，就成为本发明要解决的问题。In other words, the aforementioned method will synchronize the slave device to the wrong master device clock, causing the error between the master device and the slave device to be unable to be reduced. This is not the situation that the designer wants to see. Therefore, in order to achieve global clock synchronization ，Propose a global clock synchronization method combining data packets and short pulses that can reduce the amount of data sent in the clock synchronization algorithm, thereby reducing the power consumption of data communication, and can automatically restore the clock count value when an electrostatic shock occurs , It becomes the problem to be solved by the present invention.
发明内容Summary of the invention
为达到上述目的，本发明提出一种结合数据包和短脉冲的全局时钟同步方法，主要包括以下步骤：To achieve the above objective, the present invention proposes a global clock synchronization method combining data packets and short pulses, which mainly includes the following steps:
(1)一个主设备完成初始化后，主设备的一个计数器基于一个时钟计数周期进行计数作业，主设备将包含一个主设备时钟计数值的一个时钟计数数据包发送给至少一个从设备；(1) After a master device completes initialization, a counter of the master device performs a counting operation based on a clock count cycle, and the master device sends a clock count data packet containing a master device clock count value to at least one slave device;
(2)从设备接收到主设备发送的时钟计数数据包后，基于时钟计数数据包，初始化从设备的一个从设备时钟计数值，并开始计数作业；(2) After the slave device receives the clock count data packet sent by the master device, based on the clock count data packet, it initializes a slave device clock count value of the slave device and starts the counting operation;
(3)主设备每经过一个第一时间间隔将一个短脉冲发送给从设备，使从设备收到短脉冲后，依据第一时间间隔更新从设备时钟计数值；(3) The master device sends a short pulse to the slave device every time a first time interval has elapsed, so that after the slave device receives the short pulse, it updates the clock count value of the slave device according to the first time interval;
(4)主设备每经过一个第二时间间隔将时钟计数数据包发送给从设备，使从设备依据时钟计数数据包的主设备时钟计数值，同步主设备时钟计数值与从设备时钟计数值，其中，第二时间间隔大于第一时间间隔；以及(4) The master device sends the clock count data packet to the slave device every second time interval, so that the slave device counts the master device clock count value of the data packet according to the clock, and synchronizes the master device clock count value with the slave device clock count value. Wherein, the second time interval is greater than the first time interval; and
(5)当从设备发生静电冲击或其它异常而造成重启，使从设备暂存的时钟计数值被归零，进而让从设备每次接收到主设备每经过第一时间间隔而发送的短脉冲，而不断计算出错误的时钟计数值时，可于主设备每经过第二时间间隔而发送时钟计数数据包时，让从设备依 据接收到的时钟计数数据包，将其计数器暂存的从设备时钟计数值，设定为主设备时钟计数值，以达到自动恢复同步从设备与主设备时钟计数值的目的。(5) When the slave device is restarted due to electrostatic shock or other abnormalities, the clock count value temporarily stored in the slave device is reset to zero, so that the slave device receives the short pulse sent by the master device every time the first time interval has passed. , And continuously calculate the wrong clock count value, when the master device sends a clock count data packet every second time interval, let the slave device count the data packet according to the received clock and temporarily store its counter in the slave device The clock count value is set as the clock count value of the master device to achieve the purpose of automatically recovering the clock count value of the slave device and the master device.
(6)当主设备发生静电冲击等异常，造成主设备时钟计数被清零后，主设备进行初始化，然后主设备和从设备重新执行步骤(1)至步骤(4)。(6) When the master device has an abnormality such as an electrostatic shock, which causes the clock count of the master device to be cleared, the master device initializes, and then the master device and the slave device execute steps (1) to (4) again.
因此，本发明实施后，与前面提到的硬件全局时钟同步方法比较，本发明可达成让主设备减少发送给各个需同步的从设备(子***)的时钟计数数据包的次数，从而减少全局时钟同步方法中需要发送的数据量，节省数据通讯功耗的效果，同时本发明在主设备或从设备发生静电冲击或其它异常时，仍可自动恢复其时钟计数值。Therefore, after the implementation of the present invention, compared with the aforementioned hardware global clock synchronization method, the present invention can reduce the number of clock count data packets sent to each slave device (subsystem) to be synchronized by the master device, thereby reducing the global clock synchronization method. The amount of data that needs to be sent in the clock synchronization method saves the effect of data communication power consumption. At the same time, the present invention can still automatically restore the clock count value of the master device or the slave device when an electrostatic shock or other abnormality occurs.
为使贵审查委员得以清楚了解本发明的目的、技术特征及其实施后的功效，兹以下列说明搭配图示进行说明，敬请参阅。In order for your reviewer to have a clear understanding of the purpose, technical features and effects of the present invention after implementation, the following description and illustrations are used for illustration, please refer to it.
附图说明Description of the drawings
图1为常规全局时钟同步算法中数据包替换为短脉冲的示意图。Figure 1 is a schematic diagram of replacing data packets with short pulses in the conventional global clock synchronization algorithm.
图2为全局时钟同步演算法中数据包替换为短脉冲后发生异常的示意图。Figure 2 is a schematic diagram of an abnormality occurring after the data packet is replaced with a short pulse in the global clock synchronization algorithm.
图3为本发明的***架构图。Figure 3 is a system architecture diagram of the present invention.
图4为本发明的实施流程图。Figure 4 is a flow chart of the implementation of the present invention.
图5为本发明的实施示意图(一)。Figure 5 is a schematic diagram (1) of the implementation of the present invention.
图6为本发明的实施示意图(二)。Figure 6 is a schematic diagram (2) of the implementation of the present invention.
图7为本发明的另一实施例。Fig. 7 is another embodiment of the present invention.
符号说明Symbol Description
10数位硬件***10-digit hardware system
101主设备           102从设备101 master device 102 slave device
102’从设备         102”从设备102’Slave device 102”Slave device
T计数器             D1’时钟计数数据包T counter D1' clock counting data packet
P’短脉冲        D1～D2时钟计数数据包P’Short pulse D1～D2 clock count data packet
D_NEW时钟计数数据包D_NEW clock count packet
P短脉冲          I1第一时间间隔P Short pulse I1 First time interval
I2第二时间间隔I2 second time interval
S结合数据包和短脉冲的全局时钟同步方法S Global clock synchronization method combining data packet and short pulse
S10主设备发送第一笔时钟计数数据包The S10 master device sends the first clock count packet
S20从设备接收时钟计数数据包后开始计数时钟S20 starts counting the clock after receiving the clock counting data packet from the device
S30主设备经过第一时间间隔发送短脉冲The S30 master device sends short pulses after the first time interval
S40主设备经过第二时间间隔发送时钟计数数据包The S40 master device sends a clock count data packet after the second time interval
具体实施方式Detailed ways
请参阅图3，其为本发明的***架构图，本发明提出一种结合数据包和短脉冲的全局时钟同步方法，主要通过一个数位硬件***10实现，并且是基于硬件实现(即通过PCB电路板或专门数据线连接的多个芯片之间的计数器T完成同步，一般同步误差较小)，而不是基于软件实现(即通过网路对连接的多个服务器或计算机之间的时钟计数值进行同步，一般同步误差较大)，数字硬件***10主要包括一个主设备101及至少一个从设备(102、102’、102”)，其中，主设备101及各从设备(102、102’、102”)分别具有一个计数器T，计数器T供执行计数任务及比对计数数据使用。Please refer to FIG. 3, which is a system architecture diagram of the present invention. The present invention proposes a global clock synchronization method combining data packets and short pulses, which is mainly implemented by a digital hardware system 10, and is based on hardware (ie, through the PCB circuit The counter T between multiple chips connected by a board or a special data line is synchronized, and the synchronization error is generally small), rather than based on software (that is, the clock count value between multiple connected servers or computers is performed through the network. Synchronization, generally the synchronization error is relatively large), the digital hardware system 10 mainly includes a master device 101 and at least one slave device (102, 102', 102"), where the master device 101 and each slave device (102, 102', 102") ") Each has a counter T, which is used for performing counting tasks and comparing counting data.
承上，主设备101和从设备(102、102’、102”)可为同一电路板上的芯片，或是以数据线连接的安装有芯片的不同电路板。主设备101和从设备(102、102’、102”)之间可通过数据线完成连接，而前面所述的数据线可以是差分线或单端线，当主设备101通过数据线定时将主设备101的时钟计数数据包发送给所有从设备(102、102’、102”)，各从设备(102、102’、102”)接收主设备101的时钟计数数据包后，可进一步触发计数器T进行计数。In addition, the master device 101 and the slave device (102, 102', 102") can be chips on the same circuit board, or different circuit boards with chips mounted on the same circuit board connected by data lines. The master device 101 and the slave device (102 , 102', 102”) can be connected through a data line, and the aforementioned data line can be a differential line or a single-ended line, when the master device 101 regularly sends the clock count data packet of the master device 101 to all through the data line After the slave devices (102, 102', 102") and each slave device (102, 102', 102") receive the clock counting data packet of the master device 101, the counter T can be further triggered to count.
承上，从设备(102、102’、102”)可对比主设备101的时钟计数数据包的数据调整从设备(102、102’、102”)，使从设备(102、102’、102”) 的时钟计数数据与主设备101的时钟计数数据误差在一个极小的误差范围内，至此，从设备(102、102’、102”)的计数器T即可锁定主设备101的计数器T，从设备(102、102’、102”)可以将这个锁定信号通过发送时钟计数数据包的数据线来传送，也可以建立专门的锁定数据线发送给主设备101，或者从设备(102、102’、102”)可以不发送锁定信息给主设备101，以简化全局时钟同步程序。Continuing, the slave device (102, 102', 102") can adjust the slave device (102, 102', 102") by comparing the clock count data packet data of the master device 101, so that the slave device (102, 102', 102") The error between the clock count data of the master device 101 and the clock count data of the master device 101 is within a very small error range. At this point, the counter T of the slave device (102, 102', 102") can lock the counter T of the master device 101. The device (102, 102', 102") can transmit this lock signal through the data line that sends the clock counting data packet, or it can establish a special lock data line and send it to the master device 101, or the slave device (102, 102', 102") The lock information may not be sent to the master device 101 to simplify the global clock synchronization procedure.
承上，在前面所说的全局时钟同步传输的过程中，主设备101可以定时将完整的时钟计数值，通过数据线以数据包的形式发送给从设备(102、102’、102”)，数据线只能为专门用于全局时钟同步的专用数据线，不能是设备间通讯的通用数据线，若采用专门用于全局时钟同步的专用数据线，可使主设备101与从设备(102、102’、102”)之间传输其它数据时，不会因为传输其它数据而影响到主设备101精准发送时钟计数的时间。In summary, in the aforementioned global clock synchronization transmission process, the master device 101 can periodically send the complete clock count value to the slave device (102, 102', 102") through the data line in the form of a data packet, The data line can only be a dedicated data line dedicated to global clock synchronization. It cannot be a general data line for communication between devices. If a dedicated data line dedicated to global clock synchronization is used, the master device 101 and the slave device (102, 102, When other data is transmitted between 102' and 102"), the transmission of other data will not affect the time that the master device 101 accurately sends the clock count.
请继续参阅图4，并请搭配参阅图3及图5，本发明提出的结合数据包和短脉冲的全局时钟同步方法S，执行于数字硬件***10时，可执行以下步骤：Please continue to refer to Fig. 4, and please refer to Figs. 3 and 5 together, the global clock synchronization method S combining data packets and short pulses proposed by the present invention is executed in the digital hardware system 10, and the following steps can be performed:
(1)主设备101发送第N笔时钟计数数据包(步骤S10)：一个主设备101完成初始化后，主设备101的一个计数器T基于一个时钟计数周期进行计数作业，主设备101将包含一个主设备时钟计数值的一个时钟计数数据包D1(如图中所示的第N个主设备时钟计数数据包)发送给至少一个从设备(102、102’、102”)。(1) The master device 101 sends the Nth clock counting data packet (step S10): After a master device 101 is initialized, a counter T of the master device 101 performs a counting operation based on a clock counting cycle, and the master device 101 will include a master device 101. A clock count data packet D1 of the device clock count value (the Nth master device clock count data packet as shown in the figure) is sent to at least one slave device (102, 102', 102").
(2)从设备(102、102’、102”)接收时钟计数数据包后开始计数时钟(步骤S20)：承步骤S10，从设备(102、102’、102”)接收到主设备101发送的时钟计数数据包D1后，基于时钟计数数据包D1中的主设备时钟计数值，初始化从设备(102、102’、102”)的一个从设备时钟计数值，并以其计数器T开始计数作业。(2) The slave device (102, 102', 102") starts counting the clock after receiving the clock counting data packet (step S20): following step S10, the slave device (102, 102', 102") receives the data sent by the master device 101 After the clock count data packet D1, based on the master clock count value in the clock count data packet D1, initialize a slave device clock count value of the slave device (102, 102', 102"), and start counting with its counter T.
(3)主设备101经过第一时间间隔I1发送短脉冲(步骤S30)：承步骤S20，主设备101每经过第一时间间隔I1(例如图5所示的1000μS，即1mS(毫秒)，但并不限于此数值)将一个短脉冲P发送给 从设备(102、102’、102”)，使从设备(102、102’、102”)收到短脉冲P后，依据第一时间间隔I1更新从设备时钟计数值。(3) The master device 101 sends a short pulse after the first time interval I1 (step S30): following step S20, the master device 101 elapses every time the first time interval I1 (for example, 1000 μS shown in FIG. 5, that is, 1 mS (millisecond), but It is not limited to this value) Send a short pulse P to the slave device (102, 102', 102"), so that the slave device (102, 102', 102”) receives the short pulse P according to the first time interval I1 Update the clock count value of the slave device.
(4)主设备101经过第二时间间隔I2发送时钟计数数据包(步骤S40)：承步骤S30，主设备101每经过第二时间间隔I2(例如图5所示的10000μS，即10mS，但并不限于此数值)，可将另一个时钟计数数据包D2(如图5所示的第N+1个主设备时钟计数数据包)发送给从设备(102、102’、102”)，使从设备(102、102’、102”)依据时钟计数数据包D2的主设备时钟计数值，同步主设备时钟计数值与从设备时钟计数值，其中，第二时间间隔I2大于第一时间间隔I1。(4) The master device 101 sends a clock count data packet after the second time interval I2 (step S40): Following step S30, the master device 101 elapses every second time interval I2 (for example, 10000μS as shown in FIG. 5, that is, 10mS, but not Not limited to this value), another clock counting data packet D2 (the N+1th master clock counting data packet shown in Figure 5) can be sent to the slave device (102, 102', 102"), so that the slave The devices (102, 102', 102") synchronize the clock count value of the master device with the clock count value of the slave device according to the master device clock count value of the clock count data packet D2, wherein the second time interval I2 is greater than the first time interval I1.
(5)承步骤S30或步骤S40，因此，当从设备(102、102’、102”)发生静电冲击或其它异常而造成重启，使从设备(102、102’、102”)暂存的时钟计数值被归零，进而于步骤S30(主设备101经过第一时间间隔I1发送短脉冲)执行时，不断让从设备(102、102’、102”)计算出错误的时钟计数值(如图6所示的从设备时钟计数值6000μS)，则当步骤S40再度被执行时，使从设备(102、102’、102”)暂存的从设备时钟计数值与主设备时钟计数值达到同步。(5) Follow step S30 or step S40. Therefore, when the slave device (102, 102', 102") is restarted due to electrostatic shock or other abnormality, the clock of the slave device (102, 102', 102") will be temporarily stored The count value is reset to zero, and then when step S30 (the master device 101 sends a short pulse after the first time interval I1) is executed, the slave device (102, 102', 102") is continuously allowed to calculate the wrong clock count value (as shown in the figure) The clock count value of the slave device shown in 6 is 6000μS), when step S40 is executed again, the clock count value of the slave device temporarily stored by the slave device (102, 102', 102") is synchronized with the clock count value of the master device.
请继续搭配参阅图6，更具体地说，假设主设备101在主设备时钟计数为23000μS时，于步骤S30发送短脉冲P给从设备(102、102’、102”)，但若从设备(102、102’、102”)在这时受到了一次静电冲击，导致从设备(102、102’、102”)的所有寄存器数据都被归零，而此时从设备(102、102’、102”)也因为发生静电冲击，而没有收到主设备101发送的短脉冲P，所以从设备(102、102’、102”)的计数器T将由从设备时钟计数0μS重新开始计数，其后一直到主设备101的主设备时钟计数为29000μS时，从设备(102、102’、102”)此时计算的从设备时钟计数为第0+6000＝6000μS，导致从设备时钟计数与正确的主设备时钟计数(29000μS)误差过大。Please refer to Figure 6. More specifically, suppose that the master device 101 sends a short pulse P to the slave device (102, 102', 102") in step S30 when the clock count of the master device is 23000μS, but if the slave device ( 102, 102', 102”) was subjected to an electrostatic shock at this time, causing all the register data of the slave device (102, 102', 102”) to be zeroed, and at this time, the slave device (102, 102', 102”) ") Also because of the occurrence of electrostatic shock, and did not receive the short pulse P sent by the master device 101, so the counter T of the slave device (102, 102', 102") will be counted by the slave device clock counting 0μS to restart counting, and thereafter until When the master device clock count of the master device 101 is 29000μS, the slave device clock count calculated by the slave device (102, 102', 102") at this time is 0+6000=6000μS, resulting in the slave device clock count and the correct master device clock The count (29000μS) error is too large.
本发明在步骤S40再度被执行时，例如当主设备101为第30000μS时，从设备(102、102’、102”)可载入其于步骤S40所接收的主设备101发送的时钟计数数据包D2(如图6所示的第N+1个主设备 时钟计数数据包)的主设备时钟计数值(30000μS)，并设定从设备(102、102’、102”)的计数器T的从设备时钟计数值为第30000μS，从而能纠正之前错误计算的时钟计数值(6000μS)，保证了从设备(102、102’、102”)能频繁的调整自己的时钟计数，减少从设备(102、102’、102”)和主设备101之间的时钟计数误差。When the present invention is executed again in step S40, for example, when the master device 101 is the 30000th, the slave device (102, 102', 102") can load the clock count data packet D2 sent by the master device 101 received in step S40 (The N+1th master device clock count packet shown in Figure 6) the master device clock count value (30000μS), and set the slave device clock of the counter T of the slave device (102, 102', 102") The count value is 30000μS, which can correct the previously incorrectly calculated clock count value (6000μS), ensuring that the slave device (102, 102', 102") can frequently adjust its own clock count, reducing the number of slave devices (102, 102') , 102") and the clock count error between the master device 101.
承上，当第一时间间隔I1与第二时间间隔I2发生重叠时，主设备101仅需执行步骤S40，使主设备时钟计数值与从设备时钟计数值在此步骤达成同步。In conclusion, when the first time interval I1 and the second time interval I2 overlap, the master device 101 only needs to perform step S40 to synchronize the clock count value of the master device and the clock count value of the slave device in this step.
承上，当步骤S30执行时，主设备101发送时钟计数值的时间可以是用短脉冲P的上升缘(rising edge，也可称上升沿)，也可以是短脉冲P的下降缘(falling edge，也可称下降沿)In summary, when step S30 is performed, the time for the master device 101 to send the clock count value can be the rising edge of the short pulse P (rising edge, also called the rising edge), or the falling edge of the short pulse P (falling edge). , Can also be called falling edge)
请参阅图7，其为本发明的另一实施例，并请搭配参阅图3，当本发明在步骤S30执行时，本实施例与图4～图6的技术基本相同，主要差异在于，步骤S20、步骤S30或步骤S40在执行时，如主设备101发生静电冲击或其它异常而造成重启，则主设备101于本实施例可先重新执行步骤S10，进行初始化以及基于新的主设备时钟计数值，重新发送时钟计数数据包D_NEW至从设备(102、102’、102”)，以续行步骤S20，让从设备(102、102’、102”)在收到新的时钟计数数据包D_NEW后，可抛弃先前从主设备101所接收的主设备时钟计数值，并导入新的主设备时钟计数及进行初始化与重新进行计数作业，以开始新的全局时钟同步。Please refer to FIG. 7, which is another embodiment of the present invention. Please also refer to FIG. 3. When the present invention is executed in step S30, the present embodiment is basically the same as the technology of FIGS. 4-6. The main difference lies in the steps During the execution of S20, step S30 or step S40, if the main device 101 is restarted due to an electrostatic shock or other abnormality, the main device 101 may re-execute step S10 in this embodiment to initialize and count based on the new main device clock Value, resend the clock count data packet D_NEW to the slave device (102, 102', 102") to continue to step S20, and let the slave device (102, 102', 102”) receive the new clock count data packet D_NEW After that, the master clock count value previously received from the master device 101 can be discarded, and a new master clock count can be imported and initialized and recounted to start a new global clock synchronization.
综上可知，本发明不但可在具体应用中取代常规熟知发送主设备时钟计数数据包的全局时钟同步方法，而且对主设备101和从设备(102、102’、102”)遇到的静电冲击等各种异常事件，可以自动恢复并尽早上报异常发生，同时，本发明据以实施后，因为不必每次都要发送时钟计数数据包，可减少全局时钟同步主设备101和从设备(102、102’、102”)之间的数据传输量，进而能减少数位硬件***10的时钟同步所需要的通讯功耗。In summary, the present invention can not only replace the conventional and well-known global clock synchronization method for sending clock count data packets of the master device in specific applications, but also impact the static electricity that the master device 101 and the slave device (102, 102', 102") encounter Various abnormal events can be automatically recovered and reported as early as possible. At the same time, after the present invention is implemented, it is unnecessary to send clock count data packets every time, which can reduce the global clock synchronization master device 101 and slave device (102, 102', 102"), thereby reducing the communication power consumption required for clock synchronization of the digital hardware system 10.
以上所述者，仅为本发明较佳的实施例而已，并非用以限定本发 明实施的范围；任何熟悉此技术者，在不脱离本发明的精神与范围下所作的均等变化与修饰，皆应涵盖于本发明的专利范围内。The above are only preferred embodiments of the present invention, and are not intended to limit the scope of implementation of the present invention; anyone who is familiar with this technology can make equal changes and modifications without departing from the spirit and scope of the present invention. Should be covered within the scope of the patent of the present invention.

Claims (7)

  1. 一种结合数据包和短脉冲的全局时钟同步方法，其特征在于，包括：A global clock synchronization method combining data packets and short pulses is characterized in that it includes:
    (A)一主设备完成初始化后，所述主设备的一计数器基于一时钟计数周期进行计数作业，所述主设备将包含一主设备时钟计数值的一时钟计数数据包发送给至少一从设备；(A) After a master device completes initialization, a counter of the master device performs a counting operation based on a clock count cycle, and the master device sends a clock count data packet containing a master device clock count value to at least one slave device ；
    (B)所述从设备接收到所述主设备发送的所述时钟计数数据包后，基于所述时钟计数数据包，初始化所述从设备的一从设备时钟计数值，并开始计数作业；(B) After the slave device receives the clock count data packet sent by the master device, based on the clock count data packet, initialize a slave device clock count value of the slave device and start a counting operation;
    (C)所述主设备每经过一第一时间间隔将一短脉冲发送给所述从设备，使所述从设备收到所述短脉冲后，依据所述第一时间间隔更新所述从设备时钟计数值；(C) The master device sends a short pulse to the slave device every time a first time interval has elapsed, so that after receiving the short pulse, the slave device updates the slave device according to the first time interval Clock count value;
    (D)所述主设备每经过一第二时间间隔将所述时钟计数数据包发送给所述从设备，使所述从设备依据所述时钟计数数据包的所述主设备时钟计数值，同步所述主设备时钟计数值与所述从设备时钟计数值，其中，所述第二时间间隔大于所述第一时间间隔；以及(D) The master device sends the clock count data packet to the slave device every second time interval, so that the slave device synchronizes the clock count value of the master device according to the clock count data packet The master device clock count value and the slave device clock count value, wherein the second time interval is greater than the first time interval; and
    (E)当所述从设备发生静电冲击或其它异常而造成重启，使从设备暂存的所述时钟计数值归零，进而于所述主设备经过第一时间间隔发送短脉冲步骤执行时，不断使所述从设备计算出错误的时钟计数值，则当所述主设备经过第二时间间隔发送时钟计数数据包步骤再度被执行时，使所述从设备的时钟计数值与所述主设备的时钟计数值达到同步。(E) When the slave device is restarted due to an electrostatic shock or other abnormality, the clock count value temporarily stored by the slave device is reset to zero, and then the master device sends a short pulse step after the first time interval is executed, The slave device continuously calculates the wrong clock count value, and when the master device sends the clock count data packet step after the second time interval is executed again, the clock count value of the slave device is set to be the same as that of the master device. The count value of the clock reaches synchronization.
  2. 如权利要求1所述的结合数据包和短脉冲的全局时钟同步方法，其特征在于，当所述从设备的时钟计数值与所述主设备时钟计数值的误差在误差容许范围内，则所述从设备发送锁定信号至所述主设备。The global clock synchronization method combining data packets and short pulses according to claim 1, wherein when the error between the clock count value of the slave device and the clock count value of the master device is within the error tolerance range, then The slave device sends a lock signal to the master device.
  3. 如权利要求1所述的结合数据包和短脉冲的全局时钟同步方法，其特征在于，当所述主设备发生静电冲击或其它异常而造成重启，则所述主设备先执行(A)步骤，以进行初始化以及基于新的所述主设 备时钟计数值，重新发送所述时钟计数数据包至所述从设备，以续行(B)步骤。The method for global clock synchronization combining data packets and short pulses according to claim 1, wherein when the main device is restarted due to an electrostatic shock or other abnormality, the main device first performs step (A), To perform initialization and based on the new master device clock count value, resend the clock count data packet to the slave device to continue step (B).
  4. 如权利要求1或3所述的结合数据包和短脉冲的全局时钟同步方法，其特征在于，当所述从设备接收到新的所述时钟计数数据包，则所述从设备丢弃过去计算的所述从设备时钟计数值，随后所述从设备依据新的所述主设备时钟计数值进行初始化，以重新进行计数作业。The global clock synchronization method combining data packets and short pulses according to claim 1 or 3, characterized in that, when the slave device receives a new clock count data packet, the slave device discards the previously calculated data packet The clock count value of the slave device is then initialized by the slave device according to the new clock count value of the master device to restart the counting operation.
  5. 如权利要求1所述的结合数据包和短脉冲的全局时钟同步方法，其特征在于，所述第一时间间隔与所述第二时间间隔发生重叠时，所述主设备仅执行(D)步骤，使所述主设备时钟计数值与所述从设备时钟计数值于(D)步骤达成同步。The global clock synchronization method combining data packets and short pulses according to claim 1, wherein when the first time interval and the second time interval overlap, the master device only performs step (D) , The clock count value of the master device and the clock count value of the slave device are synchronized in step (D).
  6. 如权利要求1所述的结合数据包和短脉冲的全局时钟同步方法，其特征在于，所述主设备发送所述时钟计数数据包或所述短脉冲时，是通过一对差分线或一根单端资料线发送给所述从设备。The global clock synchronization method combining data packets and short pulses according to claim 1, wherein the master device sends the clock counting data packet or the short pulse through a pair of differential lines or one The single-ended data line is sent to the slave device.
  7. 如权利要求1所述的结合数据包和短脉冲的全局时钟同步方法，其特征在于，(C)步骤执行时，所述主设备发送所述短脉冲的上升沿或下降沿。The global clock synchronization method combining data packets and short pulses according to claim 1, wherein, when step (C) is performed, the master device sends the rising edge or the falling edge of the short pulse.
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