CN102882669A - Two-wire interface time synchronization protocol method - Google Patents
Two-wire interface time synchronization protocol method Download PDFInfo
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- CN102882669A CN102882669A CN2012103019104A CN201210301910A CN102882669A CN 102882669 A CN102882669 A CN 102882669A CN 2012103019104 A CN2012103019104 A CN 2012103019104A CN 201210301910 A CN201210301910 A CN 201210301910A CN 102882669 A CN102882669 A CN 102882669A
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Abstract
The invention provides a two-wire interface time synchronization protocol method. The method comprises the following steps that: S0, a time-service master control board is defined; S1, the time-service master control board extracts time information; S2, the time-service master control board packages the time information; S3, the time-service master control board transmits the packaged time information to a controlled board; S4, the controlled board receives the packaged time information which is transmitted by the time-service master control board; S5, the controlled board decrypts the packaged time information; S6, the controlled board reads the time information; S7, the controlled board verifies the time information; and S8, the controlled board updates time; wherein in the S7, the controlled board verifies the time information by a cyclic redundancy check code. The method has the advantages of simplicity and reliability in requirements, and the method is high in time synchronization accuracy, low in cost and can be easily implemented.
Description
Technical field
The present invention relates to method for synchronizing time, refer to especially a kind of two line interface time synchronization protocol methods.
Background technology
Existing time synchronization protocol mainly is IEEE1588, and this agreement is used more in fields such as communication, Industry Control.The IEEE1588 of communication, industrial circle realizes mainly the bottom-layer network framework based on Ethernet, and IEEE1588 and Ethernet all are for large-scale, complicated network design, need software, hardware collaborative work, and very complicated, cost is also very high.Although IEEE1588 can realize 1 delicate precision,, be not suitable in the mini-system, for example the time synchronized between the polylith circuit board in the cabinet.
Summary of the invention
In order to address the above problem, the present invention proposes a kind of two line interface time synchronization protocol methods.A kind of two line interface time synchronization protocol methods that the present invention proposes, the method of reliable time synchronized is carried out in solution in such as cabinet between the polylith circuit board in a mini system, it is simple, reliable that this method requires, and timing tracking accuracy is high, cost is low simultaneously, realizes simple.
Technical scheme of the present invention is achieved in that
A kind of two line interface time synchronization protocol methods comprise
S0: definition time service master control borad;
S1: time service master control borad extracting time information;
S2: the time service master control borad encapsulates temporal information;
S3: the time service master control borad is sent to controlled board with packaged temporal information;
S4: controlled board receives the packaged temporal information that the time service master control borad sends;
S5: controlled board is with packaged temporal information deciphering;
S6: controlled board reads temporal information;
S7: controlled board checking time information;
S8: controlled board update time; Wherein,
Among the step S7, controlled board is by cyclic redundancy check (CRC) code checking time information.
Above-mentioned a kind of two line interface time synchronization protocol methods, wherein, pass through low-frequency clock line and serial data line parallel join between described time service master control borad and the controlled board, described time service master control borad is provided with timing clock, this timing clock is set every 0.1ms, export a pulse by the low-frequency clock line, simultaneously packaged temporal information is sent to controlled board by serial data line.
Above-mentioned a kind of two line interface time synchronization protocol methods, wherein, described pulse frequency is 8KHz ~ 12KHz, duty ratio is 20% ~ 70%.
Above-mentioned a kind of two line interface time synchronization protocol methods, wherein, the time service master control borad among the described step S0 comprises main time service master control borad and from the time service master control borad, described step S5 comprises:
S501: whether the temporal information of verification master time service master control borad is complete, if complete, meets step S6, if imperfect, meets step S502;
S502: whether verification is complete from the temporal information of time service master control borad, if complete, meets step S6, if imperfect, meets step S1.
Above-mentioned a kind of two line interface time synchronization protocol methods, wherein, described step S7 comprises 3 checking procedures, and is specific as follows:
S701: the verification of physical electrical layer, reject the disturbing pulse information of appearance by the speed of restriction low-speed clock line and serial data line;
S702: the verification of link data layer, comprise the packet of positive and negative data in order to transmission, described packet attaches cyclic redundancy check (CRC) code;
S703: the system layer verification, by adopting the framework checking time information of simultaneously time service of two time service master control borads.
Beneficial effect of the present invention is: timing tracking accuracy is higher, can accomplish the precision that sub-micro is wonderful; Realize simple and to the support of master-slave back-up, greatly improve system reliability; With low cost, can utilize cheaply programmable chip to realize whole agreement.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the flow chart of a kind of two line interface time synchronization protocol methods of the present invention;
Fig. 2 is the flow chart of controlled board checking time information in a kind of two line interface time synchronization protocol methods of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Embodiment 1
Shown in Fig. 1-2, a kind of two line interface time synchronization protocol methods comprise
S0: definition time service master control borad, described time service master control borad comprise main time service master control borad with from the time service master control borad.
S1: time service master control borad extracting time information.
S2: the time service master control borad encapsulates temporal information, by one 32 binary counter is filled in the time information data bag of transmission, realizes the encapsulation to temporal information.
S3: the time service master control borad is sent to controlled board with packaged temporal information.
S4: controlled board receives the packaged temporal information that the time service master control borad sends.
S5: controlled board is deciphered packaged temporal information, wherein,
S501, whether the temporal information of verification master time service master control borad is complete, if complete, meets step S6, if imperfect, meets step S502;
S502, whether verification is complete from the temporal information of time service master control borad, if complete, meets step S6, if imperfect, meets step S1.
S6: controlled board reads temporal information.
S7: controlled board is by cyclic redundancy check (CRC) code checking time information, and this step comprises three checking procedures, is respectively:
S701, the verification of physical electrical layer mainly provides larger time sequence allowance in order to the speed that limits low-speed clock line and serial data line, thereby rejects the disturbing pulse information that occurs;
S702, the verification of link data layer mainly comprises the packet of positive and negative data in order to transmission, and described packet attach cyclic redundancy check (CRC) code, can be again the correctness of the temporal information of reception be made guarantee;
S703, the system layer verification by adopting the framework checking time information of simultaneously time service of two time service master control borads, improves the reliability of time service in system level.
S8: controlled board update time.
Above-mentioned a kind of two line interface time synchronization protocol methods, wherein, described temporal information is relative time information.
Above-mentioned a kind of two line interface time synchronization protocol methods, wherein, pass through low-frequency clock line and serial data line parallel join between described time service master control borad and the controlled board, described time service master control borad is provided with timing clock, this timing clock is set every 0.1ms, export a pulse by the low-frequency clock line, simultaneously packaged temporal information is sent to controlled board by serial data line; Described pulse frequency is 8KHz, and duty ratio is 20%.
Embodiment 2
The step of a kind of two line interface time synchronization protocol methods of present embodiment is with embodiment 1.
Described temporal information is relative time information.Pass through low-frequency clock line and serial data line parallel join between described time service master control borad and the controlled board, described time service master control borad is provided with timing clock, this timing clock is set every 0.1ms, export a pulse by the low-frequency clock line, simultaneously packaged temporal information is sent to controlled board by serial data line; Described pulse frequency is 12KHz, and duty ratio is 70%.
Embodiment 3
The step of a kind of two line interface time synchronization protocol methods of present embodiment is with embodiment 1.
Described temporal information is relative time information.Pass through low-frequency clock line and serial data line parallel join between described time service master control borad and the controlled board, described time service master control borad is provided with timing clock, this timing clock is set every 0.1ms, export a pulse by the low-frequency clock line, simultaneously packaged temporal information is sent to controlled board by serial data line; Described pulse frequency is 9KHz, and duty ratio is 55%.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. a line interface time synchronization protocol method is characterized in that: comprise
S0: definition time service master control borad;
S1: time service master control borad extracting time information;
S2: the time service master control borad encapsulates temporal information;
S3: the time service master control borad is sent to controlled board with packaged temporal information;
S4: controlled board receives the packaged temporal information that the time service master control borad sends;
S5: controlled board is with packaged temporal information deciphering;
S6: controlled board reads temporal information;
S7: controlled board checking time information;
S8: controlled board update time; Wherein,
Among the step S7, controlled board is by cyclic redundancy check (CRC) code checking time information.
2. a kind of two line interface time synchronization protocol methods according to claim 1, it is characterized in that, pass through low-frequency clock line and serial data line parallel join between described time service master control borad and the controlled board, described time service master control borad is provided with timing clock, this timing clock is set every 0.1ms, export a pulse by the low-frequency clock line, simultaneously packaged temporal information is sent to controlled board by serial data line.
3. a kind of two line interface time synchronization protocol methods according to claim 2 is characterized in that described pulse frequency is 8KHz ~ 12KHz, and duty ratio is 20% ~ 70%.
4. a kind of two line interface time synchronization protocol methods according to claim 2 is characterized in that, the time service master control borad among the described step S0 comprises main time service master control borad and from the time service master control borad, described step S5 comprises:
S501: whether the temporal information of verification master time service master control borad is complete, if complete, meets step S6, if imperfect, meets step S502;
S502: whether verification is complete from the temporal information of time service master control borad, if complete, meets step S6, if imperfect, meets step S1.
5. a kind of two line interface time synchronization protocol methods according to claim 4 is characterized in that described step S7 comprises 3 checking procedures, and is specific as follows:
S701: the verification of physical electrical layer, reject the disturbing pulse information of appearance by the speed of restriction low-speed clock line and serial data line;
S702: the verification of link data layer, comprise the packet of positive and negative data in order to transmission, described packet attaches cyclic redundancy check (CRC) code;
S703: the system layer verification, by adopting the framework checking time information of simultaneously time service of two time service master control borads.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106899371A (en) * | 2015-12-18 | 2017-06-27 | 中兴通讯股份有限公司 | Method for synchronizing time and device |
| CN110912634A (en) * | 2019-10-25 | 2020-03-24 | 深圳震有科技股份有限公司 | Method for realizing clock synchronization based on SPI, storage medium and terminal equipment |
| WO2021147502A1 (en) * | 2020-01-20 | 2021-07-29 | 南京深视光点科技有限公司 | Method for global time synchronization by combining data packet and short pulse |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101296066A (en) * | 2008-06-30 | 2008-10-29 | 杭州华三通信技术有限公司 | Real time clock synchronization method of distributed system, master control board and cable fastener plate |
| CN102497245A (en) * | 2011-12-19 | 2012-06-13 | 杭州华三通信技术有限公司 | Clock synchronization method and clock management interface board |
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- 2012-08-23 CN CN2012103019104A patent/CN102882669A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101296066A (en) * | 2008-06-30 | 2008-10-29 | 杭州华三通信技术有限公司 | Real time clock synchronization method of distributed system, master control board and cable fastener plate |
| CN102497245A (en) * | 2011-12-19 | 2012-06-13 | 杭州华三通信技术有限公司 | Clock synchronization method and clock management interface board |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106899371A (en) * | 2015-12-18 | 2017-06-27 | 中兴通讯股份有限公司 | Method for synchronizing time and device |
| CN110912634A (en) * | 2019-10-25 | 2020-03-24 | 深圳震有科技股份有限公司 | Method for realizing clock synchronization based on SPI, storage medium and terminal equipment |
| WO2021147502A1 (en) * | 2020-01-20 | 2021-07-29 | 南京深视光点科技有限公司 | Method for global time synchronization by combining data packet and short pulse |
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