WO2021147086A1 - 显示基板及其驱动方法、显示装置 - Google Patents

显示基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2021147086A1
WO2021147086A1 PCT/CN2020/074001 CN2020074001W WO2021147086A1 WO 2021147086 A1 WO2021147086 A1 WO 2021147086A1 CN 2020074001 W CN2020074001 W CN 2020074001W WO 2021147086 A1 WO2021147086 A1 WO 2021147086A1
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WIPO (PCT)
Prior art keywords
circuit
pixel
driving
light
data
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PCT/CN2020/074001
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English (en)
French (fr)
Inventor
黄炜赟
邱远游
黄耀
龙跃
陆忠
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/074001 priority Critical patent/WO2021147086A1/zh
Priority to CN202080000101.2A priority patent/CN113439299A/zh
Priority to CN202010130251.7A priority patent/CN111326560B/zh
Priority to JP2022502521A priority patent/JP2023520267A/ja
Priority to KR1020217038802A priority patent/KR20220129999A/ko
Priority to EP20891410.1A priority patent/EP4095921A4/en
Priority to PCT/CN2020/080182 priority patent/WO2021147160A1/zh
Priority to CN202080000311.1A priority patent/CN113508466A/zh
Priority to US17/297,641 priority patent/US11968865B2/en
Priority to US17/428,847 priority patent/US11980071B2/en
Priority to PCT/CN2021/073243 priority patent/WO2021147987A1/zh
Publication of WO2021147086A1 publication Critical patent/WO2021147086A1/zh
Priority to US18/390,381 priority patent/US20240172497A1/en
Priority to US18/396,840 priority patent/US20240138214A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element

Definitions

  • the embodiments of the present disclosure relate to a display substrate, a driving method thereof, and a display device.
  • Organic Light Emitting Diode (OLED) display devices have the characteristics of wide viewing angle, high contrast, and fast response speed. In addition, compared with inorganic light-emitting display devices, organic light-emitting diode display devices have advantages such as higher light-emitting brightness and lower driving voltage. Due to the above-mentioned characteristics and advantages, organic light-emitting diode (OLED) display devices have gradually received widespread attention and can be applied to devices with display functions such as mobile phones, displays, notebook computers, digital cameras, and instrumentation.
  • At least one embodiment of the present disclosure provides a display substrate including a plurality of pixel driving unit groups.
  • Each of the plurality of pixel drive unit groups includes at least two pixel drive units, and the at least two pixel drive units are connected between a first power supply voltage terminal and a first terminal of the same light-emitting element, and are configured to drive together The same light-emitting element;
  • the at least two pixel drive units include a first pixel circuit and a second pixel circuit, the first pixel circuit includes a first drive circuit and a first data writing circuit, the first data writing
  • the input circuit is configured to receive a first data signal and write the first data signal to the first driving circuit, and the first driving circuit is configured to control the flow through the first driving circuit based on the first data signal.
  • the display substrate further includes: a first display area and a second display area that do not overlap each other, and at least one first wiring.
  • the plurality of pixel drive unit groups are located in the second display area; the plurality of pixel drive unit groups include at least one first drive unit group; the first display area includes at least one first light-emitting element; At least one first driving unit group is configured to drive the at least one first light-emitting element in a one-to-one correspondence; and the at least one first wiring is electrically connected to the at least one first driving unit group and the at least one The first driving unit group corresponds to the at least one first light-emitting element connected in one-to-one correspondence.
  • the plurality of pixel driving unit groups further includes at least one second driving unit group; the second display area includes at least one second light-emitting element; and the at least one The second driving unit group is configured to drive the at least one second light-emitting element in a one-to-one correspondence.
  • the at least one second driving unit group and the at least one second light emitting element driven by the at least one second driving unit group correspond to each other in a one-to-one correspondence.
  • the normal directions of the display surface of the display substrate at least partially overlap with each other.
  • the at least one first light-emitting element includes a plurality of first light-emitting elements
  • the at least one second light-emitting element includes a plurality of second light-emitting elements
  • the first The distribution density per unit area of the plurality of first light-emitting elements in the display area is equal to the distribution density per unit area of the plurality of second light-emitting elements in the second display area.
  • the plurality of first light-emitting elements and the plurality of second light-emitting elements are arranged in an array as a whole.
  • the display substrate further includes: a third display area at least partially surrounding the second display area.
  • the third display area includes a plurality of third light-emitting elements; and the distribution density per unit area of the plurality of first light-emitting elements in the first display area is smaller than that of the plurality of third light-emitting elements in the third display area.
  • the distribution density per unit area of the component is smaller than that of the plurality of third light-emitting elements in the third display area.
  • the at least one first driving unit group includes a plurality of first driving unit groups; the at least one second driving unit group includes a plurality of second driving unit groups; and
  • the plurality of first driving unit groups and the plurality of second driving unit groups are arranged in an array as a whole and alternately arranged in the row direction of the display substrate and the column direction of the display substrate.
  • At least two pixel driving units included in each of the plurality of pixel driving unit groups are arranged side by side in the column direction of the display substrate; Two second light-emitting elements driven by two adjacent second driving unit groups in the row direction of the substrate are located in different rows; two second driving units adjacent to each other in the column direction of the display substrate The two second light-emitting elements driven by the group are located in the same column; the two first light-emitting elements are driven to be located in different rows by the two adjacent first drive unit groups in the row direction of the display substrate, respectively; and The two first light-emitting elements driven by the two adjacent first driving unit groups in the column direction of the display substrate are located in the same column.
  • the first data writing circuit and the second data writing circuit are electrically connected to the same data signal terminal to receive the first data signal and the first data signal.
  • Two data signals; and the first data signal and the second data signal are the same.
  • the first data writing circuit is electrically connected to a first data signal terminal via a first data line to receive the first data signal terminal provided by the first data signal terminal.
  • Data signal the second data writing circuit is electrically connected to a second data signal terminal via a second data line to receive the second data signal provided by the second data signal terminal; and the first data line
  • the data line is different from the second data line, and the first data signal terminal and the second data signal terminal are different data signal terminals.
  • At least two pixel driving units included in each of the plurality of pixel driving unit groups are arranged side by side in the row direction of the display substrate; the display substrate further includes mutual Non-overlapping first display area and second display area; and the first data line is routed from the area between the first display area and the second display area to the second display area, the The second data line extends along the column direction of the display substrate.
  • the display substrate further includes a sensor.
  • the sensor is disposed on the non-display side of the display substrate, overlaps the first display area in the normal direction of the display surface of the display substrate, and is configured to receive and process the first display area passing through the first display area.
  • the light signal of the display area is disposed on the non-display side of the display substrate, overlaps the first display area in the normal direction of the display surface of the display substrate, and is configured to receive and process the first display area passing through the first display area. The light signal of the display area.
  • At least one embodiment of the present disclosure further provides a display device, which includes any display substrate provided by at least one embodiment of the present disclosure.
  • the display device further includes a first data driving circuit and a second data driving circuit.
  • the first data driving circuit is configured to provide the first data signal to the first data writing circuit via a first data signal terminal located in the first data driving circuit; and the second data driving circuit It is configured to provide the second data signal to the second data writing circuit via a second data signal terminal located in the second data driving circuit.
  • the display substrate further includes a plurality of third pixel circuits; and the plurality of light-emitting elements driven by the plurality of third pixel circuits are different from the plurality of pixel driving units
  • the first data driving circuit is further configured to provide a data signal to at least one of the plurality of third pixel circuits.
  • At least one embodiment of the present disclosure further provides a driving method for driving any display substrate provided by at least one embodiment of the present disclosure, which includes: providing the first data to the first data writing circuit Signal, and providing the second data signal to the second data writing circuit; and causing the first driving circuit to control the first driving current flowing through the first driving circuit based on the first data signal, And making the second driving circuit control the second driving current flowing through the second driving circuit based on the second data signal to drive the same light-emitting element.
  • the driving method in a case where the gray scale to be displayed of the same light-emitting element is less than a predetermined gray scale, the driving method includes: The data voltage of the second data signal is not equal to the data voltage of the first data signal provided to the first data writing circuit.
  • the predetermined gray scale is greater than the minimum gray scale of the display substrate and smaller than the maximum gray scale of the display substrate.
  • the data voltage of the second data signal provided to the second data writing circuit is a voltage corresponding to zero gray scale.
  • the driving method in a case where the gray scale to be displayed of the same light-emitting element is greater than or equal to the predetermined gray scale, the driving method includes: writing to the second data The data voltage of the second data signal provided by the circuit is equal to the data voltage of the first data signal provided to the first data writing circuit.
  • Fig. 1A is a schematic cross-sectional view of a display substrate
  • FIG. 1B is a schematic plan view of the display substrate shown in FIG. 1A;
  • FIG. 1C is a schematic diagram of a partial area of the display substrate shown in FIG. 1B;
  • FIG. 2A is a schematic diagram of a structure of a 7T1C pixel circuit
  • FIG. 2B is a driving timing diagram of the 7T1C pixel circuit shown in FIG. 2A;
  • FIG. 2C shows a schematic plan view of another display substrate
  • FIG. 2D shows a schematic diagram of a partial area of the first display area and the second display area included in the display substrate shown in FIG. 2C;
  • FIG. 3 is an exemplary block diagram of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a pixel driving unit group of the display substrate shown in FIG. 3;
  • FIG. 5A is an exemplary circuit diagram of the pixel driving unit group shown in FIG. 4;
  • FIG. 5B is a driving timing diagram of the pixel driving unit group shown in FIG. 5A;
  • FIG. 6 shows the change curve of the driving current of the red sub-pixel with time
  • FIG. 7 is a schematic cross-sectional view of a display substrate provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic plan view of an example of the display substrate shown in FIG. 7;
  • FIG. 9 is a schematic diagram of a partial area of the first display area and the second display area of the display substrate shown in FIG. 8;
  • FIG. 10 is a schematic diagram of a partial area of a third display area of the display substrate shown in FIG. 8;
  • FIG. 11 shows a schematic diagram of a partial area of the second display area shown in FIG. 9;
  • FIG. 12 shows another schematic diagram of a partial area of the second display area shown in FIG. 9;
  • FIG. 13 shows another schematic diagram of a partial area of the first display area and the second display area shown in FIG. 8;
  • FIG. 14 is an exemplary block diagram of a display device provided by at least one embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of the display device shown in FIG. 14;
  • FIG. 16 shows a third pixel circuit of the display substrate shown in FIG. 15;
  • FIG. 17 is a schematic plan view of the display device shown in FIG. 14;
  • FIG. 18 is another schematic plan view of the display device shown in FIG. 14;
  • FIG. 19A is still another schematic plan view of the display device shown in FIG. 14;
  • FIG. 19B shows the area between the first display area and the second display area of the display substrate of the display device shown in FIG. 19A;
  • FIG. 20 is an exemplary flowchart of a driving method of a display substrate provided by at least one embodiment of the present disclosure.
  • the inventors of the present disclosure noticed that the current display substrates with under-screen sensors (cameras) have relatively low luminous brightness in the display areas corresponding to the under-screen sensors (cameras), thereby affecting the quality of images displayed by the display substrates. Exemplary description will be given below in conjunction with FIG. 1A, FIG. 1B, FIG. 2A, and FIG. 2B.
  • FIG. 1A is a schematic cross-sectional view of a display substrate 500
  • FIG. 1B is a schematic plan view of the display substrate 500 shown in FIG. 1A
  • FIG. 1C is a schematic diagram of a partial area 513 of the display substrate 500 shown in FIG. 1B.
  • the display substrate 500 shown in FIG. 1B corresponds to the BB' line of the display substrate 10 shown in FIG. 1A.
  • the display substrate 500 includes a display layer 510 and a sensing layer 520, and the sensing layer 520 is disposed on the non-display side of the display substrate 500 (that is, the side away from the user).
  • the display layer 510 includes a first display area 511 and a second display area 512; the first display area 511 includes a plurality of first light-emitting elements 531 arranged in an array, and the second display area 512 includes an array A plurality of second light emitting elements 532 are arranged.
  • the plurality of first light-emitting elements 531 and the plurality of second light-emitting elements 532 have the same structure and performance characteristics.
  • the sensing layer 520 includes a sensor 521.
  • the sensor 521 and the first display area 511 overlap in the normal direction of the display surface of the display substrate 500, and are configured to receive and process the first display area. 511 light signal.
  • the light-emitting elements 531 in the first display area 511 are The distribution density per unit area is smaller than the distribution density per unit area of the plurality of second light-emitting elements 532 in the second display area 512.
  • the display layer 510 further includes a plurality of first pixel circuits and a plurality of second pixel circuits (not shown in FIGS. 1A-1C, see FIG. 2A); the plurality of first pixel circuits are configured to drive multiple pixels in one-to-one correspondence.
  • One first light-emitting element 531 and multiple second pixel circuits are configured to drive multiple second light-emitting elements 532 in a one-to-one correspondence.
  • the plurality of first pixel circuits and the plurality of second pixel circuits have the same circuit structure.
  • the data signal (e.g., data voltage) received by the plurality of first pixel circuits that drive the plurality of first light-emitting elements is equal to the data signal (e.g., data voltage) received by the plurality of second pixel circuits that drive the plurality of second light-emitting elements.
  • the light-emitting brightness of the plurality of first light-emitting elements is less than the light-emitting brightness of the plurality of second light-emitting elements, and therefore the brightness of the image area corresponding to the first display area 511 in the image displayed by the display substrate is The brightness difference of the image area corresponding to the second display area 512 is relatively large.
  • each of the plurality of first pixel circuits and the plurality of second pixel circuits can be implemented as a 2T1C pixel circuit, a 3T1C pixel circuit, a 5T1C pixel circuit, a 7T1C pixel circuit, or other applicable pixel circuits.
  • the 2T1C pixel circuit is a pixel circuit including two transistors and a storage capacitor Cst
  • the 7T1C pixel circuit is a pixel circuit including seven transistors and a storage capacitor Cst.
  • the display substrate 500 shown in FIG. 1A and FIG. 1B will be exemplarily described by taking each of the plurality of first pixel circuits and the plurality of second pixel circuits as a 7T1C pixel circuit 580.
  • FIG. 2A is a schematic structural diagram of a 7T1C pixel circuit 580.
  • the 7T1C pixel circuit 580 includes a first transistor CT1, a second transistor CT2, a third transistor CT3, a fourth transistor CT4, a fifth transistor CT5, a sixth transistor C6, a seventh transistor CT7, and a storage capacitor Cst.
  • the first transistor CT1-the seventh transistor CT7 are all P-type transistors.
  • the first terminal of the storage capacitor Cst is connected to the first power supply voltage terminal VDD to receive the first power supply voltage V1; the second terminal of the storage capacitor Cst is connected to the first node N1; the first terminal of the light emitting element EL Terminal is connected to the fourth node N4, the second terminal of the light emitting element EL is connected to the second power supply voltage terminal VSS to receive the second power supply voltage V2; the control terminal of the first transistor CT1 is connected to the first node N1; the first transistor CT1 The first terminal of the first transistor CT1 is connected to the second node N2, the second terminal of the first transistor CT1 is connected to the third node N3; the first terminal of the second transistor CT2 is connected to the second node N2, and the second terminal of the second transistor CT2 is connected to The data signal terminal DAT is connected to receive a data signal (for example, a data voltage) Vdata; the first terminal of the third transistor CT3 is connected to the first node N1, and the second terminal of the third transistor CT3
  • control terminal GAT1 of the second transistor CT2 and the control terminal GAT2 of the third transistor CT3 are both connected to the scan signal terminal GAT (not shown in the figure);
  • control terminal EM1 of the fifth transistor CT5 and the control terminal of the seventh transistor CT7 EM2 are all connected to the light-emitting control terminal EM (not shown in the figure);
  • the control terminal of the fourth transistor CT4 is configured as the first reset control terminal RST1;
  • the control terminal of the sixth transistor CT6 is configured as the second reset control terminal RST2.
  • FIG. 2A also shows the first node N1, the second node N2, the third node N3, the fourth node N4, and the light emitting element EL.
  • FIG. 2B is a driving timing diagram of the 7T1C pixel circuit 580 shown in FIG. 2A. As shown in FIG. 2B, each driving cycle of the 7T1C pixel circuit 580 includes a first phase t1, a second phase t2, and a third phase t3.
  • the first reset control terminal RST1 receives the active level, and the scan signal terminal GAT, the second reset control terminal RST2 and the light-emitting control terminal EM all receive the invalid level; this
  • the fourth transistor CT4 is turned on, the second transistor CT2, the third transistor CT3, the fifth transistor CT5, the sixth transistor CT6, and the seventh transistor CT7 are turned off; the fourth transistor CT4 is configured to receive the first reset signal (for example, Reset voltage) Vinit1, and write the first reset signal Vinit1 to the storage capacitor Cst to reset the storage capacitor Cst; the voltage of the first node N1 is Vinit1, and Vinit1 is, for example, a negative value.
  • the first transistor CT1 is turned on.
  • the scan signal terminal GAT and the second reset control terminal RST2 receive the valid level
  • the first reset control terminal RST1 and the light-emitting control terminal EM receive the invalid level
  • the first transistor CT1-the third transistor CT3 and the sixth transistor CT6 are turned on
  • the fourth transistor CT4, the fifth transistor CT5 and the seventh transistor CT7 are turned off
  • the second transistor CT2 receives the data signal Vdata
  • the data signal Vdata is turned on
  • the first transistor CT1 and the third transistor CT3 are written to the control terminal of the first transistor CT1.
  • the storage capacitor Cst stores the data signal Vdata written to the control terminal of the first transistor CT1 at the control terminal of the first transistor CT1.
  • the voltage of a node N1 is Vdata+Vth; the sixth transistor CT6 is configured to receive a second reset signal (for example, a reset voltage) Vinit2, and write the second reset signal Vinit2 to the first end of the light-emitting element EL to emit light
  • a second reset signal for example, a reset voltage
  • Vinit2 The first terminal of the element EL is reset
  • Vinit2 Vinit2
  • Vinit2 is, for example, a negative value.
  • the light-emitting control terminal EM receives the valid level
  • the first reset control terminal RST1, the scan signal terminal GAT, and the second reset control terminal RST2 receive the invalid level
  • the first transistor CT1, the fifth transistor CT5, and the seventh transistor CT7 are turned on
  • the second transistor CT2, the third transistor CT3, the fourth transistor CT4, and the sixth transistor CT6 are turned off
  • the first transistor CT1 is configured to be based on storage
  • the data signal (for example, the data voltage) Vdata in the storage capacitor Cst and the received first power supply voltage V1 are controlled to flow through the first transistor CT1 and from the first power supply voltage terminal VDD to the light emitting element EL for driving the light emitting element.
  • the driving current of EL; the voltage of the first node N1 is Vdata+Vth, and the voltage of the second node N2 is VDD; the driving current Id can be expressed by the following formula.
  • k ⁇ Cox ⁇ W/L; ⁇ is the mobility of carriers in the first transistor CT1, Cox is the capacitance of the gate oxide layer of the first transistor CT1, and W/L is the channel of the first transistor CT1
  • Vth is the threshold voltage of the first transistor CT1
  • Vth is the gate-source voltage of the first transistor CT1
  • Vg is the gate voltage of the first transistor CT1
  • Vs is the source voltage of the first transistor CT1.
  • the 7T1C pixel circuit 580 shown in FIGS. 2A and 2B has a threshold compensation function.
  • FIG. 2C shows a schematic plan view of another display substrate 200.
  • the display substrate 200 includes a first display area 211, a second display area 212, and a third display area 213.
  • FIG. 2D shows a schematic diagram of a partial area RE1 of the first display area 211 and the second display area 212 included in the display substrate 200 shown in FIG. 2C.
  • the first display area 211 includes a plurality of first pixel units 271 arranged in an array, and each first pixel unit 271 includes a first light-emitting element and a pixel circuit;
  • the second display area 212 includes an array array.
  • a plurality of second pixel units 272 are arranged, each of the second pixel units 272 includes a second light-emitting element but does not include a pixel circuit; the second display area 212 also includes a plurality of pixel driving units 281 arranged in an array and an array arrangement
  • the redundant driving unit 282, each pixel driving unit 281 and each redundant driving unit 282 respectively include a pixel circuit but not a light-emitting element.
  • the third display area 213 includes a plurality of third pixel units arranged in an array, and each third pixel unit includes a third light-emitting element and a pixel circuit.
  • the pixel circuits included in the first pixel unit 271, the third pixel unit, the pixel driving unit 281, and the redundant driving unit 282 have the same structure, and they are all, for example, the pixel circuit 580 shown in FIG. 2A.
  • the pixel circuit provided in the redundant driving unit 282 is used to make the electrical environment of the second display area 212 uniform (for example, make the load of the resistance and the capacitance uniform).
  • the first color can be red, green, blue, or other suitable colors.
  • the distribution density per unit area of the multiple first light-emitting elements in the first display area 211 is equal to the distribution density per unit area of the multiple second light-emitting elements in the second display area 212; the multiple first light-emitting elements in the first display area 211
  • the distribution density per unit area is smaller than the distribution density per unit area of the plurality of third light-emitting elements in the third display area 213.
  • At least one embodiment of the present disclosure provides a display substrate, a driving method thereof, and a display device.
  • the display substrate includes a plurality of pixel driving unit groups.
  • Each of the plurality of pixel driving unit groups includes at least two pixel driving units, and the at least two pixel driving units are connected between the first power supply voltage terminal and the first terminal of the same light-emitting element, and are configured to jointly drive the same light-emitting element;
  • the at least two pixel driving units include a first pixel circuit and a second pixel circuit.
  • the first pixel circuit includes a first driving circuit and a first data writing circuit.
  • the first data writing circuit is configured to receive a first data signal and The first data signal is written to the first driving circuit, and the first driving circuit is configured to control the first driving current flowing through the first driving circuit and for driving the same light-emitting element based on the first data signal; and the second pixel circuit includes A second driving circuit and a second data writing circuit, the second data writing circuit is configured to receive the second data signal and write the second data signal to the second driving circuit, the second driving circuit is configured to be based on the second The data signal controls the second driving current flowing through the second driving circuit and used to drive the same light-emitting element.
  • the display substrate can improve the brightness of the light-emitting element driven by the pixel driving unit group of the display substrate.
  • FIG. 3 is an exemplary block diagram of a display substrate 10 provided by at least one embodiment of the present disclosure.
  • the display substrate 10 may be an organic light emitting diode display substrate.
  • the display substrate 10 includes a plurality of pixel driving unit groups 100 and a plurality of light emitting elements 140, and the plurality of pixel driving unit groups 100 are configured to drive the plurality of light emitting elements 140 in a one-to-one correspondence. It should be noted that, for clarity, FIG. 3 only shows one pixel driving unit group 100 and the light-emitting elements 140 driven by the pixel driving unit group 100.
  • each of the plurality of pixel driving unit groups 100 includes at least two pixel driving units 110, and the at least two pixel driving units 110 are connected between the first power supply voltage terminal VDD and the first terminal of the same light emitting element 140. (That is, at least two pixel driving units 110 are connected in parallel between the first power supply voltage terminal VDD and the first terminal of the same light-emitting element 140), and are configured to jointly drive the same light-emitting element 140.
  • the display substrate 10 shown in FIG. 3 exemplifies the display substrate 10 provided by at least one embodiment of the present disclosure by taking the example that each of the plurality of pixel driving unit groups 100 includes two pixel driving units 110.
  • each of the plurality of pixel driving unit groups 100 includes two pixel driving units 110.
  • at least one embodiment of the present disclosure is not limited thereto.
  • at least part of the pixel driving unit group 100 of the display substrate 10 provided by at least one embodiment of the present disclosure may include three, four, or other data-applicable pixel driving units.
  • the first power supply voltage terminal VDD is configured to provide the first power supply voltage.
  • the first terminal of the same light-emitting element 140 is simultaneously connected to the signal output terminals of at least two pixel driving units 110 included in the pixel driving unit group 100, and the second terminal of the same light-emitting element 140 is connected to the second power supply voltage terminal VSS.
  • the first power supply voltage provided by the first power supply voltage terminal VDD is greater than the second power supply voltage provided by the second power supply voltage terminal VSS.
  • the light-emitting element 140 may be an organic light-emitting element, and the organic light-emitting element may be, for example, an organic light-emitting diode, but at least one embodiment of the present disclosure is not limited thereto.
  • the light-emitting element 140 may be an inorganic light-emitting element, for example, the inorganic light-emitting element may be an inorganic light-emitting diode (LED), such as Micro-LED, Mini-LED, and the like.
  • LED inorganic light-emitting diode
  • At least two pixel driving units 110 include a first pixel circuit 120 and a second pixel circuit 130; the first pixel circuit 120 and the second pixel circuit 130 are connected in parallel with each other, and the signal output terminal of the first pixel circuit 120 is The signal output ends of the second pixel circuit 130 are connected to each other, and are all connected to the first end of the same light-emitting element 140 described above.
  • the structures of the first pixel circuit 120 and the second pixel circuit 130 included in at least two pixel driving units 110 for driving the same light-emitting element are different from each other.
  • the first pixel circuit 120 and the second pixel circuit 130 can be implemented as any combination of 3T1C pixel circuits, 5T1C pixel circuits, 7T1C pixel circuits, 8T1C pixel circuits, 8T2C pixel circuits, and other applicable pixel circuits.
  • the first pixel circuit 120 includes a first driving circuit 121 and a first data writing circuit 122.
  • the first data writing circuit 122 is configured to receive a first data signal and write the first data signal to
  • the first driving circuit 121 (for example, the first terminal of the first driving circuit 121)
  • the first driving circuit 121 is configured to control the flow through the first data signal (for example, based on the first data signal and the first power supply voltage).
  • a driving circuit 121 is used to drive the first driving current of the same light-emitting element 140.
  • the second pixel circuit 130 includes a second driving circuit 131 and a second data writing circuit 132, and the second data writing circuit 132 is configured to receive the second data signal and write the second data signal to the second driving circuit 131 (
  • the second driving circuit 131 is configured to control the flow through the second driving circuit 131 based on the second data signal (for example, based on the second data signal and the first power supply voltage) and use The second driving current for driving the same light-emitting element 140.
  • the first driving current and the second driving current may flow through the same light emitting element 140 at the same time. In this case, the current flowing through the same light emitting element 140 is close to the sum of the first driving current and the second driving current.
  • the value of the A parameter and the value of the B parameter are close to mean: the ratio of the difference between the value of the A parameter and the value of the B parameter to the value of the A parameter is less than 15% (for example, less than 10% or less than 5% ).
  • each of the plurality of pixel driving unit groups 100 include at least two pixel driving units 110, and making the at least two pixel driving units drive the same light-emitting element 140 together, it is possible to make the at least two pixel driving units 110 include at least two pixel driving units 110.
  • a pixel circuit 120 and a second pixel circuit 130 respectively generate a first driving current and a second driving current for driving the same light-emitting element 140 in the light-emitting phase, thereby improving the brightness of the light-emitting element 140 driven by the pixel driving unit group 100.
  • the first pixel circuit 120 and the second pixel circuit 130 have the same structure (eg, circuit structure), but at least one embodiment of the present disclosure is not limited thereto.
  • the first pixel circuit 120 and the second pixel circuit 130 may have different structures (for example, circuit structures).
  • each of the plurality of pixel driving unit groups 100 includes a plurality of (at least three) pixel driving units 110
  • each of the plurality of pixel driving units 110 includes one pixel circuit
  • the plurality of pixel driving units 110 The included plurality of pixel circuits have, for example, the same structure.
  • the first data writing circuit 122 is configured to be connected to the first data signal terminal DAT1 to receive the first data signal provided by the first data signal terminal DAT1.
  • the second data writing circuit 132 is configured to be connected to the second data signal terminal DAT2 to receive the second data signal provided by the second data signal terminal DAT2.
  • the first data signal and the second data signal are voltage signals.
  • the first data signal terminal DAT1 and the second data signal terminal DAT2 are the same data signal terminal.
  • the first data signal and the second data signal are the same data signal.
  • the first data signal terminal DAT1 and the second data signal terminal DAT2 are different data signal terminals.
  • the first data signal and the second data signal may be the same data signal or different data. Signal.
  • FIG. 4 is a schematic diagram of the pixel driving unit group 100 of the display substrate 10 shown in FIG. 3.
  • FIG. 4 also shows the light-emitting element 140, the first power supply voltage terminal VDD, the second power supply voltage terminal VSS, and the like.
  • the display substrate 10 shown in FIG. 4 takes the same structure of the first pixel circuit 120 and the structure of the second pixel circuit 130 as an example to illustrate the display substrate 10 provided by at least one embodiment of the present disclosure, but At least one embodiment of the present disclosure is not limited thereto.
  • the first pixel circuit 120 further includes a first signal storage circuit 123, a first compensation connection circuit 124 and a first reset circuit 125.
  • the first signal storage circuit 123 is configured to store the first data signal written to the control terminal of the first driving circuit 121 at the control terminal of the first driving circuit 121.
  • the first signal storage circuit 123 is connected between the first power supply voltage terminal VDD and the control terminal of the first driving circuit 121.
  • the first data writing circuit 122 writes the first data signal to the first end of the first driving circuit 121; the first compensation connection circuit 124 is connected to the second end and the first end of the first driving circuit 121 Between the control terminals of a driving circuit 121 and configured to pass the first data signal written to the first terminal of the first driving circuit 121 through the first driving circuit 121 (for example, through the first driving circuit 121 and the first driving circuit 121).
  • a compensation connection circuit 124) is written to the control terminal of the first driving circuit 121.
  • the first compensation connection circuit 124 to write the data signal written to the first terminal of the first driving circuit 121 to the control terminal of the first driving circuit 121 via the first driving circuit 121
  • the threshold characteristic of the first driving circuit 121 is written into the control terminal of the first driving circuit 121 and stored in the first signal storage circuit 123, so that the threshold characteristic of the first driving circuit 121 can be eliminated for the first driving circuit 121.
  • the first driving current flowing through the first driving circuit 121 and from the first power supply voltage terminal VDD to the light-emitting element 140 is adversely affected by the first driving current for driving the light-emitting element 140, that is, by providing the first compensation connection circuit 124, the current
  • the first pixel circuit 120 provided by at least one disclosed embodiment has a threshold compensation function.
  • control terminal GAT1 of the first data writing circuit 122 and the control terminal GAT2 of the first compensation connection circuit 124 are configured to receive the same first scan signal, thereby causing the first data to be written to the first driving circuit 121
  • the first data signal at the terminal can be written to the control terminal of the first driving circuit 121 by turning on the first driving circuit 121 and the first compensation connection circuit 124 during the data writing and compensation stage of the first pixel circuit 120.
  • the first reset circuit 125 is connected to the first signal storage circuit 123, and the first reset circuit 125 is configured to receive the first reset signal and write the first reset signal to the first signal storage circuit 123 to
  • the first signal storage circuit 123 is reset.
  • the first reset signal may be the first reset voltage.
  • the first reset voltage is a negative value (for example, -3V), so that in the case of process deviation, after resetting the first signal storage circuit 123, the first driving circuit 121 can still be turned on.
  • the first reset circuit 125 is configured to reset the first signal storage circuit 123 in the reset phase of the first pixel circuit 120.
  • the first terminal of the first reset circuit 125 is connected to the first signal storage circuit 123; the second terminal of the first reset circuit 125 is connected to the first reset signal terminal Init1 to receive the first reset signal terminal Init1.
  • Reset signal; the control terminal of the first reset circuit 125 is denoted as RST1.
  • the second pixel circuit 130 further includes a second signal storage circuit 133, a second compensation connection circuit 134 and a third reset circuit 135.
  • the second signal storage circuit 133 is configured to store the second data signal written to the control terminal of the second driving circuit 131 at the control terminal of the second driving circuit 131.
  • the second signal storage circuit 133 is connected between the first power supply voltage terminal VDD and the control terminal of the second driving circuit 131.
  • the second data writing circuit 132 writes the second data signal to the first end of the second driving circuit 131;
  • the second compensation connection circuit 134 is connected to the second end and the first end of the second driving circuit 131 Between the control terminals of the two driving circuits 131 and configured to pass the second data signal written to the first terminal of the second driving circuit 131 through the second driving circuit 131 (for example, through the second driving circuit 131 and the second driving circuit 131).
  • the second compensation connection circuit 134) is written to the control terminal of the second driving circuit 131.
  • the second pixel circuit 130 provided by at least one embodiment of the present disclosure can have a threshold compensation function.
  • control terminal GAT3 of the second data writing circuit 132 and the control terminal GAT4 of the second compensation connection circuit 134 are configured to receive the same second scan signal, thereby causing the first data to be written to the second driving circuit 131
  • the second data signal at the terminal can be written to the control terminal of the second driving circuit 131 by turning on the second driving circuit 131 and the second compensation connection circuit 134 during the data writing and compensation phase of the second pixel circuit 130.
  • the first scan signal and the second scan signal may be the same scan signal, thereby enabling the data writing and compensation phase of the first pixel circuit 120 and the data writing and compensation phase of the second pixel circuit 130 to be synchronized.
  • control terminal GAT1 of the first data writing circuit 122, the control terminal GAT3 of the second data writing circuit 132, the control terminal GAT2 of the first compensation connection circuit 124, and the control terminal GAT4 of the second compensation connection circuit 134 are connected to the same
  • the scanning signal terminal GAT or the scanning signal line (not shown in the figure) can thereby simplify the structure of the display substrate 10.
  • the third reset circuit 135 is connected to the second signal storage circuit 133, and the third reset circuit 135 is configured to receive the third reset signal and write the third reset signal to the second signal storage circuit 133 to The second signal storage circuit 133 is reset.
  • the third reset signal may be a third reset voltage.
  • the third reset voltage is a negative value (for example, -3V), so that in the case of process deviation, after resetting the second signal storage circuit 133, the second driving circuit 131 can still be turned on.
  • the third reset circuit 135 is configured to reset the second signal storage circuit 133 during the reset phase of the second pixel circuit 130.
  • the first terminal of the third reset circuit 135 is connected to the second signal storage circuit 133; the second terminal of the third reset circuit 135 is connected to the third reset signal terminal Init3 to receive the third reset signal terminal Init3.
  • Reset signal; the control terminal of the third reset circuit 135 is denoted as RST3.
  • the control terminal RST1 of the first reset circuit 125 and the control terminal RST3 of the third reset circuit 135 are configured to receive the same first reset control signal, thereby making the reset phase of the first pixel circuit 120 and the second pixel circuit 130
  • the reset phase is synchronized.
  • the control terminal RST1 of the first reset circuit 125 and the control terminal RST3 of the third reset circuit 135 are configured to be connected to the same first reset control terminal RSTT1 or a reset signal line (not shown in the figure), thereby simplifying this
  • the structure of the substrate 10 is shown.
  • the first reset signal terminal Init1 and the third reset signal terminal Init3 are the same reset signal terminal. In this case, the first reset signal and the third reset signal are the same reset signal.
  • the first pixel circuit 120 further includes a first control circuit 126 and a second control circuit 127
  • the second pixel circuit 130 further includes a third control circuit 136 and a fourth control circuit 137.
  • the first control circuit 126 is connected between the first terminal of the first driving circuit 121 and the first power supply voltage terminal VDD, and is configured to control whether the first driving circuit 121 is connected to the first power supply voltage terminal VDD. Electric connection. For example, by providing the first control circuit 126, it is possible to prevent the first power supply voltage provided by the first power supply voltage terminal VDD from affecting the data written to the first terminal of the first driving circuit 121 during the data writing and compensation stage of the first pixel circuit 120. The first data signal has an adverse effect.
  • the second control circuit 127 is connected between the second end of the first drive circuit 121 and the first end of the same light-emitting element 140, and is configured to control whether the first drive circuit 121 emits light with the same light as described above.
  • the first end of the element 140 is electrically connected. For example, by providing the second control circuit 127, the voltage at the second end of the first driving circuit 121 and the voltage at the first end of the light-emitting element 140 can be prevented from interfering with each other during the data writing and compensation phase of the first pixel circuit 120.
  • the voltage at the second end of the first driving circuit 121 can be prevented from adversely affecting the resetting of the first end of the light-emitting element 140 and the light-emitting element 140 can be prevented from emitting light.
  • the voltage at the first terminal of the light-emitting element 140 can be prevented from adversely affecting the voltage at the second terminal of the first driving circuit 121 and threshold compensation.
  • the third control circuit 136 is connected between the first terminal of the second driving circuit 131 and the first power supply voltage terminal VDD, and is configured to control whether the second driving circuit 131 is connected to the first power supply voltage terminal VDD. Electric connection. For example, by providing the third control circuit 136, it is possible to prevent the first power supply voltage provided by the first power supply voltage terminal VDD from affecting the data written to the first terminal of the second driving circuit 131 during the data writing and compensation stage of the second pixel circuit 130. The second data signal has an adverse effect.
  • the fourth control circuit 137 is connected between the second end of the second drive circuit 131 and the first end of the same light-emitting element 140, and is configured to control whether the second drive circuit 131 emits the same light as the above
  • the first end of the element 140 is electrically connected.
  • the voltage at the second end of the second driving circuit 131 and the voltage at the first end of the light-emitting element 140 can be prevented from interfering with each other during the data writing and compensation phase of the second pixel circuit 130.
  • control terminal EM1 of the first control circuit 126, the control terminal EM2 of the second control circuit 127, the control terminal EM3 of the third control circuit 136, and the control terminal EM4 of the fourth control circuit 137 are configured to receive the same light emission control signal Therefore, the first control circuit 126, the second control circuit 127, the third control circuit 136, and the fourth control circuit 137 are turned on at the same time, and the first driving circuit 121 and the second driving circuit 131 (or the first pixel circuit 120 The light emitting element 140 can be driven in synchronization with the second pixel circuit 130).
  • control terminal EM1 of the first control circuit 126, the control terminal EM2 of the second control circuit 127, the control terminal EM3 of the third control circuit 136, and the control terminal EM4 of the fourth control circuit 137 are connected to the same light emission control terminal EM or light emission. Control lines (not shown in the figure), thereby simplifying the structure of the display substrate 10.
  • the first pixel circuit 120 further includes a second reset circuit 128, and the second pixel circuit 130 further includes a fourth reset circuit 138.
  • the second reset circuit 128 is configured to receive a second reset signal and write the second reset signal to the first end of the same light-emitting element 140 to reset the first end of the same light-emitting element 140.
  • the first terminal of the second reset circuit 128 is connected to the first terminal of the light-emitting element 140; the second terminal of the second reset circuit 128 is connected to the second reset signal terminal Init2 to receive the second reset.
  • the second reset signal provided by the signal terminal Init2; the control terminal of the second reset circuit 128 is denoted as RST2.
  • the fourth reset circuit 138 is configured to receive a fourth reset signal and write the fourth reset signal to the first end of the same light-emitting element 140 to reset the first end of the same light-emitting element 140.
  • the first terminal of the fourth reset circuit 138 is connected to the first terminal of the light-emitting element 140; the second terminal of the fourth reset circuit 138 is connected to the fourth reset signal terminal Init2 to receive the fourth reset signal terminal
  • the fourth reset signal provided by Init2; the control terminal of the fourth reset circuit 138 is denoted as RST2.
  • control terminal RST2 of the second reset circuit 128 and the control terminal RST4 of the fourth reset circuit 138 are configured to receive the same reset control signal, so that the second reset circuit 128 and the fourth reset circuit 138 synchronize the same light-emitting element.
  • the first end of the 140 is reset.
  • the control terminal RST2 of the second reset circuit 128 and the control terminal RST4 of the fourth reset circuit 138 are configured to be connected to the same second reset control terminal RSTT2 or a reset signal line (not shown in the figure), thereby simplifying this
  • the structure of the substrate 10 is shown.
  • the second reset signal terminal Init2 and the fourth reset signal terminal Init4 are the same reset signal terminal.
  • the second reset signal and the fourth reset signal are the same reset signal.
  • the first reset signal terminal Init1, the second reset signal terminal Init2, the third reset signal terminal Init3, and the fourth reset signal terminal Init4 are the same reset signal terminal.
  • the first reset signal and the second reset signal , The third reset signal and the fourth reset signal are the same reset signal.
  • the second reset circuit 128 and the fourth reset circuit 138 are configured to eliminate the electric charge that may remain on the light emitting element 140.
  • the first end of the light-emitting element 140 may be reset before the light-emitting stage to improve the accuracy of the brightness of the light-emitting element 140 and the contrast of the display substrate 10.
  • the first end of the light-emitting element 140 may be reset during the data writing and compensation phase or the reset phase.
  • each of the plurality of pixel driving unit groups 100 provided by at least one embodiment of the present disclosure is not limited to include the second reset circuit 128 and the fourth reset circuit 138 at the same time.
  • at least one of the At least part (for example, each) of the plurality of pixel driving unit groups 100 provided by the embodiment may include one of the second reset circuit 128 and the fourth reset circuit 138.
  • the first pixel circuit 120 includes the second reset circuit 128, but the second pixel circuit 130 does not include the fourth reset circuit 138.
  • the pixel driving unit 110 shown in FIG. 4 exemplarily describes at least one embodiment of the present disclosure by taking the first pixel circuit 120 and the second pixel circuit 130 simultaneously having a compensation function, a reset function, and a light emission control function as an example.
  • the first pixel circuit 120 and the second pixel circuit 130 provided by at least one embodiment of the present disclosure may not have the above three functions, or only Part of the functions of the above three functions (that is, less than three functions).
  • the specific structures of the first pixel circuit 120 and the second pixel circuit 130 of the pixel driving unit 110 can be adaptively changed.
  • FIG. 5A is an exemplary circuit diagram of the pixel driving unit group 100 shown in FIG. 4.
  • FIG. 5A also shows the organic light emitting element EL, the first power supply voltage terminal VDD, the second power supply voltage terminal VSS, the first node N1-eighth node N8, and so on.
  • the first driving circuit 121 includes a first transistor T1, the control terminal of the first transistor T1 is connected to the first node N1, the first terminal of the first transistor T1 is connected to the second node N2, and the first transistor T1 is connected to the second node N2.
  • the second terminal of a transistor T1 is connected to the third node N3.
  • the first data writing circuit 122 includes a second transistor T2, the first signal storage circuit 123 includes a first storage capacitor Cst1; the first end of the second transistor T2 is connected to the second node N2, The second terminal of the second transistor T2 is connected to the first data signal terminal DAT1 to receive the first data signal provided by the first data signal terminal DAT1; the first terminal of the first storage capacitor Cst1 is connected to the first power supply voltage terminal VDD, The second end of the first storage capacitor Cst1 is connected to the first node N1.
  • the first compensation connection circuit 124 includes a third transistor T3; the first terminal of the third transistor T3 is connected to the first node N1, and the second terminal of the third transistor T3 is connected to the third node N3 .
  • the control terminal GAT1 of the second transistor T2 and the control terminal GAT2 of the third transistor T3 are both connected to the same scan signal terminal GAT or the same scan signal line (not shown in the figure).
  • the first reset circuit 125 includes a fourth transistor T4, the control terminal of the fourth transistor T4 is denoted as RST1, the first terminal of the fourth transistor T4 is connected to the first node N1, and the fourth transistor T4 The second terminal of is connected to the first reset signal terminal to receive the first reset signal provided by the first reset signal terminal.
  • the first control circuit 126 includes a fifth transistor T5, and the second control circuit 127 includes a seventh transistor T7; the first terminal of the fifth transistor T5 is connected to the first power supply voltage terminal VDD to receive For the first power supply voltage, the second end of the fifth transistor T5 is connected to the second node N2; the first end of the seventh transistor T7 is connected to the third node N3, and the second end of the seventh transistor T7 is connected to the fourth node N4.
  • the second reset circuit 128 includes a sixth transistor T6; the control terminal of the sixth transistor T6 is denoted as RST2, the first terminal of the sixth transistor T6 is connected to the fourth node N4, and the sixth transistor T6 The second terminal of is connected to the second reset signal terminal to receive the second reset signal provided by the second reset signal terminal.
  • the second driving circuit 131 includes an eighth transistor T8, the control terminal of the eighth transistor T8 is connected to the fifth node N5, the first terminal of the eighth transistor T8 is connected to the sixth node N6, and the first terminal of the eighth transistor T8 is connected to the sixth node N6.
  • the second end of the eight transistor T8 is connected to the seventh node N7.
  • the eighth transistor T8 and the first transistor T1 may have the same specifications (for example, threshold voltage), but at least one embodiment of the present disclosure is not limited thereto.
  • the second data writing circuit 132 includes a ninth transistor T9, and the second signal storage circuit 133 includes a second storage capacitor Cst2; the first end of the ninth transistor T9 is connected to the sixth node N6, The second terminal of the ninth transistor T9 is connected to the second data signal terminal DAT2 to receive the second data signal provided by the second data signal terminal DAT2; the first terminal of the second storage capacitor Cst2 is connected to the first power supply voltage terminal VDD, The second end of the second storage capacitor Cst2 is connected to the fifth node N5.
  • the second compensation connection circuit 134 includes a tenth transistor T10; the first end of the tenth transistor T10 is connected to the fifth node N5, and the second end of the tenth transistor T10 is connected to the seventh node N7 .
  • the third reset circuit 135 includes an eleventh transistor T11, the control terminal of the eleventh transistor T11 is marked as RST3, the first terminal of the eleventh transistor T11 is connected to the fifth node N5, and the first terminal of the eleventh transistor T11 is connected to the fifth node N5.
  • the second terminal of the eleven transistor T11 is connected to the third reset signal terminal to receive the third reset signal provided by the third reset signal terminal.
  • the third control circuit 136 includes a twelfth transistor T12
  • the fourth control circuit 137 includes a fourteenth transistor T14
  • the first terminal of the twelfth transistor T12 is connected to the first power supply voltage terminal VDD
  • the second end of the twelfth transistor T12 is connected to the sixth node N6
  • the first end of the fourteenth transistor T14 is connected to the seventh node N7
  • the second end of the fourteenth transistor T14 is connected To the eighth node N8.
  • the fourth reset circuit 138 includes a thirteenth transistor T13; the control terminal of the thirteenth transistor T13 is marked as RST4, the first terminal of the thirteenth transistor T13 is connected to the eighth node N8, and the first terminal of the thirteenth transistor T13 is connected to the eighth node N8.
  • the second terminal of the thirteen transistor T13 is connected to the fourth reset signal terminal to receive the fourth reset signal provided by the fourth reset signal terminal.
  • the eighth node N8 and the fourth node N4 are the same node.
  • the light emitting element 140 includes an organic light emitting element EL, a first end (for example, anode) of the organic light emitting element EL is connected to the fourth node N4, and a second end (for example, cathode) of the organic light emitting element EL
  • the second power supply voltage terminal VSS is connected to receive the second power supply voltage provided by the second power supply voltage terminal VSS.
  • control terminal GAT1 of the second transistor T2 and the control terminal GAT3 of the third transistor T3, the control terminal GAT3 of the ninth transistor T9 and the control terminal GAT4 of the tenth transistor T10 are configured to receive the same scan signal; in this case ,
  • the data writing and compensation phase of the first pixel circuit 120 is synchronized with the data writing and compensation phase of the second pixel circuit 130, and is referred to as the data writing and compensation phase of the pixel driving unit group 100.
  • control terminal GAT1 of the second transistor T2 and the control terminal GAT3 of the third transistor T3, the control terminal GAT3 of the ninth transistor T9 and the control terminal GAT4 of the tenth transistor T10 are all connected to the same scan signal terminal GAT or the same scan signal line (Not shown in the figure).
  • control terminal RST1 of the fourth transistor T4 and the control terminal RST3 of the eleventh transistor T11 are configured to receive the same first reset control signal; in this case, the reset phase of the first pixel circuit 120 and the second pixel circuit
  • the reset phase of 130 is synchronized and is referred to as the reset phase of the pixel driving unit group 100.
  • the control terminal RST1 of the fourth transistor T4 and the control terminal RST3 of the eleventh transistor T11 are connected to the same first reset control terminal RSTT1 or a first reset control line (not shown in the figure).
  • control terminal EM1 of the fifth transistor T5 the control terminal EM2 of the seventh transistor T7, the control terminal EM3 of the twelfth transistor T12, and the control terminal EM4 of the fourteenth transistor T14 are configured to receive the same light emission control signal; this
  • the light-emitting phase of the first pixel circuit 120 and the light-emitting phase of the second pixel circuit 130 are synchronized, and are referred to as the light-emitting phase of the pixel driving unit group 100.
  • control terminal EM1 of the fifth transistor T5 the control terminal EM2 of the seventh transistor T7, the control terminal EM3 of the twelfth transistor T12, and the control terminal EM4 of the fourteenth transistor T14 are connected to the same emission control terminal EM or emission control line (Not shown in the figure).
  • the control terminal RST3 of the sixth transistor T6 and the control terminal RST4 of the thirteenth transistor T13 are configured to receive the same second reset control signal; in this case, the second reset stage and the second reset stage of the first pixel circuit 120
  • the second reset phase of the pixel circuit 130 is synchronized.
  • the control terminal RST3 of the sixth transistor T6 and the control terminal RST4 of the thirteenth transistor T13 are connected to the same second reset control terminal RSTT2 or a second reset control line (not shown in the figure).
  • the second reset phase of the first pixel circuit 120 and the second reset phase of the second pixel circuit 130 may be synchronized with the data writing and compensation phase of the pixel driving unit group 100 or with the reset phase of the pixel driving unit group 100.
  • the third reset signal and the fourth reset signal are configured as the same reset signal.
  • the first transistor T1 to the fourteenth transistor T14 may all be P-type transistors (for example, PMOS transistors, that is, an n-type substrate, p-channel, MOS transistors that carry current through the flow of holes).
  • the first transistor T1-fourteenth transistor T14 is turned off when receiving a high level (first level), and when receiving a low level (second level, the second level is less than the first level)
  • the high level (the first level) is the inactive level (that is, the level that makes the transistor turn off)
  • the low level (the second level) is the active level (that is, the The level at which the transistor is turned on).
  • first transistor T1-fourteenth transistor T14 is not limited to be implemented as P-type transistors. According to actual application requirements, one or more of the first transistor T1-fourteenth transistor T14 can also be implemented as N-type transistors. Transistor.
  • first node N1 to the eighth node N8 is intended to more conveniently describe the connection relationship between the components, and it is not necessary to provide, for example, solder joints or pads in the pixel driving unit group 100 as actual node.
  • FIG. 5B is a driving timing diagram of the pixel driving unit group 100 shown in FIG. 5A.
  • each driving cycle of the pixel driving unit group 100 shown in FIG. 5A includes a reset phase S_re, a data writing and compensation phase S_wc, and a light emitting phase S_EM.
  • the data writing and compensation phase S_wc is temporally located between the reset phase S_re and the light-emitting phase S_EM.
  • the first reset control terminal RSTT1 (corresponding to the control terminal RST1 of the fourth transistor T4 and the control terminal RST3 of the eleventh transistor T11) receives the effective level, and the scan signal Terminal GAT (corresponding to the control terminal GAT1 of the second transistor T2 and the control terminal GAT3 of the third transistor T3, the control terminal GAT3 of the ninth transistor T9 and the control terminal GAT4 of the tenth transistor T10), the second reset control terminal RSTT2 (corresponding to At the control terminal RST3 of the sixth transistor T6 and the control terminal RST4 of the thirteenth transistor T13) and the light emission control terminal EM (corresponding to the control terminal EM1 of the fifth transistor T5, the control terminal EM2 of the seventh transistor T7, and the twelfth transistor
  • the control terminal EM3 of T12 and the control terminal EM4 of the fourteenth transistor T14) receive the inactive level; in this case, the fourth transistor T4 and the eleventh
  • the transistor T5-seventh transistor T7, the ninth transistor T9, the tenth transistor T10, and the twelfth transistor T12-fourteenth transistor T14 are turned off, and the fourth transistor T4 is configured to receive the first reset signal (for example, reset voltage) Vinit1, And write the first reset signal Vinit1 to the first storage capacitor Cst1 to reset the first storage capacitor Cst1; the eleventh transistor T11 is configured to receive the third reset signal (for example, the reset voltage) Vinit3, and reset the third The signal Vinit3 is written into the second storage capacitor Cst2 to reset the second storage capacitor Cst2; the voltage of the first node N1 is Vinit1, the voltage of the fifth node N5 is Vinit3, and Vinit1 and Vinit3 are, for example, negative values (for example, -3V ). For example, after the first reset signal Vinit1 is written into the first storage capacitor Cst1, the first transistor T1 is turned on; after the third reset signal Vinit3 is written into the second storage capacitor Cs
  • the scan signal terminal GAT and the second reset control terminal RSTT2 receive valid levels
  • the first reset control terminal RSTT1 and the light-emitting control terminal EM receive invalid levels.
  • the first transistor T1-the third transistor T3, the sixth transistor T6, the eighth transistor T8-the tenth transistor T10, and the thirteenth transistor T13 are turned on
  • the transistor T7, the eleventh transistor T11, the twelfth transistor T12, and the fourteenth transistor T14 are turned off.
  • the second transistor T2 receives the first data signal (for example, the first data voltage) Vd1, and the first data signal Vd1 is written via the turned-on first transistor T1 and the third transistor T3
  • the first storage capacitor Cst1 stores the first data signal Vd1 written to the control terminal of the first transistor T1 at the control terminal of the first transistor T1
  • the voltage of the first node N1 is Vd1+Vth1
  • Vth1 is the threshold voltage of the first transistor T1.
  • the ninth transistor T9 receives the second data signal (for example, the second data voltage) Vd2, and the second data signal Vd2 is written via the turned-on eighth transistor T8 and the tenth transistor T10
  • the second storage capacitor Cst2 stores the second data signal Vd2 written to the control terminal of the eighth transistor T8 at the control terminal of the eighth transistor T8, and the voltage of the fifth node N5 is Vd2+Vth2
  • Vth2 is the threshold voltage of the eighth transistor T8.
  • the sixth transistor T6 and the thirteenth transistor T13 are configured to receive the same reset signal (for example, the second reset voltage Vinit2), and write the same reset signal to the organic light emitting element
  • the first end of the EL is used to reset the first end of the organic light emitting element EL, and the voltages of the fourth node N4 and the eighth node N8 are Vinit2.
  • the light-emitting control terminal EM receives the valid level
  • the first reset control terminal RSTT1 receives the scan signal terminal GAT
  • the second reset control terminal RSTT2 receive the invalid level
  • the first transistor T1, the fifth transistor T5, the seventh transistor T7, the eighth transistor T8, the twelfth transistor T12, and the fourteenth transistor T14 are turned on
  • the second transistor T2-fourth transistor T4, sixth transistor T6 The ninth transistor T9, the eleventh transistor T11 and the thirteenth transistor T13 are turned off.
  • the first transistor T1 is configured to control the first driving current flowing through the first transistor T1 and used to drive the same organic light emitting element EL based on the first data signal and the first power supply voltage; the eighth transistor T8 is configured based on the second data The signal and the first power supply voltage control the second driving current that flows through the first transistor T1 and is used to drive the same organic light emitting element EL; the voltage of the first node N1 is Vd1+Vth1, and the voltage of the fifth node N5 is Vd2+Vth2; The voltages of the second node N2 and the sixth node N6 are VDD.
  • the inventor of the present disclosure confirmed that the pixel driving unit group 100 shown in FIG. 5A can be improved by the pixel driving unit group shown in FIG. 5A by performing simulation calculations on the display substrate 10 including the pixel driving unit group 100 shown in FIG. 5A.
  • the brightness of the organic light emitting element EL driven by 100 (compared to the pixel circuit 580 shown in FIG. 2A).
  • the display substrate 10 adopts an RGBG pixel arrangement (Pentile pixel arrangement), and each of the above-mentioned red sub-pixel R, green sub-pixel G, blue sub-pixel B, and green sub-pixel G of the display substrate 10 includes The pixel driving unit group 100 shown in FIG.
  • the above-mentioned red sub-pixel R, green sub-pixel G, blue sub-pixel B, and green sub-pixel G include the first data writing circuit 122 and the second data writing circuit 122 of the pixel driving unit group 100
  • the data writing circuit 132 is configured to receive the same data signal (that is, the data voltage Vd), for example, the first data writing circuit 122 and the second data writing circuit 132 are configured to be connected to the same data signal terminal;
  • the data voltages Vd received by the pixel driving unit group 100 included in the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G are 2.7V, 3.3V, 2.28V, and 3.3V, respectively.
  • the display substrate 500 also adopts an RGBG pixel arrangement (Pentile pixel arrangement), and each of the above-mentioned red sub-pixel R, green sub-pixel G, blue sub-pixel B, and green sub-pixel G in the display substrate 500 includes FIG. 2A
  • the pixel circuit 580 shown; the data voltages Vd received by the pixel circuits included in the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G in the display substrate 500 are 2.7V, 3.3V, 2.28V and 3.3V.
  • Each of the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G in the display substrate 500 includes the voltage values of the first node N1-fourth node N4 of the pixel circuit and the organic light emitting
  • the voltage value of N4 and the current value flowing through the organic light-emitting element EL can be seen in Table 1.
  • each of the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G of the display substrate 10 includes the fifth node N5-eighth node N8 of the pixel drive unit group 100
  • the voltage values are respectively equal to (substantially equal to) the voltage values of the first node N1-the fourth node N4 of the above-mentioned pixel driving unit group 100.
  • the value of the A parameter and the value of the B parameter are substantially equal to mean that the ratio of the difference between the value of the A parameter and the value of the B parameter to the value of the A parameter is less than 3% (for example, less than 1%).
  • the duration of one image frame is both 16.56 ms.
  • the driving current of the red sub-pixel R including the pixel driving unit group 100 shown in FIG. 5A and the driving current of the red sub-pixel R including the pixel circuit 580 shown in FIG. 2A The ratio of the current is 179.8%; the driving current of the green sub-pixel G (the first green sub-pixel G) including the pixel driving unit group 100 shown in FIG. 5B and the green sub-pixel G including the pixel circuit 580 shown in FIG. 2A
  • the ratio of the driving current of the driving current is 185.3%; the ratio of the driving current of the blue sub-pixel B including the pixel driving unit group 100 shown in FIG. 5B to the driving current of the blue sub-pixel B including the pixel circuit 580 shown in FIG.
  • the driving current of the green sub-pixel G (the second green sub-pixel G) including the pixel driving unit group 100 shown in FIG. 5B and the driving current of the green sub-pixel G including the pixel circuit 580 shown in FIG. 2A
  • the ratio of is 185.3%, that is, for the first simulation example described above, the driving current provided by the pixel driving unit group 100 is about 1.8 times the driving current provided by the pixel circuit 580.
  • the second simulation example is similar to the first simulation example, therefore, only the differences between the two simulation examples will be explained here, and the similarities will not be repeated.
  • the difference between the second simulation example and the first simulation example lies in the driving unit group 100 or pixels included in the red sub-pixel R, green sub-pixel G, blue sub-pixel B, and green sub-pixel G in the second simulation example
  • the data voltage Vd received by the circuit 580 is 2.9V, 3.2V, 2.5V, and 3.2V, respectively.
  • the driving current value provided by each of the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G in the display substrate 500 and the display substrate 10 can be referred to Table 2. It should be noted that, considering that the driving current provided by the first green sub-pixel G and the second green sub-pixel G are close (or substantially the same), therefore, Table 2 only shows the driving current provided by one green sub-pixel G Current value.
  • the driving current of the red sub-pixel R including the pixel driving unit group 100 shown in FIG. 5A and the driving current of the red sub-pixel R including the pixel circuit 580 shown in FIG. 2A The ratio of the current is 185.15%; the ratio of the driving current of the green sub-pixel G including the pixel driving unit group 100 shown in FIG. 5B to the driving current of the green sub-pixel G including the pixel circuit 580 shown in FIG. 2A is 186.10%; The ratio of the driving current of the blue sub-pixel B including the pixel driving unit group 100 shown in FIG. 5B to the driving current of the blue sub-pixel B including the pixel circuit 580 shown in FIG. 2A is 193.56%, that is, for the above In the second simulation example, the driving current provided by the pixel driving unit group 100 is more than 1.8 times the driving current provided by the pixel circuit 580.
  • the inventors of the present disclosure have also noticed in their research that although driving the same light-emitting element 140 by using at least two pixel driving units 110 included in the pixel driving unit group 100 can increase the driving current flowing through the light-emitting element 140, in pixel driving
  • the pixel driving unit group 100 provides The driving current may not meet the zero gray scale requirement for the driving current (that is, the driving current Id flowing through the organic light emitting element EL is less than 1 pA), and therefore the brightness of the light emitting element 140 may deviate (for example, greater than) the predetermined zero gray Order brightness.
  • the third simulation example is similar to the first simulation example. Therefore, only the differences between the two simulation examples will be explained here, and the similarities will not be repeated.
  • the difference between the third simulation example and the first simulation example lies in the driving unit group 100 or pixels included in the red sub-pixel R, green sub-pixel G, blue sub-pixel B, and green sub-pixel G of the third simulation example
  • the data voltage Vd received by the circuit 580 is 6.5V.
  • the driving current value provided by each of the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G in the display substrate 500 and the display substrate 10 can be referred to Table 3.
  • 6.5V is the data voltage corresponding to the zero gray scale of the organic light emitting element EL.
  • Table 3 only shows the driving current value of one green sub-pixel G.
  • the driving current Id provided by the pixel circuit 580 included in the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B included in the display substrate 500 are all less than 1 pA; however, The driving current Id provided by the pixel driving unit group 100 included in the red sub-pixel R and the green sub-pixel G included in the display substrate 10 is greater than 1 pA, that is, the pixel driving included in the red sub-pixel R and the green sub-pixel G included in the display substrate 10 The driving current Id provided by the unit group 100 cannot make the red sub-pixel R and the green sub-pixel G display zero gray scale.
  • the red sub-pixel R and the green sub-pixel G included in the display substrate 10 include the driving provided by the pixel driving unit group 100
  • the current Id does not meet the zero gray scale requirement for the drive current (that is, the drive current Id is less than 1 pA).
  • the inventor of the present disclosure has also noticed in research that the red sub-pixel R and the green sub-pixel included in the display substrate 10 can be made by adjusting (for example, increasing) the data signal (data voltage Vd) provided to the pixel driving unit group 100
  • the driving current Id provided by the pixel driving unit group 100 included in G satisfies the zero gray scale requirement for driving current.
  • the fourth simulation example is similar to the first simulation example. Therefore, only the differences between the two simulation examples will be explained here, and the similarities will not be repeated.
  • the difference between the fourth simulation example and the first simulation example lies in the driving unit group 100 or pixels included in the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G in the fourth simulation example
  • the data voltage Vd received by the circuit 580 is 6.7V.
  • the driving current value provided by each of the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G in the display substrate 500 and the display substrate 10 can be referred to Table 4.
  • the driving current Id provided by the pixel driving unit group 100 included in the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B included in the display substrate 10 are all less than 1 pA, That is, they all satisfy the zero gray scale requirement for driving current.
  • the inventors of the present disclosure have also noticed in their research that although the data signal (data voltage Vd) provided to the pixel drive unit group 100 can be adjusted (for example, increased) to make each pixel drive unit group 100 of the display substrate 10 provide
  • the driving current Id satisfies the zero gray scale requirement for the driving current, but this requires pre-processing (for example, compensation or correction) of the data signal (data voltage Vd) provided to the pixel driving unit group 100.
  • the inventor of the present disclosure has also noticed in research that the first data writing circuit 122 and the second data writing circuit 132 of the pixel driving unit group 100 are configured to receive the same data signal (that is, the data voltage In the case of Vd), the brightness of the light-emitting element 140 is more sensitive to fluctuations in the voltage value of the data signal at a low gray scale, that is, at a low gray scale, the voltage value of the data signal received by the pixel driving unit group 100 is less than With small fluctuations, the brightness of the light-emitting element 140 may vary greatly.
  • the brightness transition performance of the low grayscale image may be poor.
  • the inventors of the present disclosure have also noticed in their research that the data signals provided to the pixel drive unit group 100 can be controlled in segments so that each pixel drive unit group 100 of the display substrate 10 can increase the drive current at a high gray scale.
  • the value of Id and the low gray scale make the driving current value more accurate, so as to improve the brightness transition performance of the low gray scale image displayed by the display substrate 10 in the case of increasing the brightness of the high gray scale image.
  • the first data writing circuit 122 and the second data writing circuit 132 of the pixel driving unit group 100 are configured to receive the same data.
  • Signal for example, the data voltage corresponding to the gray scale of the light-emitting element 140.
  • the pixel driving unit group 100 simultaneously uses the first pixel circuit 120 and the second pixel circuit 130 to drive the light-emitting element 140;
  • the first data writing circuit 122 and the second data writing circuit 132 of the pixel driving unit group 100 are configured to receive different data signals (that is, data Voltage Vd).
  • the data voltage received by the second data writing circuit 132 is made to correspond to the zero gray scale voltage (for example, 6.7-7.0V), and the The data voltage received by the first data writing circuit 122 corresponds to the data voltage of the to-be-displayed grayscale of the light-emitting element 140.
  • the pixel driving unit group 100 only uses the first pixel circuit 120 to drive the light-emitting element 140.
  • the predetermined gray scale is greater than the minimum gray scale of the display substrate (or light emitting element) and smaller than the maximum gray scale of the display substrate (or light emitting element).
  • the allowable display brightness of the display substrate or the light-emitting element 140 is greater than or equal to 0 gray scale and less than or equal to 255 gray scale, 0 ⁇ X ⁇ 255.
  • the predetermined gray scale X is between 10-35 gray scales.
  • the predetermined gray level X is greater than or equal to 16 gray levels and less than or equal to 32 gray levels.
  • the following is a fifth simulation example to illustrate that by segmenting the data signal provided to the pixel driving unit group 100, the value of the driving current Id provided by the pixel driving unit group 100 of the display substrate 10 can be made more accurate at low gray scales. .
  • the fifth simulation example is similar to the first simulation example. Therefore, only the differences between the two simulation examples will be explained here, and the similarities will not be repeated.
  • the difference between the fifth simulation example and the first simulation example is that the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G included in the display substrate 10 include a pixel drive unit group
  • the first data writing circuit 122 and the second data writing circuit 132 of 100 are configured to receive different data signals.
  • the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G included in the display substrate 10 include the data voltages received by the first data writing circuit 122 of the pixel driving unit group 100.
  • the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G of the display substrate 10 include the data voltages received by the second data writing circuit 132 of the pixel drive unit group 100. It is 7V.
  • the driving current value provided by each of the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the green sub-pixel G in the display substrate 10 can be referred to Table 5.
  • the driving current Id provided by the pixel driving unit group 100 included in the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B included in the display substrate 10 are all less than 1 pA, That is, they all satisfy the zero gray scale requirement for driving current.
  • the inventor of the present disclosure also noticed in his research that the data voltage received by the second data writing circuit 132 corresponds to the zero gray-scale voltage (for example, 6.7V), and the data received by the first data writing circuit 122
  • the driving current fluctuates.
  • the data voltage of the gray scale to be displayed is greater than the predetermined voltage, there is no fluctuation in the driving current.
  • FIG. 6 shows the change curve of the driving current Id of the red sub-pixel with time T.
  • the data voltage received by the second data writing circuit 132 is 6.7V.
  • the curve CR1, curve CR2, curve CR3, curve CR4, curve CR5, and curve CR6 shown in FIG. 6 respectively receive data voltages of 5.5V, 5.6V, 5.7V, 5.8V, and 5.9V at the first data writing circuit 122.
  • the driving current Id fluctuates (see the partial protrusions in the dashed box shown in FIG.
  • the grayscale value corresponding to 5.7V can be used as the predetermined grayscale value X_R of the red sub-pixel.
  • a similar method can also be used to determine the predetermined grayscale values X_B and X_G.
  • FIG. 7 is a schematic cross-sectional view of a display substrate 10 provided by at least one embodiment of the present disclosure.
  • the display substrate 10 includes a display side and a non-display side, and the displayed screen of the display substrate 10 is configured to be displayed on the display side of the display substrate 10, that is, the display side of the display substrate 10 is the light-emitting side of the display substrate 10.
  • the display side and the non-display side face each other in the normal direction of the display surface of the display substrate 10 (for example, a direction perpendicular to the display substrate 10).
  • the display substrate 10 includes a display layer 160 and a sensing layer 170, the sensing layer 170 is disposed on the non-display side of the display substrate 10; the display layer 160 includes a display area 104, and the display area 104 includes a first display area 101.
  • the second display area 102 and the third display area 103; the sensing layer 170 includes a sensor 171, and the sensor 171 and the first display area 101 are in the normal direction of the display surface of the display substrate 10 (for example, perpendicular to the display substrate 10). Direction), and are configured to receive and process the light signal passing through the first display area 101, and the light signal may be visible light, infrared light, or the like.
  • the senor 171 may be an image sensor 171, and may be used to collect an image of the external environment facing the light-collecting surface of the sensor 171; the sensor 171 may also be an infrared sensor, a distance sensor, or the like.
  • the sensor 171 in the case where the display device 20 including the display substrate 10 is a mobile terminal such as a mobile phone or a notebook, the sensor 171 can be used to implement a camera of the mobile terminal such as a mobile phone or a notebook.
  • the sensor 171 may include sensor pixels arranged in an array.
  • each photosensitive pixel may include a photosensitive detector (for example, a photodiode, a phototransistor) and a switching transistor (for example, a switching transistor).
  • the photodiode can convert the light signal irradiated on it into an electrical signal, and the switching transistor can be electrically connected with the photodiode to control whether the photodiode is in the state of collecting the light signal and the time for collecting the light signal.
  • FIG. 8 is a schematic plan view of an example of the display substrate 10 shown in FIG. 7, and the display substrate 10 shown in FIG. 7 corresponds to the line AA' of the display substrate 10 shown in FIG. 8.
  • the first display area 101, the second display area 102, and the third display area 103 do not overlap each other.
  • the second display area 102 surrounds (eg, completely surrounds) the first display area 101.
  • the third display area 103 at least surrounds the second display area 102.
  • the third display area 103 partially surrounds the second display area 102.
  • the shape of the first display area 101 may be a circle, and the shape of the second display area 102 may be a rectangle, but the embodiment of the present disclosure is not limited thereto.
  • the shapes of the first display area 101 and the second display area 102 may be irregular shapes or other suitable shapes.
  • FIG. 9 is a schematic diagram of the first display area 101 and the partial area REG1 of the second display area 102 of the display substrate 10 shown in FIG. 8.
  • FIG. 10 is a schematic diagram of a partial area REG2 of the third display area 103 of the display substrate 10 shown in FIG. 8.
  • the first display area 101 includes a plurality of first light-emitting elements 141
  • the second display area 102 includes a plurality of second light-emitting elements 142.
  • the distribution density per unit area of the plurality of first light-emitting elements 141 in the first display area 101 is equal to the distribution density per unit area of the plurality of second light-emitting elements 142 in the second display area 102.
  • the plurality of first light emitting elements 141 and the plurality of second light emitting elements 142 are arranged in an array as a whole.
  • the third display area 103 includes a plurality of third light emitting elements 143 arranged in an array.
  • the first light-emitting element 141, the second light-emitting element 142, and the third light-emitting element 143 may all be organic light-emitting elements, and the organic light-emitting elements may be, for example, organic light-emitting diodes, but at least one embodiment of the present disclosure is not limited thereto.
  • the first light-emitting element 141, the second light-emitting element 142, and the third light-emitting element 143 may all be inorganic light-emitting elements.
  • the first light emitting element 141, the second light emitting element 142, and the third light emitting element 143 may have the same structure.
  • the distribution density per unit area of the plurality of first light-emitting elements 141 in the first display area 101 is smaller than the distribution density per unit area of the plurality of third light-emitting elements 143 in the third display area 103.
  • the distribution density per unit area of the plurality of second light-emitting elements 142 in the second display area 102 is smaller than the distribution density per unit area of the plurality of third light-emitting elements 143 in the third display area 103.
  • the first display area 101 and the second display area 102 may be referred to as low-resolution areas of the display substrate 10.
  • the distance between two adjacent first light-emitting elements 141 in the first direction D1 is greater than the distance between two adjacent third light-emitting elements 143 in the first direction D1, and the two adjacent ones in the second direction D2
  • the distance between the first light-emitting elements 141 is greater than the distance between two adjacent third light-emitting elements 143 in the second direction D2.
  • the distance between two adjacent first light-emitting elements 141 in the first direction D1 is substantially equal to four times the distance between two adjacent third light-emitting elements 143 in the first direction D1, and in the second direction D2
  • the distance between two adjacent first light emitting elements 141 is substantially equal to twice the distance between two adjacent third light emitting elements 143 in the second direction D2.
  • the distance between two adjacent first light-emitting elements 141 in the first direction D1 is in the range of 280-380 microns, and the distance between two adjacent first light-emitting elements 141 in the second direction D2 is 100- In the range of 160 microns; the distance between two adjacent third light-emitting elements 143 in the first direction D1 and the second direction D2 is in the range of 110-130 microns. It should be noted that, here, the distance between two elements refers to the distance between the centers of the two elements.
  • the second display area 102 includes a plurality of pixel driving unit groups 100 arranged in an array, that is, the plurality of pixel driving unit groups 100 are located in the second display area 102.
  • each of the plurality of pixel driving unit groups 100 includes at least two driving units 110, the two driving units 110 include a first pixel circuit 120 and a second pixel circuit 130, and the first pixel circuit 120 and the second pixel circuit 130 Have the same circuit structure.
  • each of the two driving units 110 includes one pixel circuit.
  • the plurality of pixel driving unit groups 100 includes a plurality of first driving unit groups 111; the plurality of first driving unit groups 111 are configured to drive a plurality of first light-emitting elements 141 in a one-to-one correspondence.
  • the structure of each of the plurality of first driving unit groups 111 is the same as the structure of the pixel driving unit group 100.
  • FIG. 9 shows that as shown in FIG.
  • each of the plurality of first driving unit groups 111 includes a first pixel circuit 120 and a second pixel circuit 130, and the signal output ends of the first pixel circuit 120 and the second pixel circuit 130 are connected to each other, It is electrically connected to the same first light-emitting element 141 located in the first display area 101 to jointly drive the same first light-emitting element 141 described above.
  • the light-emitting brightness of the plurality of first light-emitting elements 141 can be improved, and thus the display substrate 10 including the plurality of first light-emitting elements can be improved.
  • the brightness of the first display area 101 of a light-emitting element 141 that is, the overall brightness of the low-resolution area of the display substrate 10 is improved.
  • the first display area 101 is not provided with the pixel driving unit group 100 or the pixel circuit, it is possible to The transmittance of the first display area 101 (the transmittance of light incident on the first display area 101) is increased. Since the sensor 171 and the first display area 101 overlap in the normal direction of the display surface of the display substrate 10 (see FIG. 7), the incidence of the element pairs in the first display area 101 into the first display area 101 can be reduced. The light signal transmitted toward the sensor 171 is blocked, so that the signal-to-noise ratio of the image output by the sensor 171 can be improved.
  • the first display area 101 may be referred to as a high light transmission area of a low resolution area of the display substrate 10.
  • the display substrate 10 further includes a plurality of first wirings 144; the plurality of first wirings 144 are electrically connected to the plurality of first driving unit groups 111 and one-to-one with the plurality of first driving unit groups 111.
  • the connected plurality of first light-emitting elements 141 corresponds to the connected plurality of first light-emitting elements 141.
  • each of the above-mentioned multiple first wires 144 can be implemented as a transparent wire, which can further improve the transmittance of the first display area 101 and the signal-to-noise ratio of the image output by the sensor 171.
  • the plurality of first driving unit groups 111 for driving the plurality of first light-emitting elements 141 are not limited to be provided in the second display area 102. In some examples, without considering the transmittance of the first display area 101, at least part (for example, all) of the plurality of first driving unit groups 111 for driving the plurality of first light-emitting elements 141 may also be Set in the first display area 101.
  • the plurality of pixel driving unit groups 100 further includes a plurality of second driving unit groups 112; the plurality of second driving unit groups 112 are configured to drive at least one second light-emitting element 142 in a one-to-one correspondence.
  • the structure of each of the plurality of second driving unit groups 112 is the same as the structure of the pixel driving unit group 100.
  • the plurality of second driving unit groups 112 to drive the plurality of second light-emitting elements 142 in one-to-one correspondence, the light-emitting brightness of the plurality of second light-emitting elements 142 can be improved, and thus the display substrate 10 including the plurality of second light-emitting elements can be improved.
  • the brightness of the second display area 102 of the two light-emitting elements 142 that is, the overall brightness of the low-resolution area of the display substrate 10 is improved.
  • each of the plurality of second driving unit groups 112 includes a second light-emitting element 142, a first pixel circuit 120, and a second pixel circuit 130, and the first pixel circuit 120 and the second pixel circuit 130 It is configured to jointly drive the second light emitting element 142.
  • the third display area 103 includes a plurality of pixel units 150 arranged in an array, and the plurality of third light-emitting elements 143 are respectively located in the plurality of pixel units 150.
  • each of the plurality of pixel units 150 further includes a third pixel circuit 121, and the third pixel circuit 121 included in each of the plurality of pixel units 150 is used to drive the third light-emitting element 143 in the pixel unit 150.
  • the first pixel circuit 120, the second pixel circuit 130, and the third pixel circuit 121 have the same structure.
  • the third light-emitting element 143 is driven by a single pixel circuit (the third pixel circuit 121), and the first light-emitting element 141 and the second light-emitting element 142 are driven by the pixel driving unit group 100, the third light-emitting element 143 included in the pixel unit 150 is
  • the data voltage received by the pixel circuit 121 is equal to the data voltage received by the pixel driving unit group 100
  • the brightness of the first light-emitting element 141 and the second light-emitting element 142 is greater than the brightness of the third light-emitting element 143, thereby enabling the first display
  • the brightness of the area 101 and the second display area 102 more closely matches the brightness of the third display area 103 (for example, when the received data voltage is the same, the brightness of the first display area 101 and the second display area 102 is closer to the third display area.
  • the brightness of the display area 103 that is, the brightness of the areas with different display resolutions of the display substrate 10 are more matched.
  • the pixel driving unit group 100 of the display substrate 10 shown in FIGS. 8 and 9 borrows the redundancy in the display substrate 10 shown in FIGS. 2C and 2D.
  • the pixel circuit in the remaining pixel unit serves as the second pixel circuit 130 of the pixel driving unit group 100. Therefore, the display substrate 10 shown in FIGS. 8 and 9 can improve the pixel driving unit group 100 without additional pixel circuits.
  • the brightness of the driven light-emitting element 140 is compared to the display substrate 10 shown in FIGS. 2C and 2D.
  • FIG. 9 is only used to show that the first driving unit group 111 includes a first pixel circuit 120 and a second pixel circuit 130, the first light-emitting element 141 is electrically connected to the first driving unit group 111, and the second driving unit group 112 includes a second light-emitting element 142 and a first pixel circuit 120 and a second pixel circuit 130 that drive the second light-emitting element 142 together.
  • FIG. 10 is only used to show that the pixel unit 150 includes the third light-emitting element 143 and is used to drive the second light-emitting element 142.
  • the third pixel circuit 121 of three light-emitting elements 143 does not limit the first light-emitting element 141, the second light-emitting element 142, the third light-emitting element 143, the first pixel circuit 120, the second pixel circuit 130, and the third pixel circuit 121
  • the specific shape and relative positional relationship of the first light-emitting element 141, the second light-emitting element 142, the third light-emitting element 143, the first pixel circuit 120 and the second pixel circuit 130 and the relative positional relationship can be determined according to actual application requirements. set up.
  • the plurality of pixel driving unit groups 100 shown in FIG. 9 includes a plurality of first driving unit groups 111
  • the first display area 101 includes a plurality of first light-emitting elements 141
  • the plurality of first wirings 144 are electrically connected to each other.
  • the plurality of pixel driving unit groups 100 includes one, two, or other suitable number (that is, at least one) of the first driving unit group 111; correspondingly, the first display area 101 includes at least one first light emitting Element 141; the display substrate 10 includes at least one first wiring 144; at least one first driving unit group 111 is configured to drive at least one first light-emitting element 141 in a one-to-one correspondence; at least one first wiring 144 is electrically connected to at least one The first driving unit group 111 and at least one first light emitting element 141 connected to the at least one first driving unit group 111 in a one-to-one correspondence.
  • the number of first driving unit groups 111 in the second display area 102 and the number of first wirings 144 are equal to the number of first light-emitting elements 141 included in the first display area 101.
  • the plurality of pixel driving unit groups 100 shown in FIG. 9 includes a plurality of second driving unit groups 112
  • the second display area 102 includes a plurality of second light-emitting elements 142
  • the plurality of second driving unit groups 112 are configured In order to drive the plurality of second light-emitting elements 142 in one-to-one correspondence, the plurality of second driving unit groups 112 respectively drive the plurality of second light-emitting elements 142 in one-to-one correspondence with the plurality of second driving unit groups 112, along the display substrate 10
  • the normal directions of the display surface of the display surface at least partially overlap each other, but at least one embodiment of the present disclosure is not limited thereto.
  • the plurality of pixel driving unit groups 100 further includes one, two or other suitable number (that is, at least one) of the second driving unit group 112; correspondingly, the second display area 102 includes at least one second driving unit group 112; Light emitting element 142; at least one second driving unit group 112 is configured to drive at least one second light emitting element 142 in a one-to-one correspondence; at least one second driving unit group 112 and at least one second driving unit group 112 are respectively driven in a one-to-one correspondence
  • the at least one second light-emitting element 142 at least partially overlaps each other in the direction along the normal line of the display surface of the display substrate 10.
  • the number of second driving unit groups 112 in the second display area 102 is equal to the number of second light emitting elements 142 included in the second display area 102.
  • FIG. 11 shows a schematic diagram of a partial area of the second display area 102 shown in FIG. 9.
  • the plurality of first driving unit groups 111 and the plurality of second driving unit groups 112 are arranged in an array as a whole and alternately arranged in the row direction of the display substrate 10 and the column direction of the display substrate 10;
  • At least two pixel driving units 110 included in each of the plurality of pixel driving unit groups 100 are arranged side by side in the row direction of the display substrate 10.
  • the first data writing circuit 122 (not shown in FIG. 11, see FIG. 4) of the first pixel circuit 120 of the pixel driving unit group 100 is connected to the first data signal terminal via the first data line 161 DAT1 is electrically connected to receive the first data signal provided by the first data signal terminal DAT1;
  • the second data writing circuit 132 (not shown in FIG. 11, see FIG. 4) of the second pixel circuit 130 of the pixel driving unit group 100 is passed through
  • the second data line 162 is electrically connected to the second data signal terminal DAT2 to receive the second data signal provided by the second data signal terminal DAT2;
  • the first data line 161 and the second data line 162 are different data lines.
  • the signal terminal DAT1 and the second data signal terminal DAT2 are different data signal terminals.
  • the first data signal and the second data signal may be the same data signal or different data signals.
  • the transmission direction of the data signal in the first data line 161 and the transmission direction of the data signal in the second data line 162 are opposite, but the embodiment of the present disclosure is not limited thereto.
  • the transmission direction of the data signal in the first data line 161 and the transmission direction of the data signal in the second data line 162 are the same.
  • first data line 161 and the second data line 162 may be located on the same electrode layer or on different electrode layers.
  • both the first data line 161 and the second data line 162 are in direct contact with the same film layer.
  • the pixel driving unit The first data writing circuit 122 and the second data writing circuit 132 of the group 100 are configured to receive the same data signal (for example, the data voltage corresponding to the to-be-displayed gray scale of the light-emitting element 140).
  • the pixel The driving unit group 100 simultaneously uses the first pixel circuit 120 and the second pixel circuit 130 to drive the light emitting element 140.
  • the data voltage received by the second data writing circuit 132 is made to correspond to the zero gray scale voltage (for example, 0 ⁇ X ⁇ 255). , 6.7-7.0V), and make the data voltage received by the first data writing circuit 122 correspond to the data voltage of the to-be-displayed grayscale of the light-emitting element 140; in this case, the pixel driving unit group 100 only uses the first pixel circuit 120 drives the light emitting element 140.
  • first data writing circuit 122 and the second data writing circuit 132 are not limited to being electrically connected to different data signal terminals, and there is no need to perform segmental control on the data signal provided to the pixel driving unit group 100.
  • the first data writing circuit 122 and the second data writing circuit 132 are electrically connected to the same data signal terminal to simplify the structure of the display substrate 10; in this case, the first data received by the first data writing circuit 122 The signal is the same as the second data signal received by the second data writing circuit 132.
  • the following is an exemplary description with reference to FIG. 12.
  • FIG. 12 shows another schematic diagram of a partial area of the second display area 102 shown in FIG. 9.
  • the example shown in FIG. 12 is similar to the example shown in FIG. 11, therefore, only the differences between the two are described here, and the same dimensions are not repeated here.
  • the first data writing circuit 122 and the second data writing circuit 132 are electrically connected to the same data signal terminal DAT via the first data line 161 and the second data line 162, respectively, to receive the first data.
  • Signal and second data signal; the first data signal and the second data signal are the same.
  • first data writing circuit 122 and the second data writing circuit 132 are not limited to being electrically connected to the same data signal terminal via the first data line 161 and the second data line 162 respectively. According to actual application requirements, the first The data writing circuit 122 and the second data writing circuit 132 may be electrically connected to the same data signal terminal via the same data line to further simplify the structure of the display substrate 10.
  • the display substrate 10 may include a plurality of scanning signal lines (for example, gate lines) and a plurality of data lines arranged to cross each other (for example, perpendicularly), and a plurality of voltage control lines arranged in parallel with the scanning signal lines.
  • each pixel circuit (for example, the first pixel circuit 120 and the second pixel circuit 130) is connected to a corresponding scan signal line and a corresponding data line.
  • the scan signal terminal corresponding to each pixel circuit may be connected to the corresponding scan signal line.
  • the signal line is connected, the data signal terminal corresponding to each pixel circuit can be connected to the corresponding data line, and the first power supply voltage terminal VDD and the second power supply voltage terminal VSS corresponding to each pixel circuit can be connected to the corresponding voltage control line. connect.
  • a plurality of scan signal lines respectively extend along the row direction of the display substrate 10 of the display substrate 10 (for example, the first direction D1 shown in FIGS. 9-12), and the plurality of scan data lines respectively have columns along the display substrate 10.
  • a portion extending in a direction for example, the second direction D2 shown in FIGS. 9-12).
  • the first direction D1 and the second direction D2 cross (e.g., perpendicular).
  • the pixel driving unit group 100 provided by at least one embodiment of the present disclosure may be used to drive the first display. Based on the light-emitting elements 140 in the area 101 and the second display area 102, the data signal provided to the pixel driving unit group 100 is additionally compensated. For example, a timing controller may be used to compensate the data signal of the data signal provided to the pixel driving unit group 100.
  • FIG. 13 shows another schematic diagram of the first display area 101 and the partial area REG2 of the second display area 102 shown in FIG. 8.
  • the plurality of first driving unit groups 111 and the plurality of second driving unit groups 112 are arranged in an array as a whole and alternately arranged in the row direction and the column direction of the display substrate 10; At least two pixel driving units 110 included in each of the unit groups 100 are arranged side by side in the column direction of the display substrate 10.
  • two second light-emitting elements 142 respectively driven by two second driving unit groups 112 adjacent in the row direction of the display substrate 10 are located in different rows;
  • the two second light emitting elements 142 driven by the two adjacent second driving unit groups 112 are located in the same column;
  • the two first light emitting elements 142 are respectively driven by the two first driving unit groups 111 adjacent in the row direction of the display substrate.
  • the elements 141 are located in different rows; the two first light-emitting elements 141 respectively driven by the two first driving unit groups 111 adjacent in the column direction of the display substrate are located in the same column; in this case, the first display area 101
  • the distribution of the first light-emitting elements 141 and the distribution of the second light-emitting elements 142 in the second display area 102 are more uniform, so that the quality of the image displayed by the display substrate 10 can be improved.
  • At least one embodiment of the present disclosure also provides a display device 20, which includes any pixel circuit or any display substrate 10 provided in at least one embodiment of the present disclosure.
  • FIG. 14 is an exemplary block diagram of a display device 20 provided by at least one embodiment of the present disclosure. As shown in FIG. 14, the display device 20 includes any display substrate 10 provided by at least one embodiment of the present disclosure.
  • FIG. 15 is a schematic diagram of the display device 20 shown in FIG. 14.
  • the display device 20 further includes a first data driving circuit 191 and a second data driving circuit 192.
  • the first data driving circuit 191 is configured to provide a first data signal to the first data writing circuit 122 via a first data signal terminal DAT1 located in the first data driving circuit 191;
  • the second data driving circuit 192 is configured to provide a first data signal via a first data signal terminal DAT1 located in the first data driving circuit 191;
  • the second data signal terminal DAT2 in the data driving circuit 192 provides the second data signal to the second data writing circuit 132.
  • FIG. 16 shows the third pixel circuit of the display substrate shown in FIG. 15.
  • the display substrate 10 further includes a plurality of third pixel circuits 121; the first data driving circuit 191 is also configured to provide a data signal to at least one of the plurality of third pixel circuits 121.
  • the circuit structure of each of the plurality of third pixel circuits 121 is the same as that of the first pixel circuit 120.
  • the plurality of light-emitting elements (third light-emitting elements 143) driven by the plurality of third pixel circuits 121 are different from the plurality of light-emitting elements driven by the plurality of pixel driving unit groups 100, that is, the third pixel circuit 121 and the pixel driving unit
  • the group 100 is configured to drive different light-emitting elements.
  • the multiple light-emitting elements driven by the multiple third pixel circuits 121 have the same structure as the multiple light-emitting elements driven by the multiple pixel drive unit groups 100.
  • FIG. 17 is a schematic plan view of the display device 20 shown in FIG. 14.
  • the display substrate 10 for example, the display layer 160 of the display substrate 10) of the display device 20 includes a display area 104 and a peripheral area 105 at least partially surrounding the display area 104.
  • the peripheral area 105 is provided with a first data driving circuit 191 and a second data driving circuit 192.
  • the first data driving circuit 191 is configured to pass through the first data signal terminal DAT1 located in the first data driving circuit 191 and the first data line 161.
  • the first data writing circuit 122 provides the first data signal;
  • the second data driving circuit 192 is configured to write to the second data signal terminal DAT2 and the second data line 162 in the second data driving circuit 192 132 provides a second data signal.
  • the first data line 161 provides data signals for the normal resolution area of the display substrate 10 (that is, the third display area 103); the first data line 161 is also the low resolution area of the display substrate 10 (for example, the first At least one of the display area 101 and the second display area 102) provides a first data signal, and the second data line 162 is only a low-resolution area of the display substrate 10 (for example, at least one of the first display area 101 and the second display area 102).
  • A) Provide a second data signal.
  • the first data driving circuit 191 and the second data driving circuit 192 are provided on both sides of the display area 104 in the column direction of the display substrate 10 of the display substrate 10.
  • at least one of the first data driving circuit 191 and the second data driving circuit 192 is implemented as a driving chip.
  • the driving chip may be bonded on the display substrate 10 via a flexible circuit board, and provide data signals for display to a plurality of data lines via the flexible circuit, so as to drive the display substrate 10 to realize a display function.
  • the peripheral area 105 may also be provided with gate drive integration (GOA, not shown in the figure) on the array substrate, and multiple output terminals of the GOA are respectively connected to multiple gate lines GL to provide gate scanning for the multiple gate lines.
  • GOA gate drive integration
  • the display device 20 shown in FIG. 17 is driven by two driving chips.
  • both the first data line 161 and the second data line 162 extend along the column direction of the display substrate 10.
  • FIG. 18 is another schematic plan view of the display device 20 shown in FIG. 14.
  • the display device 20 shown in FIG. 18 is similar to the display device 20 shown in FIG. 17. Therefore, only two differences will be described here, and the similarities will not be repeated.
  • the first data driving circuit 191 and the second data driving circuit 192 are provided on the same side of the display area 104 in the column direction of the display substrate 10.
  • the first data driving circuit 191 and the second data driving circuit 192 are arranged in the same driving chip 106.
  • FIG. 19A is another schematic plan view of the display device 20 shown in FIG. 14.
  • the display device 20 shown in FIG. 19A is similar to the display device 20 shown in FIG. 18. Therefore, only two differences will be described here, and the similarities will not be repeated.
  • the second data line 162 is routed from the area between the first display area 101 and the second display area 102 to the second display area 102. Therefore, the data line 162 also includes a line along the first direction D1.
  • the extended part it should be noted that the area between the first display area 101 and the second display area 102 refers to the first light emitting element 141 located at the outermost position in the first display area 101 and the first light emitting element 141 located at the outermost distance from the second display area 102.
  • part of the first data line 161 may also be routed from the area between the first display area 101 and the second display area 102 to the second display area 102.
  • FIG. 19B shows the area between the first display area 101 and the second display area 102 of the display substrate 10 of the display device 20 shown in FIG. 19A.
  • the second data line 162 is routed from the area between the first display area 101 and the second display area 102 to the second display area 102.
  • the display device can increase the brightness (for example, overall brightness) of the low-resolution area of the display device (that is, the first display area and the second display area); correspondingly, the upper limit of the brightness of the low-resolution area of the display device And the brightness adjustment range has also been improved.
  • the brightness for example, overall brightness
  • At least one embodiment of the present disclosure further provides a driving method for driving any display substrate provided by at least one embodiment of the present disclosure, which includes: providing a first data signal to a first data writing circuit, and The second data writing circuit provides a second data signal; and causes the first drive circuit to control the first drive current flowing through the first drive circuit based on the first data signal, and causes the second drive circuit to control the flow through the first drive circuit based on the second data signal
  • the second driving current of the second driving circuit drives the same light-emitting element.
  • FIG. 20 is an exemplary flowchart of a driving method of a display substrate provided by at least one embodiment of the present disclosure.
  • the driving method of the display substrate provided by at least one embodiment of the present disclosure will be exemplarily described below in conjunction with FIG. 20.
  • the driving method of the display substrate includes the following steps S110 and S120.
  • Step S110 Provide a first data signal to the first data writing circuit, and provide a second data signal to the second data writing circuit.
  • Step S120 enabling the first driving circuit to control the first driving current flowing through the first driving circuit based on the first data signal, and enabling the second driving circuit to control the second driving current flowing through the second driving circuit based on the second data signal, To drive the same light-emitting element.
  • each of the plurality of pixel driving unit groups include at least two pixel driving units, and allowing at least two pixel driving units to jointly drive the same light-emitting element, it is possible to make the first pixel circuit and the first pixel circuit included in the at least two pixel driving units and The second pixel circuit separately generates the first driving current and the second driving current for driving the same light-emitting element in the light-emitting phase, thereby improving the brightness of the light-emitting element driven by the pixel driving unit group.
  • the driving method includes: making the data voltage of the second data signal provided to the second data writing circuit not equal to the data voltage provided to the first data writing circuit The data voltage of the first data signal.
  • the predetermined gray scale is greater than the minimum gray scale of the display substrate and smaller than the maximum gray scale of the display substrate.
  • the predetermined gray scale X is between 10-35 gray scales.
  • the predetermined gray level X is greater than or equal to 16 gray levels and less than or equal to 32 gray levels.
  • the data voltage of the second data signal provided to the second data writing circuit is a voltage corresponding to zero gray scale, and the first data is written
  • the first data signal provided by the circuit corresponds to the data voltage of the to-be-displayed gray scale of the same light-emitting element; in this case, the pixel driving unit group only uses the first pixel circuit to drive the light-emitting element.
  • the driving method includes: making the data voltage of the second data signal provided to the second data writing circuit equal to that provided to the first data writing circuit The data voltage of the first data signal; in this case, the pixel driving unit group simultaneously uses the first pixel circuit and the second pixel circuit to drive the light-emitting element.
  • the data voltage of the second data signal provided to the second data writing circuit and the data voltage of the first data signal provided to the first data writing circuit are both equal to the data corresponding to the to-be-displayed gray scale of the same light-emitting element. Voltage.
  • each pixel drive unit group of the display substrate can increase the value of the drive current at a high gray level and make the drive current value more at a low gray level. Accurate, thereby improving the quality of the image displayed on the display substrate.

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Abstract

一种显示基板及其驱动方法、显示装置。该显示基板(10)包括多个像素驱动单元组(100)。每个像素驱动单元组(100)包括至少两个像素驱动单元(110)，其连接在第一电源电压端(VDD)和同一发光元件(140)的第一端之间，被配置为共同驱动同一发光元件(140)；至少两个像素驱动单元(110)包括具有第一驱动电路(121)和第一数据写入电路(122)的第一像素电路(120)以及具有第二驱动电路(131)和第二数据写入电路(122)的第二像素电路(130)，第一数据写入电路(122)和第二数据写入电路(122)分别被配置为将接收的第一数据信号写入至第一驱动电路(121)以及将接收的第二数据信号写入至第二驱动电路(131)，第一驱动电路(121)和第二驱动电路(131)分别被配置为控制用于驱动同一发光元件(140)的第一驱动电流和第二驱动电流。该显示基板(10)可以提升发光元件(140)的亮度。

Description

显示基板及其驱动方法、显示装置 技术领域
本公开的实施例涉及一种显示基板及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示器件具有视角宽、对比度高、响应速度快等特点。并且，相比于无机发光显示器件，有机发光二极管显示器件具有更高的发光亮度、更低的驱动电压等优势。由于具有上述特点和优势，有机发光二极管(OLED)显示器件逐渐受到人们的广泛关注并且可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
发明内容
本公开的至少一个实施例提供了一种显示基板，其包括多个像素驱动单元组。所述多个像素驱动单元组的每个包括至少两个像素驱动单元，所述至少两个像素驱动单元连接在第一电源电压端和同一发光元件的第一端之间，被配置为共同驱动所述同一发光元件；所述至少两个像素驱动单元包括第一像素电路和第二像素电路，所述第一像素电路包括第一驱动电路和第一数据写入电路，所述第一数据写入电路被配置为接收第一数据信号且将所述第一数据信号写入至所述第一驱动电路，所述第一驱动电路被配置为基于所述第一数据信号控制流经所述第一驱动电路且用于驱动所述同一发光元件的第一驱动电流；以及所述第二像素电路包括第二驱动电路和第二数据写入电路，所述第二数据写入电路被配置为接收第二数据信号且将所述第二数据信号写入至所述第二驱动电路，所述第二驱动电路被配置为基于所述第二数据信号控制流经所述第二驱动电路且用于驱动所述同一发光元件的第二驱动电流。
例如，在所述显示基板的至少一个示例中，所述显示基板还包括：互不重叠的第一显示区域和第二显示区域，以及至少一条第一走线。所述多个像素驱动单元组位于所述第二显示区域中；所述多个像素驱动单元组包括至少一个第一驱动单元组；所述第一显示区域包括至少一个第一发光元件；所述至少一 个第一驱动单元组被配置为一一对应地驱动所述至少一个第一发光元件；以及所述至少一条第一走线电连接所述至少一个第一驱动单元组和与所述至少一个第一驱动单元组一一对应连接的所述至少一个第一发光元件。
例如，在所述显示基板的至少一个示例中，所述多个像素驱动单元组还包括至少一个第二驱动单元组；所述第二显示区域包括至少一个第二发光元件；以及所述至少一个第二驱动单元组被配置为一一对应地驱动所述至少一个第二发光元件。
例如，在所述显示基板的至少一个示例中，所述至少一个第二驱动单元组分别和所述至少一个第二驱动单元组一一对应驱动的所述至少一个第二发光元件，在沿所述显示基板的显示面的法线方向彼此至少部分重叠。
例如，在所述显示基板的至少一个示例中，所述至少一个第一发光元件包括多个第一发光元件，所述至少一个第二发光元件包括多个第二发光元件；以及所述第一显示区域中所述多个第一发光元件的单位面积分布密度等于所述第二显示区域中所述多个第二发光元件的单位面积分布密度。
例如，在所述显示基板的至少一个示例中，所述多个第一发光元件和所述多个第二发光元件整体上以阵列方式布置。
例如，在所述显示基板的至少一个示例中，所述显示基板还包括：至少部分围绕所述第二显示区域的第三显示区域。所述第三显示区域包括多个第三发光元件；以及所述第一显示区域中所述多个第一发光元件的单位面积分布密度小于所述第三显示区域中所述多个第三发光元件的单位面积分布密度。
例如，在所述显示基板的至少一个示例中，所述至少一个第一驱动单元组包括多个第一驱动单元组；所述至少一个第二驱动单元组包括多个第二驱动单元组；以及所述多个第一驱动单元组和所述多个第二驱动单元组整体上以阵列方式布置且在所述显示基板的行方向和所述显示基板的列方向上交替布置。
例如，在所述显示基板的至少一个示例中，所述多个像素驱动单元组的每个包括的至少两个像素驱动单元在所述显示基板的列方向上并列布置；分别被在所述显示基板的行方向上相邻的两个所述第二驱动单元组驱动的两个第二发光元件位于不同行；分别被在所述显示基板的列方向上相邻的两个所述第二驱动单元组驱动的两个第二发光元件位于同一列；分别被在所述显示基板的行方向上相邻的两个所述第一驱动单元组驱动两个第一发光元件位于不 同行；以及分别被在所述显示基板的列方向上相邻的两个所述第一驱动单元组驱动的两个第一发光元件位于同一列。
例如，在所述显示基板的至少一个示例中，所述第一数据写入电路和所述第二数据写入电路与同一数据信号端电连接，以接收所述第一数据信号和所述第二数据信号；以及所述第一数据信号和所述第二数据信号相同。
例如，在所述显示基板的至少一个示例中，所述第一数据写入电路经由第一数据线与第一数据信号端电连接，以接收所述第一数据信号端提供的所述第一数据信号；所述第二数据写入电路经由第二数据线与第二数据信号端电连接，以接收所述第二数据信号端提供的所述第二数据信号；以及所述第一数据线和所述第二数据线为不同的数据线，以及所述第一数据信号端和所述第二数据信号端为不同的数据信号端。
例如，在所述显示基板的至少一个示例中，所述多个像素驱动单元组的每个包括的至少两个像素驱动单元在所述显示基板的行方向上并列布置；所述显示基板还包括互不重叠的第一显示区域和第二显示区域；以及所述第一数据线从所述第一显示区域和所述第二显示区域之间的区域走线至所述第二显示区域，所述第二数据线沿所述显示基板的列方向延伸。
例如，在所述显示基板的至少一个示例中，所述显示基板还包括传感器。所述传感器设置在所述显示基板的非显示侧，与所述第一显示区域在所述显示基板的显示面的法线方向上叠置，且被配置为接收并处理穿过所述第一显示区域的光信号。
本公开的至少一个实施例还提供了一种显示装置，其包括本公开的至少一个实施例提供的任一显示基板。
例如，在所述显示装置的至少一个示例中，所述显示装置还包括第一数据驱动电路和第二数据驱动电路。所述第一数据驱动电路配置为经由位于所述第一数据驱动电路中的第一数据信号端向所述第一数据写入电路提供所述第一数据信号；以及所述第二数据驱动电路配置为经由位于所述第二数据驱动电路中的第二数据信号端向所述第二数据写入电路提供所述第二数据信号。
例如，在所述显示装置的至少一个示例中，所述显示基板还包括多个第三像素电路；以及所述多个第三像素电路驱动的多个发光元件不同于所述多个像素驱动单元组驱动的多个发光元件，所述第一数据驱动电路还配置为向所述多个第三像素电路中至少之一提供数据信号。
本公开的至少一个实施例还提供了一种用于驱动本公开的至少一个实施例提供的任一显示基板的驱动方法，其包括：向所述第一数据写入电路提供所述第一数据信号，以及向所述第二数据写入电路提供所述第二数据信号；以及使得所述第一驱动电路基于所述第一数据信号控制流经所述第一驱动电路的第一驱动电流，以及使得所述第二驱动电路基于所述第二数据信号控制流经所述第二驱动电路的第二驱动电流，以驱动所述同一发光元件。
例如，在所述驱动方法的至少一个示例中，在所述同一发光元件的待显示灰阶小于预定灰阶的情况下，所述驱动方法包括：使得向所述第二数据写入电路提供的第二数据信号的数据电压不等于向所述第一数据写入电路提供的第一数据信号的数据电压。所述预定灰阶大于所述显示基板的最小灰阶且小于所述显示基板的最大灰阶。
例如，在所述驱动方法的至少一个示例中，向所述第二数据写入电路提供的所述第二数据信号的数据电压为对应于零灰阶的电压。
例如，在所述驱动方法的至少一个示例中，在所述同一发光元件的待显示灰阶大于等于所述预定灰阶的情况下，所述驱动方法包括：使得向所述第二数据写入电路提供的第二数据信号的数据电压等于向所述第一数据写入电路提供的第一数据信号的数据电压。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A是一种显示基板的截面示意图；
图1B是图1A所示的显示基板的平面示意图；
图1C是图1B所示的显示基板的部分区域的示意图；
图2A为一种7T1C像素电路的结构示意图；
图2B为图2A所示的7T1C像素电路的驱动时序图；
图2C示出了另一种显示基板的平面示意图；
图2D示出了图2C所示的显示基板包括的第一显示区域和第二显示区域的部分区域的示意图；
图3是本公开的至少一个实施例提供的显示基板的示例性框图；
图4是图3所示的显示基板的像素驱动单元组的示意图；
图5A是图4所示的像素驱动单元组的示例性电路图；
图5B是图5A所示的像素驱动单元组驱动时序图；
图6示出了红色子像素的驱动电流随时间的变化曲线；
图7是本公开的至少一个实施例提供的显示基板的截面示意图；
图8是图7所示的显示基板的一个示例的平面示意图；
图9是图8所示的显示基板的第一显示区域和第二显示区域的部分区域的示意图；
图10是图8所示的显示基板的第三显示区域的部分区域的示意图；
图11示出了图9所示的第二显示区域的部分区域的一个示意图；
图12示出了图9所示的第二显示区域的部分区域的另一个示意图；
图13示出了图8所示的第一显示区域和第二显示区域的部分区域的另一种示意图；
图14是本公开的至少一个实施例提供的显示装置的示例性框图；
图15是图14所示的显示装置的一个示意图；
图16示出了图15所示的显示基板的第三像素电路；
图17是图14所示的显示装置的一种平面示意图；
图18是图14所示的显示装置的另一种平面示意图；
图19A是图14所示的显示装置的再一种平面示意图；
图19B示出了图19A所示的显示装置的显示基板的第一显示区域和第二显示区域之间的区域；以及
图20是本公开的至少一个实施例提供的显示基板的驱动方法的示例性流程图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例的附图，对本发明实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本发明的一部分实施例，而不是全部的实施例。基于所描述的本发明的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
本公开的发明人注意到，当前的具有屏下传感器(摄像头)的显示基板的对应于屏下传感器(摄像头)的显示区域的发光亮度较低，由此影响了显示基板显示的图像的质量。下面结合图1A、图1B、图2A和图2B进行示例性说明。
图1A是一种显示基板500的截面示意图，图1B是图1A所示的显示基板500的平面示意图，图1C是图1B所示的显示基板500的部分区域513的示意图。图1B所示的显示基板500对应于图1A所示的显示基板10的BB’线。
如图1A所示，该显示基板500包括显示层510和感测层520，感测层520设置在显示基板500的非显示侧(即背离使用者一侧)。如图1A-图1C所示，显示层510包括第一显示区域511和第二显示区域512；第一显示区域511包括阵列排布的多个第一发光元件531，第二显示区域512包括阵列排布的多个第二发光元件532。例如，多个第一发光元件531和多个第二发光元件532具有相同的结构和性能特性。
如图1A所示，感测层520包括传感器521，传感器521与第一显示区域511在显示基板500的显示面的法线方向上叠置，且被配置为接收并处理穿过第一显示区域511的光信号。
如图1C所示，为了减小第一显示区域511中的元件对入射至第一显示区域511并朝向传感器521传输的光信号的遮挡，第一显示区域511中多个第一发光元件531的单位面积分布密度小于第二显示区域512中多个第二发光元件532的单位面积分布密度。然而，这使得第一显示区域511的有效发光 面积小于第二显示区域512的有效发光面积，并使得显示基板500显示的图像中对应于第一显示区域511的图像区域的亮度可能低于预定亮度。
例如，显示层510还包括多个第一像素电路和多个第二像素电路(图1A-图1C未示出，参见图2A)；多个第一像素电路被配置为一一对应的驱动多个第一发光元件531，多个第二像素电路被配置为一一对应的驱动多个第二发光元件532。例如，多个第一像素电路和多个第二像素电路具有相同的电路结构。
例如，在驱动多个第一发光元件的多个第一像素电路接收的数据信号(例如，数据电压)等于驱动多个第二发光元件的多个第二像素电路接收的数据信号(例如，数据电压)的情况下，多个第一发光元件的发光亮度小于多个第二发光元件的发光亮度，并因此使得显示基板显示的图像中对应于第一显示区域511的图像区域的亮度与图像中对应于第二显示区域512的图像区域的亮度差距相对较大。
多个第一像素电路和多个第二像素电路的电路结构可以根据实际应用需求进行设定。例如，多个第一像素电路和多个第二像素电路的每个可以实现为2T1C像素电路、3T1C像素电路、5T1C像素电路7T1C像素电路或其它适用的像素电路。需要说明的是，2T1C像素电路为包括两个晶体管和一个存储电容Cst的像素电路，7T1C像素电路为包括七个晶体管和一个存储电容Cst的像素电路。
下面以多个第一像素电路和多个第二像素电路的每个实现为7T1C像素电路580对图1A和图1B所示的显示基板500做示例性说明。
图2A为一种7T1C像素电路580的结构示意图。如图2A所示，该7T1C像素电路580包括第一晶体管CT1、第二晶体管CT2、第三晶体管CT3、第四晶体管CT4、第五晶体管CT5、第六晶体管C6、第七晶体管CT7和存储电容Cst。例如，第一晶体管CT1-第七晶体管CT7均为P型晶体管。
如图2A所示，存储电容Cst的第一端与第一电源电压端VDD相连，以接收第一电源电压V1；存储电容Cst的第二端与第一节点N1相连；发光元件EL的第一端与第四节点N4相连，发光元件EL的第二端与第二电源电压端VSS相连，以接收第二电源电压V2；第一晶体管CT1的控制端与第一节点N1相连；第一晶体管CT1的第一端与第二节点N2相连，第一晶体管CT1的第二端与第三节点N3相连；第二晶体管CT2的第一端与第二节点N2相 连，第二晶体管CT2的第二端与数据信号端DAT相连，以接收数据信号(例如，数据电压)Vdata；第三晶体管CT3的第一端与第一节点N1相连，第三晶体管CT3的第二端与第三节点N3相连；第四晶体管CT4的第一端与第一节点N1相连；第四晶体管CT4的第二端与第一复位信号端Init1相连，以接收第一复位信号端Init1提供的第一复位信号Vinit1；第五晶体管CT5的第一端与第一电源电压端VDD相连，第五晶体管CT5的第一端与第二节点N2相连；第六晶体管CT6的第一端与第四节点N4相连；第六晶体管CT6的第二端与第二复位信号端Init2相连，以接收第二复位信号Vinit2；第七晶体管CT7的第一端与第三节点N3相连，第七晶体管CT7的第二端与第四节点N4相连。例如，第二晶体管CT2的控制端GAT1和第三晶体管CT3的控制端GAT2均连接至扫描信号端GAT(图中未示出)；第五晶体管CT5的控制端EM1和第七晶体管CT7的控制端EM2均连接至发光控制端EM(图中未示出)；第四晶体管CT4的控制端被配置为第一复位控制端RST1；第六晶体管CT6的控制端被配置为第二复位控制端RST2。
为描述方便，图2A还示出了第一节点N1、第二节点N2、第三节点N3、第四节点N4和发光元件EL。
图2B为图2A所示的7T1C像素电路580的驱动时序图。如图2B所示，该7T1C像素电路580的每个驱动周期包括第一阶段t1、第二阶段t2和第三阶段t3。
如图2A和图2B所示，在第一阶段t1中，第一复位控制端RST1接收有效电平，扫描信号端GAT、第二复位控制端RST2和发光控制端EM均接收无效电平；此种情况下，第四晶体管CT4开启，第二晶体管CT2、第三晶体管CT3、第五晶体管CT5、第六晶体管CT6和第七晶体管CT7关闭；第四晶体管CT4被配置接收第一复位信号(例如，复位电压)Vinit1，且将第一复位信号Vinit1写入至存储电容Cst，以对存储电容Cst复位；第一节点N1的电压为Vinit1，Vinit1例如为负值。例如，在对存储电容Cst复位之后，第一晶体管CT1开启.
如图2A和图2B所示，在第二阶段t2中，扫描信号端GAT和第二复位控制端RST2接收有效电平，第一复位控制端RST1和发光控制端EM接收无效电平；此种情况下，第一晶体管CT1-第三晶体管CT3以及第六晶体管CT6开启，第四晶体管CT4、第五晶体管CT5和第七晶体管CT7关闭；第二晶体 管CT2接收数据信号Vdata，且数据信号Vdata经由开启的第一晶体管CT1和第三晶体管CT3被写入至第一晶体管CT1的控制端，存储电容Cst在第一晶体管CT1的控制端存储被写入至第一晶体管CT1的控制端的数据信号Vdata，第一节点N1的电压为Vdata+Vth；第六晶体管CT6被配置接收第二复位信号(例如，复位电压)Vinit2，且将第二复位信号Vinit2写入至发光元件EL的第一端，以对发光元件EL的第一端复位，第四节点N4的电压为Vinit2，Vinit2例如为负值。
如图2A和图2B所示，在第三阶段t3中，发光控制端EM接收有效电平，第一复位控制端RST1、扫描信号端GAT和第二复位控制端RST2接收无效电平；此种情况下，第一晶体管CT1、第五晶体管CT5和第七晶体管CT7开启，第二晶体管CT2、第三晶体管CT3、第四晶体管CT4和第六晶体管CT6关闭；第一晶体管CT1被配置为，基于存储在存储电容Cst中的数据信号(例如，数据电压)Vdata以及所接收的第一电源电压V1，控制流经第一晶体管CT1且从第一电源电压端VDD至发光元件EL、用于驱动发光元件EL的驱动电流；第一节点N1的电压为Vdata+Vth，第二节点N2的电压为VDD；驱动电流Id可以由以下的公式表示。
Figure PCTCN2020074001-appb-000001
此处，k＝μ×Cox×W/L；μ为第一晶体管CT1中载流子的迁移率，Cox为第一晶体管CT1的栅氧化层的电容，W/L为第一晶体管CT1的沟道的宽长比，Vth为第一晶体管CT1的阈值电压，Vth为第一晶体管CT1的栅源电压，Vg为第一晶体管CT1的栅极电压，Vs为第一晶体管CT1的源极电压。
由上述公式可知，第一晶体管CT1生成的驱动电流Id与第一晶体管CT1的阈值电压无关，因此，图2A和图2B所示的7T1C像素电路580具有阈值补偿功能。
图2C示出了另一种显示基板200的平面示意图。如图2C所示，该显示基板200包括第一显示区域211、第二显示区域212和第三显示区域213。图 2D示出了图2C所示的显示基板200包括的第一显示区域211和第二显示区域212的部分区域RE1的示意图。如图2D所示，第一显示区域211包括阵列排布的多个第一像素单元271，每个第一像素单元271包括一个第一发光元件和一个像素电路；第二显示区域212包括阵列排布的多个第二像素单元272，每个第二像素单元272包括一个第二发光元件但不包括像素电路；第二显示区域212还包括阵列排布的多个像素驱动单元281以及阵列排布的冗余驱动单元282，每个像素驱动单元281和每个冗余驱动单元282分别包括一个像素电路但不包括发光元件。例如，第三显示区域213包括阵列排布的多个第三像素单元，每个第三像素单元包括一个第三发光元件和一个像素电路。例如，第一像素单元271、第三像素单元、像素驱动单元281和冗余驱动单元282包括的像素电路的结构相同，且例如均为图2A所示的像素电路580。例如，冗余驱动单元282中设置的像素电路用于使得以使得第二显示区域212的电学环境均匀(例如，使得电阻和电容的负载均匀)。
例如，第二显示区域212的显示第一颜色的第二像素单元272的第二发光元件的发光面积与第三显示区域213的显示第一颜色的第三像素单元的第三发光元件的发光面积彼此不同。例如，第一显示区域211的显示第一颜色的第一像素单元271的第一发光元件的发光面积与第三显示区域213的显示第一颜色的第三像素单元的第三发光元件的发光面积彼此不同。例如，第一颜色可以为红色、绿色、蓝色或其它适用的颜色。
例如，第一显示区域211的多个第一发光元件的单位面积分布密度等于第二显示区域212的多个第二发光元件的单位面积分布密度；第一显示区域211的多个第一发光元件的单位面积分布密度小于第三显示区域213的多个第三发光元件的单位面积分布密度。
本公开的至少一个实施例提供了一种显示基板及其驱动方法、显示装置。该显示基板包括多个像素驱动单元组。多个像素驱动单元组的每个包括至少两个像素驱动单元，至少两个像素驱动单元连接在第一电源电压端和同一发光元件的第一端之间，被配置为共同驱动同一发光元件；至少两个像素驱动单元包括第一像素电路和第二像素电路，第一像素电路包括第一驱动电路和第一数据写入电路，第一数据写入电路被配置为接收第一数据信号且将第一数据信号写入至第一驱动电路，第一驱动电路被配置为基于第一数据信号控制流经第一驱动电路且用于驱动同一发光元件的第一驱动电流；以及第二像素 电路包括第二驱动电路和第二数据写入电路，第二数据写入电路被配置为接收第二数据信号且将第二数据信号写入至第二驱动电路，第二驱动电路被配置为基于第二数据信号控制流经第二驱动电路且用于驱动同一发光元件的第二驱动电流。该显示基板可以提升被显示基板的像素驱动单元组驱动的发光元件的亮度。
下面通过几个示例或实施例对根据本公开实施例提供的显示基板进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例或实施例中不同特征可以相互组合，从而得到新的示例或实施例，这些新的示例或实施例也都属于本公开保护的范围。
图3是本公开的至少一个实施例提供的显示基板10的示例性框图。例如，该显示基板10可以为有机发光二极管显示基板。
如图3所示，该显示基板10包括多个像素驱动单元组100和多个发光元件140，多个像素驱动单元组100被配置为一一对应地驱动多个发光元件140。需要说明的是，为清楚起见，图3仅示出了一个像素驱动单元组100以及被该像素驱动单元组100驱动的发光元件140。
如图3所示，多个像素驱动单元组100的每个包括至少两个像素驱动单元110，至少两个像素驱动单元110连接在第一电源电压端VDD和同一发光元件140的第一端之间(也即，至少两个像素驱动单元110彼此并联在第一电源电压端VDD和同一发光元件140的第一端之间)，被配置为共同驱动同一发光元件140。
需要说明的是，图3所示的显示基板10以多个像素驱动单元组100的每个包括两个像素驱动单元110为例对本公开的至少一个实施例提供的显示基板10做示例性说明，但本公开的至少一个实施例不限于此。例如，本公开的至少一个实施例提供的显示基板10的至少部分像素驱动单元组100可以包括三个、四个或其它适用数据的像素驱动单元。
例如，第一电源电压端VDD被配置为提供第一电源电压。例如，上述同一发光元件140的第一端同时与像素驱动单元组100包括的至少两个像素驱动单元110的信号输出端相连，上述同一发光元件140的第二端与第二电源电压端VSS相连，以接收第二电源电压端VSS提供的第二电源电压。例如，第一电源电压端VDD提供的第一电源电压大于第二电源电压端VSS提供的第二电源电压。
例如，该发光元件140可以为有机发光元件，有机发光元件例如可以为有机发光二极管，但本公开的至少一个实施例不限于此。例如，该发光元件140可以为无机发光元件，例如无机发光元件可以为无机发光二极管(LED)，例如Micro-LED、Mini-LED等。
如图3所示，至少两个像素驱动单元110包括第一像素电路120和第二像素电路130；第一像素电路120和第二像素电路130彼此并联，第一像素电路120的信号输出端和第二像素电路130的信号输出端彼此相连，且均与上述同一发光元件140的第一端相连。
例如，用于驱动同一发光元件的至少两个像素驱动单元110包括的第一像素电路120和第二像素电路130的结构彼此不同。例如，第一像素电路120和第二像素电路130可以实现为3T1C像素电路、5T1C像素电路、7T1C像素电路、8T1C像素电路、8T2C像素电路和其它适用的像素电路的任意组合。
如图3所示，第一像素电路120包括第一驱动电路121和第一数据写入电路122，第一数据写入电路122被配置为接收第一数据信号且将第一数据信号写入至第一驱动电路121(例如，第一驱动电路121的第一端)，第一驱动电路121被配置为基于第一数据信号(例如，基于第一数据信号和第一电源电压)控制流经第一驱动电路121且用于驱动同一发光元件140的第一驱动电流。第二像素电路130包括第二驱动电路131和第二数据写入电路132，第二数据写入电路132被配置为接收第二数据信号且将第二数据信号写入至第二驱动电路131(例如，第二驱动电路131的第一端)，第二驱动电路131被配置为基于第二数据信号(例如，基于第二数据信号和第一电源电压)控制流经第二驱动电路131且用于驱动同一发光元件140的第二驱动电流。例如，第一驱动电流和第二驱动电流可以同时流经上述同一发光元件140，此种情况下，流经上述同一发光元件140的电流接近第一驱动电流和第二驱动电流之和。在一些示例中，A参数的值和B参数的值接近是指：A参数的值和B参数的值的差值与A参数的值的比值小于15％(例如，小于10％或小于5％)。
例如，通过使得多个像素驱动单元组100的每个包括至少两个像素驱动单元110，且使得至少两个像素驱动单共同驱动同一发光元件140，可以使得至少两个像素驱动单元110包括的第一像素电路120和第二像素电路130在发光阶段分别生成驱动同一发光元件140的第一驱动电流和第二驱动电流，由此可以提升被像素驱动单元组100驱动的发光元件140的亮度。
例如，第一像素电路120和第二像素电路130具有相同的结构(例如，电路结构)，但本公开的至少一个实施例不限于此。例如，第一像素电路120和第二像素电路130可以具有不完全相同的结构(例如，电路结构)。例如，在多个像素驱动单元组100的每个包括多个(至少三个)像素驱动单元110的情况下，多个像素驱动单元110的每个包括一个像素电路，且多个像素驱动单元110包括的多个像素电路例如具有相同的结构。
例如，如图3所示，第一数据写入电路122被配置为与第一数据信号端DAT1相连，以接收第一数据信号端DAT1提供的第一数据信号。例如，如图3所示，第二数据写入电路132被配置为与第二数据信号端DAT2相连，以接收第二数据信号端DAT2提供的第二数据信号。例如，第一数据信号和第二数据信号为电压信号。在一个示例中，第一数据信号端DAT1和第二数据信号端DAT2为相同的数据信号端，此种情况下，第一数据信号和第二数据信号为相同的数据信号。在另一个示例中，第一数据信号端DAT1和第二数据信号端DAT2为不同的数据信号端，此种情况下，第一数据信号和第二数据信号可以为相同的数据信号或者不同的数据信号。
图4是图3所示的显示基板10的像素驱动单元组100的示意图。为方便描述，图4还示出了发光元件140、第一电源电压端VDD、第二电源电压端VSS等。
需要说明的是，图4所示的显示基板10以第一像素电路120的结构和第二像素电路130的结构相同为例对本公开的至少一个实施例提供的显示基板10做示例性说明，但本公开的至少一个实施例不限于此。
如图4所示，第一像素电路120还包括第一信号存储电路123、第一补偿连接电路124和第一复位电路125。
如图4所示，第一信号存储电路123被配置为在第一驱动电路121的控制端存储被写入至第一驱动电路121的控制端的第一数据信号。例如，第一信号存储电路123连接在第一电源电压端VDD和第一驱动电路121的控制端之间。
如图4所示，第一数据写入电路122将第一数据信号写入至第一驱动电路121的第一端；第一补偿连接电路124连接在第一驱动电路121的第二端和第一驱动电路121的控制端之间，并且被配置为将被写入至第一驱动电路121的第一端的第一数据信号经由第一驱动电路121(例如，经由第一驱动电 路121和第一补偿连接电路124)写入至第一驱动电路121的控制端。
例如，通过使得第一补偿连接电路124被配置为将被写入至第一驱动电路121的第一端的数据信号经由第一驱动电路121写入至第一驱动电路121的控制端，可以将第一驱动电路121的阈值特性写入第一驱动电路121的控制端，并存储在第一信号存储电路123中，由此可以消除第一驱动电路121的阈值特性对第一驱动电路121生成的流经第一驱动电路121且从第一电源电压端VDD至发光元件140、用于驱动发光元件140的第一驱动电流的不利影响，也即，通过设置第一补偿连接电路124，可以使得本公开的至少一个实施例提供的第一像素电路120具有阈值补偿功能。
例如，第一数据写入电路122的控制端GAT1和第一补偿连接电路124的控制端GAT2被配置为接收相同的第一扫描信号，由此使得被写入至第一驱动电路121的第一端的第一数据信号可以在第一像素电路120的数据写入和补偿阶段，经由开启第一驱动电路121和第一补偿连接电路124写入至第一驱动电路121的控制端。
如图4所示，第一复位电路125与第一信号存储电路123相连，第一复位电路125被配置接收第一复位信号，且将第一复位信号写入至第一信号存储电路123，以对第一信号存储电路123复位。例如，第一复位信号可以为第一复位电压。例如，该第一复位电压为负值(例如，-3V)，以使得在存在工艺偏差的情况下，在对第一信号存储电路123复位之后，第一驱动电路121依然能够开启。例如，第一复位电路125被配置为在第一像素电路120的复位阶段对第一信号存储电路123复位。
例如，第一复位电路125的第一端与第一信号存储电路123相连；第一复位电路125的第二端与第一复位信号端Init1相连，以接收第一复位信号端Init1提供的第一复位信号；第一复位电路125的控制端记为RST1。
如图4所示，第二像素电路130还包括第二信号存储电路133、第二补偿连接电路134和第三复位电路135。
如图4所示，第二信号存储电路133被配置为在第二驱动电路131的控制端存储被写入至第二驱动电路131的控制端的第二数据信号。例如，第二信号存储电路133连接在第一电源电压端VDD和第二驱动电路131的控制端之间。
如图4所示，第二数据写入电路132将第二数据信号写入至第二驱动电 路131的第一端；第二补偿连接电路134连接在第二驱动电路131的第二端和第二驱动电路131的控制端之间，并且被配置为将被写入至第二驱动电路131的第一端的第二数据信号经由第二驱动电路131(例如，经由第二驱动电路131和第二补偿连接电路134)写入至第二驱动电路131的控制端。通过设置第二补偿连接电路134，可以使得本公开的至少一个实施例提供的第二像素电路130具有阈值补偿功能。
例如，第二数据写入电路132的控制端GAT3和第二补偿连接电路134的控制端GAT4被配置为接收相同的第二扫描信号，由此使得被写入至第二驱动电路131的第一端的第二数据信号可以在第二像素电路130的数据写入和补偿阶段，经由开启第二驱动电路131和第二补偿连接电路134写入至第二驱动电路131的控制端。例如，第一扫描信号和第二扫描信号可以为相同的扫描信号，由此使得第一像素电路120的数据写入和补偿阶段和第二像素电路130的数据写入和补偿阶段同步。例如，第一数据写入电路122的控制端GAT1、第二数据写入电路132的控制端GAT3、第一补偿连接电路124的控制端GAT2以及第二补偿连接电路134的控制端GAT4连接至同一扫描信号端GAT或者扫描信号线(图中未示出)，由此可以简化该显示基板10的结构。
如图4所示，第三复位电路135与第二信号存储电路133相连，第三复位电路135被配置接收第三复位信号，且将第三复位信号写入至第二信号存储电路133，以对第二信号存储电路133复位。例如，第三复位信号可以为第三复位电压。例如，该第三复位电压为负值(例如，-3V)，以使得在存在工艺偏差的情况下，在对第二信号存储电路133复位之后，第二驱动电路131依然能够开启。例如，第三复位电路135被配置为在第二像素电路130的复位阶段对第二信号存储电路133复位。
例如，第三复位电路135的第一端与第二信号存储电路133相连；第三复位电路135的第二端与第三复位信号端Init3相连，以接收第三复位信号端Init3提供的第三复位信号；第三复位电路135的控制端记为RST3。
例如，第一复位电路125的控制端RST1和第三复位电路135的控制端RST3被配置为接收相同的第一复位控制信号，由此使得第一像素电路120的复位阶段和第二像素电路130的复位阶段同步。例如，第一复位电路125的控制端RST1和第三复位电路135的控制端RST3被配置为连接至同一第一 复位控制端RSTT1或复位信号线(图中未示出)，由此可以简化该显示基板10的结构。例如，第一复位信号端Init1和第三复位信号端Init3为相同的复位信号端，此种情况下，第一复位信号和第三复位信号为相同的复位信号。
如图4所示，第一像素电路120还包括第一控制电路126和第二控制电路127，第二像素电路130还包括第三控制电路136和第四控制电路137。
如图4所示，第一控制电路126连接在第一驱动电路121的第一端和第一电源电压端VDD之间，且被配置为控制第一驱动电路121是否与第一电源电压端VDD电连接。例如，通过设置第一控制电路126，可以避免第一电源电压端VDD提供的第一电源电压在第一像素电路120的数据写入和补偿阶段对写入至第一驱动电路121第一端的第一数据信号产生不利影响。
如图4所示，第二控制电路127连接在第一驱动电路121的第二端与上述同一发光元件140的第一端之间，且被配置为控制第一驱动电路121是否与上述同一发光元件140的第一端电连接。例如，通过设置第二控制电路127，可以在第一像素电路120的数据写入和补偿阶段避免第一驱动电路121第二端的电压与发光元件140的第一端的电压相互干扰。例如，通过设置第二控制电路127，在数据写入和补偿阶段，可以避免第一驱动电路121第二端的电压对发光元件140的第一端的复位产生不利影响以及避免发光元件140发光。又例如，通过设置第二控制电路127，在数据写入和补偿阶段，可以避免发光元件140的第一端的电压对第一驱动电路121第二端的电压以及阈值补偿产生不利影响。
如图4所示，第三控制电路136连接在第二驱动电路131的第一端和第一电源电压端VDD之间，且被配置为控制第二驱动电路131是否与第一电源电压端VDD电连接。例如，通过设置第三控制电路136，可以避免第一电源电压端VDD提供的第一电源电压在第二像素电路130的数据写入和补偿阶段对写入至第二驱动电路131第一端的第二数据信号产生不利影响。
如图4所示，第四控制电路137连接在第二驱动电路131的第二端与上述同一发光元件140的第一端之间，且被配置为控制第二驱动电路131是否与上述同一发光元件140的第一端电连接。例如，例如，通过设置第二控制电路127，可以在第二像素电路130的数据写入和补偿阶段避免第二驱动电路131第二端的电压与发光元件140的第一端的电压相互干扰。
例如，第一控制电路126的控制端EM1、第二控制电路127的控制端 EM2、第三控制电路136的控制端EM3以及第四控制电路137的控制端EM4被配置为接收相同的发光控制信号，由此使得第一控制电路126、第二控制电路127、第三控制电路136和第四控制电路137同时开启，并使得第一驱动电路121和第二驱动电路131(或者第一像素电路120和第二像素电路130)可以同步驱动发光元件140。
例如，第一控制电路126的控制端EM1、第二控制电路127的控制端EM2、第三控制电路136的控制端EM3以及第四控制电路137的控制端EM4连接至同一发光控制端EM或发光控制线(图中未示出)，由此可以简化该显示基板10的结构。
如图4所示，第一像素电路120还包括第二复位电路128，第二像素电路130还包括第四复位电路138。
如图4所示，第二复位电路128被配置为接收第二复位信号，且将第二复位信号写入至同一发光元件140的第一端，以对上述同一发光元件140的第一端复位。例如，如图4所示，第二复位电路128的第一端与发光元件140的第一端相连；第二复位电路128的第二端与第二复位信号端Init2相连，以接收第二复位信号端Init2提供的第二复位信号；第二复位电路128的控制端记为RST2。
如图4所示，第四复位电路138被配置为接收第四复位信号，且将第四复位信号写入至同一发光元件140的第一端，以对上述同一发光元件140的第一端复位。如图4所示，第四复位电路138的第一端与发光元件140的第一端相连；第四复位电路138的第二端与第四复位信号端Init2相连，以接收第四复位信号端Init2提供的第四复位信号；第四复位电路138的控制端记为RST2。
例如，第二复位电路128的控制端RST2和第四复位电路138的控制端RST4被配置为接收相同的复位控制信号，以使得第二复位电路128和第四复位电路138同步对上述同一发光元件140的第一端复位。例如，第二复位电路128的控制端RST2和第四复位电路138的控制端RST4被配置为连接至同一第二复位控制端RSTT2或复位信号线(图中未示出)，由此可以简化该显示基板10的结构。例如，第二复位信号端Init2和第四复位信号端Init4为相同的复位信号端，此种情况下，第二复位信号和第四复位信号为相同的复位信号。例如，第一复位信号端Init1、第二复位信号端Init2、第三复位信号端 Init3和第四复位信号端Init4为相同的复位信号端，此种情况下，第一复位信号和第二复位信号、第三复位信号和第四复位信号为相同的复位信号。
例如，第二复位电路128和第四复位电路138被配置为消除发光元件140上可能残留的电荷。例如，可以在发光阶段之前对发光元件140的第一端复位，以提升发光元件140的亮度的准确性以及显示基板10的对比度。例如，可以在数据写入和补偿阶段或者复位阶段对发光元件140的第一端复位。
需要说明的是，本公开的至少一个实施例提供的多个像素驱动单元组100的每个不限于同时包括第二复位电路128和第四复位电路138，在一些示例中，本公开的至少一个实施例提供的多个像素驱动单元组100的至少部分(例如，每个)可以包括第二复位电路128和第四复位电路138的一个。例如，第一像素电路120包括第二复位电路128，但第二像素电路130不包括第四复位电路138。
需要说明的是，图4所示的像素驱动单元110以第一像素电路120和第二像素电路130同时具有补偿功能、复位功能和发光控制功能为例对本公开的至少一个实施例进行示例性说明，但本公开的至少一个实施例不限于此，例如，根据实际应用需求，本公开的至少一个实施例提供的第一像素电路120和第二像素电路130可以不具有上述三个功能，或者仅具有上述三个功能的部分功能(也即，少于三个功能)。对应地，可以对像素驱动单元110的第一像素电路120和第二像素电路130的具体结构进行适应性的变化。
图5A是图4所示的像素驱动单元组100的示例性电路图。为方便描述，图5A还示出了有机发光元件EL、第一电源电压端VDD、第二电源电压端VSS、第一节点N1-第八节点N8等。
如图4和图5A所示，第一驱动电路121包括第一晶体管T1，第一晶体管T1的控制端连接至第一节点N1，第一晶体管T1的第一端连接至第二节点N2，第一晶体管T1的第二端连接至第三节点N3。
如图4和图5A所示，第一数据写入电路122包括第二晶体管T2，第一信号存储电路123包括第一存储电容Cst1；第二晶体管T2的第一端连接至第二节点N2，第二晶体管T2的第二端连接至第一数据信号端DAT1，以接收第一数据信号端DAT1提供的第一数据信号；第一存储电容Cst1的第一端连接至第一电源电压端VDD，第一存储电容Cst1的第二端连接至第一节点N1。
如图4和图5A所示，第一补偿连接电路124包括第三晶体管T3；第三 晶体管T3的第一端连接至第一节点N1，第三晶体管T3的第二端连接至第三节点N3。例如，第二晶体管T2的控制端GAT1和第三晶体管T3的控制端GAT2均连接至同一扫描信号端GAT或同一扫描信号线(图中未示出)。
如图4和图5A所示，第一复位电路125包括第四晶体管T4，第四晶体管T4的控制端记为RST1，第四晶体管T4的第一端连接至第一节点N1，第四晶体管T4的第二端连接至第一复位信号端，以接收第一复位信号端提供的第一复位信号。
如图4和图5A所示，第一控制电路126包括第五晶体管T5，第二控制电路127包括第七晶体管T7；第五晶体管T5的第一端连接至第一电源电压端VDD，以接收第一电源电压，第五晶体管T5的第二端连接至第二节点N2；第七晶体管T7的第一端连接至第三节点N3，第七晶体管T7的第二端连接至第四节点N4。
如图4和图5A所示，第二复位电路128包括第六晶体管T6；第六晶体管T6的控制端记为RST2，第六晶体管T6的第一端连接至第四节点N4，第六晶体管T6的第二端连接至第二复位信号端，以接收第二复位信号端提供的第二复位信号。
如图4和图5A所示，第二驱动电路131包括第八晶体管T8，第八晶体管T8的控制端连接至第五节点N5，第八晶体管T8的第一端连接至第六节点N6，第八晶体管T8第二端连接至第七节点N7。
例如，第八晶体管T8和第一晶体管T1可以具有相同的规格(例如，阈值电压)，但本公开的至少一个实施例不限于此。
如图4和图5A所示，第二数据写入电路132包括第九晶体管T9，第二信号存储电路133包括第二存储电容Cst2；第九晶体管T9的第一端连接至第六节点N6，第九晶体管T9的第二端连接至第二数据信号端DAT2，以接收第二数据信号端DAT2提供的第二数据信号；第二存储电容Cst2的第一端连接至第一电源电压端VDD，第二存储电容Cst2的第二端连接至第五节点N5。
如图4和图5A所示，第二补偿连接电路134包括第十晶体管T10；第十晶体管T10的第一端连接至第五节点N5，第十晶体管T10的第二端连接至第七节点N7。
如图4和图5A所示，第三复位电路135包括第十一晶体管T11，第十一晶体管T11的控制端记为RST3，第十一晶体管T11的第一端连接至第五节点 N5，第十一晶体管T11的第二端连接至第三复位信号端，以接收第三复位信号端提供的第三复位信号。
如图4和图5A所示，第三控制电路136包括第十二晶体管T12，第四控制电路137包括第十四晶体管T14；第十二晶体管T12的第一端连接至第一电源电压端VDD，以接收第一电源电压，第十二晶体管T12的第二端连接至第六节点N6；第十四晶体管T14的第一端连接至第七节点N7，第十四晶体管T14的第二端连接至第八节点N8。
如图4和图5A所示，第四复位电路138包括第十三晶体管T13；第十三晶体管T13的控制端记为RST4，第十三晶体管T13的第一端连接至第八节点N8，第十三晶体管T13的第二端连接至第四复位信号端，以接收第四复位信号端提供的第四复位信号。例如，第八节点N8和第四节点N4为同一节点。
如图4和图5A所示，发光元件140包括有机发光元件EL，有机发光元件EL的第一端(例如，阳极)连接第四节点N4，有机发光元件EL的第二端(例如，阴极)连接第二电源电压端VSS，以接收第二电源电压端VSS提供的第二电源电压。
例如，第二晶体管T2的控制端GAT1和第三晶体管T3的控制端GAT3、第九晶体管T9的控制端GAT3和第十晶体管T10的控制端GAT4被配置为接收相同的扫描信号；此种情况下，第一像素电路120的数据写入和补偿阶段和第二像素电路130的数据写入和补偿阶段同步，且被称为像素驱动单元组100的数据写入和补偿阶段。例如，第二晶体管T2的控制端GAT1和第三晶体管T3的控制端GAT3、第九晶体管T9的控制端GAT3和第十晶体管T10的控制端GAT4均连接至同一扫描信号端GAT或同一扫描信号线(图中未示出)。
例如，第四晶体管T4的控制端RST1和第十一晶体管T11的控制端RST3被配置为接收相同的第一复位控制信号；此种情况下，第一像素电路120的复位阶段和第二像素电路130的复位阶段同步，且被称为像素驱动单元组100的复位阶段。例如，第四晶体管T4的控制端RST1和第十一晶体管T11的控制端RST3连接至同一第一复位控制端RSTT1或第一复位控制线(图中未示出)。
例如，第五晶体管T5的控制端EM1、第七晶体管T7的控制端EM2、第十二晶体管T12的控制端EM3和第十四晶体管T14的控制端EM4被配置为 接收相同的发光控制信号；此种情况下，第一像素电路120的发光阶段和第二像素电路130的发光阶段同步，且被称为像素驱动单元组100的发光阶段。例如，第五晶体管T5的控制端EM1、第七晶体管T7的控制端EM2、第十二晶体管T12的控制端EM3和第十四晶体管T14的控制端EM4连接至同一发光控制端EM或发光控制线(图中未示出)。
例如，第六晶体管T6的控制端RST3和第十三晶体管T13的控制端RST4被配置为接收相同的第二复位控制信号；此种情况下，第一像素电路120的第二复位阶段和第二像素电路130的第二复位阶段同步。例如，第六晶体管T6的控制端RST3和第十三晶体管T13的控制端RST4连接至同一第二复位控制端RSTT2或第二复位控制线(图中未示出)。例如，第一像素电路120的第二复位阶段和第二像素电路130的第二复位阶段可以与像素驱动单元组100的数据写入和补偿阶段同步或者与像素驱动单元组100的复位阶段同步。例如，第三复位信号和第四复位信号配置为相同的复位信号。
例如，第一晶体管T1-第十四晶体管T14可以均为P型晶体管(例如，PMOS管，也即，n型衬底、p沟道，靠空穴的流动运送电流的MOS管)，此种情况下，第一晶体管T1-第十四晶体管T14在接收到高电平(第一电平)时截止，在接收到低电平(第二电平，第二电平小于第一电平)时导通，也即，高电平(第一电平)为无效电平(也即，使得晶体管关闭的电平)，低电平(第二电平)为有效电平(也即，使得晶体管导通的电平)。需要说明的是，第一晶体管T1-第十四晶体管T14不限于均实现为P型晶体管，根据实际应用需求，第一晶体管T1-第十四晶体管T14的一个或多个还可以实现为N型晶体管。
需要说明的是，引入第一节点N1-第八节点N8旨在更为方便的描述各元件之间的连接关系，并非一定要在像素驱动单元组100中设置例如焊点或焊盘作为实际的节点。
图5B是图5A所示的像素驱动单元组100驱动时序图。例如，如图5B所示，图5A所示的像素驱动单元组100的每个驱动周期包括复位阶段S_re、数据写入和补偿阶段S_wc和发光阶段S_EM。例如，如图5B所示，数据写入和补偿阶段S_wc在时间上位于复位阶段S_re和发光阶段S_EM之间。
如图5A和图5B所示，在复位阶段S_re中，第一复位控制端RSTT1(对应于第四晶体管T4的控制端RST1和第十一晶体管T11的控制端RST3)接 收有效电平，扫描信号端GAT(对应于第二晶体管T2的控制端GAT1和第三晶体管T3的控制端GAT3、第九晶体管T9的控制端GAT3和第十晶体管T10的控制端GAT4)、第二复位控制端RSTT2(对应于第六晶体管T6的控制端RST3和第十三晶体管T13的控制端RST4)和发光控制端EM(对应于第五晶体管T5的控制端EM1、第七晶体管T7的控制端EM2、第十二晶体管T12的控制端EM3和第十四晶体管T14的控制端EM4)接收无效电平；此种情况下，第四晶体管T4和第十一晶体管T11开启，第二晶体管T2、第三晶体管T3、第五晶体管T5-第七晶体管T7、第九晶体管T9、第十晶体管T10以及第十二晶体管T12-第十四晶体管T14关闭，第四晶体管T4被配置接收第一复位信号(例如，复位电压)Vinit1，且将第一复位信号Vinit1写入至第一存储电容Cst1，以对第一存储电容Cst1复位；第十一晶体管T11被配置接收第三复位信号(例如，复位电压)Vinit3，且将第三复位信号Vinit3写入至第二存储电容Cst2，以对第二存储电容Cst2复位；第一节点N1的电压为Vinit1，第五节点N5的电压为Vinit3，Vinit1和Vinit3例如为负值(例如，-3V)。例如，第一复位信号Vinit1写入至第一存储电容Cst1之后，第一晶体管T1开启；第三复位信号Vinit3写入至第二存储电容Cst2之后，第八晶体管T8开启。
如图5A和图5B所示，在数据写入和补偿阶段S_wc中，扫描信号端GAT和第二复位控制端RSTT2接收有效电平，第一复位控制端RSTT1和发光控制端EM接收无效电平；此种情况下，第一晶体管T1-第三晶体管T3、第六晶体管T6、第八晶体管T8-第十晶体管T10以及第十三晶体管T13开启，第四晶体管T4、第五晶体管T5、第七晶体管T7、第十一晶体管T11、第十二晶体管T12和第十四晶体管T14关闭。
在数据写入和补偿阶段S_wc中，第二晶体管T2接收第一数据信号(例如，第一数据电压)Vd1，且第一数据信号Vd1经由开启的第一晶体管T1和第三晶体管T3被写入至第一晶体管T1的控制端，第一存储电容Cst1在第一晶体管T1的控制端存储被写入至第一晶体管T1的控制端的第一数据信号Vd1，第一节点N1的电压为Vd1+Vth1，此处，Vth1为第一晶体管T1的阈值电压。
在数据写入和补偿阶段S_wc中，第九晶体管T9接收第二数据信号(例如，第二数据电压)Vd2，且第二数据信号Vd2经由开启的第八晶体管T8和 第十晶体管T10被写入至第八晶体管T8的控制端，第二存储电容Cst2在第八晶体管T8的控制端存储被写入至第八晶体管T8的控制端的第二数据信号Vd2，第五节点N5的电压为Vd2+Vth2，此处，Vth2为第八晶体管T8的阈值电压。
在数据写入和补偿阶段S_wc中，第六晶体管T6和第十三晶体管T13被配置接收相同的复位信号(例如，第二复位电压Vinit2)，且将上述相同的复位信号写入至有机发光元件EL的第一端，以对有机发光元件EL的第一端复位，第四节点N4和第八节点N8的电压为Vinit2。
如图5A和图5B所示，在发光阶段S_EM中，发光控制端EM接收有效电平，第一复位控制端RSTT1、扫描信号端GAT和第二复位控制端RSTT2接收无效电平；此种情况下，第一晶体管T1、第五晶体管T5、第七晶体管T7、第八晶体管T8、第十二晶体管T12和第十四晶体管T14开启，第二晶体管T2-第四晶体管T4、第六晶体管T6、第九晶体管T9-第十一晶体管T11以及第十三晶体管T13关闭。第一晶体管T1被配置为基于第一数据信号和第一电源电压控制流经第一晶体管T1且用于驱动同一有机发光元件EL的第一驱动电流；第八晶体管T8被配置为基于第二数据信号和第一电源电压控制流经第一晶体管T1且用于驱动同一有机发光元件EL的第二驱动电流；第一节点N1的电压为Vd1+Vth1，第五节点N5的电压为Vd2+Vth2；第二节点N2和第六节点N6的电压为VDD。
例如，本公开的发明人通过对包括图5A所示的像素驱动单元组100的显示基板10进行仿真计算确认图5A所示的像素驱动单元组100可以提升被图5A所示的像素驱动单元组100驱动的有机发光元件EL的亮度(相比于图2A所示的像素电路580)。下面结合两个仿真示例进行示例性说明。
在第一个示例中，显示基板10采用RGBG像素排列(Pentile像素排列)，且显示基板10的上述红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G的每个包括图5A所示的像素驱动单元组100；上述红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G包括的像素驱动单元组100的第一数据写入电路122和第二数据写入电路132被配置为接收相同的数据信号(也即，数据电压Vd)，例如，第一数据写入电路122和第二数据写入电路132被配置为与相同的数据信号端相连；上述红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G包括的像素驱动单元组100接收的数据电压 Vd分别为2.7V、3.3V、2.28V和3.3V。
作为对比，显示基板500也采用RGBG像素排列(Pentile像素排列)，且显示基板500中的上述红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G的每个包括图2A所示的像素电路580；显示基板500中的上述红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G包括的像素电路接收的数据电压Vd分别为2.7V、3.3V、2.28V和3.3V。
显示基板500中的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G的每个包括的像素电路的第一节点N1-第四节点N4的电压值及流经有机发光元件EL的电流值，以及显示基板10的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G的每个包括的像素驱动单元组100的第一节点N1-第四节点N4的电压值及流经有机发光元件EL的电流值可以参见表1。
需要说明的是，显示基板10的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G的每个包括的像素驱动单元组100的第五节点N5-第八节点N8的电压值分别等于(实质上等于)上述像素驱动单元组100的第一节点N1-第四节点N4的电压值。在一些示例中，A参数的值和B参数的值实质上相等是指：A参数的值和B参数的值的差值与A参数的值的比值小于3％(例如，小于1％)。需要说明的是，在上述仿真示例中，对于显示基板500和显示基板10，一个图像帧的时长均为16.56ms。
表1
Figure PCTCN2020074001-appb-000002
如表1所示，在第一个仿真示例中，包括图5A所示的像素驱动单元组100的红色子像素R的驱动电流与包括图2A所示的像素电路580的红色子像素R的驱动电流的比值为179.8％；包括图5B所示的像素驱动单元组100的绿色子像素G(第一个绿色子像素G)的驱动电流与包括图2A所示的像素电 路580的绿色子像素G的驱动电流的比值为185.3％；包括图5B所示的像素驱动单元组100的蓝色子像素B的驱动电流与包括图2A所示的像素电路580的蓝色子像素B的驱动电流的比值为193.5％；包括图5B所示的像素驱动单元组100的绿色子像素G(第二个绿色子像素G)的驱动电流与包括图2A所示的像素电路580的绿色子像素G的驱动电流的比值为185.3％，也即，对于上述第一个仿真示例，像素驱动单元组100提供的驱动电流是像素电路580提供的驱动电流的约1.8倍。
第二个仿真示例与第一个仿真示例相似，因此，在此将仅阐述两个仿真示例的不同之处，相同之处不再赘述。第二个仿真示例和第一个仿真示例的不同之处在于第二个仿真示例的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G包括的驱动单元组100或像素电路580接收的数据电压Vd分别为2.9V、3.2V、2.5V和3.2V。
显示基板500和显示基板10中的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G的每个提供的驱动电流值可以参见表2。需要说明的是，考虑到第一个绿色子像素G和第二个绿色子像素G提供的驱动电流接近(或者实质上相同)，因此，表2仅示出了一个绿色子像素G提供的驱动电流值。
表2
Figure PCTCN2020074001-appb-000003
如表2所示，在第二个仿真示例中，包括图5A所示的像素驱动单元组100的红色子像素R的驱动电流与包括图2A所示的像素电路580的红色子像素R的驱动电流的比值为185.15％；包括图5B所示的像素驱动单元组100的绿色子像素G的驱动电流与包括图2A所示的像素电路580的绿色子像素G的驱动电流的比值为186.10％；包括图5B所示的像素驱动单元组100的蓝色子像素B的驱动电流与包括图2A所示的像素电路580的蓝色子像素B的驱动电流的比值为193.56％，也即，对于上述第二个仿真示例，像素驱动单元组 100提供的驱动电流是像素电路580提供的驱动电流的1.8倍以上。
本公开的发明人在研究中还注意到，尽管通过使用像素驱动单元组100包括的至少两个像素驱动单元110驱动同一发光元件140可以提升流经该发光元件140的驱动电流，但是在像素驱动单元组100的第一数据写入电路122和第二数据写入电路132被配置为接收相同的对应于零灰阶的数据电压Vd(例如，6.5V)的情况下，像素驱动单元组100提供的驱动电流可能不满足零灰阶对驱动电流的规定(也即，流经有机发光元件EL的驱动电流Id小于1pA)，并因此使得发光元件140的亮度可能偏离(例如，大于)预定零灰阶亮度。下面结合第三个仿真示例进行说明。
第三个仿真示例与第一个仿真示例相似，因此，在此将仅阐述两个仿真示例的不同之处，相同之处不再赘述。第三个仿真示例和第一个仿真示例的不同之处在于第三个仿真示例的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G包括的驱动单元组100或像素电路580接收的数据电压Vd均为6.5V。显示基板500和显示基板10中的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G的每个提供的驱动电流值可以参见表3。例如，对于像素电路580，6.5V是对应于有机发光元件EL的零灰阶的数据电压。
表3
Figure PCTCN2020074001-appb-000004
需要说明的是，考虑到第一个绿色子像素G和第二个绿色子像素G驱动电流接近(或者实质上相同)，因此，表3仅示出了一个绿色子像素G驱动电流值。
如表3所示，在第三个仿真示例中，显示基板500包括的红色子像素R、绿色子像素G和蓝色子像素B包括的像素电路580提供的驱动电流Id均小于1pA；然而，显示基板10包括的红色子像素R和绿色子像素G包括的像 素驱动单元组100提供的驱动电流Id大于1pA，也即，显示基板10包括的红色子像素R和绿色子像素G包括的像素驱动单元组100提供的驱动电流Id无法使得红色子像素R和绿色子像素G显示零灰阶，因此，显示基板10包括的红色子像素R和绿色子像素G包括的像素驱动单元组100提供的驱动电流Id不满足零灰阶对驱动电流的规定(也即，驱动电流Id小于1pA)。
本公开的发明人在研究中还注意到，可以通过调整(例如，增加)提供给像素驱动单元组100的数据信号(数据电压Vd)来使得显示基板10包括的红色子像素R和绿色子像素G包括的像素驱动单元组100提供的驱动电流Id满足零灰阶对驱动电流的规定。下面结合第四个仿真示例进行说明。
第四个仿真示例与第一个仿真示例相似，因此，在此将仅阐述两个仿真示例的不同之处，相同之处不再赘述。第四个仿真示例和第一个仿真示例的不同之处在于第四个仿真示例的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G包括的驱动单元组100或像素电路580接收的数据电压Vd均为6.7V。显示基板500和显示基板10中的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G的每个提供的驱动电流值可以参见表4。
表4
Figure PCTCN2020074001-appb-000005
如表4所示，在第四个仿真示例中，显示基板10包括的红色子像素R、绿色子像素G和蓝色子像素B包括的像素驱动单元组100提供的驱动电流Id均小于1pA，也即，均满足零灰阶对驱动电流的规定。
本公开的发明人在研究中还注意到，尽管可以通过调整(例如，增加)提供给像素驱动单元组100的数据信号(数据电压Vd)来使得显示基板10的各个像素驱动单元组100提供的驱动电流Id满足零灰阶对驱动电流的规定，但这需要对提供给像素驱动单元组100的数据信号(数据电压Vd)进行预先处理(例如，补偿或校正)。
此外，本公开的发明人在研究中还注意到，在像素驱动单元组100的第一数据写入电路122和第二数据写入电路132被配置为接收相同的数据信号 (也即，数据电压Vd)的情况下，发光元件140的亮度在低灰阶下对数据信号的电压值的波动较为敏感，也即，在低灰阶下，在像素驱动单元组100接收的数据信号的电压值的具有较小的波动的情况下，发光元件140的亮度的变化可能较大。对应地，在显示基板10显示的低灰阶图像时，低灰阶图像的亮度过渡性能可能较差。
本公开的发明人在研究中还注意到，可以通过对提供给像素驱动单元组100的数据信号进行分段控制来使得显示基板10的各个像素驱动单元组100可以在高灰阶下提升驱动电流Id的值以及在低灰阶下使得驱动电流值更为准确，以在提升高灰阶图像的亮度的情况下，提升显示基板10显示的低灰阶图像的亮度过渡性能。
例如，在发光元件140待显示的灰阶大于等于预定灰阶X的情况下，使得像素驱动单元组100的第一数据写入电路122和第二数据写入电路132被配置为接收相同的数据信号(例如，对应于发光元件140的待显示灰阶的数据电压)，此种情况下，像素驱动单元组100同时使用第一像素电路120和第二像素电路130驱动发光元件140；在发光元件140待显示的灰阶小于预定灰阶X的情况下，使得像素驱动单元组100的第一数据写入电路122和第二数据写入电路132被配置为接收不同的数据信号(也即，数据电压Vd)。
例如，在发光元件140的待显示的灰阶小于预定灰阶X的情况下，使得第二数据写入电路132接收的数据电压对应于零灰阶电压(例如，6.7-7.0V)，并使得第一数据写入电路122接收的数据电压对应于发光元件140的待显示灰阶的数据电压，此种情况下，像素驱动单元组100仅使用第一像素电路120驱动发光元件140。
例如，预定灰阶大于显示基板(或发光元件)的最小灰阶且小于显示基板(或发光元件)的最大灰阶。例如，在显示基板或发光元件140的允许显示的亮度大于等于0灰阶小于等于255灰阶的情况下，0＜X＜255。例如，预定灰阶X位于10-35灰阶之间。例如，预定灰阶X大于等于16灰阶小于等于32灰阶。
下面结合第五个仿真示例说明通过对提供给像素驱动单元组100的数据信号进行分段控制可以使得显示基板10的像素驱动单元组100提供的驱动电流Id的值在低灰阶下更为准确。
第五个仿真示例与第一个仿真示例相似，因此，在此将仅阐述两个仿真示 例的不同之处，相同之处不再赘述。第五个仿真示例和第一个仿真示例的不同之处在于，上述显示基板10的包括的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G包括的像素驱动单元组100的第一数据写入电路122和第二数据写入电路132被配置为接收不同的数据信号。例如，上述显示基板10的包括的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G包括的像素驱动单元组100的第一数据写入电路122接收的数据电压均为6.5V，上述显示基板10的包括的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G包括的像素驱动单元组100的第二数据写入电路132接收的数据电压均为7V。显示基板10中的红色子像素R、绿色子像素G、蓝色子像素B和绿色子像素G的每个提供的驱动电流值可以参见表5。
表5
Figure PCTCN2020074001-appb-000006
如图表5所示，在第五个仿真示例中，显示基板10包括的红色子像素R、绿色子像素G和蓝色子像素B包括的像素驱动单元组100提供的驱动电流Id均小于1pA，也即，均满足零灰阶对驱动电流的规定。
本公开的发明人在研究中还注意到，在使得第二数据写入电路132接收的数据电压对应于零灰阶电压(例如，6.7V)，并使得第一数据写入电路122接收的数据电压对应于发光元件140的待显示灰阶的数据电压的情况下，在对应于发光元件140的待显示灰阶的数据电压小于预定电压的情况下，驱动电流存在波动，在对应于发光元件140的待显示灰阶的数据电压大于预定电压的情况下，驱动电流不存在波动。下面结合图6所示的示例进行说明。
图6示出了红色子像素的驱动电流Id随时间T的变化曲线。在图6所示的示例中，第二数据写入电路132接收的数据电压为6.7V。图6所示的曲线CR1、曲线CR2、曲线CR3、曲线CR4、曲线CR5和曲线CR6分别在第一数据写入电路122接收的数据电压为5.5V、5.6V、5.7V、5.8V和5.9V的情况下获得。如图6所示，在第一数据写入电路122接收的数据电压为5.5V和5.6V时，驱动电流Id存在波动(参见图6所示的虚线框中的局部凸起)，这是由于 发光控制端EM接收有效电平后，第四节点N4的电荷向第三节点N3回流导致的。然而，在第一数据写入电路122接收的数据电压大于等于5.7V时，驱动电流Id则不存在波动。因此，可以将5.7V对应的灰阶值作为红色子像素的预定灰阶值X_R。例如，对于蓝色子像素B和绿色子像素G，也可以采用类似的方法确定预定灰阶值X_B和X_G。
图7是本公开的至少一个实施例提供的显示基板10的截面示意图。例如，该显示基板10包括显示侧和非显示侧，显示基板10的显示的画面被配置为在显示基板10的显示侧显示，也即，显示基板10的显示侧为显示基板10的出光侧。显示侧和非显示侧在显示基板10的显示面的法线方向(例如，垂直于显示基板10的方向)上对置。
如图7所示，该显示基板10包括显示层160和感测层170，感测层170设置在显示基板10的非显示侧；显示层160包括显示区域104，显示区域104包括第一显示区域101、第二显示区域102和第三显示区域103；感测层170包括传感器171，传感器171与第一显示区域101在显示基板10的显示面的法线方向(例如，垂直于显示基板10的方向)上叠置，且被配置为接收并处理穿过第一显示区域101的光信号，该光信号可以为可见光、红外光等。
例如，传感器171可以是图像传感器171，并可以用于采集传感器171的集光面面对的外部环境的图像；该传感器171还可以是红外传感器、距离传感器等。例如，在包括该显示基板10的显示装置20为诸如手机、笔记本的移动终端的情况下，该传感器171可用于实现诸如手机、笔记本的移动终端的摄像头。例如，该传感器171可以包括阵列排布传感像素。例如，每个感光像素可以包括光敏探测器(例如，光电二极管、光电晶体管)和开关晶体管(例如，开关晶体管)。光电二极管可以将照射到其上的光信号转换为电信号，开关晶体管可以与光电二极管电连接，以控制光电二极管是否处于采集光信号的状态以及采集光信号的时间。
图8是图7所示的显示基板10的一个示例的平面示意图，图7所示的显示基板10对应于图8所示的显示基板10的AA’线。
例如，如图7和图8所示，第一显示区域101、第二显示区域102和第三显示区域103互不重叠。例如，如图7和图8所示，第二显示区域102围绕(例如，完全围绕)第一显示区域101。例如，第三显示区域103至少围绕第二显示区域102。例如，如图7和图8所示，第三显示区域103部分围绕第二 显示区域102。
例如，第一显示区域101的形状可以为圆形，第二显示区域102的形状可以为矩形，但本公开的实施例不限于此。又例如，第一显示区域101和第二显示区域102的形状可以为不规则形状或者其它适用的形状。
图9是图8所示的显示基板10的第一显示区域101和第二显示区域102的部分区域REG1的示意图。图10是图8所示的显示基板10的第三显示区域103的部分区域REG2的示意图。
例如，如图9所示，第一显示区域101包括多个第一发光元件141，第二显示区域102包括多个第二发光元件142。例如，如图9所示，第一显示区域101中多个第一发光元件141的单位面积分布密度等于第二显示区域102中多个第二发光元件142的单位面积分布密度。例如，如图9所示，多个第一发光元件141和多个第二发光元件142整体上以阵列方式布置。
如图10所示，第三显示区域103包括多个阵列布置的第三发光元件143。例如，第一发光元件141、第二发光元件142和第三发光元件143均可以为有机发光元件，有机发光元件例如可以为有机发光二极管，但本公开的至少一个实施例不限于此。例如，第一发光元件141、第二发光元件142和第三发光元件143均可以为无机发光元件。例如，第一发光元件141、第二发光元件142和第三发光元件143可以具有相同的结构。
例如，第一显示区域101中多个第一发光元件141的单位面积分布密度小于第三显示区域103中多个第三发光元件143的单位面积分布密度。例如，第二显示区域102中多个第二发光元件142的单位面积分布密度小于第三显示区域103中多个第三发光元件143的单位面积分布密度。例如，第一显示区域101和第二显示区域102可以被称为显示基板10的低分辨率区域。
例如，在第一方向D1上相邻的两个第一发光元件141的间距大于在第一方向D1上相邻的两个第三发光元件143的间距，在第二方向D2上相邻的两个第一发光元件141的间距大于在第二方向D2上相邻的两个第三发光元件143的间距。例如，在第一方向D1上相邻的两个第一发光元件141的间距实质上等于在第一方向D1上相邻的两个第三发光元件143的间距的四倍，在第二方向D2上相邻的两个第一发光元件141的间距实质上等于在第二方向D2上相邻的两个第三发光元件143的间距的两倍。例如，在第一方向D1上相邻的两个第一发光元件141的间距位于280-380微米的范围内，在第二方向D2 上相邻的两个第一发光元件141的间距位于100-160微米的范围内；在第一方向D1和第二方向D2上相邻的两个第三发光元件143的间距位于110-130微米的范围内。需要说明的是，此处，两个元件的间距是指两个元件的中心的间距。
如图9所示，第二显示区域102包括阵列排布的多个像素驱动单元组100，也即，多个像素驱动单元组100位于第二显示区域102中。例如，多个像素驱动单元组100的每个包括至少两个驱动单元110，两个驱动单元110包括第一像素电路120和第二像素电路130，且第一像素电路120和第二像素电路130具有相同的电路结构。例如，两个驱动单元110的每个包括一个像素电路。
如图9所示，多个像素驱动单元组100包括多个第一驱动单元组111；多个第一驱动单元组111被配置为一一对应地驱动多个第一发光元件141。例如，多个第一驱动单元组111的每个的结构与像素驱动单元组100的结构相同。例如，如图9所示，多个第一驱动单元组111的每个包括第一像素电路120和第二像素电路130，第一像素电路120和第二像素电路130的信号输出端彼此相连，且与位于第一显示区域101中的同一第一发光元件141电连接，以共同驱动上述同一第一发光元件141。
例如，通过使用多个第一驱动单元组111一一对应地驱动多个第一发光元件141，可以提升多个第一发光元件141的发光亮度，由此可以提升显示基板10的包括多个第一发光元件141的第一显示区域101的亮度，也即，提升显示基板10的低分辨率区域的整体亮度。
例如，由于用于驱动多个第一发光元件141的多个第一驱动单元组111设置在第二显示区域102，且第一显示区域101未设置像素驱动单元组100或像素电路，因此，可以提升第一显示区域101的透过率(入射至第一显示区域101上的光线的透过率)。由于传感器171与第一显示区域101在显示基板10的显示面的法线方向上叠置(参见图7)，因此，可以减小第一显示区域101中的元件对入射至第一显示区域101并朝向传感器171传输的光信号的遮挡，由此可以提升传感器171输出的图像的信噪比。例如，第一显示区域101可以被称为显示基板10的低分辨率区域的高透光区。
例如，如图9所示，显示基板10还包括多条第一走线144；多条第一走线144电连接多个第一驱动单元组111和与多个第一驱动单元组111一一对 应连接的多个第一发光元件141。例如，上述多条第一走线144的每条可以实现为透明走线，由此可以进一步地提升第一显示区域101的透过率以及传感器171输出的图像的信噪比。
需要说明的是，用于驱动多个第一发光元件141的多个第一驱动单元组111不限于设置在第二显示区域102中。在一些示例中，在不考虑第一显示区域101的透过率的情况下，用于驱动多个第一发光元件141的多个第一驱动单元组111的至少部分(例如，全部)还可以设置在第一显示区域101中。
例如，如图9所示，多个像素驱动单元组100还包括多个第二驱动单元组112；多个第二驱动单元组112被配置为一一对应地驱动至少一个第二发光元件142。例如，多个第二驱动单元组112的每个的结构与像素驱动单元组100的结构相同。例如，通过使用多个第二驱动单元组112一一对应地驱动多个第二发光元件142，可以提升多个第二发光元件142的发光亮度，由此可以提升显示基板10的包括多个第二发光元件142的第二显示区域102的亮度，也即，提升显示基板10的低分辨率区域的整体亮度。
例如，如图9所示，多个第二驱动单元组112分别和多个第二驱动单元组112一一对应驱动的多个第二发光元件142，在沿显示基板10的显示面的法线方向彼此至少部分重叠。例如，如图9所示，多个第二驱动单元组112的每个包括第二发光元件142、第一像素电路120和第二像素电路130，且第一像素电路120和第二像素电路130被配置为共同驱动第二发光元件142。
例如，如图10所示，第三显示区域103包括多个阵列布置的像素单元150，多个第三发光元件143分别位于多个像素单元150中。例如，多个像素单元150的每个还包括第三像素电路121，多个像素单元150的每个包括的第三像素电路121用于驱动该像素单元150中的第三发光元件143。例如，第一像素电路120、第二像素电路130和第三像素电路121具有相同的结构。
例如，由于第三发光元件143被单个像素电路(第三像素电路121)驱动，第一发光元件141和第二发光元件142被像素驱动单元组100驱动，因此，在像素单元150包括的第三像素电路121接收的数据电压等于像素驱动单元组100接收的数据电压的情况下，第一发光元件141和第二发光元件142的亮度大于第三发光元件143的亮度，由此可以使得第一显示区域101和第二显示区域102的亮度更为匹配第三显示区域103的亮度(例如，在接收的数据电压相同的情况下，第一显示区域101和第二显示区域102的亮度更接近 第三显示区域103的亮度)，也即，使得显示基板10的具有不同显示分辨率的区域的亮度更为匹配。
例如，相比于图2C和图2D所示的显示基板10，图8和图9所示的显示基板10的像素驱动单元组100借用了图2C和图2D所示的显示基板10中的冗余像素单元中的像素电路作为像素驱动单元组100的第二像素电路130，因此，图8和图9所示的显示基板10在无需额外设置像素电路的情况下，提升被像素驱动单元组100驱动的发光元件140的亮度。
有以下几点需要说明。
(1)图9仅用于示出第一驱动单元组111包括第一像素电路120和第二像素电路130，第一发光元件141和第一驱动单元组111电连接，以及第二驱动单元组112包括第二发光元件142以及驱动共同驱动第二发光元件142的第一像素电路120和第二像素电路130，图10仅用于示出像素单元150包括第三发光元件143以及用于驱动第三发光元件143的第三像素电路121，而并没有限定第一发光元件141、第二发光元件142、第三发光元件143、第一像素电路120、第二像素电路130和第三像素电路121的具体形状以及相对位置关系，第一发光元件141、第二发光元件142、第三发光元件143、第一像素电路120和第二像素电路130的具体形状以及相对位置关系可以根据实际应用需求进行设定。
(2)尽管图9所示的多个像素驱动单元组100包括多个第一驱动单元组111，第一显示区域101包括多个第一发光元件141，多条第一走线144电连接多个第一驱动单元组111和与多个第一驱动单元组111一一对应连接的多个第一发光元件141，但本公开的至少一个实施例不限于此。在一个示例中，多个像素驱动单元组100包括一个、两个或其它适用数目的(也即，至少一个)第一驱动单元组111；对应地，第一显示区域101包括至少一个第一发光元件141；显示基板10包括至少一条第一走线144；至少一个第一驱动单元组111被配置为一一对应地驱动至少一个第一发光元件141；至少一条第一走线144电连接至少一个第一驱动单元组111和与至少一个第一驱动单元组111一一对应连接的至少一个第一发光元件141。例如，第二显示区域102的第一驱动单元组111的数目以及第一走线144的数目等于第一显示区域101包括的第一发光元件141的数目。
(3)尽管图9所示的多个像素驱动单元组100包括多个第二驱动单元组 112，第二显示区域102包括多个第二发光元件142，多个第二驱动单元组112被配置为一一对应地驱动多个第二发光元件142，多个第二驱动单元组112分别和多个第二驱动单元组112一一对应驱动的多个第二发光元件142，在沿显示基板10的显示面的法线方向彼此至少部分重叠，但本公开的至少一个实施例不限于此。在一个示例中，多个像素驱动单元组100还包括一个、两个或其它适用数目的(也即，至少一个)第二驱动单元组112；对应地，第二显示区域102包括至少一个第二发光元件142；至少一个第二驱动单元组112被配置为一一对应地驱动至少一个第二发光元件142；至少一个第二驱动单元组112分别和至少一个第二驱动单元组112一一对应驱动的至少一个第二发光元件142，在沿显示基板10的显示面的法线方向彼此至少部分重叠。例如，第二显示区域102的第二驱动单元组112的数目等于第二显示区域102包括的第二发光元件142的数目。
图11示出了图9所示的第二显示区域102的部分区域的一个示意图。例如，如图11所示，多个第一驱动单元组111和多个第二驱动单元组112整体上以阵列方式布置且在显示基板10的行方向和显示基板10的列方向上交替布置；多个像素驱动单元组100的每个包括的至少两个像素驱动单元110在显示基板10的行方向上并列布置。
例如，如图11所示，像素驱动单元组100的第一像素电路120的第一数据写入电路122(图11未示出，参见图4)经由第一数据线161与第一数据信号端DAT1电连接，以接收第一数据信号端DAT1提供的第一数据信号；像素驱动单元组100的第二像素电路130的第二数据写入电路132(图11未示出，参见图4)经由第二数据线162与第二数据信号端DAT2电连接，以接收第二数据信号端DAT2提供的第二数据信号；第一数据线161和第二数据线162为不同的数据线，第一数据信号端DAT1和第二数据信号端DAT2为不同的数据信号端。
例如，对于图11所示的第二显示区域102以及包括该第二显示区域102的显示基板10，第一数据信号和第二数据信号可以为相同的数据信号或不同的数据信号。
例如，在同一时间段，第一数据线161中的数据信号的传输方向和第二数据线162的数据信号的传输方向相反，但本公开的实施例不限于此。又例如，在同一时间段，第一数据线161中的数据信号的传输方向和第二数据线 162的数据信号的传输方向相同。
例如，第一数据线161和第二数据线162可以位于同一电极层或者位于不同电极层。例如，第一数据线161和第二数据线162均与同一膜层直接接触。
例如，在发光元件140(例如，第一发光元件141或第二发光元件142)的待显示的灰阶大于等于预定灰阶X(例如，0＜X＜255)的情况下，使得像素驱动单元组100的第一数据写入电路122和第二数据写入电路132被配置为接收相同的数据信号(例如，对应于发光元件140的待显示灰阶的数据电压)，此种情况下，像素驱动单元组100同时使用第一像素电路120和第二像素电路130驱动发光元件140。
例如，在发光元件140的待显示的灰阶小于预定灰阶X(例如，0＜X＜255)的情况下，使得第二数据写入电路132接收的数据电压对应于零灰阶电压(例如，6.7-7.0V)，并使得第一数据写入电路122接收的数据电压对应于发光元件140的待显示灰阶的数据电压；此种情况下，像素驱动单元组100仅使用第一像素电路120驱动发光元件140。
需要说明的是，第一数据写入电路122和第二数据写入电路132不限于与不同的数据信号端电连接，在无需对提供给像素驱动单元组100的数据信号进行分段控制的情况下，第一数据写入电路122和第二数据写入电路132与同一数据信号端电连接，以简化显示基板10的结构；此种情况下，第一数据写入电路122接收的第一数据信号与第二数据写入电路132接收的第二数据信号相同。下面结合图12进行示例性说明。
图12示出了图9所示的第二显示区域102的部分区域的另一个示意图。图12所示的示例与图11所示的示例类似，因此，在此仅阐述两者不同之处，相同尺寸不再赘述。例如，如图12所示，第一数据写入电路122和第二数据写入电路132分别经由第一数据线161和第二数据线162与同一数据信号端DAT电连接，以接收第一数据信号和第二数据信号；第一数据信号和第二数据信号相同。
需要说明的是，第一数据写入电路122和第二数据写入电路132不限于分别经由第一数据线161和第二数据线162与同一数据信号端电连接，根据实际应用需求，第一数据写入电路122和第二数据写入电路132可以经由相同的数据线与同一数据信号端电连接，以进一步地简化显示基板10的结构。
例如，该显示基板10可以包括相互交叉(例如，垂直)设置的多条扫描信号线(例如，栅线)和多条数据线，以及与扫描信号线平行设置的多条电压控制线。例如，每个像素电路(例如，第一像素电路120和第二像素电路130)与对应扫描信号线和对应的数据线相连接，例如，每个像素电路对应的扫描信号端可以与对应的扫描信号线相连接，每个像素电路对应的数据信号端可以与对应的数据线相连接，每个像素电路对应的第一电源电压端VDD和第二电源电压端VSS可以与对应的电压控制线相连接。例如，多条扫描信号线分别沿显示基板10的显示基板10的行方向(例如，图9-图12所示的第一方向D1)延伸，多条扫描数据线分别具有沿显示基板10的列方向(例如，图9-图12所示的第二方向D2)延伸的部分。例如，第一方向D1与第二方向D2交叉(例如，垂直)。
例如，为了使得第一显示区域101和第二显示区域102的亮度与第一显示区域101的亮度更为一致，可以在采用本公开的至少一个实施例提供的像素驱动单元组100驱动第一显示区域101和第二显示区域102的发光元件140的基础上，额外对提供给像素驱动单元组100的数据信号进行补偿。例如，可以使用时序控制器对提供给像素驱动单元组100的数据信号的数据信号进行补偿。
图13示出了图8所示的第一显示区域101和第二显示区域102的部分区域REG2的另一种示意图。例如，如图12所示，多个第一驱动单元组111和多个第二驱动单元组112整体上以阵列方式布置且在显示基板10的行方向和列方向上交替布置；多个像素驱动单元组100的每个包括的至少两个像素驱动单元110在显示基板10的列方向上并列布置。
例如，如图13所示，分别被在显示基板10的行方向上相邻的两个第二驱动单元组112驱动的两个第二发光元件142位于不同行；分别被在显示基板10的列方向上相邻的两个第二驱动单元组112驱动的两个第二发光元件142位于同一列；分别被在显示基板的行方向上相邻的两个第一驱动单元组111驱动两个第一发光元件141位于不同行；分别被在显示基板的列方向上相邻的两个第一驱动单元组111驱动的两个第一发光元件141位于同一列；此种情况下，第一显示区域101中的第一发光元件141的分布以及第二显示区域102中的第二发光元件142的分布更为均匀，由此可以提升显示基板10显示的图像的质量。
本公开的至少一个实施例还提供了一种显示装置20，其包括本公开的至少一个实施例提供的任一像素电路或任一显示基板10。
图14是本公开的至少一个实施例提供的显示装置20的示例性框图。如图14所示，该显示装置20包括本公开的至少一个实施例提供的任一显示基板10。
图15是图14所示的显示装置20的一个示意图。例如，如图15所示，显示装置20还包括第一数据驱动电路191和第二数据驱动电路192。第一数据驱动电路191配置为经由位于第一数据驱动电路191中的第一数据信号端DAT1向第一数据写入电路122提供第一数据信号；第二数据驱动电路192配置为经由位于第二数据驱动电路192中的第二数据信号端DAT2向第二数据写入电路132提供第二数据信号。
图16示出了图15所示的显示基板的第三像素电路。例如，如图16所示，显示基板10还包括多个第三像素电路121；第一数据驱动电路191还配置为多个第三像素电路121中至少之一提供数据信号。例如，如图16所示，多个第三像素电路121的每个的电路结构与第一像素电路120相同。
例如，多个第三像素电路121驱动的多个发光元件(第三发光元件143)不同于多个像素驱动单元组100驱动的多个发光元件，也即，第三像素电路121和像素驱动单元组100被配置为驱动不同的发光元件。例如，多个第三像素电路121驱动的多个发光元件与多个像素驱动单元组100驱动的多个发光元件具有相同的结构。
图17是图14所示的显示装置20的一种平面示意图。如图17所示，该显示装置20的显示基板10(例如，显示基板10的显示层160)包括显示区域104以及至少部分围绕显示区域104的周边区域105。周边区域105设置有第一数据驱动电路191和第二数据驱动电路192，第一数据驱动电路191配置为经由位于第一数据驱动电路191中的第一数据信号端DAT1以及第一数据线161向第一数据写入电路122提供第一数据信号；第二数据驱动电路192配置为经由位于第二数据驱动电路192中的第二数据信号端DAT2以及第二数据线162向第二数据写入电路132提供第二数据信号。例如，第一数据线161为显示基板10的正常分辨率区域(也即，第三显示区域103)提供数据信号；第一数据线161还为显示基板10的低分辨率区域(例如，第一显示区域101和第二显示区域102的至少一个)提供第一数据信号，第二数据线162 仅为显示基板10的低分辨率区域(例如，第一显示区域101和第二显示区域102的至少一个)提供第二数据信号。
例如，如图17所示，第一数据驱动电路191和第二数据驱动电路192在显示基板10的显示基板10的列方向上设置在显示区域104的两侧。例如，第一数据驱动电路191和第二数据驱动电路192的至少一个实现为驱动芯片。例如，驱动芯片可经由柔性电路板邦定在显示基板10上，并经由柔性电路向多根数据线提供显示用的数据信号，以驱动显示基板10实现显示功能。例如，周边区域105还可以设置有阵列基板上的栅驱动集成(GOA，图中未示出)，GOA的多个输出端分别与多根栅线GL相连，以向多根栅线提供栅扫描信号。例如，图17所示的显示装置20被两个驱动芯片驱动。
例如，如图17所示，第一数据线161和第二数据线162均沿显示基板10的列方向延伸。
图18是图14所示的显示装置20的另一种平面示意图。图18所示的显示装置20与图17所示的显示装置20类似，因此，在此仅阐述两种不同之处，相同之处不再赘述。
例如，如图18所示，第一数据驱动电路191和第二数据驱动电路192在显示基板10的列方向上设置在显示区域104的同一侧。例如，第一数据驱动电路191和第二数据驱动电路192的设置在同一个驱动芯片106中。
图19A是图14所示的显示装置20的再一种平面示意图。图19A所示的显示装置20与图18所示的显示装置20类似，因此，在此仅阐述两种不同之处，相同之处不再赘述。例如，如图19A所示，第二数据线162从第一显示区域101和第二显示区域102之间的区域走线至第二显示区域102，因此，数据线162还包括沿第一方向D1延伸的部分。需要说明的是，第一显示区域101和第二显示区域102之间的区域是指第一显示区域101中位于最外侧的第一发光元件141与第二显示区域102中距离最外侧的第一发光元件141最近的像素驱动单元组100之间的区域。例如，部分第一数据线161也可以从第一显示区域101和第二显示区域102之间的区域走线至第二显示区域102。
图19B示出了图19A所示的显示装置20的显示基板10的第一显示区域101和第二显示区域102之间的区域。如图19B所示，第二数据线162从第一显示区域101和第二显示区域102之间的区域走线至第二显示区域102。
需要说明的是，对于该显示装置20的其它组成部分(例如，图像数据编 码/解码装置、时钟电路等)可以采用适用的部件，这些均是本领域的普通技术人员所应该理解的，在此不做赘述，也不应作为对本公开的限制。
例如，该显示装置可以提升显示装置的低分辨率区域(也即，第一显示区域和第二显示区域)的亮度(例如，整体亮度)；对应地，显示装置的低分辨率区域的亮度上限以及亮度调节范围也得到了提升。
本公开的至少一个实施例还提供了一种用于驱动本公开的至少一个实施例提供的任一显示基板的驱动方法，其包括：向第一数据写入电路提供第一数据信号，以及向第二数据写入电路提供第二数据信号；以及使得第一驱动电路基于第一数据信号控制流经第一驱动电路的第一驱动电流，以及使得第二驱动电路基于第二数据信号控制流经第二驱动电路的第二驱动电流，以驱动同一发光元件。
图20是本公开的至少一个实施例提供的显示基板的驱动方法的示例性流程图。下面结合图20对本公开的至少一个实施例提供的显示基板的驱动方法进行示例性说明。如图20所示，该显示基板的驱动方法包括以下的步骤S110和步骤S120。
步骤S110：向第一数据写入电路提供第一数据信号，以及向第二数据写入电路提供第二数据信号。
步骤S120：使得第一驱动电路基于第一数据信号控制流经第一驱动电路的第一驱动电流，以及使得第二驱动电路基于第二数据信号控制流经第二驱动电路的第二驱动电流，以驱动同一发光元件。
例如，通过使得多个像素驱动单元组的每个包括至少两个像素驱动单元，且使得至少两个像素驱动单共同驱动同一发光元件，可以使得至少两个像素驱动单元包括的第一像素电路和第二像素电路在发光阶段分别生成驱动同一发光元件的第一驱动电流和第二驱动电流，由此可以提升被像素驱动单元组驱动的发光元件的亮度。
例如，在同一发光元件的待显示灰阶小于预定灰阶的情况下，驱动方法包括：使得向第二数据写入电路提供的第二数据信号的数据电压不等于向第一数据写入电路提供的第一数据信号的数据电压。
例如，预定灰阶大于显示基板的最小灰阶且小于显示基板的最大灰阶。例如，在发光元件的允许显示的亮度大于等于0灰阶小于等于255灰阶的情况下，预定灰阶X位于10-35灰阶之间。例如，预定灰阶X大于等于16灰阶小 于等于32灰阶。
例如，在同一发光元件的待显示灰阶小于预定灰阶的情况下，向第二数据写入电路提供的第二数据信号的数据电压为对应于零灰阶的电压，向第一数据写入电路提供的第一数据信号对应于上述同一发光元件的待显示灰阶的数据电压；此种情况下，像素驱动单元组仅使用第一像素电路驱动发光元件。
例如，在同一发光元件的待显示灰阶大于等于预定灰阶的情况下，驱动方法包括：使得向第二数据写入电路提供的第二数据信号的数据电压等于向第一数据写入电路提供的第一数据信号的数据电压；此种情况下，像素驱动单元组同时使用第一像素电路和第二像素电路驱动发光元件。例如，向第二数据写入电路提供的第二数据信号的数据电压以及向第一数据写入电路提供的第一数据信号的数据电压均等于对应于上述同一发光元件的待显示灰阶的数据电压。
例如，通过对提供给像素驱动单元组的数据信号进行分段控制可以使得显示基板的各个像素驱动单元组可以在高灰阶下提升驱动电流的值以及在低灰阶下使得驱动电流值更为准确，由此可以提高显示基板显示的图像的质量。
虽然上文中已经用一般性说明及具体实施方式，对本公开作了详尽的描述，但在本公开实施例基础上，可以对之作一些修改或改进，这对本领域技术人员而言是显而易见的。因此，在不偏离本公开精神的基础上所做的这些修改或改进，均属于本公开要求保护的范围。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种显示基板，包括多个像素驱动单元组，
    其中，所述多个像素驱动单元组的每个包括至少两个像素驱动单元，所述至少两个像素驱动单元连接在第一电源电压端和同一发光元件的第一端之间，被配置为共同驱动所述同一发光元件；
    所述至少两个像素驱动单元包括第一像素电路和第二像素电路，
    所述第一像素电路包括第一驱动电路和第一数据写入电路，所述第一数据写入电路被配置为接收第一数据信号且将所述第一数据信号写入至所述第一驱动电路，所述第一驱动电路被配置为基于所述第一数据信号控制流经所述第一驱动电路且用于驱动所述同一发光元件的第一驱动电流；以及
    所述第二像素电路包括第二驱动电路和第二数据写入电路，所述第二数据写入电路被配置为接收第二数据信号且将所述第二数据信号写入至所述第二驱动电路，所述第二驱动电路被配置为基于所述第二数据信号控制流经所述第二驱动电路且用于驱动所述同一发光元件的第二驱动电流。
  2. 根据权利要求1所述的显示基板，还包括：
    互不重叠的第一显示区域和第二显示区域，以及
    至少一条第一走线，
    其中，所述多个像素驱动单元组位于所述第二显示区域中；
    所述多个像素驱动单元组包括至少一个第一驱动单元组；
    所述第一显示区域包括至少一个第一发光元件；
    所述至少一个第一驱动单元组被配置为一一对应地驱动所述至少一个第一发光元件；以及
    所述至少一条第一走线电连接所述至少一个第一驱动单元组和与所述至少一个第一驱动单元组一一对应连接的所述至少一个第一发光元件。
  3. 根据权利要求2所述的显示基板，其中，所述多个像素驱动单元组还包括至少一个第二驱动单元组；
    所述第二显示区域包括至少一个第二发光元件；以及
    所述至少一个第二驱动单元组被配置为一一对应地驱动所述至少一个第二发光元件。
  4. 根据权利要求3所述的显示基板，其中，所述至少一个第二驱动单元 组分别和所述至少一个第二驱动单元组一一对应驱动的所述至少一个第二发光元件，在沿所述显示基板的显示面的法线方向彼此至少部分重叠。
  5. 根据权利要求3或4所述的显示基板，其中，所述至少一个第一发光元件包括多个第一发光元件，所述至少一个第二发光元件包括多个第二发光元件；以及
    所述第一显示区域中所述多个第一发光元件的单位面积分布密度等于所述第二显示区域中所述多个第二发光元件的单位面积分布密度。
  6. 根据权利要求5所述的显示基板，其中，所述多个第一发光元件和所述多个第二发光元件整体上以阵列方式布置。
  7. 根据权利要求5或6所述的显示基板，还包括至少部分围绕所述第二显示区域的第三显示区域，
    其中，所述第三显示区域包括多个第三发光元件；以及
    所述第一显示区域中所述多个第一发光元件的单位面积分布密度小于所述第三显示区域中所述多个第三发光元件的单位面积分布密度。
  8. 根据权利要求5-7任一所述的显示基板，其中，所述至少一个第一驱动单元组包括多个第一驱动单元组；
    所述至少一个第二驱动单元组包括多个第二驱动单元组；以及
    所述多个第一驱动单元组和所述多个第二驱动单元组整体上以阵列方式布置且在所述显示基板的行方向和所述显示基板的列方向上交替布置。
  9. 根据权利要求8所述的显示基板，其中，所述多个像素驱动单元组的每个包括的至少两个像素驱动单元在所述显示基板的列方向上并列布置；
    分别被在所述显示基板的行方向上相邻的两个所述第二驱动单元组驱动的两个第二发光元件位于不同行；
    分别被在所述显示基板的列方向上相邻的两个所述第二驱动单元组驱动的两个第二发光元件位于同一列；
    分别被在所述显示基板的行方向上相邻的两个所述第一驱动单元组驱动两个第一发光元件位于不同行；以及
    分别被在所述显示基板的列方向上相邻的两个所述第一驱动单元组驱动的两个第一发光元件位于同一列。
  10. 根据权利要求1-9任一所述的显示基板，其中，所述第一数据写入电路和所述第二数据写入电路与同一数据信号端电连接，以接收所述第一数据 信号和所述第二数据信号；以及
    所述第一数据信号和所述第二数据信号相同。
  11. 根据权利要求1-8任一所述的显示基板，其中，所述第一数据写入电路经由第一数据线与第一数据信号端电连接，以接收所述第一数据信号端提供的所述第一数据信号；
    所述第二数据写入电路经由第二数据线与第二数据信号端电连接，以接收所述第二数据信号端提供的所述第二数据信号；以及
    所述第一数据线和所述第二数据线为不同的数据线，以及所述第一数据信号端和所述第二数据信号端为不同的数据信号端。
  12. 根据权利要求11所述的显示基板，其中，所述多个像素驱动单元组的每个包括的至少两个像素驱动单元在所述显示基板的行方向上并列布置；
    所述显示基板还包括互不重叠的第一显示区域和第二显示区域；以及
    所述第一数据线从所述第一显示区域和所述第二显示区域之间的区域走线至所述第二显示区域，所述第二数据线沿所述显示基板的列方向延伸。
  13. 根据权利要求2-12任一所述的显示基板，还包括传感器，其中，所述传感器设置在所述显示基板的非显示侧，与所述第一显示区域在所述显示基板的显示面的法线方向上叠置，且被配置为接收并处理穿过所述第一显示区域的光信号。
  14. 一种显示装置，包括如权利要求1-13任一所述的显示基板。
  15. 根据权利要求14所述的显示装置，还包括第一数据驱动电路和第二数据驱动电路，
    其中，所述第一数据驱动电路配置为经由位于所述第一数据驱动电路中的第一数据信号端向所述第一数据写入电路提供所述第一数据信号；以及
    所述第二数据驱动电路配置为经由位于所述第二数据驱动电路中的第二数据信号端向所述第二数据写入电路提供所述第二数据信号。
  16. 根据权利要求14或15所述的显示装置，其中，所述显示基板还包括多个第三像素电路；以及
    所述多个第三像素电路驱动的多个发光元件不同于所述多个像素驱动单元组驱动的多个发光元件，所述第一数据驱动电路还配置为向所述多个第三像素电路中至少之一提供数据信号。
  17. 一种如权利要求1-13任一所述的显示基板的驱动方法，包括：
    向所述第一数据写入电路提供所述第一数据信号，以及向所述第二数据写入电路提供所述第二数据信号；以及
    使得所述第一驱动电路基于所述第一数据信号控制流经所述第一驱动电路的第一驱动电流，以及使得所述第二驱动电路基于所述第二数据信号控制流经所述第二驱动电路的第二驱动电流，以驱动所述同一发光元件。
  18. 根据权利要求17所述的显示基板的驱动方法，其中，在所述同一发光元件的待显示灰阶小于预定灰阶的情况下，所述驱动方法包括：
    使得向所述第二数据写入电路提供的第二数据信号的数据电压不等于向所述第一数据写入电路提供的第一数据信号的数据电压，
    其中，所述预定灰阶大于所述显示基板的最小灰阶且小于所述显示基板的最大灰阶。
  19. 根据权利要求18所述的显示基板的驱动方法，其中，向所述第二数据写入电路提供的所述第二数据信号的数据电压为对应于零灰阶的电压。
  20. 根据权利要求18或19所述的显示基板的驱动方法，其中，在所述同一发光元件的待显示灰阶大于等于所述预定灰阶的情况下，所述驱动方法包括：
    使得向所述第二数据写入电路提供的第二数据信号的数据电压等于向所述第一数据写入电路提供的第一数据信号的数据电压。
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