WO2021128492A1 - 液晶显示面板和液晶显示装置 - Google Patents

液晶显示面板和液晶显示装置 Download PDF

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Publication number
WO2021128492A1
WO2021128492A1 PCT/CN2020/071235 CN2020071235W WO2021128492A1 WO 2021128492 A1 WO2021128492 A1 WO 2021128492A1 CN 2020071235 W CN2020071235 W CN 2020071235W WO 2021128492 A1 WO2021128492 A1 WO 2021128492A1
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Prior art keywords
layer
via hole
metal
thickness
liquid crystal
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PCT/CN2020/071235
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English (en)
French (fr)
Inventor
张婷
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Tcl华星光电技术有限公司
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Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US16/640,743 priority Critical patent/US20230213825A1/en
Publication of WO2021128492A1 publication Critical patent/WO2021128492A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting

Definitions

  • This application relates to the field of display technology, in particular to a liquid crystal display panel and a liquid crystal display device.
  • the existing liquid crystal display panel designed with 3T (namely main transistor, sub-transistor, and sharing transistor) is shown in Figure 1. While the sub-pixels are charged by means of deep and shallow holes, the sharing transistors leak to a common potential, thereby making There is a potential difference between the main pixel and the sub-pixel to reduce the color shift. However, in the process of setting the deep and shallow holes, due to the overlapping arrangement of the deep and shallow holes, as shown in Figure 1 and Figure 2, the depth of the deep hole will be large.
  • the length of the indium tin oxide is large, which causes the impedance of the indium tin oxide layer to increase, and when the insulating layer is prepared, the photoresist will fall into the deep hole, causing the indium tin oxide to be unable to connect with the metal layer. This leads to abnormal signal transmission during signal transmission.
  • the existing liquid crystal display panel has the technical problem that the impedance of the indium tin oxide layer increases due to the overlap of the deep and shallow holes, and the signal transmission is abnormal.
  • the embodiments of the present application provide a liquid crystal display panel and a liquid crystal display device, which are used to solve the technical problems of the existing liquid crystal display panel that the impedance of the indium tin oxide layer increases due to the overlap of the deep and shallow holes and the signal transmission is abnormal.
  • An embodiment of the present application provides a liquid crystal display panel, including:
  • the first metal layer is disposed on the substrate
  • a gate insulating layer disposed on the first metal layer
  • An active layer disposed on the gate insulating layer
  • the second metal layer is disposed on the active layer
  • a passivation layer disposed on the second metal layer
  • the metal connection layer is arranged on the passivation layer
  • the metal connection layer is connected to the first metal layer through a first via hole
  • the metal connection layer is connected to the second metal layer through a second via hole
  • the depth of the first via hole is equal to that of the first metal layer.
  • the difference in the depth of the second via hole is smaller than the sum of the thicknesses of the gate insulating layer, the active layer and the second metal layer.
  • the projection of the first metal layer on the side surface of the liquid crystal display panel overlaps with the projection of the second metal layer on the side surface of the liquid crystal display panel.
  • a planarization layer is provided between the passivation layer and the metal connection layer, and the thickness of the first via passing through the planarization layer is equal to the thickness of the second via passing through The thickness of the planarization layer.
  • the thickness of the first via hole passing through the passivation layer is smaller than the thickness of the second via hole passing through the passivation layer.
  • the thickness of the gate insulating layer through the first via hole is smaller than the thickness of the gate insulating layer under the second via hole.
  • the depth of the first via is equal to the depth of the second via.
  • a planarization layer is provided between the passivation layer and the metal connection layer, and the thickness of the first via through the planarization layer is smaller than that of the second via through The thickness of the planarization layer.
  • a planarization layer is provided between the passivation layer and the metal connection layer, and the thickness of the first via through the planarization layer is greater than that of the second via through The thickness of the planarization layer, and the difference between the depth of the first via hole and the depth of the second via hole is smaller than the gate insulating layer, the active layer, the second metal layer, and the planarization layer The sum of the thickness.
  • the cross-sectional area of the first via is smaller than the cross-sectional area of the second via.
  • a buffer layer is provided between the substrate and the first metal layer, and the thickness of the buffer layer under the first via hole is greater than the thickness of the buffer layer under the second via hole.
  • the present application provides a liquid crystal display device, the liquid crystal display device includes a liquid crystal display panel and a backlight module, the liquid crystal display panel includes:
  • the first metal layer is disposed on the substrate
  • a gate insulating layer disposed on the first metal layer
  • An active layer disposed on the gate insulating layer
  • the second metal layer is disposed on the active layer
  • a passivation layer disposed on the second metal layer
  • the metal connection layer is arranged on the passivation layer
  • the metal connection layer is connected to the first metal layer through a first via hole
  • the metal connection layer is connected to the second metal layer through a second via hole
  • the depth of the first via hole is equal to that of the first metal layer.
  • the difference in the depth of the second via hole is smaller than the sum of the thicknesses of the gate insulating layer, the active layer and the second metal layer.
  • the projection of the first metal layer on the side surface of the liquid crystal display panel overlaps with the projection of the second metal layer on the side surface of the liquid crystal display panel.
  • a planarization layer is provided between the passivation layer and the metal connection layer, and the thickness of the first via passing through the planarization layer is equal to the thickness of the second via passing through The thickness of the planarization layer.
  • the thickness of the first via hole passing through the passivation layer is smaller than the thickness of the second via hole passing through the passivation layer.
  • the thickness of the gate insulating layer through the first via hole is smaller than the thickness of the gate insulating layer under the second via hole.
  • the depth of the first via is equal to the depth of the second via.
  • a planarization layer is provided between the passivation layer and the metal connection layer, and the thickness of the first via through the planarization layer is smaller than that of the second via through The thickness of the planarization layer.
  • a planarization layer is provided between the passivation layer and the metal connection layer, and the thickness of the first via through the planarization layer is greater than that of the second via through The thickness of the planarization layer, and the difference between the depth of the first via hole and the depth of the second via hole is smaller than the gate insulating layer, the active layer, the second metal layer, and the planarization layer The sum of the thickness.
  • the cross-sectional area of the first via is smaller than the cross-sectional area of the second via.
  • a buffer layer is provided between the substrate and the first metal layer, and the thickness of the buffer layer under the first via hole is greater than the thickness of the buffer layer under the second via hole.
  • the embodiments of the present application provide a liquid crystal display panel and a liquid crystal display device.
  • the liquid crystal display panel includes a substrate, a first metal layer, a gate insulating layer, an active layer, a second metal layer, a passivation layer, and a metal connection layer.
  • the first metal layer is disposed on the substrate, the gate insulating layer is disposed on the first metal layer, the active layer is disposed on the gate insulating layer, and the second metal layer is disposed On the active layer, the passivation layer is disposed on the second metal layer, and the metal connection layer is disposed on the passivation layer, wherein the metal connection layer is connected to the second metal layer through the first via hole.
  • the first metal layer is connected, the metal connection layer is connected to the second metal layer through a second via hole, and the difference between the depth of the first via hole and the depth of the second via hole is less than The sum of the thicknesses of the gate insulating layer, the active layer, and the second metal layer; by connecting the first metal layer and the second metal layer to the metal connection layer through the first via hole and the second via hole, respectively, so that the first The via hole is separated from the second via hole, and the difference between the depth of the first via hole and the depth of the second via hole is smaller than the sum of the thicknesses of the gate insulating layer, the active layer, and the second metal layer, so that the first The depth of a via is reduced, so that when the metal connection layer is routed from the first via, the length of the metal trace is reduced, thereby reducing impedance, and because the depth of the first via is reduced, the possibility of breaking the metal trace is reduced , The possibility of poor connection is reduced, thereby reducing the impedance of the metal connection layer, and solving
  • FIG. 1 is a first schematic diagram of a liquid crystal display panel in the prior art.
  • FIG. 2 is a second schematic diagram of a liquid crystal display panel in the prior art.
  • FIG. 3 is a first schematic diagram of a liquid crystal display panel provided by an embodiment of the application.
  • FIG. 4 is a second schematic diagram of a liquid crystal display panel provided by an embodiment of the application.
  • FIG. 5 is a third schematic diagram of a liquid crystal display panel provided by an embodiment of the application.
  • FIG. 6 is a schematic diagram of a liquid crystal display device provided by an embodiment of the application.
  • the present application provides a liquid crystal display panel and a liquid crystal display device.
  • a liquid crystal display panel and a liquid crystal display device.
  • the embodiments of the present application address the technical problems of the existing liquid crystal display panel that the impedance of the indium tin oxide layer increases due to the overlap of the shallow and deep holes, and the signal transmission is abnormal.
  • the embodiments of the present application are used to solve the problem.
  • the existing 3T design liquid crystal display panel includes a first metal layer 111, a gate insulating layer 112, an active layer 113, a second metal layer 114, a passivation layer 115, and a planarization layer. 116 and the indium tin oxide layer 117.
  • indium tin oxide is provided to connect the drain of the sharing transistor to the common potential, thereby reducing the potential of the sub-pixel and realizing the main pixel The potential difference with the sub-pixel, as shown in FIG.
  • the indium tin oxide connects the first metal layer 111 and the second metal layer 114 through the via hole 118, wherein the indium tin oxide 118 connects to the first metal layer 111 through the deep hole 1181 Connected, the indium tin oxide 118 is connected to the second metal layer 114 through the shallow hole 1182, so that the common potential discharges the sub-pixels, realizes the potential difference between the main pixel and the sub-pixels, and reduces the color shift, but it can be seen from Figure 2 ,
  • the deep hole needs to pass through multiple film layers, which makes the depth of the deep hole larger.
  • the passivation layer and the planarization layer will be filled in the deep hole.
  • the tin layer and the first metal layer cannot be connected, and the length of the indium tin oxide is large, which causes the problem of large impedance of the indium tin oxide, which leads to a large signal loss or even impossible to transmit in the signal transmission process, that is, the existing liquid crystal display panel.
  • the impedance of the indium tin oxide layer increases due to the overlap of the deep and shallow holes, and the signal transmission is abnormal.
  • an embodiment of the present application provides a liquid crystal display panel, and the liquid crystal display panel includes:
  • the first metal layer 212 is disposed on the substrate 211;
  • the gate insulating layer 213 is disposed on the first metal layer 212;
  • the active layer 214 is disposed on the gate insulating layer 213;
  • the second metal layer 215 is disposed on the active layer 214;
  • the passivation layer 216 is disposed on the second metal layer 215;
  • the metal connection layer 218 is disposed on the passivation layer 216;
  • the metal connection layer 218 is connected to the first metal layer 212 through a first via 221
  • the metal connection layer 218 is connected to the second metal layer 215 through a second via 222
  • the first The difference between the depth L1 of the via hole and the depth L2 of the second via hole is smaller than the sum L3 of the thickness of the gate insulating layer, the active layer and the second metal layer.
  • An embodiment of the application provides a liquid crystal display panel, which includes a substrate, a first metal layer, a gate insulating layer, an active layer, a second metal layer, a passivation layer, and a metal connection layer.
  • the metal layer is disposed on the substrate, the gate insulating layer is disposed on the first metal layer, the active layer is disposed on the gate insulating layer, and the second metal layer is disposed on the On the active layer, the passivation layer is disposed on the second metal layer, the metal connection layer is disposed on the passivation layer, and the metal connection layer is connected to the passivation layer through the first via hole.
  • the first metal layer is connected, the metal connection layer is connected to the second metal layer through a second via hole, and the difference between the depth of the first via hole and the depth of the second via hole is smaller than that of the gate
  • the depth of the hole is reduced, so that when the metal connection layer is routed from the first via, the length of the metal trace is reduced, thereby reducing impedance, and because the depth of the first via is reduced, the possibility of breaking the metal trace is reduced, which is not good.
  • connection is reduced, thereby reducing the impedance of the metal connection layer, and solving the technical problems of the existing liquid crystal display panel that the impedance of the indium tin oxide layer increases due to the overlapping of deep and shallow holes, and the signal transmission is abnormal.
  • the thickness of the film layer refers to the thickness of any part of the film layer.
  • the cross-sectional area of the via refers to the cross-sectional area of the bottom of the via, that is, the minimum value of the cross-sectional area of the via.
  • the projection of the first metal layer 211 on the side surface 311 of the liquid crystal display panel is the same as the projection of the second metal layer 215 on the side surface 311 of the liquid crystal display panel.
  • the projections on the above overlap; when setting the first metal layer and the second metal layer, remove the first metal layer under the second via, so that the first metal layer will not be placed under the second via, resulting in the second
  • the height of the via hole relative to the substrate is larger, resulting in a larger depth of the first via hole, and the projection of the first metal layer on the side of the liquid crystal display panel is different from that of the second metal layer on the side of the liquid crystal display panel.
  • the projection has overlap, so that the depth difference between the depth of the first via hole and the depth of the second via hole is reduced, so that the depth of the first via hole is reduced.
  • passivation Film layers such as layers are not easy to accumulate in the first via hole, and the length of the metal connection layer in the first via hole is reduced, so that the metal connection layer normally transmits signals and the impedance on the metal connection layer is reduced.
  • a planarization layer 217 is provided between the passivation layer 216 and the metal connection layer 218, and the first via 221 passes through the planarization layer 217
  • the thickness is equal to the thickness of the second via 222 passing through the planarization layer 217, that is, for a liquid crystal display panel provided with a planarization layer, without changing the thickness of the planarization layer, due to the first via
  • the difference between the depth and the depth of the second via is smaller than the sum of the thickness of the gate insulating layer, the active layer, and the second metal layer, so that the depth of the first via is reduced.
  • the voltage drop of the metal connection layer can be reduced, and the problem of poor connection between the metal connection layer and the first metal layer can be reduced.
  • the material of the planarization layer includes one of copper and soluble polytetrafluoroethylene.
  • the thickness of the first via hole passing through the passivation layer is smaller than the thickness of the second via hole passing through the passivation layer, because the first via hole and the second via hole It is necessary to pass through the passivation layer to reduce the thickness of the passivation layer through which the first via hole passes. Accordingly, the thickness of the first metal layer can be increased, thereby reducing the depth of the first via hole, thereby further making the metal connection The length of the layer at the first via hole is reduced, and the length of the metal connection layer in other areas remains unchanged, thereby reducing the impedance of the metal connection layer, and further reducing the possibility that the insulating layer and the planarization layer are filled in the first via hole Sex.
  • the thickness of the first via hole passing through the gate insulating layer is smaller than the thickness of the gate insulating layer under the second via hole.
  • the thickness of the gate insulating layer may be The thickness of the gate insulating layer under the first via hole is reduced, thereby correspondingly increasing the thickness of the first metal layer, so that the depth of the first via hole is reduced, while the thickness of the gate insulating layer under the second via hole remains unchanged , So that the depth of the first via hole and the second via hole are similar, so that the length of the metal connection layer is reduced, and the voltage drop of the metal connection layer is reduced.
  • the depth of the first via hole is equal to the depth of the second via hole, and before the first via hole and the second via hole are formed, each film layer is processed so that the first metal The projections of the upper end of the layer and the upper end of the second metal layer on the side of the liquid crystal display panel coincide, so that the depth of the first via is equal to the depth of the second via, which greatly reduces the depth of the first via, Therefore, when the metal connection layer is provided, the length of the metal connection layer is reduced, and because the first via is shallow, the possibility of the metal connection layer breaking in the first via is reduced, and the passivation layer and the planarization layer are filled in the first via.
  • the possibility of the via hole is reduced, and the metal connection layer is better connected to the first metal layer, so that the signal on the second metal layer is better transmitted to the first metal layer, and the voltage of the sub-pixel is reduced, so that the main pixel is connected to the first metal layer. There is a potential difference in the sub-pixels, reducing color shift.
  • a planarization layer is provided between the passivation layer and the metal connection layer, and the thickness of the first via through the planarization layer is smaller than that of the second via.
  • the thickness of the planarization layer that is, when the planarization layer is provided, the thickness of the planarization layer at the first via hole is reduced, so that the depth of the first via hole is reduced, and the length of the metal connection layer is reduced.
  • a planarization layer is provided between the passivation layer and the metal connection layer, and the thickness of the first via hole passing through the planarization layer is greater than that of the second via hole.
  • the thickness of the planarization layer, and the difference between the depth of the first via hole and the depth of the second via is smaller than the gate insulating layer, the active layer, the second metal layer, and the planarization layer.
  • the sum of the thickness of the layers, when the planarization layer is provided, the thickness of the planarization layer at the first via hole can be greater than the thickness of the planarization layer at the second via hole, but the depth of the first via hole is equal to that of the second via hole.
  • the difference in the depth of the via hole is smaller than the sum of the thicknesses of the gate insulating layer, the active layer, the second metal layer, and the planarization layer.
  • the thickness of the planarization layer here refers to any of the planarization layers.
  • the thickness of the metal connection layer can reduce the depth of the first via hole and the depth of the second via hole, thereby greatly reducing the thickness of the metal connection layer.
  • the cross-sectional area of the first via is smaller than the cross-sectional area of the second via.
  • the cross-sectional area of the first via Refers to the cross-sectional area of the side in contact with the first metal layer.
  • the cross-sectional area is the minimum cross-sectional area of the first via.
  • the corresponding cross-sectional area of the second via refers to the side in contact with the second metal layer.
  • the cross-sectional area is the smallest cross-sectional area of the second via, so that the cross-sectional area of the first via is smaller than the cross-sectional area of the second via, so that the metal connection layer is in the first via When wiring, the wiring is shorter, thereby reducing the voltage drop of the metal connection layer.
  • the material of the metal connection layer includes indium tin oxide.
  • a buffer layer is provided between the substrate and the first metal layer, and the thickness of the buffer layer under the first via hole is greater than the thickness of the buffer layer under the second via hole
  • an auxiliary layer is provided between the substrate and the first metal layer, and the auxiliary layer is used to increase the height of the first metal layer.
  • the thickness of the layer is greater than the thickness of the auxiliary layer under the second via, that is, by adding the auxiliary layer, the height of the first via and the second via is increased, thereby reducing the depth of the first via and the second via , So that the length of the metal connection layer is reduced, and the impedance is reduced accordingly.
  • the diameter of the first via hole is set to 9 microns
  • the second via hole The diameter of is 7 microns.
  • the diameter of the first via can reach 9 microns
  • the diameter of the second via can also reach 7 microns
  • the distance from the second via to the edge of the second metal layer Is 6 ⁇ 2, where “6” is the size of D2 in Fig. 4, “ ⁇ 2” means that both sides of the second via hole to both sides of the second metal layer are both “6”, and the first metal layer and The distance between the second metal layer, D1 in FIG.
  • the size of the first via hole and the second via hole can be changed accordingly to obtain the distance between the second via hole and the edge of the second metal layer, and the first The distance between the metal layer and the second metal layer, that is, by using the design of the first via hole and the second via hole in the embodiment of the present application, the size of the first via hole and the second via hole can reach a preset size, thereby It is avoided that the insulating layer is filled into the first via hole and the second via hole, resulting in poor connection between the indium tin oxide and the first metal layer, resulting in abnormal signal transmission.
  • an embodiment of the present application provides a liquid crystal display device.
  • the liquid crystal display device includes a liquid crystal display panel and a backlight module.
  • the liquid crystal display panel includes:
  • the first metal layer 212 is disposed on the substrate 211;
  • the gate insulating layer 213 is disposed on the first metal layer 212;
  • the active layer 214 is disposed on the gate insulating layer 213;
  • the second metal layer 215 is disposed on the active layer 214;
  • the passivation layer 216 is disposed on the second metal layer 215;
  • the metal connection layer 218 is disposed on the passivation layer 216;
  • the metal connection layer 218 is connected to the first metal layer 212 through a first via 221
  • the metal connection layer 218 is connected to the second metal layer 215 through a second via 222
  • the first The difference between the depth L1 of the via hole and the depth L2 of the second via hole is smaller than the sum L3 of the thickness of the gate insulating layer, the active layer and the second metal layer.
  • the embodiment of the application provides a liquid crystal display device, the liquid crystal display device includes a liquid crystal display panel and a backlight module, the liquid crystal display panel includes a substrate, a first metal layer, a gate insulating layer, an active layer, and a second metal layer , A passivation layer and a metal connection layer, the first metal layer is disposed on the substrate, the gate insulating layer is disposed on the first metal layer, and the active layer is disposed on the gate On the insulating layer, the second metal layer is disposed on the active layer, the passivation layer is disposed on the second metal layer, and the metal connection layer is disposed on the passivation layer, wherein, The metal connection layer is connected to the first metal layer through a first via hole, the metal connection layer is connected to the second metal layer through a second via hole, and the depth of the first via hole is the same as that of the first metal layer.
  • the difference between the depths of the two via holes is smaller than the sum of the thicknesses of the gate insulating layer, the active layer and the second metal layer; by passing the first metal layer and the second metal layer through the first via hole and the second metal layer, respectively
  • the via hole is connected to the metal connection layer, so that the first via hole is separated from the second via hole, and the difference between the depth of the first via hole and the depth of the second via hole is smaller than that of the gate insulating layer, the active layer, and the second via hole.
  • the sum of the thickness of the two metal layers reduces the depth of the first via, so that when the metal connection layer is routed from the first via, the length of the metal trace is reduced, thereby reducing the impedance.
  • Depth is reduced, the possibility of metal trace breakage is reduced, and the possibility of bad connection is reduced, thereby reducing the impedance of the metal connection layer, and solving the problem of the existing liquid crystal display panel due to the overlap of deep and shallow holes, which leads to the increase of the impedance of the indium tin oxide layer.
  • the backlight module includes a back plate 611, a light source 612 and an optical film 613.
  • the projection of the first metal layer on the side surface of the liquid crystal display panel is the same as the projection of the second metal layer on the side surface of the liquid crystal display panel. coincide.
  • a planarization layer is provided between the passivation layer and the metal connection layer, and the thickness of the first via hole passing through the planarization layer is equal to the thickness of the planarization layer.
  • the second via hole passes through the thickness of the planarization layer.
  • the thickness of the passivation layer of the first via hole is smaller than the thickness of the passivation layer of the second via hole.
  • the thickness of the gate insulating layer through the first via hole is smaller than the thickness of the gate insulating layer under the second via hole.
  • the depth of the first via hole is equal to the depth of the second via hole.
  • a planarization layer is provided between the passivation layer and the metal connection layer, and the thickness of the first via hole passing through the planarization layer is less than the thickness of the planarization layer.
  • the second via hole passes through the thickness of the planarization layer.
  • a planarization layer is provided between the passivation layer and the metal connection layer, and the thickness of the first via hole passing through the planarization layer is greater than the thickness of the planarization layer.
  • the second via hole passes through the thickness of the planarization layer, and the difference between the depth of the first via hole and the depth of the second via hole is smaller than that of the gate insulating layer, the active layer, and the second via hole. The sum of the thickness of the two metal layer and the planarization layer.
  • the cross-sectional area of the first via is smaller than the cross-sectional area of the second via.
  • a buffer layer is provided between the substrate and the first metal layer, and the thickness of the buffer layer under the first via hole is greater than that of the second via hole The thickness of the lower buffer layer.
  • the embodiments of the present application provide a liquid crystal display panel and a liquid crystal display device.
  • the liquid crystal display panel includes a substrate, a first metal layer, a gate insulating layer, an active layer, a second metal layer, a passivation layer and a metal connection layer,
  • the first metal layer is disposed on the substrate, the gate insulating layer is disposed on the first metal layer, the active layer is disposed on the gate insulating layer, and the second metal Layer is disposed on the active layer, the passivation layer is disposed on the second metal layer, the metal connection layer is disposed on the passivation layer, and the metal connection layer passes through the first pass
  • a hole is connected to the first metal layer, the metal connection layer is connected to the second metal layer through a second via hole, the difference between the depth of the first via hole and the depth of the second via hole, Less than the sum of the thickness of the gate insulating layer, the active layer and the second metal layer; by connecting the first metal layer and the second metal layer to the metal connection layer

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Abstract

一种液晶显示面板和液晶显示装置，液晶显示面板通过将第一金属层（212）和第二金属层（215）分别通过第一过孔（221）和第二过孔（222）与金属连接层（218）连接，且使得第一过孔（221）的深度与第二过孔（222）的深度的差值，小于栅极绝缘层（213）、有源层（214）和第二金属层（215）的厚度之和，从而使得第一过孔（221）的深度降低，金属走线的长度降低，从而降低阻抗。

Description

液晶显示面板和液晶显示装置 技术领域
本申请涉及显示技术领域，尤其是涉及一种液晶显示面板和液晶显示装置。
 背景技术
现有采用3T（即主晶体管、副晶体管和分享晶体管）设计的液晶显示面板如图1所示，会通过采用深浅孔的方式使得副像素充电的同时，通过分享晶体管漏电到公共电位，从而使得主像素和副像素之间存在电位差，降低色偏，但在深浅孔的设置过程中，由于深浅孔交叠设置，如图1、图2所示，会造成深孔深度较大，在制备氧化铟锡时，氧化铟锡的长度较大，导致氧化铟锡层的阻抗增大，且在制备绝缘层时，光刻胶等会掉入深孔，造成氧化铟锡无法与金属层连接，从而在信号传输过程中导致信号传输异常。
所以，现有液晶显示面板存在由于深浅孔交叠导致氧化铟锡层阻抗增大，信号传输异常的技术问题。
 技术问题
本申请实施例提供一种液晶显示面板和液晶显示装置，用于解决现有液晶显示面板存在由于深浅孔交叠导致氧化铟锡层阻抗增大，信号传输异常的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种液晶显示面板，包括：
衬底；
第一金属层，设置于所述衬底上；
栅极绝缘层，设置于所述第一金属层上；
有源层，设置于所述栅极绝缘层上；
第二金属层，设置于所述有源层上；
钝化层，设置于所述第二金属层上；
金属连接层，设置于所述钝化层上；
其中，所述金属连接层通过第一过孔与所述第一金属层连接，所述金属连接层通过第二过孔与所述第二金属层连接，所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层和第二金属层的厚度之和。
在一些实施例中，所述第一金属层在所述液晶显示面板的侧面上的投影，与所述第二金属层在所述液晶显示面板的侧面上的投影存在重合。
在一些实施例中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，等于所述第二过孔穿过所述平坦化层的厚度。
在一些实施例中，所述第一过孔穿过所述钝化层的厚度，小于所述第二过孔穿过所述钝化层的厚度。
在一些实施例中，所述第一过孔穿过所述栅极绝缘层的厚度，小于所述第二过孔下的栅极绝缘层的厚度。
在一些实施例中，所述第一过孔的深度等于所述第二过孔的深度。
在一些实施例中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，小于所述第二过孔穿过所述平坦化层的厚度。
在一些实施例中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，大于所述第二过孔穿过所述平坦化层的厚度，且所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层、第二金属层和平坦化层的厚度之和。
在一些实施例中，所述第一过孔的横截面积小于所述第二过孔的横截面积。
在一些实施例中，所述衬底与所述第一金属层之间设有缓冲层，所述第一过孔下的缓冲层的厚度大于所述第二过孔下的缓冲层的厚度。
同时，本申请提供一种液晶显示装置，该液晶显示装置包括液晶显示面板和背光模组，所述液晶显示面板包括：
衬底；
第一金属层，设置于所述衬底上；
栅极绝缘层，设置于所述第一金属层上；
有源层，设置于所述栅极绝缘层上；
第二金属层，设置于所述有源层上；
钝化层，设置于所述第二金属层上；
金属连接层，设置于所述钝化层上；
其中，所述金属连接层通过第一过孔与所述第一金属层连接，所述金属连接层通过第二过孔与所述第二金属层连接，所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层和第二金属层的厚度之和。
在一些实施例中，所述第一金属层在所述液晶显示面板的侧面上的投影，与所述第二金属层在所述液晶显示面板的侧面上的投影存在重合。
在一些实施例中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，等于所述第二过孔穿过所述平坦化层的厚度。
在一些实施例中，所述第一过孔穿过所述钝化层的厚度，小于所述第二过孔穿过所述钝化层的厚度。
在一些实施例中，所述第一过孔穿过所述栅极绝缘层的厚度，小于所述第二过孔下的栅极绝缘层的厚度。
在一些实施例中，所述第一过孔的深度等于所述第二过孔的深度。
在一些实施例中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，小于所述第二过孔穿过所述平坦化层的厚度。
在一些实施例中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，大于所述第二过孔穿过所述平坦化层的厚度，且所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层、第二金属层和平坦化层的厚度之和。
在一些实施例中，所述第一过孔的横截面积小于所述第二过孔的横截面积。
在一些实施例中，所述衬底与所述第一金属层之间设有缓冲层，所述第一过孔下的缓冲层的厚度大于所述第二过孔下的缓冲层的厚度。
 有益效果
本申请实施例提供液晶显示面板和液晶显示装置，该液晶显示面板包括衬底、第一金属层、栅极绝缘层、有源层、第二金属层、钝化层和金属连接层，所述第一金属层设置于所述衬底上，所述栅极绝缘层设置于所述第一金属层上，所述有源层设置于所述栅极绝缘层上，所述第二金属层设置于所述有源层上，所述钝化层设置于所述第二金属层上，所述金属连接层设置于所述钝化层上，其中，所述金属连接层通过第一过孔与所述第一金属层连接，所述金属连接层通过第二过孔与所述第二金属层连接，所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层和第二金属层的厚度之和；通过将第一金属层和第二金属层分别通过第一过孔和第二过孔与金属连接层连接，使得第一过孔与第二过孔分离，且使得第一过孔的深度与第二过孔的深度的差值，小于栅极绝缘层、有源层和第二金属层的厚度之和，从而使得第一过孔的深度降低，使得在金属连接层从第一过孔走线时，金属走线的长度降低，从而降低阻抗，且由于第一过孔的深度降低，金属走线的断裂可能性降低，不良连接的可能性降低，从而降低了金属连接层的阻抗，解决了现有液晶显示面板存在由于深浅孔交叠导致氧化铟锡层阻抗增大，信号传输异常的技术问题。
 附图说明
图1为现有技术的液晶显示面板的第一示意图。
图2为现有技术的液晶显示面板的第二示意图。
图3为本申请实施例提供的液晶显示面板的第一示意图。
图4为本申请实施例提供的液晶显示面板的第二示意图。
图5为本申请实施例提供的液晶显示面板的第三示意图。
图6为本申请实施例提供的液晶显示装置的示意图。
 本发明的实施方式
本申请提供一种液晶显示面板和液晶显示装置，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请实施例针对现有液晶显示面板存在由于深浅孔交叠导致氧化铟锡层阻抗增大，信号传输异常的技术问题，本申请实施例用以解决该问题。
如图1、图2所示，现有的3T设计的液晶显示面板包括第一金属层111、栅极绝缘层112、有源层113、第二金属层114、钝化层115、平坦化层116和氧化铟锡层117，现有技术中，为了实现主像素和副像素的电位差，会提供氧化铟锡将分享晶体管的漏极与公共电位连接，从而降低副像素的电位，实现主像素与副像素的电位差，如图2所示，氧化铟锡通过过孔118将第一金属层111和第二金属层114连接，其中，氧化铟锡118通过深孔1181与第一金属层111连接，氧化铟锡118通过浅孔1182与第二金属层114连接，从而使得公共电位对副像素进行放电，实现主像素与副像素的电位差，降低色偏，但从图2中可以看出，深孔需要穿过多个膜层，使得深孔的深度较大，造成在深孔形成氧化铟锡层时，会出现钝化层、平坦化层等膜层填充在深孔内，氧化铟锡层与第一金属层无法连接、氧化铟锡的长度较大，造成氧化铟锡阻抗较大的问题，从而导致在信号传输过程中，信号损失较大甚至无法传输，即现有液晶显示面板存在由于深浅孔交叠导致氧化铟锡层阻抗增大，信号传输异常的技术问题。
如图3所示，本申请实施例提供一种液晶显示面板，该液晶显示面板包括：
衬底211；
第一金属层212，设置于所述衬底211上；
栅极绝缘层213，设置于所述第一金属层212上；
有源层214，设置于所述栅极绝缘层213上；
第二金属层215，设置于所述有源层214上；
钝化层216，设置于所述第二金属层215上；
金属连接层218，设置于所述钝化层216上；
其中，所述金属连接层218通过第一过孔221与所述第一金属层212连接，所述金属连接层218通过第二过孔222与所述第二金属层215连接，所述第一过孔的深度L1与所述第二过孔的深度L2的差值，小于所述栅极绝缘层、有源层和第二金属层的厚度之和L3。
本申请实施例提供一种液晶显示面板，该液晶显示面板包括衬底、第一金属层、栅极绝缘层、有源层、第二金属层、钝化层和金属连接层，所述第一金属层设置于所述衬底上，所述栅极绝缘层设置于所述第一金属层上，所述有源层设置于所述栅极绝缘层上，所述第二金属层设置于所述有源层上，所述钝化层设置于所述第二金属层上，所述金属连接层设置于所述钝化层上，其中，所述金属连接层通过第一过孔与所述第一金属层连接，所述金属连接层通过第二过孔与所述第二金属层连接，所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层和第二金属层的厚度之和；通过将第一金属层和第二金属层分别通过第一过孔和第二过孔与金属连接层连接，使得第一过孔与第二过孔分离，且使得第一过孔的深度与第二过孔的深度的差值，小于栅极绝缘层、有源层和第二金属层的厚度之和，从而使得第一过孔的深度降低，使得在金属连接层从第一过孔走线时，金属走线的长度降低，从而降低阻抗，且由于第一过孔的深度降低，金属走线的断裂可能性降低，不良连接的可能性降低，从而降低了金属连接层的阻抗，解决了现有液晶显示面板存在由于深浅孔交叠导致氧化铟锡层阻抗增大，信号传输异常的技术问题。
需要说明的是，本申请实施例中，膜层的厚度在膜层的各个区域的厚度不同时，膜层的厚度指该膜层任何一处的厚度。
需要说明的是，针对截面为倒梯形的过孔，则过孔的横截面积指过孔的下底的横截面积，即过孔的横截面积的最小值。
在一种实施例中，如图4所示，所述第一金属层211在所述液晶显示面板的侧面311上的投影，与所述第二金属层215在所述液晶显示面板的侧面311上的投影存在重合；在设置第一金属层和第二金属层时，将第二过孔下的第一金属层去除，使得第一金属层不会设置在第二过孔下，导致第二过孔的相对于衬底的高度较大，从而导致第一过孔的深度较大，而使第一金属层在液晶显示面板的侧面的投影，与第二金属层在液晶显示面板的侧面的投影具有重合，则使得第一过孔的深度与第二过孔的深度之间的深度差降低，从而使得第一过孔的深度降低，在第一过孔内设置金属连接层时，钝化层等膜层不易堆积在第一过孔内，且金属连接层在第一过孔内的长度降低，从而使得金属连接层正常传输信号，且金属连接层上的阻抗降低。
在一种实施例中，如图3所示，所述钝化层216与所述金属连接层218之间设有平坦化层217，所述第一过孔221穿过所述平坦化层217的厚度，等于所述第二过孔222穿过所述平坦化层217的厚度，即对于设有平坦化层的液晶显示面板，在不改变平坦化层的厚度的同时，由于第一过孔和第二过孔的深度之差小于栅极绝缘层、有源层、第二金属层的厚度之和，使得第一过孔的深度降低，则对于设有平坦化层的液晶显示面板，也可以降低金属连接层的压降，降低金属连接层与第一金属层连接不良的问题。
在一种实施例中，所述平坦化层的材料包括铜和可溶性聚四氟乙烯中的一种。
在一种实施例中，所述第一过孔穿过所述钝化层的厚度，小于所述第二过孔穿过所述钝化层的厚度，由于第一过孔与第二过孔具需要穿过钝化层，将第一过孔穿过的钝化层的厚度降低，相应的可以提高第一金属层的厚度，从而使得第一过孔的深度降低，从而进一步的使得金属连接层在第一过孔处的长度降低，且金属连接层在其他区域的长度不变，从而降低了金属连接层的阻抗，且进一步降低绝缘层和平坦化层填充在第一过孔内的可能性。
在一种实施例中，所述第一过孔穿过所述栅极绝缘层的厚度，小于所述第二过孔下的栅极绝缘层的厚度，在设置栅极绝缘层时，可以将第一过孔下的栅极绝缘层的厚度降低，从而相应的提高第一金属层的厚度，使得第一过孔的深度降低，而在第二过孔下的栅极绝缘层的厚度不变，使得第一过孔与第二过孔的深度相近，从而使得金属连接层的长度降低，降低金属连接层的压降。
在一种实施例中，所述第一过孔的深度等于所述第二过孔的深度，在形成第一过孔和第二过孔前，提供对各个膜层进行处理，使得第一金属层的上端与第二金属层的上端在液晶显示面板的侧面的投影重合，从而使得第一过孔的深度与第二过孔的深度相等，使得极大的降低了第一过孔的深度，从而在设置金属连接层时，金属连接层的长度降低，且由于第一过孔较浅，金属连接层在第一过孔内断裂的可能性降低，钝化层和平坦化层填充在第一过孔内的可能性降低，金属连接层与第一金属层连接较好，从而较好的将第二金属层上的信号传递到第一金属层上，降低副像素的电压，使得主像素与副像素出现电位差，降低色偏。
在一种实施例中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，小于所述第二过孔穿过所述平坦化层的厚度；即在设置平坦化层时，将第一过孔处的平坦化层的厚度降低，从而使得第一过孔的深度降低，使得金属连接层的长度降低。
在一种实施例中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，大于所述第二过孔穿过所述平坦化层的厚度，且所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层、第二金属层和平坦化层的厚度之和，在设置平坦化层时，可以使第一过孔处的平坦化层的厚度大于第二过孔处的平坦化层的厚度，但使得第一过孔的深度与第二过孔的深度的差值，小于栅极绝缘层、有源层、第二金属层和平坦化层的厚度之和，需要说明的是，此处平坦化层的厚度指平坦化层的任一处的厚度，则可以降低第一过孔的深度，且降低第二过孔的深度，从而极大的降低金属连接层的厚度。
在一种实施例中，所述第一过孔的横截面积小于所述第二过孔的横截面积，对于倒梯形的过孔，如图3所示，第一过孔的横截面积指与第一金属层接触的一侧的横截面积，该横截面积为第一过孔的最小横截面积，相应的第二过孔的横截面积指与第二金属层接触一侧的横截面积，该横截面积为第二过孔的最小横截面积，使得第一过孔的横截面积小于所述第二过孔的横截面积，从而使得金属连接层在第一过孔走线时，走线较短，从而降低金属连接层的压降。
在一种实施例中，金属连接层的材料包括氧化铟锡。
在一种实施例中，所述衬底与所述第一金属层之间设有缓冲层，所述第一过孔下的缓冲层的厚度大于所述第二过孔下的缓冲层的厚度，通过使得第一金属层下的缓冲层的厚度增大，从而使得第一金属层的高度增加，相应的第一过孔的深度降低，从而使得金属连接层的长度降低。
在一种实施例中，所述衬底与所述第一金属层之间设有辅助层，所述辅助层用于提高所述第一金属层的高度，所述第一过孔下的辅助层的厚度大于所述第二过孔下的辅助层的厚度，即通过增加辅助层，使得第一过孔和第二过孔的高度提升，从而降低第一过孔和第二过孔的深度，使得金属连接层的长度降低，阻抗相应降低。
  第二过孔直径 第二过孔到第二金属层边缘的距离 第一金属层与第二金属层的间距 第一过孔直径
现有技术 - - - 7（6）
实施例1 7 6×2 2 9
实施例2 9 5×2 2 9
实施例3 11 4×2 2 9
实施例4 7 4×2 3 8
表一
如表一、图5所示，现有技术中在需要将深孔制作为最小横截面直径为7微米时，由于钝化层、平坦化层的影响，会导致无法形成为7微米的直径，而是6微米的直径，在深孔中会填充有绝缘物质，从而导致氧化铟锡与第一金属层连接不良，信号传输异常，而本申请中在设定不同的第一过孔直径和第二过孔直径时，如表一所示，实施例1至实施例4分别为设定的不同直径的第一过孔与第二过孔，得到的第一过孔和第二过孔的实际尺寸、以及第二过孔到第二金属层的边缘的距离、第一金属层与第二金属层的间距，例如实施例1中设定第一过孔的直径为9微米，第二过孔的直径为7微米，从表一中可以看到，第一过孔的直径能够达到9微米，第二过孔的直径也能达到7微米，第二过孔到第二金属层的边缘的距离为6×2，其中“6”为图4中的D2的大小，“×2”表示第二过孔的两侧到第二金属层的两侧边缘均为“6”，第一金属层与第二金属层的间距即图5中的D1为2微米，相应的变化第一过孔和第二过孔的尺寸，能够得到第二过孔到第二金属层的边缘的距离、以及第一金属层和第二金属层的间距，即使用本申请实施例中的第一过孔和第二过孔的设计，可以使第一过孔与第二过孔的尺寸达到预设的尺寸，从而避免了绝缘层填充到第一过孔和第二过孔中，造成氧化铟锡与第一金属层连接不良，从而导致信号传输异常。
如图6所示，本申请实施例提供一种液晶显示装置，该液晶显示装置包括液晶显示面板和背光模组，所述液晶显示面板包括：
衬底211；
第一金属层212，设置于所述衬底211上；
栅极绝缘层213，设置于所述第一金属层212上；
有源层214，设置于所述栅极绝缘层213上；
第二金属层215，设置于所述有源层214上；
钝化层216，设置于所述第二金属层215上；
金属连接层218，设置于所述钝化层216上；
其中，所述金属连接层218通过第一过孔221与所述第一金属层212连接，所述金属连接层218通过第二过孔222与所述第二金属层215连接，所述第一过孔的深度L1与所述第二过孔的深度L2的差值，小于所述栅极绝缘层、有源层和第二金属层的厚度之和L3。
本申请实施例提供一种液晶显示装置，该液晶显示装置包括液晶显示面板和背光模组，该液晶显示面板包括衬底、第一金属层、栅极绝缘层、有源层、第二金属层、钝化层和金属连接层，所述第一金属层设置于所述衬底上，所述栅极绝缘层设置于所述第一金属层上，所述有源层设置于所述栅极绝缘层上，所述第二金属层设置于所述有源层上，所述钝化层设置于所述第二金属层上，所述金属连接层设置于所述钝化层上，其中，所述金属连接层通过第一过孔与所述第一金属层连接，所述金属连接层通过第二过孔与所述第二金属层连接，所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层和第二金属层的厚度之和；通过将第一金属层和第二金属层分别通过第一过孔和第二过孔与金属连接层连接，使得第一过孔与第二过孔分离，且使得第一过孔的深度与第二过孔的深度的差值，小于栅极绝缘层、有源层和第二金属层的厚度之和，从而使得第一过孔的深度降低，使得在金属连接层从第一过孔走线时，金属走线的长度降低，从而降低阻抗，且由于第一过孔的深度降低，金属走线的断裂可能性降低，不良连接的可能性降低，从而降低了金属连接层的阻抗，解决了现有液晶显示面板存在由于深浅孔交叠导致氧化铟锡层阻抗增大，信号传输异常的技术问题。
在一种实施例中，如图6所示，所述背光模组包括背板611、光源612和光学膜片613。
在一种实施例中，在液晶显示装置中，所述第一金属层在所述液晶显示面板的侧面上的投影，与所述第二金属层在所述液晶显示面板的侧面上的投影存在重合。
在一种实施例中，在液晶显示装置中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，等于所述第二过孔穿过所述平坦化层的厚度。
在一种实施例中，在液晶显示装置中，所述第一过孔穿过所述钝化层的厚度，小于所述第二过孔穿过所述钝化层的厚度。
在一种实施例中，在液晶显示装置中，所述第一过孔穿过所述栅极绝缘层的厚度，小于所述第二过孔下的栅极绝缘层的厚度。
在一种实施例中，在液晶显示装置中，所述第一过孔的深度等于所述第二过孔的深度。
在一种实施例中，在液晶显示装置中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，小于所述第二过孔穿过所述平坦化层的厚度。
在一种实施例中，在液晶显示装置中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，大于所述第二过孔穿过所述平坦化层的厚度，且所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层、第二金属层和平坦化层的厚度之和。
在一种实施例中，在液晶显示装置中，所述第一过孔的横截面积小于所述第二过孔的横截面积。
在一种实施例中，在液晶显示装置中，所述衬底与所述第一金属层之间设有缓冲层，所述第一过孔下的缓冲层的厚度大于所述第二过孔下的缓冲层的厚度。
根据以上实施例可知：
本申请实施例提供一种液晶显示面板和液晶显示装置，该液晶显示面板包括衬底、第一金属层、栅极绝缘层、有源层、第二金属层、钝化层和金属连接层，所述第一金属层设置于所述衬底上，所述栅极绝缘层设置于所述第一金属层上，所述有源层设置于所述栅极绝缘层上，所述第二金属层设置于所述有源层上，所述钝化层设置于所述第二金属层上，所述金属连接层设置于所述钝化层上，其中，所述金属连接层通过第一过孔与所述第一金属层连接，所述金属连接层通过第二过孔与所述第二金属层连接，所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层和第二金属层的厚度之和；通过将第一金属层和第二金属层分别通过第一过孔和第二过孔与金属连接层连接，使得第一过孔与第二过孔分离，且使得第一过孔的深度与第二过孔的深度的差值，小于栅极绝缘层、有源层和第二金属层的厚度之和，从而使得第一过孔的深度降低，使得在金属连接层从第一过孔走线时，金属走线的长度降低，从而降低阻抗，且由于第一过孔的深度降低，金属走线的断裂可能性降低，不良连接的可能性降低，从而降低了金属连接层的阻抗，解决了现有液晶显示面板存在由于深浅孔交叠导致氧化铟锡层阻抗增大，信号传输异常的技术问题。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种液晶显示面板，其包括：
    衬底；
    第一金属层，设置于所述衬底上；
    栅极绝缘层，设置于所述第一金属层上；
    有源层，设置于所述栅极绝缘层上；
    第二金属层，设置于所述有源层上；
    钝化层，设置于所述第二金属层上；
    金属连接层，设置于所述钝化层上；
    其中，所述金属连接层通过第一过孔与所述第一金属层连接，所述金属连接层通过第二过孔与所述第二金属层连接，所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层和第二金属层的厚度之和。
  2. 如权利要求1所述的液晶显示面板，其中，所述第一金属层在所述液晶显示面板的侧面上的投影，与所述第二金属层在所述液晶显示面板的侧面上的投影存在重合。
  3. 如权利要求1所述的液晶显示面板，其中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，等于所述第二过孔穿过所述平坦化层的厚度。
  4. 如权利要求3所述的液晶显示面板，其中，所述第一过孔穿过所述钝化层的厚度，小于所述第二过孔穿过所述钝化层的厚度。
  5. 如权利要求3所述的液晶显示面板，其中，所述第一过孔穿过所述栅极绝缘层的厚度，小于所述第二过孔下的栅极绝缘层的厚度。
  6. 如权利要求3所述的液晶显示面板，其中，所述第一过孔的深度等于所述第二过孔的深度。
  7. 如权利要求1所述的液晶显示面板，其中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，小于所述第二过孔穿过所述平坦化层的厚度。
  8. 如权利要求1所述的液晶显示面板，其中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，大于所述第二过孔穿过所述平坦化层的厚度，且所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层、第二金属层和平坦化层的厚度之和。
  9. 如权利要求1所述的液晶显示面板，其中，所述第一过孔的横截面积小于所述第二过孔的横截面积。
  10. 如权利要求1所述的液晶显示面板，其中，所述衬底与所述第一金属层之间设有缓冲层，所述第一过孔下的缓冲层的厚度大于所述第二过孔下的缓冲层的厚度。
  11. 一种液晶显示装置，其包括液晶显示面板和背光模组，所述液晶显示面板包括：
    衬底；
    第一金属层，设置于所述衬底上；
    栅极绝缘层，设置于所述第一金属层上；
    有源层，设置于所述栅极绝缘层上；
    第二金属层，设置于所述有源层上；
    钝化层，设置于所述第二金属层上；
    金属连接层，设置于所述钝化层上；
    其中，所述金属连接层通过第一过孔与所述第一金属层连接，所述金属连接层通过第二过孔与所述第二金属层连接，所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层和第二金属层的厚度之和。
  12. 如权利要求11所述的液晶显示装置，其中，所述第一金属层在所述液晶显示面板的侧面上的投影，与所述第二金属层在所述液晶显示面板的侧面上的投影存在重合。
  13. 如权利要求11所述的液晶显示装置，其中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，等于所述第二过孔穿过所述平坦化层的厚度。
  14. 如权利要求13所述的液晶显示装置，其中，所述第一过孔穿过所述钝化层的厚度，小于所述第二过孔穿过所述钝化层的厚度。
  15. 如权利要求13所述的液晶显示装置，其中，所述第一过孔穿过所述栅极绝缘层的厚度，小于所述第二过孔下的栅极绝缘层的厚度。
  16. 如权利要求13所述的液晶显示装置，其中，所述第一过孔的深度等于所述第二过孔的深度。
  17. 如权利要求11所述的液晶显示装置，其中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，小于所述第二过孔穿过所述平坦化层的厚度。
  18. 如权利要求11所述的液晶显示装置，其中，所述钝化层与所述金属连接层之间设有平坦化层，所述第一过孔穿过所述平坦化层的厚度，大于所述第二过孔穿过所述平坦化层的厚度，且所述第一过孔的深度与所述第二过孔的深度的差值，小于所述栅极绝缘层、有源层、第二金属层和平坦化层的厚度之和。
  19. 如权利要求11所述的液晶显示装置，其中，所述第一过孔的横截面积小于所述第二过孔的横截面积。
  20. 如权利要求11所述的液晶显示装置，其中，所述衬底与所述第一金属层之间设有缓冲层，所述第一过孔下的缓冲层的厚度大于所述第二过孔下的缓冲层的厚度。
PCT/CN2020/071235 2019-12-24 2020-01-09 液晶显示面板和液晶显示装置 WO2021128492A1 (zh)

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