WO2021120315A1 - 像素混合补偿电路及像素混合补偿方法 - Google Patents

像素混合补偿电路及像素混合补偿方法 Download PDF

Info

Publication number
WO2021120315A1
WO2021120315A1 PCT/CN2019/129274 CN2019129274W WO2021120315A1 WO 2021120315 A1 WO2021120315 A1 WO 2021120315A1 CN 2019129274 W CN2019129274 W CN 2019129274W WO 2021120315 A1 WO2021120315 A1 WO 2021120315A1
Authority
WO
WIPO (PCT)
Prior art keywords
thin film
film transistor
electrically connected
node
pixel
Prior art date
Application number
PCT/CN2019/129274
Other languages
English (en)
French (fr)
Inventor
张留旗
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/641,238 priority Critical patent/US11348526B2/en
Publication of WO2021120315A1 publication Critical patent/WO2021120315A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0828—Several active elements per pixel in active matrix panels forming a digital to analog [D/A] conversion circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the invention relates to the field of display technology, in particular to a pixel mixing compensation circuit and a pixel mixing compensation method.
  • Organic light emitting diode is a self-luminous display technology that has the advantages of wide viewing angle, high contrast, low power consumption, and bright colors. Due to these advantages, active organic electroluminescent diodes (active The proportion of matrix organic light emitting diode (AMOLED) in the display industry is increasing year by year. Oxide thin film transistors are widely used in large-size AMOLEDs due to the advantages of high mobility and good uniformity.
  • the purpose of the present invention is to provide a pixel hybrid compensation circuit and a pixel hybrid compensation method, by adding a fourth thin film transistor (T4) and a second capacitor (Cp) between the source and drain of the third thin film transistor (T3). ), the fourth thin film transistor (T4) is only turned on line by line in the detection phase (normally lit and turned off to prevent mutual influence between different lines), and the second capacitor (Cp) is used to change the potential of the second node (S) Coupling feedback to the sensing line, the external compensation circuit detects the potential change of the second node (S) based on the sensing line (that is, the current change caused by the threshold voltage Vth and mobility drift), which can directly reflect the current change; and The voltage value that needs to be adjusted is sent to the data signal (Data), and the data signal (Data) adjusts the voltage of the first node (G), keeping the Vgs of the first thin film transistor (T1) unchanged, and completing the adjustment of the first thin film transistor (T1) ) Compensation.
  • each pixel hybrid compensation circuit which includes a plurality of pixel internal drive circuits arranged in an array, and an external compensation circuit electrically connected to each pixel's internal drive circuit through a first switch (Scan) Circuit; each pixel internal driving circuit includes: a first thin film transistor (T1), the gate of the first thin film transistor is electrically connected to the first node (G), the source of the first thin film transistor is electrically connected The second node (S), the drain of the first thin film transistor is connected to the power supply voltage (VDD); the second thin film transistor (T2), the gate of the second thin film transistor is connected to the write signal (WR), The source of the second thin film transistor is connected to a data signal (Data), and the drain of the second thin film transistor is electrically connected to the first node (G); a third thin film transistor (T3), the third thin film transistor The gate of the third thin film transistor is connected to the write signal (WR), the source of the third thin film transistor is electrically connected to the first node (G);
  • the external compensation circuit includes: an analog-to-digital converter, the input terminal of which is electrically connected to the sensing line (Sensing) in the corresponding column pixel internal driving circuit, and the output terminal of which is electrically connected to the input terminal of the current comparator ; Voltage comparator, the output terminal of which is electrically connected to the input terminal of the control module; the control module, whose output terminal is electrically connected to the input terminal of the memory; the memory, whose output terminal is electrically connected to the input terminal of the digital-to-analog converter; The output terminal is electrically connected to the source of the second thin film transistor (T2) in the internal driving circuit of the corresponding column of pixels.
  • T2 the second thin film transistor
  • first thin film transistor (T1), the second thin film transistor (T2), the third thin film transistor (T3), and the fourth thin film transistor (T4) are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, Or amorphous silicon thin film transistors.
  • write signal (WR) and scan signal (Sen) are provided by an external timing controller.
  • the write signal (WR), the scan signal (Sen), and the data signal (Data) are combined to sequentially correspond to a detection phase, and the detection phase includes: a first phase, a first phase, and a first phase.
  • the second thin film transistor (T2), the third thin film transistor (T3), and the fourth thin film transistor (T4) are all turned on; in the second stage, the write signal (WR) provides low Potential, the scan signal (Sen) provides a high potential, the data signal (Data) provides a high potential, the second thin film transistor (T2) and the third thin film transistor (T3) are turned off, and the reference voltage (Vref) is disconnected from the sensing line; in the third stage, the write signal (WR) provides a low potential, the scan signal (Sen) provides a high potential, and the data signal (
  • the combination of the write signal (WR), the scan signal (Sen), and the data signal (Data) successively corresponds to a detection phase, and further includes a driving light-emitting phase; In the light-emitting phase, the write signal (WR) provides a high potential, the scan signal (Sen) provides a low potential, and the data signal (Data) provides a high potential.
  • the high potential provided by the scan signal (Sen) is greater than the high potential provided by the write signal (WR); the high potential provided by the scan signal (Sen) is greater than the high potential provided by the data signal (Data) .
  • the present invention provides a pixel mixing compensation method, including the following steps: providing the pixel mixing compensation circuit as described above; entering the first stage of the detection stage, in the first stage, the write signal (WR) provides low Potential, the scan signal (Sen) provides a high potential, the data signal (Data) provides a high potential, the second thin film transistor (T2), the third thin film transistor (T3), and the fourth thin film
  • the transistors (T4) are all turned on, and the data signal (Data) and the reference voltage (Vref) write initial potentials to the first node (G) and the second node (S) respectively; enter the second phase of the detection phase
  • the write signal (WR) provides a low potential
  • the scan signal (Sen) provides a high potential
  • the data signal (Data) provides a high potential
  • the third thin film transistor (T3) are turned off, and the reference voltage Vref is disconnected from the sensing line, the power supply voltage (VDD) starts to charge the second node
  • the third stage detecting the potentials of different pixels on the sensing line (Sensing) in different gray levels at time t and recording the initial value Vs0; looping the detection stage, in each stage Measure the potential Vsi on the sensing line (Sensing) at the same time point t, i represents the number of cycles of the detection step until Vsi is the same as the initial value Vs0, if the detected Vsi is different from the Vs0, it will pass The external compensation circuit starts to perform voltage compensation on the internal driving circuit of the pixel.
  • the write signal (WR) provides a high potential
  • the scan signal (Sen) provides a low potential
  • the data signal (Data) provides a high potential
  • the present invention provides a pixel hybrid compensation circuit and a pixel hybrid compensation method.
  • the fourth The thin film transistor (T4) is only turned on row by row during the detection phase (normally lit and turned off to prevent the mutual influence between different rows), and the second capacitor (Cp) is used to couple the change in the potential of the second node (S) to the induction
  • the external compensation circuit detects the potential change of the second node (S) based on the sensing line (that is, the current change caused by the threshold voltage Vth and mobility drift), which can directly reflect the current change; and the voltage that needs to be adjusted
  • the value is sent to the data signal (Data), and the data signal (Data) adjusts the voltage of the first node (G) to keep the Vgs of the first thin film transistor (T1) unchanged, thereby completing the compensation for the first thin film transistor (T1).
  • FIG. 1 is a circuit diagram of a pixel hybrid compensation circuit provided by the present invention
  • FIG. 2 is a timing diagram of the pixel hybrid compensation circuit provided by the present invention.
  • Pixel hybrid compensation circuit 100 external compensation circuit 200;
  • Analog-to-digital converter 201 voltage comparator 202; control module 203;
  • the present invention provides a pixel hybrid compensation circuit 100, which includes a plurality of pixel internal driving circuits arranged in an array, and a first switch (Scan) electrically connected to each pixel internal driving circuit External compensation circuit 200.
  • a pixel hybrid compensation circuit 100 which includes a plurality of pixel internal driving circuits arranged in an array, and a first switch (Scan) electrically connected to each pixel internal driving circuit External compensation circuit 200.
  • the internal driving circuit of each pixel includes: a first thin film transistor (T1), a second thin film transistor (T2), a third thin film transistor (T3), a fourth thin film transistor (T4), a first capacitor (Cst) and organic light emitting Diode (D1).
  • T1 first thin film transistor
  • T2 second thin film transistor
  • T3 third thin film transistor
  • T4 fourth thin film transistor
  • D1 organic light emitting Diode
  • the gate of the first thin film transistor (T1) is electrically connected to the first node (G), the source of the first thin film transistor (T1) is electrically connected to the second node (S), and the first thin film transistor The drain of (T1) is connected to the power supply voltage (VDD).
  • the gate of the second thin film transistor (T2) is connected to the write signal (WR), the source of the second thin film transistor (T2) is connected to the data signal (Data), and the second thin film transistor (T2) The drain of is electrically connected to the first node (G).
  • the third thin film transistor (T3), the gate of the third thin film transistor (T3) is connected to the write signal (WR), and the source of the third thin film transistor (T3) is electrically connected to the first node ( G), the drain of the third thin film transistor (T3) is electrically connected to a sensing line (Sensing).
  • the gate of the fourth thin film transistor (T4) is connected to the scan signal (Sen), the source of the fourth thin film transistor (T4) is electrically connected to the second capacitor (Cp), and the fourth thin film transistor (T4) The drain of) is electrically connected to the second node (S).
  • the fourth thin film transistor (T4) is only turned on row by row during the detection phase (normally lit and turned off to prevent mutual influence between different rows), and the second capacitor (Cp) is used to couple the change in the potential of the second node (S) Feedback to the sensing line (Sensing).
  • One end of the first capacitor (Cst) is electrically connected to the first node (G), and the other end is electrically connected to the second node (S).
  • One end of the second capacitor (Cp) is electrically connected to the sensing line (Sensing).
  • the anode of the organic light emitting diode (D1) is electrically connected to the second node (S), and the cathode of the organic light emitting diode (D1) is grounded.
  • the sensing line (Sensing) is electrically connected to a plurality of parasitic capacitors, each parasitic capacitor is grounded, and each parasitic capacitor is connected in parallel with each other; the sensing line (Sensing) is electrically connected to a second switch (Spre) Reference voltage (Vref).
  • the external compensation circuit 200 is used to detect whether the reference voltage Vgs of the first node and the second node are the same as the power supply voltage (VDD), and if they are not the same, according to the reference voltage Vgs and the power supply
  • the difference of the voltage (VDD) is used to calibrate the data signal input to the pixel circuit, and input the calibrated data signal to the pixel circuit.
  • the first thin film transistor (T1), the second thin film transistor (T2), the third thin film transistor (T3), and the fourth thin film transistor (T4) are all low temperature polysilicon thin film transistors, oxide semiconductor thin film transistors, or amorphous Silicon thin film transistors.
  • the external compensation circuit 200 includes: an analog-to-digital converter 201, a voltage comparator 202, a control module 203, a memory 204, and a digital-to-analog converter 205.
  • the input terminal of the analog-to-digital converter 201 is electrically connected to the sensing line in the corresponding column pixel internal driving circuit, and the output terminal is electrically connected to the input terminal of the current comparator.
  • the output terminal of the voltage comparator 202 is electrically connected to the input terminal of the control module 203.
  • the output terminal of the control module 203 is electrically connected to the input terminal of the memory 204.
  • the output terminal of the memory 204 is electrically connected to the input terminal of the digital-to-analog converter 205.
  • the output terminal of the digital-to-analog converter 205 is electrically connected to the source of the second thin film transistor (T2) in the internal driving circuit of the corresponding column of pixels.
  • the write signal (WR) and scan signal (Sen) are provided by an external timing controller.
  • the write signal (WR), the scan signal (Sen), and the data signal (Data) are combined to sequentially correspond to a detection phase, and the detection phase includes: a first Stage, a second stage and a third stage;
  • the write signal (WR) provides a low potential
  • the scan signal (Sen) provides a high potential
  • the data signal (Data) provides a high potential
  • the third thin film transistor (T3) and the fourth thin film transistor (T4) are both turned on;
  • the write signal (WR) provides a low potential
  • the scan signal (Sen) provides a high potential
  • the data signal (Data) provides a high potential
  • the third thin film transistor (T3) is turned off, and the reference voltage (Vref) is disconnected from the sensing line.
  • the write signal (WR) provides a low potential
  • the scan signal (Sen) provides a high potential
  • the data signal (Data) provides a high potential
  • the combination of the write signal (WR), the scan signal (Sen), and the data signal (Data) successively corresponds to a detection stage, and further includes a driving light-emitting stage.
  • the write signal (WR) provides a high potential
  • the scan signal (Sen) provides a low potential
  • the data signal (Data) provides a high potential
  • the high potential provided by the scan signal (Sen) is greater than the high potential provided by the write signal (WR).
  • the high potential provided by the scan signal (Sen) is greater than the high potential provided by the data signal (Data).
  • the present invention also provides a pixel mixing compensation method, which includes the following steps.
  • Step S1 Provide the pixel mixing compensation circuit 100 described above.
  • Step S2) Enter the first phase of the detection phase.
  • the write signal (WR) provides a low potential
  • the scan signal (Sen) provides a high potential
  • the data signal (Data) provides a high potential.
  • Potential the second thin film transistor (T2), the third thin film transistor (T3), and the fourth thin film transistor (T4) are all turned on, the data signal (Data) and the reference voltage (Vref) Write initial potentials to the first node (G) and the second node (S) respectively.
  • Step S3) Enter the second phase of the detection phase.
  • the write signal (WR) provides a low potential
  • the scan signal (Sen) provides a high potential
  • the data signal (Data) provides a high potential.
  • the second thin film transistor (T2) and the third thin film transistor (T3) are turned off, and the reference voltage Vref is disconnected from the sensing line, and the power supply voltage (VDD) starts to affect the second node ( S) Charge
  • the potential of the first node (G) rises due to the coupling of the first capacitor (Cst)
  • the reference voltage (Vgs) basically remains unchanged
  • the potential on the sensing line (Sensing) is due to the second
  • the coupling of the capacitance (Cp) rises synchronously.
  • Step S4) Enter the third phase of the detection phase.
  • the write signal (WR) provides a low potential
  • the scan signal (Sen) provides a high potential
  • the data signal (Data) provides a high potential.
  • Potential turn on the first switch (Scan), detect the reference voltage Vgs through the external compensation circuit 200, and perform voltage compensation on the pixel drive circuit.
  • Step S5) Cycle the detection phase, measure the potential Vsi on the sensing line (Sensing) at the same time point t in each phase, i represents the number of cycles of the detection phase until Vsi is the same as the initial value Vs0, If the detected Vsi is different from the Vs0, the external compensation circuit 200 starts to perform voltage compensation on the internal driving circuit of the pixel.
  • the signal (Data) voltage Vdata is the compensated voltage value (as shown in Figure 2, two adjustments of the Data voltage signal, that is, the first node (G) is compensated and adjusted, so that the entire Vgs voltage can be stabilized), assuming adjustment During the Vdata process, if the detection value Vsi that is completely consistent with the initial value Vs0 cannot be obtained, the closest value is taken as the voltage value of the data signal (Date)).
  • This method can complete the detection and compensation of the electrical drift of the TFT at one time, and because the detection can be completed quickly in a short time, it can detect and compensate when the machine is switched on and off, and can also detect and compensate in real time during the use of the panel.
  • Step S6 Enter the driving light-emitting phase, in the driving light-emitting phase, the write signal (WR) provides a high potential, the scan signal (Sen) provides a low potential, and the data signal (Data) provides a high potential .
  • the write signal (WR) provides a high potential
  • the scan signal (Sen) provides a low potential
  • the data signal (Data) provides a high potential .
  • a data embodiment is provided, which detects the electrical parameters of the internal driving circuit of the pixel in an embodiment.
  • the data signal (data) voltage required to be corrected and the current before and after compensation under different Vth and mobility of the thin film transistors are respectively detected.
  • the thin film transistor threshold voltage Vth corresponds to the voltage Vgs of the first node (G) and the second node (S) in the circuit diagram of FIG. 1.
  • the mobility of the TFT is U0
  • set the data voltage to 5V
  • the potential on the sensing line is detected until the detected voltage is consistent with the initial voltage, and the data voltage at this time is recorded as the compensated data signal (data) voltage value.
  • the present invention provides a pixel hybrid compensation circuit 100 and a pixel hybrid compensation method.
  • a fourth thin film transistor (T4) and a second capacitor (Cp) between the source and drain of the third thin film transistor (T3)
  • the first The four thin film transistors (T4) are only turned on row by row during the detection phase (normally lit and turned off to prevent mutual influence between different rows), and the second capacitor (Cp) is used to couple the change in the potential of the second node (S) to
  • the external compensation circuit 200 detects the potential change of the second node (S) based on the sensing line (that is, the current change caused by the threshold voltage Vth and mobility drift), which can directly reflect the current change; and will need to be adjusted
  • the voltage value of is sent to the data signal (Data), and the data signal (Data) adjusts the voltage of the first node (G), keeping the Vgs of the first thin film transistor (T1) unchanged, and then completing the first thin film transistor (T1) make up.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)
  • Control Of El Displays (AREA)

Abstract

本发明提供一种像素混合补偿电路以及像素混合补偿方法，包括呈阵列式排布的多个像素内部驱动电路以及电性连接每一像素内部驱动电路的外部补偿电路。通过在第三薄膜晶体管的源极和漏极间加入了第四薄膜晶体管和第二电容，第四薄膜晶体管仅在探测阶段逐行开启，第二电容用于将第二节点电位的变化耦合反馈到感应线上，外部补偿电路根据感应线探测得到第二节点的电位变化（即因阈值电压Vth和迁移率漂移引起的电流变化），可以直接反应电流的变化情况；并将需要调整的电压值发送至数据信号，数据信号调整第一节点的电压，保持第一薄膜晶体管的不变，进而完成对第一薄膜晶体管的补偿。

Description

像素混合补偿电路及像素混合补偿方法 技术领域
本发明涉及显示技术领域，特别是一种像素混合补偿电路及像素混合补偿方法。
 背景技术
有机电致发光二极管（organic light emitting diode，OLED）是一种自发光的显示技术，具有视角宽、对比度高、功耗低、色彩鲜艳等优点。由于这些优势，有源有机电致发光二极管（active matrix organic light emitting diode，AMOLED）在显示行业所占的比重正在逐年增加。氧化物薄膜晶体管由于迁移率高，均匀性好等优点而在大尺寸AMOLED中广泛使用。
 技术问题
但随着面板使用时间延长，薄膜晶体管以及OLED的电性会发生漂移，最终因显示不均匀等问题而失效。
因此，急需提供一种新的像素混合补偿电路及像素混合补偿方法，用以对像素内部驱动电路的薄膜晶体管进行电压补偿。
 技术解决方案
本发明的目的是，提供一种像素混合补偿电路以及像素混合补偿方法，通过在第三薄膜晶体管（T3）的源极和漏极间加入了第四薄膜晶体管（T4）和第二电容（Cp），第四薄膜晶体管（T4）仅在探测阶段逐行开启（正常点亮关断防止不同行之间的相互影响），第二电容（Cp）用于将第二节点（S）电位的变化耦合反馈到感应线上，外部补偿电路根据感应线探测得到第二节点（S）的电位变化（即因阈值电压Vth和迁移率漂移引起的电流变化），可以直接反应电流的变化情况；并将需要调整的电压值发送至数据信号（Data），数据信号（Data）调整第一节点（G）的电压，保持第一薄膜晶体管（T1）的Vgs不变，进而完成对第一薄膜晶体管（T1）的补偿。
为达到上述目的，本发明提供一种像素混合补偿电路，包括呈阵列式排布的多个像素内部驱动电路、及通过一第一开关（Scan）电性连接每一像素内部驱动电路的外部补偿电路；每一像素内部驱动电路均包括：第一薄膜晶体管(T1)，所述第一薄膜晶体管的栅极电性连接第一节点(G)，所述第一薄膜晶体管的源极电性连接第二节点(S)，所述第一薄膜晶体管的漏极接入电源电压(VDD)；第二薄膜晶体管(T2)，所述第二薄膜晶体管的栅极接入写入信号(WR)，所述第二薄膜晶体管的源极接入数据信号(Data)，所述第二薄膜晶体管的漏极电性连接第一节点(G)；第三薄膜晶体管(T3)，所述第三薄膜晶体管的栅极接入写入信号(WR)，所述第三薄膜晶体管的源极电性连接第一节点(G)，所述第三薄膜晶体管的漏极电性连接感应线(Sensing)；第四薄膜晶体管(T4)，所述第四薄膜晶体管的栅极接入扫描信号(Sen)，所述第四薄膜晶体管的源极电性连接第二电容（Cp），所述第四薄膜晶体管的漏极电性连接所述第二节点(S)；第一电容(Cst)，所述第一电容(Cst)的一端电性连接所述第一节点(G)，另一端电性连接所述第二节点(S)；第二电容（Cp），所述第二电容（Cp）的一端电性连接所述感应线(Sensing)；有机发光二极管(D1)，所述有机发光二极管(D1)的阳极电性连接所述第二节点(S)，所述有机发光二极管(D1)的阴极接地；其中，所述感应线(Sensing)电性连接多个寄生电容，每个寄生电容接地，每个寄生电容相互并联，所述感应线(Sensing)电性通过一第二开关（Spre）接入一参考电压（Vref）；所述外部补偿电路用以检测所述第一节点与所述第二节点的基准电压Vgs与所述电源电压(VDD)是否相同，若不相同，则根据所述基准电压Vgs与所述电源电压(VDD)的差值，对输入至所述像素电路的数据信号进行校准，并将校准后的数据信号输入至所述像素电路。
进一步地，所述外部补偿电路包括：模数转换器，其输入端电性连接对应的所述列像素内部驱动电路中的感应线(Sensing)，其输出端电性连接电流比较器的输入端；电压比较器，其输出端电性连接控制模块的输入端；控制模块，其输出端电性连接存储器的输入端；存储器，其输出端电性连接数模转换器的输入端；数模转换器，其输出端电性连接对应的所述列像素内部驱动电路中第二薄膜晶体管(T2)的源极。
进一步地，所述第一薄膜晶体管 (T1)、第二薄膜晶体管(T2)、第三薄膜晶体管(T3)、及第四薄膜晶体管(T4)均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
进一步地，所述写入信号(WR)以及扫描信号(Sen)通过外部时序控制器提供。
进一步地，所述写入信号(WR)、所述扫描信号(Sen)、及所述数据信号(Data)相组合，先后对应于一探测阶段，所述探测阶段包括：一第一阶段、一第二阶段以及一第三阶段；在所述第一阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均打开；在所述第二阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)以及所述第三薄膜晶体管(T3)关闭，且所述参考电压（Vref）与所述感应线断开；在所述第三阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位。
进一步地，所述写入信号(WR)、所述扫描信号(Sen)、及所述数据信号(Data)相组合，先后对应于一探测阶段之后，还包括一驱动发光阶段；在所述驱动发光阶段，所述写入信号(WR)提供高电位，所述扫描信号(Sen)提供低电位，所述数据信号(Data)提供高电位。
进一步地，所述扫描信号(Sen)提供的高电位大于所述写入信号(WR)提供的高电位；所述扫描信号(Sen)提供的高电位大于所述数据信号(Data)提供高电位。
本发明提供一种像素混合补偿方法，包括如下步骤：提供如前文所述的像素混合补偿电路；进入探测阶段的第一阶段，在所述第一阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均打开，所述数据信号(Data)和所述参考电压（Vref）分别对第一节点（G）和第二节点（S）点写入初始电位；进入探测阶段的第二阶段，在所述第二阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)以及所述第三薄膜晶体管(T3)关闭，且所述参考电压Vref与所述感应线断开，所述电源电压(VDD)开始对第二节点（S）充电，第一节点（G）的电位由于第一电容（Cst）的耦合上升，所述基准电压（Vgs）基本保持不变，所述感应线(Sensing)上的电位因所述第二电容（Cp）的耦合而同步上升；进入探测阶段的第三阶段，在所述第三阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，打开第一开关（Scan），通过所述外部补偿电路探测基准电压Vgs并对所述像素内部驱动电路进行电压补偿。
进一步地，还包括：在所述第三阶段中，在t时间点探测不同像素在不同灰阶下感应线(Sensing)上的电位并记录初始值Vs0；循环所述探测阶段，在每个阶段的相同的时间点t测量感应线(Sensing)上的电位Vsi，i代表的是循环所述探测阶的次数，直至Vsi与初始值Vs0相同，如若探测的Vsi与所述Vs0不同，则通过所述外部补偿电路开始对所述像素内部驱动电路进行电压补偿。
进一步地，进入所述驱动发光阶段，在所述驱动发光阶段，所述写入信号(WR)提供高电位，所述扫描信号(Sen)提供低电位，所述数据信号(Data)提供高电位。
 有益效果
本发明提供一种像素混合补偿电路以及像素混合补偿方法，通过在第三薄膜晶体管（T3）的源极和漏极间加入了第四薄膜晶体管（T4）和第二电容（Cp），第四薄膜晶体管（T4）仅在探测阶段逐行开启（正常点亮关断防止不同行之间的相互影响），第二电容（Cp）用于将第二节点（S）电位的变化耦合反馈到感应线上，外部补偿电路根据感应线探测得到第二节点（S）的电位变化（即因阈值电压Vth和迁移率漂移引起的电流变化），可以直接反应电流的变化情况；并将需要调整的电压值发送至数据信号（Data），数据信号（Data）调整第一节点（G）的电压，保持第一薄膜晶体管（T1）的Vgs不变，进而完成对第一薄膜晶体管（T1）的补偿。
 附图说明
图1为本发明提供的像素混合补偿电路的电路图；
图2为本发明提供的像素混合补偿电路的时序图；
像素混合补偿电路100；外部补偿电路200；
模数转换器201；电压比较器202；控制模块203；
存储器204；数模转换器205。
 本发明的实施方式
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
如图1所示，本发明提供一种像素混合补偿电路100，包括呈阵列式排布的多个像素内部驱动电路、及通过一第一开关（Scan）电性连接每一像素内部驱动电路的外部补偿电路200。
每一像素内部驱动电路均包括：第一薄膜晶体管(T1)、第二薄膜晶体管(T2)、第三薄膜晶体管(T3)、第四薄膜晶体管(T4) 、第一电容(Cst)以及有机发光二极管(D1)。
所述第一薄膜晶体管(T1)的栅极电性连接第一节点(G)，所述第一薄膜晶体管(T1)的源极电性连接第二节点(S)，所述第一薄膜晶体管(T1)的漏极接入电源电压(VDD)。
所述第二薄膜晶体管(T2)的栅极接入写入信号(WR)，所述第二薄膜晶体管(T2)的源极接入数据信号(Data)，所述第二薄膜晶体管(T2)的漏极电性连接第一节点(G)。
所述第三薄膜晶体管(T3)，所述第三薄膜晶体管(T3)的栅极接入写入信号(WR)，所述第三薄膜晶体管(T3)的源极电性连接第一节点(G)，所述第三薄膜晶体管(T3)的漏极电性连接感应线(Sensing)。
所述第四薄膜晶体管(T4)的栅极接入扫描信号(Sen)，所述第四薄膜晶体管(T4)的源极电性连接第二电容（Cp），所述第四薄膜晶体管(T4)的漏极电性连接第二节点(S)。第四薄膜晶体管（T4）仅在探测阶段逐行开启（正常点亮关断防止不同行之间的相互影响），第二电容（Cp）用于将第二节点(S)的电位的变化耦合反馈到感应线（Sensing）上。
所述第一电容(Cst)一端电性连接第一节点(G)，另一端电性连接第二节点(S)。
所述第二电容（Cp）一端电性连接所述感应线(Sensing)。
所述有机发光二极管(D1)的阳极电性连接第二节点(S)，所述有机发光二极管(D1)的的阴极接地。
其中，所述感应线(Sensing)电性连接多个寄生电容，每个寄生电容接地，每个寄生电容相互并联；所述感应线(Sensing)电性通过一第二开关（Spre）接入一参考电压（Vref）。
所述外部补偿电路200用以检测所述第一节点与所述第二节点的基准电压Vgs与所述电源电压(VDD)是否相同，若不相同，则根据所述基准电压Vgs与所述电源电压(VDD)的差值，对输入至所述像素电路的数据信号进行校准，并将校准后的数据信号输入至所述像素电路。
所述第一薄膜晶体管 (T1)、第二薄膜晶体管(T2)、第三薄膜晶体管(T3)、及第四薄膜晶体管(T4)均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
所述外部补偿电路200包括：模数转换器201、电压比较器202、控制模块203、存储器204以及数模转换器205。
所述模数转换器201的输入端电性连接对应的所述列像素内部驱动电路中的感应线(Sensing)，其输出端电性连接电流比较器的输入端。
所述电压比较器202的输出端电性连接控制模块203的输入端。
所述控制模块203的输出端电性连接存储器204的输入端。
所述存储器204的输出端电性连接数模转换器205的输入端。
所述数模转换器205的输出端电性连接对应的所述列像素内部驱动电路中第二薄膜晶体管(T2)的源极。
所述写入信号(WR)以及扫描信号(Sen)通过外部时序控制器提供。
如图2所示，所述写入信号(WR)、所述扫描信号(Sen)、及所述数据信号(Data)相组合，先后对应于一探测阶段，所述探测阶段包括：一第一阶段、一第二阶段以及一第三阶段；
在所述第一阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均打开；
在所述第二阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)以及所述第三薄膜晶体管(T3)关闭，且所述参考电压（Vref）与所述感应线断开。
在所述第三阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位。
所述写入信号(WR)、所述扫描信号(Sen)、及所述数据信号(Data)相组合，先后对应于一探测阶段之后，还包括一驱动发光阶段。
在所述驱动发光阶段，所述写入信号(WR)提供高电位，所述扫描信号(Sen)提供低电位，所述数据信号(Data)提供高电位。
所述扫描信号(Sen)提供的高电位大于所述写入信号(WR)提供的高电位。
所述扫描信号(Sen)提供的高电位大于所述数据信号(Data)提供高电位。
本发明还提供一种像素混合补偿方法，包括如下步骤。
步骤S1）提供前文所述的像素混合补偿电路100。
步骤S2）进入探测阶段的第一阶段，在所述第一阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均打开，所述数据信号(Data)和所述参考电压（Vref）分别对第一节点（G）和第二节点（S）点写入初始电位。
步骤S3）进入探测阶段的第二阶段，在所述第二阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)以及所述第三薄膜晶体管(T3)关闭，且所述参考电压Vref与所述感应线断开，所述电源电压(VDD)开始对第二节点（S）充电，第一节点（G）的电位由于第一电容（Cst）的耦合上升，所述基准电压（Vgs）基本保持不变，所述感应线(Sensing)上的电位因所述第二电容（Cp）的耦合而同步上升。
步骤S4）进入探测阶段的第三阶段，在所述第三阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，打开第一开关（Scan），通过所述外部补偿电路200探测基准电压Vgs并对所述像素驱动电路进行电压补偿。
探测感应线（Sensing）上的电位（该时间点应处于第二节点（S）电位开始饱和之前），设该点与写入信号（WR）关断时间的差为δt，探测到的电压为V0，保证在时间t内Vgs基本保持不变，即流过T1的电流基本保持不变设为I0，则根据电容充电的原理有：t * I0=（V0-Vref）* C，即对于固定的面板而言，C为常数，若固定t则（V0-Vref）与I0正比，当Vref取0V时，V0和I0成正比，即可以通过探测到的V0值直接反应I0的变化。
在所述第三阶段中，在t时间点探测不同像素在不同灰阶下感应线(Sensing)上的电位并记录初始值Vs0，即第二节点（S）的电位。
步骤S5）循环所述探测阶段，在每个阶段的相同的时间点t测量感应线(Sensing)上的电位Vsi，i代表的是循环所述探测阶的次数，直至Vsi与初始值Vs0相同，如若探测的Vsi与所述Vs0不同，则通过所述外部补偿电路200开始对所述像素内部驱动电路进行电压补偿。
当探测值Vsi与初始值Vs0一致时，说明薄膜晶体管的电性以及OLED的阳极电压未发生漂移，相同电压下电流无变化，数据信号(Data)电压保持不变。
当探测值Vsi与初始值Vs0不一致时，以数据信号(Data)的最小步长调整电压，按照探测步骤调整数据信号(Data)的电压，直到探测值Vsi等于初始值Vs0，记录此时的数据信号(Data)电压Vdata为补偿后的电压值（如图2所示，Data电压信号的两次调整，即对第一节点（G）进行补偿调整，进而使得整个Vgs电压可以稳定），假设调整Vdata过程中，无法得到与初始值Vs0完全一致的探测值Vsi，则取最接近值作为数据信号（Date）的电压值）。
本方法可以一次完成TFT电性漂移的探测与补偿，且由于探测可以在短时间内快速完成，因此可以在开关机时探测补偿，亦可以在面板的使用过程中实时的侦测补偿。
在探测的过程中，假设Cp以及sensing线上的这些寄生电容（假设第二电容（Cp）和寄生电容的和为C）。
步骤S6）进入所述驱动发光阶段，在所述驱动发光阶段，所述写入信号(WR)提供高电位，所述扫描信号(Sen)提供低电位，所述数据信号(Data)提供高电位。
根据本发明提供的像素混合补偿方法，以及以图2作为时序控制，提供一数据实施例，该数据实施例探测一实施例中像素内部驱动电路的电性参数。
表1 不同薄膜晶体管下探测所得的电性参数
δVth(V) 迁移率 VADC（V） Vdata（V） Ioled (nA) 补偿前 Ioled (nA) 补偿后 电流变异量 补偿前 电流变异量 补偿后
0 U0 5.813 5 378.42      
1.5 U0 5.818 6.576 52.67 380.5 75.56% 0.27%
-1.5 U0 5.817 3.48 994.2 375.4 44.86% 0.40%
0 1.5*U0 5.819 4.66 523.74 393.2 16.11% 1.92%
0 0.5*U0 5.819 5.833 208 372.45 29.06% 0.80%
1.5 1.5*U0 5.814 6.206 73.7 385.43 67.40% 0.92%
-1.5 0.5*U0 5.813 4.295 559.8 379.16 19.33% 0.10%
按照图2所示的时序，分别探测了不同薄膜晶体管Vth和迁移率下所需矫正的数据信号（data）电压和补偿前后的电流大小。薄膜晶体管阈值电压Vth相当于图1电路图的第一节点（G）以及第二节点（S）的电压Vgs。
初始时假设TFT的迁移率为U0，设置data电压为5V，在t时间点探测感应线上的电位，其大小如表中的所示为VADC=5.813V，之后按照所述像素混合补偿方法的步骤对感应线上的电位进行探测，直到探测到的电压和初始电压一致，记录此时的数据电压为补偿后的数据信号（data）电压值。
从电流的结果可以看出仅Vth变化时（±1.5V），不补偿时电流变异在44%以上，补偿后电流变异量在0.5%以下；仅迁移率变化时（变化0.5倍或者1.5倍），不补偿时电流变异量在16%以上，补偿后在2%以下；当Vth和迁移率同时变化时，不补偿时。
本发明提供一种像素混合补偿电路100以及像素混合补偿方法，通过在第三薄膜晶体管（T3）的源极和漏极间加入了第四薄膜晶体管（T4）和第二电容（Cp），第四薄膜晶体管（T4）仅在探测阶段逐行开启（正常点亮关断防止不同行之间的相互影响），第二电容（Cp）用于将第二节点（S）电位的变化耦合反馈到感应线上，外部补偿电路200根据感应线探测得到第二节点（S）的电位变化（即因阈值电压Vth和迁移率漂移引起的电流变化），可以直接反应电流的变化情况；并将需要调整的电压值发送至数据信号（Data），数据信号（Data）调整第一节点（G）的电压，保持第一薄膜晶体管（T1）的Vgs不变，进而完成对第一薄膜晶体管（T1）的补偿。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (10)

  1. 一种像素混合补偿电路，其中，包括呈阵列式排布的多个像素内部驱动电路、及通过一第一开关（Scan）电性连接每一像素内部驱动电路的外部补偿电路；
    每一像素内部驱动电路均包括：
    第一薄膜晶体管(T1)，所述第一薄膜晶体管的栅极电性连接第一节点(G)，所述第一薄膜晶体管的源极电性连接第二节点(S)，所述第一薄膜晶体管的漏极接入电源电压(VDD)；
    第二薄膜晶体管(T2)，所述第二薄膜晶体管的栅极接入写入信号(WR)，所述第二薄膜晶体管的源极接入数据信号(Data)，所述第二薄膜晶体管的漏极电性连接第一节点(G)；
    第三薄膜晶体管(T3)，所述第三薄膜晶体管的栅极接入写入信号(WR)，所述第三薄膜晶体管的源极电性连接第一节点(G)，所述第三薄膜晶体管的漏极电性连接感应线(Sensing)；
    第四薄膜晶体管(T4)，所述第四薄膜晶体管的栅极接入扫描信号(Sen)，所述第四薄膜晶体管的源极电性连接第二电容（Cp），所述第四薄膜晶体管的漏极电性连接所述第二节点(S)；
    第一电容(Cst)，所述第一电容(Cst)的一端电性连接所述第一节点(G)，另一端电性连接所述第二节点(S)；
    第二电容（Cp），所述第二电容（Cp）的一端电性连接所述感应线(Sensing)；
    有机发光二极管(D1)，所述有机发光二极管(D1)的阳极电性连接所述第二节点(S)，所述有机发光二极管(D1)的阴极接地；
    其中，所述感应线(Sensing)电性连接多个寄生电容，每个寄生电容接地，每个寄生电容相互并联，所述感应线(Sensing)电性通过一第二开关（Spre）接入一参考电压（Vref）；
    所述外部补偿电路用以检测所述第一节点与所述第二节点的基准电压Vgs与所述电源电压(VDD)是否相同，若不相同，则根据所述基准电压Vgs与所述电源电压(VDD)的差值，对输入至所述像素电路的数据信号进行校准，并将校准后的数据信号输入至所述像素电路。
  2. 根据权利要求1所述的像素混合补偿电路，其中，
    所述外部补偿电路包括：模数转换器、电压比较器、控制模块、存储器以及数模转换器；
    所述模数转换器，其输入端电性连接对应的所述像素内部驱动电路中的所述感应线(Sensing)，其输出端电性连接电压比较器的输入端；
    所述电压比较器，其输出端电性连接所述控制模块的输入端；
    所述控制模块，其输出端电性连接所述存储器的输入端；
    所述存储器，其输出端电性连接所述数模转换器的输入端；
    所述数模转换器，其输出端电性连接对应的所述像素内部驱动电路中第二薄膜晶体管(T2)的源极。
  3. 根据权利要求1所述的像素混合补偿电路，其中，
    所述第一薄膜晶体管 (T1)、所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均为低温多晶硅薄膜晶体管、氧化物半导体薄膜晶体管、或非晶硅薄膜晶体管。
  4. 根据权利要求1所述的像素混合补偿电路，其中，
    所述写入信号(WR)以及所述扫描信号(Sen)通过外部时序控制器提供。
  5. 根据权利要求2所述的像素混合补偿电路，其中，
    所述写入信号(WR)、所述扫描信号(Sen)、及所述数据信号(Data)相组合，先后对应于一探测阶段，所述探测阶段包括：一第一阶段、一第二阶段以及一第三阶段；
    在所述第一阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均打开；
    在所述第二阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)以及所述第三薄膜晶体管(T3)关闭，且所述参考电压（Vref）与所述感应线断开；
    在所述第三阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位。
  6. 根据权利要求5所述的像素混合补偿电路，其中，
    所述写入信号(WR)、所述扫描信号(Sen)、及所述数据信号(Data)相组合，先后对应于一探测阶段之后，还包括一驱动发光阶段；
    在所述驱动发光阶段，所述写入信号(WR)提供高电位，所述扫描信号(Sen)提供低电位，所述数据信号(Data)提供高电位。
  7. 根据权利要求5所述的像素混合补偿电路，其中，
    所述扫描信号(Sen)提供的高电位大于所述写入信号(WR)提供的高电位；
    所述扫描信号(Sen)提供的高电位大于所述数据信号(Data)提供高电位。
  8. 一种像素混合补偿方法，其中，包括如下步骤：
    提供一像素混合补偿电路，所述像素混合补偿电路包括呈阵列式排布的多个像素内部驱动电路、及通过一第一开关（Scan）电性连接每一像素内部驱动电路的外部补偿电路；每一像素内部驱动电路均包括：第一薄膜晶体管(T1)，所述第一薄膜晶体管的栅极电性连接第一节点(G)，所述第一薄膜晶体管的源极电性连接第二节点(S)，所述第一薄膜晶体管的漏极接入电源电压(VDD)；第二薄膜晶体管(T2)，所述第二薄膜晶体管的栅极接入写入信号(WR)，所述第二薄膜晶体管的源极接入数据信号(Data)，所述第二薄膜晶体管的漏极电性连接第一节点(G)；第三薄膜晶体管(T3)，所述第三薄膜晶体管的栅极接入写入信号(WR)，所述第三薄膜晶体管的源极电性连接第一节点(G)，所述第三薄膜晶体管的漏极电性连接感应线(Sensing)；第四薄膜晶体管(T4)，所述第四薄膜晶体管的栅极接入扫描信号(Sen)，所述第四薄膜晶体管的源极电性连接第二电容（Cp），所述第四薄膜晶体管的漏极电性连接所述第二节点(S)；第一电容(Cst)，所述第一电容(Cst)的一端电性连接所述第一节点(G)，另一端电性连接所述第二节点(S)；第二电容（Cp），所述第二电容（Cp）的一端电性连接所述感应线(Sensing)；有机发光二极管(D1)，所述有机发光二极管(D1)的阳极电性连接所述第二节点(S)，所述有机发光二极管(D1)的阴极接地；其中，所述感应线(Sensing)电性连接多个寄生电容，每个寄生电容接地，每个寄生电容相互并联，所述感应线(Sensing)电性通过一第二开关（Spre）接入一参考电压（Vref）；所述外部补偿电路用以检测所述第一节点与所述第二节点的基准电压Vgs与所述电源电压(VDD)是否相同，若不相同，则根据所述基准电压Vgs与所述电源电压(VDD)的差值，对输入至所述像素电路的数据信号进行校准，并将校准后的数据信号输入至所述像素电路；
    进入探测阶段的第一阶段，在所述第一阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)、所述第三薄膜晶体管(T3)、及所述第四薄膜晶体管(T4)均打开，所述数据信号(Data)和所述参考电压（Vref）分别对第一节点（G）和第二节点（S）点写入初始电位；
    进入探测阶段的第二阶段，在所述第二阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，所述第二薄膜晶体管(T2)以及所述第三薄膜晶体管(T3)关闭，且所述参考电压Vref与所述感应线断开，所述电源电压(VDD)开始对第二节点（S）充电，第一节点（G）的电位由于第一电容（Cst）的耦合上升，所述基准电压（Vgs）基本保持不变，所述感应线(Sensing)上的电位因所述第二电容（Cp）的耦合而同步上升；
    进入探测阶段的第三阶段，在所述第三阶段，所述写入信号(WR)提供低电位，所述扫描信号(Sen)提供高电位，所述数据信号(Data)提供高电位，打开第一开关（Scan），通过所述外部补偿电路探测基准电压Vgs并对所述像素内部驱动电路进行电压补偿。
  9. 根据权利要求8所述的像素混合补偿方法，其中，还包括：
    在所述第三阶段中，在t时间点探测不同像素在不同灰阶下感应线(Sensing)上的电位并记录初始值Vs0；
    循环所述探测阶段，在每个阶段的相同的时间点t测量感应线(Sensing)上的电位Vsi，i代表的是循环所述探测阶的次数，直至Vsi与初始值Vs0相同，如若探测的Vsi与所述Vs0不同，则通过所述外部补偿电路开始对所述像素内部驱动电路进行电压补偿。
  10.     根据权利要求9所述的像素混合补偿方法，其中，
    进入所述驱动发光阶段，在所述驱动发光阶段，所述写入信号(WR)提供高电位，所述扫描信号(Sen)提供低电位，所述数据信号(Data)提供高电位。
PCT/CN2019/129274 2019-12-17 2019-12-27 像素混合补偿电路及像素混合补偿方法 WO2021120315A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/641,238 US11348526B2 (en) 2019-12-17 2019-12-27 Pixel mixed compensation circuit and pixel mixed compensation method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201911304678.8A CN111063302A (zh) 2019-12-17 2019-12-17 像素混合补偿电路及像素混合补偿方法
CN201911304678.8 2019-12-17

Publications (1)

Publication Number Publication Date
WO2021120315A1 true WO2021120315A1 (zh) 2021-06-24

Family

ID=70302085

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/129274 WO2021120315A1 (zh) 2019-12-17 2019-12-27 像素混合补偿电路及像素混合补偿方法

Country Status (3)

Country Link
US (1) US11348526B2 (zh)
CN (1) CN111063302A (zh)
WO (1) WO2021120315A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114093300B (zh) * 2020-07-30 2023-04-18 京东方科技集团股份有限公司 像素电路及其驱动方法、显示基板、显示装置
CN112365848A (zh) * 2020-12-02 2021-02-12 深圳市华星光电半导体显示技术有限公司 像素电路及显示面板
CN112331144B (zh) * 2020-12-03 2022-04-01 深圳市华星光电半导体显示技术有限公司 一种显示面板的补偿方法、补偿装置和显示装置
CN112863444B (zh) * 2021-01-13 2022-05-03 深圳市华星光电半导体显示技术有限公司 驱动电路的补偿电压计算方法
CN112885302B (zh) * 2021-01-20 2022-06-07 合肥京东方卓印科技有限公司 一种像素电路及其驱动方法、显示基板和显示装置
CN113920938B (zh) * 2021-10-27 2022-08-19 锐芯微电子股份有限公司 校准装置、显示芯片和显示器
CN114783373B (zh) * 2022-04-11 2023-06-27 深圳市华星光电半导体显示技术有限公司 像素驱动电路及其驱动方法、显示面板
CN114743501B (zh) * 2022-06-09 2022-08-23 惠科股份有限公司 补偿电路、控制芯片和显示装置

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105096820A (zh) * 2014-05-12 2015-11-25 乐金显示有限公司 有机发光二极管显示装置及其驱动方法
CN105702206A (zh) * 2016-03-04 2016-06-22 北京大学深圳研究生院 一种像素矩阵的***补偿***及其方法、显示***
CN106097969A (zh) * 2016-06-17 2016-11-09 京东方科技集团股份有限公司 子像素电路的校准装置、源极驱动器及数据电压补偿方法
KR20170022368A (ko) * 2015-08-20 2017-03-02 엘지디스플레이 주식회사 유기발광 표시장치와 그 구동방법
CN106910463A (zh) * 2017-04-28 2017-06-30 深圳市华星光电技术有限公司 一种amoled驱动电路及显示装置
CN107507574A (zh) * 2017-08-31 2017-12-22 京东方科技集团股份有限公司 Oled显示面板及其补偿方法和装置、显示装置
US20180174518A1 (en) * 2016-12-19 2018-06-21 Lg Display Co., Ltd. Electroluminescent display and method of compensating for electrical characteristics of electroluminescent display

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101938880B1 (ko) * 2011-11-18 2019-01-16 엘지디스플레이 주식회사 유기발광다이오드 표시장치
KR101969436B1 (ko) * 2012-12-20 2019-04-16 엘지디스플레이 주식회사 유기 발광 디스플레이 장치의 구동 방법
KR101970574B1 (ko) * 2012-12-28 2019-08-27 엘지디스플레이 주식회사 Oled 표시 장치
KR102053444B1 (ko) * 2013-11-06 2019-12-06 엘지디스플레이 주식회사 유기발광 표시장치와 그의 이동도 보상방법
KR101577909B1 (ko) * 2014-09-05 2015-12-16 엘지디스플레이 주식회사 유기발광 표시장치의 열화 센싱 방법
TWI563489B (en) * 2015-02-24 2016-12-21 Au Optronics Corp Display and operation method thereof
KR102406346B1 (ko) * 2016-04-26 2022-06-10 주식회사 엘엑스세미콘 화소센싱장치 및 패널구동장치
KR102475589B1 (ko) * 2016-04-29 2022-12-07 엘지디스플레이 주식회사 플렉서블 유기발광 표시장치
KR102664308B1 (ko) * 2016-08-31 2024-05-09 엘지디스플레이 주식회사 유기전계발광표시장치 및 이의 구동방법
KR102597608B1 (ko) * 2016-09-30 2023-11-01 엘지디스플레이 주식회사 유기발광표시장치와 그의 구동방법
CN106504707B (zh) * 2016-10-14 2018-06-01 深圳市华星光电技术有限公司 Oled像素混合补偿电路及混合补偿方法
KR102630608B1 (ko) * 2016-12-21 2024-01-26 엘지디스플레이 주식회사 유기 발광 표시 장치와 그의 구동 방법
KR102565753B1 (ko) * 2016-12-28 2023-08-11 엘지디스플레이 주식회사 전계 발광 표시장치와 그 구동 장치
CN107016964B (zh) * 2017-04-25 2020-07-07 京东方科技集团股份有限公司 像素电路、其驱动方法和显示装置
CN107086025B (zh) * 2017-06-30 2019-12-27 京东方科技集团股份有限公司 显示面板、显示装置及显示面板的控制方法
CN207217081U (zh) * 2017-09-22 2018-04-10 京东方科技集团股份有限公司 像素电路、显示基板和显示装置
CN107516484B (zh) * 2017-10-18 2019-10-11 深圳市华星光电半导体显示技术有限公司 Amoled外部电学补偿侦测方法
CN109920373B (zh) * 2017-12-13 2021-05-18 京东方科技集团股份有限公司 电路驱动补偿方法、电路驱动方法及装置、显示装置
US10861389B2 (en) * 2018-08-08 2020-12-08 Apple Inc. Methods and apparatus for mitigating hysteresis impact on current sensing accuracy for an electronic display
CN110520923B (zh) * 2018-09-20 2022-05-13 京东方科技集团股份有限公司 具有时间共享信号线的像素电路、像素补偿方法和显示设备
KR20200046213A (ko) * 2018-10-23 2020-05-07 삼성디스플레이 주식회사 표시 장치 및 그 제조 방법
KR102619313B1 (ko) * 2018-12-17 2023-12-29 엘지디스플레이 주식회사 발광표시장치 및 이의 구동방법
KR102573691B1 (ko) * 2018-12-19 2023-09-01 엘지디스플레이 주식회사 발광표시장치 및 이의 구동방법
CN109545145B (zh) * 2019-01-02 2020-07-28 京东方科技集团股份有限公司 像素电路及其驱动方法、显示装置
CN110428779B (zh) * 2019-08-15 2021-01-22 京东方科技集团股份有限公司 像素电路、显示面板和显示设备
KR20210024274A (ko) * 2019-08-21 2021-03-05 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그의 구동 방법
CN110827763B (zh) * 2019-11-07 2021-07-06 深圳市华星光电半导体显示技术有限公司 像素电路及其驱动方法、显示装置
EP4068255A4 (en) * 2019-11-29 2022-11-23 BOE Technology Group Co., Ltd. DISPLAY SUBSTRATE AND DISPLAY APPARATUS
US11217656B2 (en) * 2019-11-29 2022-01-04 Hefei Xinsheng Optoelectronics Technology Co., Ltd. Display substrate and manufacturing method thereof, display device
KR20210092863A (ko) * 2020-01-16 2021-07-27 삼성디스플레이 주식회사 정전기 방전 보호 회로 및 이를 포함하는 유기 발광 표시 장치

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105096820A (zh) * 2014-05-12 2015-11-25 乐金显示有限公司 有机发光二极管显示装置及其驱动方法
KR20170022368A (ko) * 2015-08-20 2017-03-02 엘지디스플레이 주식회사 유기발광 표시장치와 그 구동방법
CN105702206A (zh) * 2016-03-04 2016-06-22 北京大学深圳研究生院 一种像素矩阵的***补偿***及其方法、显示***
CN106097969A (zh) * 2016-06-17 2016-11-09 京东方科技集团股份有限公司 子像素电路的校准装置、源极驱动器及数据电压补偿方法
US20180174518A1 (en) * 2016-12-19 2018-06-21 Lg Display Co., Ltd. Electroluminescent display and method of compensating for electrical characteristics of electroluminescent display
CN106910463A (zh) * 2017-04-28 2017-06-30 深圳市华星光电技术有限公司 一种amoled驱动电路及显示装置
CN107507574A (zh) * 2017-08-31 2017-12-22 京东方科技集团股份有限公司 Oled显示面板及其补偿方法和装置、显示装置

Also Published As

Publication number Publication date
US20210390908A1 (en) 2021-12-16
US11348526B2 (en) 2022-05-31
CN111063302A (zh) 2020-04-24

Similar Documents

Publication Publication Date Title
WO2021120315A1 (zh) 像素混合补偿电路及像素混合补偿方法
TWI660337B (zh) 電激發光顯示裝置及其驅動方法
WO2018068393A1 (zh) Oled像素混合补偿电路及混合补偿方法
WO2016155053A1 (zh) Amoled像素驱动电路及像素驱动方法
WO2016145693A1 (zh) Amoled像素驱动电路及像素驱动方法
WO2018045660A1 (zh) Amoled像素驱动电路及像素驱动方法
WO2010001590A1 (ja) 表示装置及びその制御方法
WO2016119304A1 (zh) Amoled像素驱动电路及像素驱动方法
WO2016155177A1 (zh) 一种检测电路、检测方法和驱动***
WO2016145692A1 (zh) Amoled像素驱动电路及像素驱动方法
WO2018072299A1 (zh) Amoled像素驱动电路及驱动方法
WO2017020360A1 (zh) Amoled像素驱动电路及像素驱动方法
WO2018045659A1 (zh) Amoled像素驱动电路及像素驱动方法
WO2019037300A1 (zh) Amoled像素驱动电路
WO2021088117A1 (zh) 像素电路及其驱动方法、显示装置
WO2019071735A1 (zh) 一种应用于显示面板的温度补偿电路、方法及显示面板
WO2017161650A1 (zh) 感测amoled像素驱动特性的***及amoled显示装置
US11749143B2 (en) Pixel circuit, display, and method
WO2018094954A1 (zh) 一种像素电路及其驱动方法、显示装置
WO2016119305A1 (zh) Amoled像素驱动电路及像素驱动方法
JP2020503553A (ja) Ｏｌｅｄ駆動薄膜トランジスタの閾値電圧検出方法
WO2019242147A1 (zh) Amoled像素驱动电路及驱动方法
WO2021203479A1 (zh) 像素驱动电路和显示面板
TWI667645B (zh) 畫素電路及其驅動方法、顯示裝置
KR20150079247A (ko) 유기발광표시장치 및 그 구동방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19956771

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19956771

Country of ref document: EP

Kind code of ref document: A1