WO2021115147A1 - 缓冲装置、芯片及电子设备 - Google Patents

缓冲装置、芯片及电子设备 Download PDF

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Publication number
WO2021115147A1
WO2021115147A1 PCT/CN2020/132737 CN2020132737W WO2021115147A1 WO 2021115147 A1 WO2021115147 A1 WO 2021115147A1 CN 2020132737 W CN2020132737 W CN 2020132737W WO 2021115147 A1 WO2021115147 A1 WO 2021115147A1
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Prior art keywords
resistor
pmos
nmos
electrically connected
voltage
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PCT/CN2020/132737
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English (en)
French (fr)
Inventor
杨伟
樊磊
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北京集创北方科技股份有限公司
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Priority to JP2022527885A priority Critical patent/JP7520975B2/ja
Priority to KR1020227021188A priority patent/KR102660177B1/ko
Publication of WO2021115147A1 publication Critical patent/WO2021115147A1/zh
Priority to US17/730,157 priority patent/US11936375B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
    • G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses

Definitions

  • the present disclosure relates to the field of integrated circuit technology, and in particular to a buffer device, a chip, and electronic equipment.
  • the technical problem to be solved by the present disclosure is how to reduce the voltage variation range of the switching point of the buffer device.
  • a buffer device including:
  • the voltage adjustment module includes a first P-type metal oxide semiconductor field effect transistor PMOS.
  • the voltage adjustment module is used to receive an input voltage and adjust the input voltage by using the threshold voltage of the first PMOS to output a driving voltage. ;
  • the buffer module is electrically connected to the voltage adjustment module, and is used for receiving an input signal, buffering the input signal under the driving voltage, and outputting the buffered signal.
  • the voltage adjustment module further includes a first current source, a first N-type metal oxide semiconductor field effect transistor NMOS, a first resistor, a second resistor, a third resistor, The fourth resistor and the first capacitor, where:
  • the anode of the first current source is electrically connected to the first end of the third resistor for receiving the input voltage
  • the cathode of the first current source is electrically connected to the source of the first PMOS, the The gate of the first NMOS and the first end of the first capacitor, wherein the input voltage is a power supply voltage
  • the gate of the first PMOS is electrically connected to the drain of the first PMOS and the first end of the first resistor, and the second end of the first resistor is electrically connected to the first end of the second resistor. end,
  • the second end of the third resistor is electrically connected to the drain of the first NMOS,
  • the source of the first NMOS is electrically connected to the first end of the fourth resistor and the buffer module for outputting the driving voltage
  • the second end of the second resistor, the second end of the first capacitor, and the second end of the fourth resistor are grounded.
  • the voltage adjustment module further includes a second current source, a second NMOS, a fifth resistor, a sixth resistor, a seventh resistor, and a second capacitor, where:
  • the anode of the second current source is electrically connected to the first end of the sixth resistor for receiving a power supply voltage
  • the cathode of the second current source is electrically connected to the source of the first PMOS and the second NMOS.
  • the gate of the first PMOS is used to receive the input voltage, and the drain of the first PMOS is electrically connected to the first end of the fifth resistor,
  • the second end of the sixth resistor is electrically connected to the drain of the second NMOS,
  • the source of the second NMOS is electrically connected to the first end of the seventh resistor and the buffer module for outputting the driving voltage
  • the second end of the fifth resistor, the second end of the second capacitor, and the second end of the seventh resistor are grounded.
  • the voltage adjustment module further includes a first operational amplifier, an eighth resistor, a ninth resistor, and a tenth resistor, where:
  • the forward input terminal of the first operational amplifier is used to receive the input voltage, and the output terminal of the first operational amplifier is electrically connected to the source of the first PMOS and the buffer module for outputting the Drive voltage,
  • the drain of the first PMOS is electrically connected to the gate of the first PMOS and the first end of the eighth resistor, and the second end of the eighth resistor is electrically connected to the first end of the ninth resistor.
  • the second end of the ninth resistor is electrically connected to the first end of the tenth resistor, and the second end of the tenth resistor is grounded,
  • the negative input end of the first operational amplifier is electrically connected to the second end of the eighth resistor and the first end of the ninth resistor.
  • the voltage adjustment module further includes a second operational amplifier, a third operational amplifier, a second PMOS, a third NMOS, a fourth NMOS, an eleventh resistor, and a twelfth operational amplifier.
  • the resistor, the thirteenth resistor, and the third current source of which:
  • the source of the first PMOS is electrically connected to the first end of the eleventh resistor for receiving a power supply voltage, and the drain of the first PMOS is electrically connected to the anode of the third current source, the The gate of the first PMOS and the forward input terminal of the second operational amplifier,
  • the negative input terminal of the second operational amplifier is electrically connected to the second terminal of the eleventh resistor and the source of the second PMOS, and the output terminal of the second operational amplifier is electrically connected to the second The gate of the PMOS,
  • the drain of the second PMOS is electrically connected to the drain of the third NMOS, the gate of the third NMOS, and the gate of the fourth NMOS,
  • the drain of the fourth NMOS is electrically connected to the negative input end of the third operational amplifier, the second end of the twelfth resistor, and the first end of the thirteenth resistor,
  • the forward input terminal of the third operational amplifier is used for receiving the input voltage, and the output terminal of the third operational amplifier is electrically connected to the first terminal of the twelfth resistor and the buffer module for outputting The driving voltage,
  • the cathode of the third current source, the source of the third NMOS, the source of the fourth NMOS, and the second end of the thirteenth resistor are grounded.
  • the buffer module includes a third PMOS, a fourth PMOS, a fifth PMOS, a fifth NMOS, a sixth NMOS, a seventh NMOS, and an inverter, where:
  • the source of the third PMOS is electrically connected to the source of the fifth PMOS for inputting a power supply voltage
  • the gate of the third PMOS is electrically connected to the gate of the fourth PMOS, the gate of the fifth NMOS, and the gate of the sixth NMOS for receiving the input signal,
  • the drain of the third PMOS is electrically connected to the drain of the fifth PMOS and the source of the fourth PMOS, and the drain of the fourth PMOS is electrically connected to the input terminal of the inverter and the source of the fourth PMOS.
  • the drain of the fifth NMOS, the source of the fifth NMOS is electrically connected to the drain of the sixth NMOS and the drain of the seventh NMOS, the source of the sixth NMOS, the seventh The source of the NMOS is grounded,
  • the output terminal of the inverter is electrically connected to the gate of the fifth PMOS and the gate of the seventh NMOS for outputting a buffered signal.
  • the device can be applied to include analog-to-digital conversion circuits, power-on reset circuits, ultrasonic sensor circuits, electronic switch circuits, signal switching control circuits, IGBT drive control circuits, and current thresholds.
  • a chip including:
  • the buffering device The buffering device.
  • an electronic device including:
  • the chip The chip.
  • the voltage adjustment module in the buffer device proposed in the embodiment of the present disclosure can adjust the input voltage by using the threshold voltage of the first PMOS, and the obtained driving voltage can compensate the process corner of the buffer module, so that the flip point voltage of the buffer module The scope becomes smaller to meet the technological requirements.
  • Fig. 1 shows a block diagram of a buffer device according to an embodiment of the present disclosure.
  • Fig. 2 shows a schematic diagram of a buffer module according to an embodiment of the present disclosure.
  • Fig. 3 shows a schematic diagram of a voltage adjustment module according to an embodiment of the present disclosure.
  • Fig. 4 shows a schematic diagram of a voltage adjustment module according to an embodiment of the present disclosure.
  • Fig. 5 shows a schematic diagram of a voltage adjustment module according to an embodiment of the present disclosure.
  • Fig. 6 shows a schematic diagram of a voltage adjustment module according to an embodiment of the present disclosure.
  • FIG. 1 shows a block diagram of a buffer device according to an embodiment of the present disclosure.
  • the device includes:
  • the voltage adjustment module 10 includes a first P-type metal oxide semiconductor field effect transistor PMOS (not shown in FIG. 1).
  • the voltage adjustment module 10 is used to receive an input voltage and use the threshold voltage of the first PMOS to The input voltage is adjusted and the drive voltage is output;
  • the buffer module 20 is electrically connected to the voltage adjustment module 10, and is used for receiving an input signal, buffering the input signal under the driving voltage, and outputting the buffered signal.
  • the voltage adjustment module in the buffer device proposed in the embodiment of the present disclosure can adjust the input voltage by using the threshold voltage of the first PMOS, and the obtained driving voltage can compensate the process corner of the buffer module, so that the flip point voltage of the buffer module The scope becomes smaller to meet the technological requirements.
  • the apparatus in the embodiments of the present disclosure may be set in an electronic device, and the electronic device may also be referred to as a mobile device.
  • the mobile device may refer to various forms of access mobile devices, user units, user equipment, user stations, mobile stations, and mobile devices.
  • Station Mobile Station, MS
  • remote station remote mobile equipment, mobile equipment, user mobile equipment, terminal equipment (terminal equipment), wireless communication equipment, user agent or user device.
  • the user equipment can also be a cellular phone, a cordless phone, a Session Initiation Protocol (SIP) phone, a wireless local loop (Wireless Local Loop, WLL) station, a personal digital processing (Personal Digital Assistant, PDA), with wireless communication Functional handheld devices, computing devices, or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, user equipment in 5G networks, or mobile in the future evolution of the Public Land Mobile Network (PLMN) Devices, etc., are not limited in the embodiments of the present disclosure.
  • SIP Session Initiation Protocol
  • WLL Wireless Local Loop
  • PDA Personal Digital Assistant
  • the buffer device of the embodiment of the present disclosure can be applied to any device/equipment that has digital signal input and needs to be buffered, including but not limited to analog-to-digital conversion circuit, power-on reset circuit, ultrasonic sensor circuit, electronic switch circuit, signal An electronic circuit device formed by any one of a switching control circuit, an IGBT drive control circuit, a current threshold detection circuit, a voltage threshold detection circuit, and a photoelectric sensor circuit.
  • the buffer module 20 may include multiple implementation manners, and a possible implementation manner of the buffer module 20 is exemplarily described below.
  • FIG. 2 shows a schematic diagram of a buffer module according to an embodiment of the present disclosure.
  • the buffer module 20 may include a third PMOS Mp3, a fourth PMOS Mp4, a fifth PMOS Mp5, a fifth NMOS Mn5, a sixth NMOS Mn6, and a seventh NMOS.
  • Mn7 inverter Not, where:
  • the source of the third PMOS Mp3 is electrically connected to the source of the fifth PMOS Mp5 for inputting the power supply voltage VDD,
  • the gate of the third PMOS Mp3 is electrically connected to the gate of the fourth PMOS Mp4, the gate of the fifth NMOS Mn5, and the gate of the sixth NMOS Mn6, for receiving the input signal Vin ,
  • the drain of the third PMOS Mp3 is electrically connected to the drain of the fifth PMOS Mp5 and the source of the fourth PMOS Mp4, and the drain of the fourth PMOS Mp4 is electrically connected to the inverter Not
  • the input terminal of the fifth NMOS Mn5 the source of the fifth NMOS Mn5 is electrically connected to the drain of the sixth NMOS Mn6 and the drain of the seventh NMOS Mn7, the sixth The source of the NMOS Mn6 and the source of the seventh NMOS Mn7 are grounded,
  • the output terminal of the inverter Not is electrically connected to the gate of the fifth PMOS Mp5 and the gate of the seventh NMOS Mn7 for outputting the buffered signal Vout.
  • the fifth PMOS Mp5 and the seventh NMOS Mn7 can realize a certain hysteresis between the logic high level and the logic low level through feedback, so as to prevent glitches caused by repeated high and low level switching near the flip point voltage.
  • buffer module 20 is exemplary, and those skilled in the art may implement the buffer module 20 in other ways.
  • the third PMOS Mp3 and the fourth PMOS Mp4 are the same (for the convenience of description, PMOS Mp will be used for description)
  • the fifth NMOS Mn5 and the sixth NMOS Mn6 are the same (for the convenience of description, NMOS Mn will be used for description)
  • C OX represents the gate capacitance per unit area of the transistor
  • W P and W N represent the width of PMOS and NMOS respectively
  • L P and L N represent the length of PMOS and NMOS respectively
  • ⁇ P and ⁇ N represent the width of PMOS and NMOS respectively.
  • the mobility, at the voltage reversal point can be based on
  • the inversion point voltage V INV of the buffer module 20 is related to the power supply voltage VDD, the size of the NMOS and PMOS, and the threshold voltage of the NMOS and PMOS.
  • ⁇ can represent a preset value
  • SNFP is the maximum value among multiple process angles, which is the worst process angle with logic high, which determines whether the buffer module can achieve a minimum logic high of 1.2 or 1.1 or 1.05;
  • FNSP is the highest value among multiple process angles.
  • the minimum value is the worst process angle of logic low, which determines whether the buffer module can achieve a logic low maximum of 0.6V.
  • the size of the power supply voltage VDD is 2.5V ⁇ 5.5V. If the power supply voltage VDD is used to directly supply power to the buffer module 20, due to the flip point voltage of the digital buffer 20 and the power supply voltage VDD, the size of NMOS and PMOS, and the size of the NMOS Related to the threshold voltage of the PMOS, the maximum value of the logic low voltage of the buffer module is 0.6V, and the minimum value of the logic high voltage is 2.0V.
  • the voltage range of the flip point is relatively large (the difference between logic high and logic low is greater than 1V), if you want to reduce the range of the flip point voltage, for example, realize that the logic is higher than the logic low and the difference is less than or equal to 0.6V (for example, the maximum value of the logic low is 0.6, and the minimum value of the logic high is 1.2 or 1.1 or 1.05), then It is necessary to eliminate the correlation between the switching point voltage and the power supply voltage VDD, the size of NMOS and PMOS, and the threshold voltage of NMOS and PMOS.
  • the embodiments of the present disclosure can eliminate the dependence of the buffer module on the power supply voltage, reduce the influence of the power supply voltage, and eliminate the influence of the threshold voltage, so that the SNFP and FNSP process angles are changed to the SS and FF process angles to reduce the range of the flip point voltage. .
  • FIG. 3 shows a schematic diagram of a voltage adjustment module according to an embodiment of the present disclosure.
  • the voltage adjustment module 10 may include a first current source I1, a first N-type metal oxide semiconductor field effect transistor NMOS Mn1, a first resistor R1, a second The resistor R2, the third resistor R3, the fourth resistor R4 and the first capacitor C1, where:
  • the anode of the first current source I1 is electrically connected to the first end of the third resistor R3 for receiving the input voltage
  • the cathode of the first current source I1 is electrically connected to the first terminal of the first PMOS Mp1
  • the gate of the first PMOS Mp1 is electrically connected to the drain of the first PMOS Mp1 and the first end of the first resistor R1, and the second end of the first resistor R1 is electrically connected to the second The first end of resistor R2,
  • the second end of the third resistor R3 is electrically connected to the drain of the first NMOS Mn1,
  • the source of the first NMOS Mn1 is electrically connected to the first end of the fourth resistor R4 and the buffer module for outputting the driving voltage VLDO,
  • the second end of the second resistor R2, the second end of the first capacitor C1, and the second end of the fourth resistor R4 are grounded.
  • the threshold voltage of each PMOS can be considered the same, and the threshold voltage of each NMOS can be considered the same. Therefore, the first PMOS Mp1 can be introduced to offset the threshold voltage pair flip of the PMOS in the buffer module 20 The influence of point voltage.
  • V INV is not affected by the power supply voltage VDD, but is related to the current source (based on the voltage Vbg), and the voltage Vbg can be the reference voltage, so it is not affected by the process angle and can be maintained It is stable, and it can be seen from the above formula that the influence of the threshold voltage VT P of the PMOS is eliminated. Therefore, the change of the flip point voltage V INV in the full process angle range is significantly smaller, and the SNFP and FNSP process angles are changed to SS And FF craft corner.
  • FIG. 4 shows a schematic diagram of a voltage adjustment module according to an embodiment of the present disclosure.
  • the voltage adjustment module 10 may further include a second current source I2, a second NMOS Mn2, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and The second capacitor C2, where:
  • the anode of the second current source I2 is electrically connected to the first end of the sixth resistor R6 for receiving the power supply voltage VDD, and the cathode of the second current source I2 is electrically connected to the source of the first PMOS Mp1, The gate of the second NMOS Mn2, the first end of the second capacitor C2,
  • the gate of the first PMOS Mp1 is used to receive the input voltage VREF_CLAMP, and the drain of the first PMOS Mp1 is electrically connected to the first end of the fifth resistor R5,
  • the second end of the sixth resistor R6 is electrically connected to the drain of the second NMOS Mn2,
  • the source of the second NMOS Mn2 is electrically connected to the first end of the seventh resistor R7 and the buffer module 20 (not shown) for outputting the driving voltage VLDO,
  • the second end of the fifth resistor R5, the second end of the second capacitor C2, and the second end of the seventh resistor R7 are grounded.
  • VLDO VREF_CLAMP+Vgsp-Vgsn2
  • suitable first PMOS Mp1 and second NMOS Mn2 can be selected, so that the overdrive voltages of the first PMOS Mp1 and the second NMOS Mn2 are approximately equal.
  • VLDO VREF_CLAMP+VTP-VTN, combined with formula 1, we can get:
  • V INV is not affected by the power supply voltage VDD, but is related to the input voltage VREF_CLAMP, and the input voltage VREF_CLAMP can be a reference voltage, so it is not affected by the process angle and can remain stable.
  • the above formula can be seen, and the influence of the threshold voltage VT P of the PMOS is eliminated. Therefore, the change of the flip point voltage V INV in the full process angle range is significantly smaller, and the SNFP and FNSP process angles are changed to SS and FF processes. angle.
  • FIG. 5 shows a schematic diagram of a voltage adjustment module according to an embodiment of the present disclosure.
  • the voltage adjustment module 10 further includes a first operational amplifier Amp1, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10, where:
  • the positive input terminal of the first operational amplifier Amp1 is used to receive the input voltage VREF, and the output terminal of the first operational amplifier Amp1 is electrically connected to the source of the first PMOS Mp and the buffer module 20, For outputting the driving voltage VLDO,
  • the drain of the first PMOS Mp1 is electrically connected to the gate of the first PMOS Mp1 and the first end of the eighth resistor R8, and the second end of the eighth resistor R8 is electrically connected to the ninth resistor.
  • the first end of the resistor R9, the second end of the ninth resistor R9 is electrically connected to the first end of the tenth resistor R10, and the second end of the tenth resistor R10 is grounded,
  • the negative input end of the first operational amplifier Amp1 is electrically connected to the second end of the eighth resistor R8 and the first end of the ninth resistor R9.
  • the gate of the first PMOS Mp1 may also be electrically connected between the eighth resistor R8 and the ninth resistor R9, or the gate of the first PMOS Mp1 may also be electrically connected between the eighth resistor R8 and the ninth resistor R9. It can be electrically connected between the ninth resistor R9 and the tenth resistor R10, and by changing the electrical connection relationship between the gate of the first PMOS Mp1 and other circuits, the magnitude of the flip point voltage can be adjusted.
  • the following will introduce an example where the gate of the first PMOS Mp1 is electrically connected to the drain of the first PMOS Mp1 and the first end of the eighth resistor.
  • VLDO VREF*(R8+R9+R10)/(R9+R10)+Vgsp, where Vgsp represents the gate-source voltage of the first PMOS Mp1, assuming the first PMOS Mp1
  • the overdrive voltage is Vov3
  • VLDO VREF*(R8+R9+R10)/(R9+R10)+VT P +Vov3, combined with formula 1, we can get:
  • the inversion point voltage V INV is not affected by the power supply voltage VDD, but is related to the input voltage VREF, and the input voltage VREF can be a reference voltage, so it is not affected by the process angle and can remain stable , And it can be seen from the above formula that the influence of the threshold voltage VT P of the PMOS is eliminated. Therefore, the change of the flip point voltage V INV in the full process angle range is significantly smaller, and the SNFP and FNSP process angles are changed to SS and FF craft corner.
  • FIG. 6 shows a schematic diagram of a voltage adjustment module according to an embodiment of the present disclosure.
  • the voltage adjustment module may further include a second operational amplifier Amp2, a third operational amplifier Amp3, a second PMOS Mp2, a third NMOS Mn3, a fourth NMOS Mn4,
  • the source of the first PMOS Mp1 is electrically connected to the first end of the eleventh resistor R11 for receiving the power supply voltage VDD, and the drain of the first PMOS Mp1 is electrically connected to the third current source I3
  • the positive electrode of the first PMOS Mp1, and the positive input terminal of the second operational amplifier Amp2 is electrically connected to the third current source I3
  • the negative input terminal of the second operational amplifier Amp2 is electrically connected to the second terminal of the eleventh resistor R11 and the source of the second PMOS Mp2, and the output terminal of the second operational amplifier Amp2 is electrically connected to The gate of the second PMOS Mp2,
  • the drain of the second PMOS Mp2 is electrically connected to the drain of the third NMOS Mn3, the gate of the third NMOS Mn3, and the gate of the fourth NMOS Mn4,
  • the drain of the fourth NMOS Mn4 is electrically connected to the negative input end of the third operational amplifier Amp3, the second end of the twelfth resistor R12, and the first end of the thirteenth resistor R13,
  • the positive input terminal of the third operational amplifier Amp3 is used to receive the input voltage VREF1, and the output terminal of the third operational amplifier Amp3 is electrically connected to the first terminal of the twelfth resistor R12 and the buffer module 20, used to output the driving voltage VLDO,
  • the cathode of the third current source I3, the source of the third NMOS Mn3, the source of the fourth NMOS Mn4, and the second end of the thirteenth resistor R13 are grounded.
  • VLDO VREF1*(R12+R13)/R13+VTP+Vov4, combined with formula 1:
  • V INV is not affected by the power supply voltage VDD, but is related to the input voltage, and the input voltage VREF1 can be the reference voltage, so it is not affected by the process angle, and can remain stable. It can be seen from the formula that the influence of the threshold voltage VT P of the PMOS is eliminated. Therefore, the change of the flip point voltage V INV in the full process angle range is significantly smaller, and the SNFP and FNSP process angles are changed to SS and FF process angles.
  • the power supply voltage VDD can vary from 2.5V to 5.5V.
  • a 5V device can be selected for circuit design.
  • the received voltage can be adjusted through the adjustment module 10 by using the technical solution of the present disclosure.
  • Obtaining the driving voltage VLDO can compensate for the process angle change of the NMOS and PMOS threshold voltages in the buffer module 20, so that the change of the flip point voltage VINV in the full process angle range becomes smaller.
  • the buffer device proposed by the embodiment of the present disclosure can be adaptively adjusted for PMOS and MOS with different process angles.
  • the driving voltage VLDO voltage is appropriately lowered through the adjustment module; at the foot of the FNSP process, the adjustment module Let the driving voltage VLDO voltage increase appropriately, and by controlling the driving voltage VLDO to lower or increase the amplitude, the worst process angle can be improved, so that the SNFP and FNSP process angles are changed to SS and FF process angles, thus flipping the point voltage
  • the change of VINV in the whole process angle range is obviously smaller.

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Abstract

一种缓冲装置、芯片及电子设备，所述装置包括：电压调整模块（10），包括第一P型金属氧化物半导体场效应晶体管PMOS，所述电压调整模块（10）用于接收输入电压，并利用所述第一PMOS的阈值电压对所述输入电压进行调整，输出驱动电压；缓冲模块（20），电连接于所述电压调整模块（10），用于接收输入信号，并在所述驱动电压下对所述输入信号进行缓冲，输出缓冲后的信号。利用第一PMOS的阈值电压对输入电压进行调整，得到的驱动电压可以对缓冲模块（20）的工艺角(corner)进行补偿，使得缓冲模块（20）的翻转点电压范围变小，满足工艺要求。

Description

缓冲装置、芯片及电子设备 技术领域
本公开涉及集成电路技术领域，尤其涉及一种缓冲装置、芯片及电子设备。
背景技术
随着集成电路技术的不断发展，数字缓冲器的应用越来越广泛，相关技术通常采用施密特触发器电路实现数字缓冲器以实现确保低延迟，然而，由于采用电源电压直接对数字缓冲器进行供电，形成数字缓冲器的晶体管由于工艺上存在缺陷，其翻转点电压变化范围太大，无法满足要求。
发明内容
技术问题
有鉴于此，本公开要解决的技术问题是，如何降低缓冲装置翻转点电压变化范围。
解决方案
为了解决上述技术问题，根据本公开的一实施例，提供了一种缓冲装置，所述装置包括：
电压调整模块，包括第一P型金属氧化物半导体场效应晶体管PMOS，所述电压调整模块用于接收输入电压，并利用所述第一PMOS的阈值电压对所述输入电压进行调整，输出驱动电压；
缓冲模块，电连接于所述电压调整模块，用于接收输入信号，并在所述驱动电压下对所述输入信号进行缓冲，输出缓冲后的信号。
对于上述装置，在一种可能的实现方式中，所述电压调整模块还包括第一电流源、第一N型金属氧化物半导体场效应晶体管NMOS、第一电阻、第二电阻、第三电阻、第四电阻及第一电容，其中：
所述第一电流源的正极电连接于所述第三电阻的第一端，用于接收所述输入电压，所述第一电流源的负极电连接于所述第一PMOS的源极、所述第一NMOS的栅极、所述第一电容的第一端，其中，所述输入电压为电源电压，
所述第一PMOS的栅极电连接于所述第一PMOS的漏极及所述第一电阻的第一端，所述第一电阻的第二端电连接于所述第二电阻的第一端，
所述第三电阻的第二端电连接于所述第一NMOS的漏极，
所述第一NMOS的源极电连接于所述第四电阻的第一端及所述缓冲模块，用于输出所述驱动电压，
所述第二电阻的第二端、所述第一电容的第二端、所述第四电阻的第二端接地。
对于上述装置，在一种可能的实现方式中，所述电压调整模块还包括第二电流源、第二NMOS、第五电阻、第六电阻、第七电阻及第二电容，其中：
所述第二电流源的正极电连接于第六电阻的第一端，用于接收电源电压，所述第二电流源的负极电连接于所述第一PMOS的源极、所述第二NMOS的栅极、所述第二电容的第一端，
所述第一PMOS的栅极用于接收所述输入电压，所述第一PMOS的漏极电连接于所述第五电阻的第一端，
所述第六电阻的第二端电连接于所述第二NMOS的漏极，
所述第二NMOS的源极电连接于所述第七电阻的第一端及所述缓冲模块，用于输出所述驱动电压，
所述第五电阻的第二端、所述第二电容的第二端、所述第七电阻的第二端接地。
对于上述装置，在一种可能的实现方式中，所述电压调整模块还包括第一运算放大器、第八电阻、第九电阻、第十电阻，其中：
所述第一运算放大器的正向输入端用于接收所述输入电压，所述第一运算放大器的输出端电连接于所述第一PMOS的源极及所述缓冲模块，用于输出所述驱动电压，
所述第一PMOS的漏极电连接于所述第一PMOS的栅极及所述第八电阻的第一端，所述第八电阻的第二端电连接于所述第九电阻的第一端，所述第九电阻的第二端电连接于所述第十电阻的第一端，所述第十电阻的第二端接地，
所述第一运算放大器的负向输入端电连接于所述第八电阻的第二端及所述第九电阻的第一端。
对于上述装置，在一种可能的实现方式中，所述电压调整模块还包括第二运算放大器、第三运算放大器、第二PMOS、第三NMOS、第四NMOS、第十一电阻、第十二电阻、第十三电阻、第三电流源，其中：
所述第一PMOS的源极电连接于所述第十一电阻的第一端，用于接收电源电压，所述第一PMOS的漏极电连接于所述第三电流源的正极、所述第一PMOS的栅极及所述第二运算放大器的正向输入端，
所述第二运算放大器的负向输入端电连接于所述第十一电阻的第二端、所述第二PMOS的源极，所述第二运算放大器的输出端电连接于所述第二PMOS的栅极，
所述第二PMOS的漏极电连接于所述第三NMOS的漏极、所述第三NMOS的栅极、所述第四NMOS的栅极，
所述第四NMOS的漏极电连接于所述第三运算放大器的负向输入端、所述第十二电阻的第二端、所述第十三电阻的第一端，
所述第三运算放大器的正向输入端用于接收所述输入电压，所述第三运算放大器的输出端电连接于所述第十二电阻的第一端及所述缓冲模块，用于输出所述驱动电压，
所述第三电流源的负极、所述第三NMOS的源极、所述第四NMOS的源极、所述第十三电阻的第二端接地。
对于上述装置，在一种可能的实现方式中，所述缓冲模块包括第三PMOS、第四PMOS、第五PMOS、第五NMOS、第六NMOS、第七NMOS、反相器，其中：
所述第三PMOS的源极电连接于所述第五PMOS的源极，用于输入电源电压，
所述第三PMOS的栅极电连接于所述第四PMOS的栅极、所述第五NMOS的栅极、所述第六NMOS的栅极，用于接收所述输入信号，
所述第三PMOS的漏极电连接于所述第五PMOS的漏极、所述第四PMOS的源极，所述第四PMOS的漏极电连接于所述反相器的输入端、所述第五NMOS的漏极，所述第五NMOS的源极电连接于所述第六NMOS的漏极及所述第七NMOS的漏极，所述第六NMOS的源极、所述第七NMOS的源极接地，
所述反相器的输出端电连接于所述第五PMOS的栅极、所述第七NMOS的栅极，用于输出缓冲后的信号。
对于上述装置，在一种可能的实现方式中，所述装置能够应用于包括模数转换电路、上电复位电路、超声波传感器电路、电子开关电路、信号切换控制电路、IGBT驱动控制电路、电流阈值检测电路和电压阈值检测电路、光电传感电路中的任意一种的电子电路装置。
为了解决上述技术问题，根据本公开的另一实施例，提供了一种芯片，所述芯片包括：
所述的缓冲装置。
为了解决上述技术问题，根据本公开的另一实施例，提供了一种电子设备，所述电子设备包括：
所述的芯片。
有益效果
本公开实施例提出的缓冲装置中电压调整模块可以利用第一PMOS的阈值电压对输入电压进行调整，得到的驱动电压可以对缓冲模块的工艺角(corner)进行补偿，使得缓冲模块的翻转点电压范围变小，满足工艺要求。
根据下面参考附图对示例性实施例的详细说明，本公开的其它特征及方面将变得清楚。
附图说明
包含在说明书中并且构成说明书的一部分的附图与说明书一起示出了本公开的示例性实施例、特征和方面，并且用于解释本公开的原理。
图1示出了根据本公开一实施方式的缓冲装置的框图。
图2示出了根据本公开一实施方式的缓冲模块的示意图。
图3示出了根据本公开一实施方式的电压调整模块的示意图。
图4示出了根据本公开一实施方式的电压调整模块的示意图。
图5示出了根据本公开一实施方式的电压调整模块的示意图。
图6示出了根据本公开一实施方式的电压调整模块的示意图。
具体实施方式
以下将参考附图详细说明本公开的各种示例性实施例、特征和方面。附图中相同的附图标记表示功能相同或相似的元件。尽管在附图中示出了实施例的各种方面，但是除非特别指出，不必按比例绘制附图。
在这里专用的词“示例性”意为“用作例子、实施例或说明性”。这里作为“示例性”所说明的任何实施例不必解释为优于或好于其它实施例。
另外，为了更好的说明本公开，在下文的具体实施方式中给出了众多的具体细节。本领域技术人员应当理解，没有某些具体细节，本公开同样可以实施。在一些实例中，对于本领域技术人员熟知的方法、手段、元件和电路未作详细描述，以便于凸显本公开的主旨。
请参阅图1，图1示出了根据本公开一实施方式的缓冲装置的框图。
如图1所示，所述装置包括：
电压调整模块10，包括第一P型金属氧化物半导体场效应晶体管PMOS(图1未示出)，所述电压调整模块10用于接收输入电压，并利用所述第一PMOS的阈值电压对所述输入电压进行调整，输出驱动电压；
缓冲模块20，电连接于所述电压调整模块10，用于接收输入信号，并在所述驱动电压下对所述输入信号进行缓冲，输出缓冲后的信号。
本公开实施例提出的缓冲装置中电压调整模块可以利用第一PMOS的阈值电压对输入电压进行调整，得到的驱动电压可以对缓冲模块的工艺角(corner)进行补偿，使得缓冲模块的翻转点电压范围变小，满足工艺要求。
本公开实施方式的装置可以设置在电子设备中，所述电子设备也可以称为移动设备，移动设备可以指各种形式的接入移动设备、用户单元、用户设备、用户站、移动站、移动台(Mobile Station，MS)、远方站、远程移动设备、移动设备、用户移动设备、终端设备(terminal equipment)、无线通信设备、用户代理或用户装置。用户设备还可以是蜂窝电话、无绳电话、会话启动协议(Session Initiation Protocol，SIP)电话、无线本地环路(Wireless Local Loop，WLL)站、个人数字处理(Personal Digital Assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备、可穿戴设备，5G网络中的用户设备或者未来演进的公用陆地移动通信网络(Public Land Mobile Network，PLMN)中的移动设备等，本公开实施例对此并不限定。
本公开实施方式的缓冲装置可以应用于任意具有数字信号输入，并需要进行缓冲处理的装置/设备中，包括但不限于模数转换电路、上电复位电路、超声波传感器电路、电子开关电路、信号切换控制电路、IGBT驱动控制电路、电流阈值检测电路和电压阈值检测电路、光电传感电路中的任意一种形成的电子电路装置。
所述缓冲模块20可以包括多种实施方式，下面对缓冲模块20的一种可能实施方式进行示例性说明。
请参阅图2，图2示出了根据本公开一实施方式的缓冲模块的示意图。
在一种可能的实施方式中，如图2所示，所述缓冲模块20可以包括第三PMOS Mp3、第四PMOS Mp4、第五PMOS Mp5、第五NMOS Mn5、第六NMOS Mn6、第七NMOS Mn7、反相器Not，其中：
所述第三PMOS Mp3的源极电连接于所述第五PMOS Mp5的源极，用于输入电源电压VDD，
所述第三PMOS Mp3的栅极电连接于所述第四PMOS Mp4的栅极、所述第五NMOS Mn5的栅极、所述第六NMOS Mn6的栅极，用于接收所述输入信号Vin，
所述第三PMOS Mp3的漏极电连接于所述第五PMOS Mp5的漏极、所述第四PMOS Mp4的源极，所述第四PMOS Mp4的漏极电连接于所述反相器Not的输入端、所述第五NMOS Mn5的漏极，所述第五NMOS Mn5的源极电连接于所述第六NMOS Mn6的漏极及所述第七NMOS Mn7的漏极，所述第六NMOS Mn6的源极、所述第七NMOS Mn7的源极接地，
所述反相器Not的输出端电连接于所述第五PMOS Mp5的栅极、所述第七NMOS Mn7的栅极，用于输出缓冲后的信号Vout。
其中，第五PMOS Mp5和第七NMOS Mn7可以通过反馈实现逻辑高电平和逻辑低电平之间有一定的迟滞，以防止在翻转点电压附近出现反复高低电平切换导致的毛刺。
应该说明的是，以上对缓冲模块20的说明是示例性的，本领域技术人员可以通过其他方式实现缓冲模块20。
下面对缓冲模块20的翻转点电压进行示例性说明。
假设第三PMOS Mp3、第四PMOS Mp4相同(为方便说明，将以PMOS Mp进行说明)，第五NMOS Mn5、第六NMOS Mn6相同(为方便说明，将以NMOS Mn进行说明)，并忽略用于产生迟滞电压的第五PMOS Mp5和第七NMOS Mn7，假设翻转点电压为V INV，PMOS Mp的阈值电压绝对值为VT P，NMOS Mn阈值电压为VT N，设
Figure PCTCN2020132737-appb-000001
其中，C OX表示晶体管单位面积的栅极电容、W P、W N分别表示PMOS、NMOS的宽度，L P、L N分别表示PMOS、NMOS的长度，μ P、μ N分别表示PMOS、NMOS的迁移率，在电压翻转点，可以根据
Figure PCTCN2020132737-appb-000002
可以得到：
Figure PCTCN2020132737-appb-000003
从公式1中可以得知，缓冲模块20的翻转点电压V INV与电源电压VDD有关、与NMOS和PMOS的尺寸有关、与NMOS和PMOS的阈值电压有关。
通过公式1可以得知，在电源电压VDD不变的情况下，工艺角中的SNFP(Slow Nmos Fast Pmos，慢速NMOS快速PMOS)是逻辑高(Logic-High)的最差工艺角，决定了缓冲模块是否可以实现逻辑高的最小值为1.2或者1.1或者1.05；工艺角中的FNSP(Fast Nmos Slow Pmos，快速NMOS慢速PMOS)是逻辑低(Logic-Low)的最差工艺角,决定了缓冲模块是否可以实现逻辑低最大值为0.6V，因此SNFP、FNSP决定了缓冲模块20的翻转点电压的范围大小。具体分析如下：
对于工艺角中的TT工艺角，假设VT N＝VT P＝VT；对于工艺角中的SS工艺角，假设VT N＝VTP＝VT+Δ；对于工艺角中的FF工艺角，假设VT N＝VT P＝VT-Δ，其中，Δ可以表示预设值，应该说明的是，本公开对Δ的具体大小不做限定，本领域技术人员可以根据实际情况和需要设定。
综合以上假设，并根据公式1可以得到：
TT工艺角：
Figure PCTCN2020132737-appb-000004
SS工艺角：
Figure PCTCN2020132737-appb-000005
FF工艺角：
Figure PCTCN2020132737-appb-000006
SNFP工艺角：
Figure PCTCN2020132737-appb-000007
FNSP工艺角：
Figure PCTCN2020132737-appb-000008
其中，SNFP是多个工艺角中的极大值，是逻辑高的最差工艺角，决定了缓冲模块是否可以实现逻辑高的最小值为1.2或者1.1或者1.05；FNSP是多个工艺角中的极小值,是逻辑低的最差工艺角，决定了缓冲模块是否可以实现逻辑低最大值为0.6V。
一般而言，电源电压VDD的大小为2.5V～5.5V，如果直接以电源电压VDD对缓冲模块20进行供电，由于数字缓冲器20的翻转点电压与电源电压VDD、NMOS和PMOS的尺寸、NMOS和PMOS的阈值电压有关，则缓冲模块的翻转点电压逻辑低的最大值为0.6V，逻辑高的最小值为2.0V，可见，其翻转点电压范围较大(逻辑高与逻辑低差值大于1V)，如果要减少翻转点电压的范围，例如实现逻辑高于逻辑低差值小于或等于0.6V(例如逻辑低的最大值为0.6，逻辑高的最小值为1.2或者1.1或者1.05)，则需要消除翻转点电压与电源电压VDD、NMOS和PMOS的尺寸、NMOS和PMOS的阈值电压的关联性。
本公开实施例可以消除缓冲模块对电源电压的依赖，降低电源电压的影响，并消除阈值电压的影响，使得SNFP和FNSP工艺角改变成SS和FF工艺角， 以实现翻转点电压的范围减小。
下面对电压调整模块10的可能实现方式进行示例性介绍。
请参阅图3，图3示出了根据本公开一实施方式的电压调整模块的示意图。
在一种可能的实施方式中，如图3所示，所述电压调整模块10可以包括第一电流源I1、第一N型金属氧化物半导体场效应晶体管NMOS Mn1、第一电阻R1、第二电阻R2、第三电阻R3、第四电阻R4及第一电容C1，其中：
所述第一电流源I1的正极电连接于所述第三电阻R3的第一端，用于接收所述输入电压，所述第一电流源I1的负极电连接于所述第一PMOS Mp1的源极、所述第一NMOS Mn1的栅极、所述第一电容C1的第一端，其中，所述输入电压为电源电压VDD，
所述第一PMOS Mp1的栅极电连接于所述第一PMOS Mp1的漏极及所述第一电阻R1的第一端，所述第一电阻R1的第二端电连接于所述第二电阻R2的第一端，
所述第三电阻R3的第二端电连接于所述第一NMOS Mn1的漏极，
所述第一NMOS Mn1的源极电连接于所述第四电阻R4的第一端及所述缓冲模块，用于输出所述驱动电压VLDO，
所述第二电阻R2的第二端、所述第一电容C1的第二端、所述第四电阻R4的第二端接地。
在一个示例中，假设第一电流源I1为Vbg/R(其中Vbg为基准电压，其大小稳定)，流过第一电阻R1和第二电阻R2以及第一PMOS Mp1，因此可以得到VLDO＝I1*(R1+R2)+Vgsp-Vgsn1，其中，Vgsp表示第一PMOS Mp1的栅源电压，Vgsn1表示第一NMOS Mn1的栅源电压。
在一个示例中，可以选择合适的第一PMOS Mp1和第一NMOS Mn1，使得第一PMOS Mp1和第一NMOS Mn1的过驱动电压大致相等，例如均为Vov1，那么可以得到Vgsp＝VTP+Vov1，Vgsn1＝VTN+Vov1，然后就可以得到VLDO电压为：VLDO＝I1*(R1+R2)+VTP-VTN＝Vbg*(R1+R2)/R+VTP-VTN，结合缓冲模块的翻转点电压公式1，就可以得到：
Figure PCTCN2020132737-appb-000009
应该说明的是，同一片晶圆上，每个PMOS的阈值电压可以认为相同，每个NMOS的阈值电压可以认为相同，因此可以引入第一PMOS Mp1以抵消缓冲模块20中PMOS的阈值电压对翻转点电压的影响。
因此，从以上公式上也可以看出，V INV不受电源电压VDD的影响，与电流源有关(基于电压Vbg相关)，而电压Vbg可以为基准电压，因此不受工艺角的影响，可以保持稳定，且从上式可以看出，消除了PMOS的阈值电压VT P的影响，因此，翻转点电压V INV在全工艺角范围内的变化明显变小，而且SNFP、FNSP工艺角被改变成SS和FF工艺角。
请参阅图4，图4示出了根据本公开一实施方式的电压调整模块的示意图。
在一种可能的实施方式中，如图4所示，所述电压调整模块10还可以包括第二电流源I2、第二NMOS Mn2、第五电阻R5、第六电阻R6、第七电阻R7及第二电容C2，其中：
所述第二电流源I2的正极电连接于第六电阻R6的第一端，用于接收电源电压VDD，所述第二电流源I2的负极电连接于所述第一PMOS Mp1的源极、所述第二NMOS Mn2的栅极、所述第二电容C2的第一端，
所述第一PMOS Mp1的栅极用于接收所述输入电压VREF_CLAMP，所述第一PMOS Mp1的漏极电连接于所述第五电阻R5的第一端，
所述第六电阻R6的第二端电连接于所述第二NMOS Mn2的漏极，
所述第二NMOS Mn2的源极电连接于所述第七电阻R7的第一端及所述缓冲模块20(未示出)，用于输出所述驱动电压VLDO，
所述第五电阻R5的第二端、所述第二电容C2的第二端、所述第七电阻R7的第二端接地。
在一个示例中，如图4所示，VLDO＝VREF_CLAMP+Vgsp-Vgsn2，可以选择合适的第一PMOS Mp1和第二NMOS Mn2，使得第一PMOS Mp1和第二 NMOS Mn2的过驱动电压大致相等，均为Vov2，其中，Vgsp表示第一PMOS Mp1的栅源电压，Vgsn2表示第二NMOS Mn2的栅源电压，那么Vgsp＝VTP+Vov2,Vgsn＝VTN+Vov2,然后就可以得到VLDO电压：VLDO＝VREF_CLAMP+VTP-VTN，结合公式1，就可以得到：
Figure PCTCN2020132737-appb-000010
因此，从以上公式上也可以看出，V INV不受电源电压VDD的影响，与输入电压VREF_CLAMP有关，而输入电压VREF_CLAMP可以为基准电压，因此不受工艺角的影响，可以保持稳定，且从上式可以看出，且消除了PMOS的阈值电压VT P的影响，因此，翻转点电压V INV在全工艺角范围内的变化明显变小，而且SNFP、FNSP工艺角被改变成SS和FF工艺角。
请参阅图5，图5示出了根据本公开一实施方式的电压调整模块的示意图。
在一种可能的实施方式中，如图5所示，所述电压调整模块10还包括第一运算放大器Amp1、第八电阻R8、第九电阻R9、第十电阻R10，其中：
所述第一运算放大器Amp1的正向输入端用于接收所述输入电压VREF，所述第一运算放大器Amp1的输出端电连接于所述第一PMOS Mp的源极及所述缓冲模块20，用于输出所述驱动电压VLDO，
所述第一PMOS Mp1的漏极电连接于所述第一PMOS Mp1的栅极及所述第八电阻R8的第一端，所述第八电阻R8的第二端电连接于所述第九电阻R9的第一端，所述第九电阻R9的第二端电连接于所述第十电阻R10的第一端，所述第十电阻R10的第二端接地，
所述第一运算放大器Amp1的负向输入端电连接于所述第八电阻R8的第二端及所述第九电阻R9的第一端。
在其他实施方式中，如图5所示，所述第一PMOS Mp1的栅极也可以电连接于第八电阻R8和第九电阻R9之间，或者，所述第一PMOS Mp1的栅极还 可以电连接于第九电阻R9和第十电阻R10之间，通过改变所述第一PMOS Mp1的栅极与其他电路的电连接关系，可以调整翻转点电压的大小。下面将以所述第一PMOS Mp1的栅极电连接于所述第一PMOS Mp1的漏极及第八电阻的第一端为例进行介绍。
在一个示例中，如图5所示，VLDO＝VREF*(R8+R9+R10)/(R9+R10)+Vgsp，其中，Vgsp表示第一PMOS Mp1的栅源电压，假设第一PMOS Mp1的过驱动电压为Vov3，那么VLDO＝VREF*(R8+R9+R10)/(R9+R10)+VT P+Vov3，结合公式1，就可以得到：
Figure PCTCN2020132737-appb-000011
因此，从以上公式上也可以看出，翻转点电压V INV不受电源电压VDD的影响，与输入电压VREF有关，而输入电压VREF可以为基准电压，因此不受工艺角的影响，可以保持稳定，且从上式可以看出，消除了PMOS的阈值电压VT P的影响，因此，翻转点电压V INV在全工艺角范围内的变化明显变小，而且SNFP、FNSP工艺角被改变成SS和FF工艺角。
请参阅图6，图6示出了根据本公开一实施方式的电压调整模块的示意图。
在一种可能的实施方式中，如图6所示，所述电压调整模块还可以包括第二运算放大器Amp2、第三运算放大器Amp3、第二PMOS Mp2、第三NMOS Mn3、第四NMOS Mn4、第十一电阻R11、第十二电阻R12、第十三电阻R13、第三电流源I3，其中：
所述第一PMOS Mp1的源极电连接于所述第十一电阻R11的第一端，用于接收电源电压VDD，所述第一PMOS Mp1的漏极电连接于所述第三电流源I3的正极、所述第一PMOS Mp1的栅极及所述第二运算放大器Amp2的正向输入端，
所述第二运算放大器Amp2的负向输入端电连接于所述第十一电阻R11的第二端、所述第二PMOS Mp2的源极，所述第二运算放大器Amp2的输出 端电连接于所述第二PMOS Mp2的栅极，
所述第二PMOS Mp2的漏极电连接于所述第三NMOS Mn3的漏极、所述第三NMOS Mn3的栅极、所述第四NMOS Mn4的栅极，
所述第四NMOS Mn4的漏极电连接于所述第三运算放大器Amp3的负向输入端、所述第十二电阻R12的第二端、所述第十三电阻R13的第一端，
所述第三运算放大器Amp3的正向输入端用于接收所述输入电压VREF1，所述第三运算放大器Amp3的输出端电连接于所述第十二电阻R12的第一端及所述缓冲模块20，用于输出所述驱动电压VLDO，
所述第三电流源I3的负极、所述第三NMOS Mn3的源极、所述第四NMOS Mn4的源极、所述第十三电阻R13的第二端接地。
如图6所示，本公开实施例可以将第一PMOS Mp1的栅源电压Vgsp转为为电流Vgsp/R11输入到第三运算放大器Amp3的负向输入端及VLDO的电阻分压电阻串反馈端(第十二电阻R12和第十三电阻R13之间)，假设第一PMOS Mp1的过驱动电压为Vov4，即Vgsp＝VTP+Vov4，可以得到VLDO电压为：VREF1*(R12+R13)/R13+(VTP+Vov4)*R12/R11，本公开可以通过调整第十二电阻R12和第十一电阻R11(R12/R11)的比例，以改变VLDO电压。
在一个示例中，可以设置R12/R11＝1,则VLDO电压为：VLDO＝VREF1*(R12+R13)/R13+VTP+Vov4，结合公式1可得：
Figure PCTCN2020132737-appb-000012
因此，从以上公式上也可以看出，V INV不受电源电压VDD的影响，与输入电压有关，而输入电压VREF1可以为基准电压，因此不受工艺角的影响，可以保持稳定，且从上式可以看出，消除了PMOS的阈值电压VT P的影响，因此，翻转点电压V INV在全工艺角范围内的变化明显变小，而且SNFP、FNSP工艺角被改变成SS和FF工艺角。
在低压供电***中，电源电压VDD的变化范围可以为2.5V-5.5V，为了 不增加成本，可以选择5V器件进行电路设计，此时可以通过采用本公开技术方案，通过调整模块10调整接收电压得到驱动电压VLDO，可以补偿缓冲模块20中NMOS和PMOS阈值电压的工艺角变化，从而使得翻转点电压VINV在全工艺角范围内变化变小。
本公开实施方式提出的缓冲装置，可以针对不同工艺角的PMOS、MOS进行自适应的调整，在SNFP工艺角下，通过调整模块让驱动电压VLDO电压适当变低；在FNSP工艺脚下，通过调整模块让驱动电压VLDO电压适当升高，通过控制驱动电压驱动电压VLDO变低或者升高的幅度，就可以改善最差工艺角，使得SNFP和FNSP工艺角改变成SS和FF工艺角，这样翻转点电压VINV在全工艺角范围内的变化明显变小。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (9)

  1. 一种缓冲装置，其特征在于，所述装置包括：
    电压调整模块，包括第一P型金属氧化物半导体场效应晶体管PMOS，所述电压调整模块用于接收输入电压，并利用所述第一PMOS的阈值电压对所述输入电压进行调整，输出驱动电压；
    缓冲模块，电连接于所述电压调整模块，用于接收输入信号，并在所述驱动电压下对所述输入信号进行缓冲，输出缓冲后的信号。
  2. 根据权利要求1所述的装置，其特征在于，所述电压调整模块还包括第一电流源、第一N型金属氧化物半导体场效应晶体管NMOS、第一电阻、第二电阻、第三电阻、第四电阻及第一电容，其中：
    所述第一电流源的正极电连接于所述第三电阻的第一端，用于接收所述输入电压，所述第一电流源的负极电连接于所述第一PMOS的源极、所述第一NMOS的栅极、所述第一电容的第一端，其中，所述输入电压为电源电压，
    所述第一PMOS的栅极电连接于所述第一PMOS的漏极及所述第一电阻的第一端，所述第一电阻的第二端电连接于所述第二电阻的第一端，
    所述第三电阻的第二端电连接于所述第一NMOS的漏极，
    所述第一NMOS的源极电连接于所述第四电阻的第一端及所述缓冲模块，用于输出所述驱动电压，
    所述第二电阻的第二端、所述第一电容的第二端、所述第四电阻的第二端接地。
  3. 根据权利要求1所述的装置，其特征在于，所述电压调整模块还包括第二电流源、第二NMOS、第五电阻、第六电阻、第七电阻及第二电容，其中：
    所述第二电流源的正极电连接于第六电阻的第一端，用于接收电源电压，所述第二电流源的负极电连接于所述第一PMOS的源极、所述第二NMOS的栅极、所述第二电容的第一端，
    所述第一PMOS的栅极用于接收所述输入电压，所述第一PMOS的漏极电连接于所述第五电阻的第一端，
    所述第六电阻的第二端电连接于所述第二NMOS的漏极，
    所述第二NMOS的源极电连接于所述第七电阻的第一端及所述缓冲模块，用于输出所述驱动电压，
    所述第五电阻的第二端、所述第二电容的第二端、所述第七电阻的第二端接地。
  4. 根据权利要求1所述的装置，其特征在于，所述电压调整模块还包括第一运算放大器、第八电阻、第九电阻、第十电阻，其中：
    所述第一运算放大器的正向输入端用于接收所述输入电压，所述第一运算放大器的输出端电连接于所述第一PMOS的源极及所述缓冲模块，用于输出所述驱动电压，
    所述第一PMOS的漏极电连接于所述第一PMOS的栅极及所述第八电阻的第一端，所述第八电阻的第二端电连接于所述第九电阻的第一端，所述第九电阻的第二端电连接于所述第十电阻的第一端，所述第十电阻的第二端接地，
    所述第一运算放大器的负向输入端电连接于所述第八电阻的第二端及所述第九电阻的第一端。
  5. 根据权利要求1所述的装置，其特征在于，所述电压调整模块还包括第二运算放大器、第三运算放大器、第二PMOS、第三NMOS、第四NMOS、第十一电阻、第十二电阻、第十三电阻、第三电流源，其中：
    所述第一PMOS的源极电连接于所述第十一电阻的第一端，用于接收电源电压，所述第一PMOS的漏极电连接于所述第三电流源的正极、所述第一PMOS的栅极及所述第二运算放大器的正向输入端，
    所述第二运算放大器的负向输入端电连接于所述第十一电阻的第二端、所述第二PMOS的源极，所述第二运算放大器的输出端电连接于所述第二PMOS的栅极，
    所述第二PMOS的漏极电连接于所述第三NMOS的漏极、所述第三NMOS的栅极、所述第四NMOS的栅极，
    所述第四NMOS的漏极电连接于所述第三运算放大器的负向输入端、所述第十二电阻的第二端、所述第十三电阻的第一端，
    所述第三运算放大器的正向输入端用于接收所述输入电压，所述第三运算放大器的输出端电连接于所述第十二电阻的第一端及所述缓冲模块，用于输出所述驱动电压，
    所述第三电流源的负极、所述第三NMOS的源极、所述第四NMOS的源极、所述第十三电阻的第二端接地。
  6. 根据权利要求1所述的装置，其特征在于，所述缓冲模块包括第三PMOS、第四PMOS、第五PMOS、第五NMOS、第六NMOS、第七NMOS、反相器，其中：
    所述第三PMOS的源极电连接于所述第五PMOS的源极，用于输入电源电压，
    所述第三PMOS的栅极电连接于所述第四PMOS的栅极、所述第五NMOS的栅极、所述第六NMOS的栅极，用于接收所述输入信号，
    所述第三PMOS的漏极电连接于所述第五PMOS的漏极、所述第四PMOS的源极，所述第四PMOS的漏极电连接于所述反相器的输入端、所述第五NMOS的漏极，所述第五NMOS的源极电连接于所述第六NMOS的漏极及所述第七NMOS的漏极，所述第六NMOS的源极、所述第七NMOS的源极接地，
    所述反相器的输出端电连接于所述第五PMOS的栅极、所述第七NMOS的栅极，用于输出缓冲后的信号。
  7. 如权利要求1～6任一项所述的缓冲装置，其特征在于，所述装置能够应用于包括模数转换电路、上电复位电路、超声波传感器电路、电子开关电路、信号切换控制电路、IGBT驱动控制电路、电流阈值检测电路和电压阈值检测电路、光电传感电路中的任意一种的电子电路装置。
  8. 一种芯片，其特征在于，所述芯片包括：
    如权利要求1～6任一项所述的缓冲装置。
  9. 一种电子设备，其特征在于，所述电子设备包括：
    如权利要求8所述的芯片。
PCT/CN2020/132737 2019-12-09 2020-11-30 缓冲装置、芯片及电子设备 WO2021115147A1 (zh)

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