WO2021114377A1 - Tft阵列基板和显示面板 - Google Patents

Tft阵列基板和显示面板 Download PDF

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Publication number
WO2021114377A1
WO2021114377A1 PCT/CN2019/127027 CN2019127027W WO2021114377A1 WO 2021114377 A1 WO2021114377 A1 WO 2021114377A1 CN 2019127027 W CN2019127027 W CN 2019127027W WO 2021114377 A1 WO2021114377 A1 WO 2021114377A1
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Prior art keywords
array substrate
tft array
source
area
layer
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PCT/CN2019/127027
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English (en)
French (fr)
Inventor
曹武
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US16/638,139 priority Critical patent/US11289514B2/en
Publication of WO2021114377A1 publication Critical patent/WO2021114377A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • This application relates to the field of display panel technology, and in particular to a TFT array substrate and a display panel.
  • a thin film transistor is used as a driving element of a display panel.
  • the active layer in the thin film transistor will generate photo-generated carriers after being irradiated by light, which will increase the leakage current of the thin film transistor, thereby affecting the quality of the display screen of the display panel, such as crosstalk, after-images and the like.
  • the array substrate (Array) containing thin film transistors can be fabricated by 4Mask (photomask) process or 5Mask process.
  • the semiconductor layer (active layer) and the source and drain electrodes are formed by using different photomasks.
  • the pattern of the semiconductor layer is generally larger. After the source and drain electrodes are formed on the layer, the semiconductor layer with a larger pattern will form a loop around the source and drain.
  • the semiconductor layer and the source and drain electrodes are formed by using the same mask with different steps.
  • metal patterns such as data lines.
  • the lower layer of the metal pattern also has a corresponding semiconductor layer, which is affected by the process.
  • exposed semiconductor layers on the source and drain electrodes and the sides of the metal pattern including the data lines and these exposed semiconductor layers will also become part of the path for the photo-generated current after being exposed to light.
  • the present application provides a TFT array substrate and a display panel.
  • the active layer located in the peripheral area into a multi-segment discontinuous structure, the problem of the photo-induced leakage current of the active layer in the thin film transistor can be improved.
  • An embodiment of the present application provides a TFT array substrate, including an active layer and source and drain electrodes disposed on the active layer;
  • the active layer includes an electrode covering area, a channel area, and surrounding the electrode covering area and A first peripheral area provided in the channel area; the source and drain electrodes are provided corresponding to the electrode covering area;
  • the active layer located in the first peripheral area is distributed in multiple sections.
  • the TFT array substrate further includes a doped layer located between the active layer and the source and drain electrodes; the doped layer includes a covering layer corresponding to the electrode A first doped region set in the region, and a second doped region set corresponding to the first peripheral region;
  • the doped layer located in the second doped region is distributed in multiple sections.
  • the doped layer includes any one of a P-type doped semiconductor and an N-type doped semiconductor.
  • the TFT array substrate further includes metal traces arranged in the same layer as the source and drain electrodes; correspondingly, the active layer further includes metal traces A covered metal trace coverage area, and a second peripheral area provided around the metal trace coverage area;
  • the active layer located in the second peripheral area is distributed in multiple sections.
  • the TFT array substrate further includes a doped layer located between the active layer and the source and drain electrodes; the doped layer includes a covering layer corresponding to the electrode Region and a third doped region provided in the metal trace coverage region, and a fourth doped region provided corresponding to the first peripheral region and the second peripheral region;
  • the doped layer located in the fourth doped region is distributed in multiple sections.
  • the metal wiring includes a data line electrically connected to the source of the source and drain electrodes.
  • the TFT array substrate further includes a passivation layer disposed on the source and drain electrodes and the metal traces, and a passivation layer on the passivation layer and in contact with the passivation layer.
  • a pixel electrode electrically connected to the drain in the source and drain electrodes;
  • the metal wiring includes a shared common electrode that is electrically connected to the source of the source and drain electrodes and is at least partially covered by the pixel electrode.
  • the TFT array substrate further includes a light-shielding layer provided corresponding to the shared common electrode; the light-shielding layer is located on the side of the active layer away from the metal traces ;
  • the projection of the light-shielding layer in the direction perpendicular to the TFT array substrate completely covers the active layer located in the metal trace coverage area and the second peripheral area in the direction perpendicular to the TFT array substrate. projection.
  • the TFT array substrate further includes a base substrate and a gate electrode and a gate insulating layer sequentially disposed on the base substrate, and the active layer is disposed on the base substrate.
  • the gate insulating layer On the gate insulating layer;
  • the orthographic projection of the gate on the base substrate completely covers the orthographic projection of the active layer located in the electrode covering area and the first peripheral area on the base substrate.
  • the material of the active layer includes any one of amorphous silicon and indium gallium zinc oxide.
  • the source and drain electrodes include source and drain electrodes arranged at intervals, and the electrode covering area includes a source covering area and a drain covering area arranged at intervals.
  • the electrode is arranged corresponding to the source covering area
  • the drain is arranged corresponding to the drain covering area
  • the source covering area and the drain covering area are connected through the channel area.
  • the embodiment of the present application also provides a display panel, which includes a TFT array substrate and a counter substrate disposed opposite to the TFT array substrate;
  • the TFT array substrate includes an active layer and source and drain electrodes arranged on the active layer; the active layer includes an electrode covering area, a channel area, and an electrode covering area and a channel area arranged around the electrode covering area and the channel area.
  • the source and drain electrodes correspond to the electrode covering area; the active layer located in the first peripheral area is distributed in multiple segments.
  • the TFT array substrate further includes a doped layer located between the active layer and the source and drain electrodes; the doped layer includes a covering area corresponding to the electrode A first doped region provided, and a second doped region provided corresponding to the first peripheral region;
  • the doped layer located in the second doped region is distributed in multiple sections.
  • the doped layer includes any one of a P-type doped semiconductor and an N-type doped semiconductor.
  • the TFT array substrate further includes metal traces arranged in the same layer as the source and drain electrodes; correspondingly, the active layer further includes metal traces covered by the metal traces.
  • the active layer located in the second peripheral area is distributed in multiple sections.
  • the TFT array substrate further includes a doped layer located between the active layer and the source and drain electrodes; the doped layer includes a covering area corresponding to the electrode A third doped region provided with the metal wiring covering region, and a fourth doped region provided corresponding to the first peripheral region and the second peripheral region;
  • the doped layer located in the fourth doped region is distributed in multiple sections.
  • the metal wiring includes a data line electrically connected to the source of the source and drain electrodes.
  • the TFT array substrate further includes a passivation layer disposed on the source and drain electrodes and the metal traces, and a passivation layer disposed on the passivation layer and connected to the passivation layer.
  • a pixel electrode electrically connected to the drain of the source and drain electrodes;
  • the metal wiring includes a shared common electrode that is electrically connected to the source of the source and drain electrodes and is at least partially covered by the pixel electrode.
  • the display panel further includes a liquid crystal layer located between the TFT array substrate and the counter substrate, and a side of the TFT array substrate close to the liquid crystal layer.
  • Color filters located between the TFT array substrate and the counter substrate, and a side of the TFT array substrate close to the liquid crystal layer.
  • the display panel further includes a liquid crystal layer located between the TFT array substrate and the counter substrate, and a side of the counter substrate close to the liquid crystal layer Color filters.
  • the active layer includes an electrode covering area and a first peripheral area, the source and drain electrodes are arranged on the electrode covering area, and the first peripheral area is arranged around the electrode covering area, that is, the first peripheral area is not Covered by the source and drain electrodes, the active layer located in the first peripheral area is made into a multi-stage discontinuous structure.
  • the area of the active layer located in the first peripheral area is reduced, thereby reducing the first peripheral area The number of photo-generated carriers generated by the active layer under illumination (including the backlight and natural light in the environment).
  • the TFT array substrate provided by the present application can effectively improve the photo-generated leakage current problem of the thin film transistor.
  • FIG. 1 is a schematic diagram of a part of the structure of a TFT array substrate provided by an embodiment of the application;
  • FIG. 2 is a top view of an active layer at the thin film transistor in FIG. 1;
  • Fig. 3 is a schematic cross-sectional structure diagram at A-A' in Fig. 1;
  • FIG. 4 is a top view of the active layer and the doped layer at the thin film transistor in FIG. 1;
  • FIG. 5 is a schematic diagram of a part of the structure of another TFT array substrate provided by an embodiment of the application.
  • FIG. 6 is a top view of the active layer in area B in FIG. 5;
  • FIG. 7 is a top view of the active layer and the doped layer in area B in FIG. 5;
  • FIG. 8 is a top view of the active layer and the doped layer at the thin film transistor in FIG. 5;
  • FIG. 9 is a schematic diagram of a part of the structure of another TFT array substrate provided by an embodiment of the application.
  • Fig. 10 is an enlarged schematic diagram of area C in Fig. 9;
  • FIG. 11 is a schematic diagram of the structure of metal traces, active layers and light shielding layers in the D area in FIG. 9;
  • Fig. 12 is a schematic cross-sectional structure diagram at E-E' in Fig. 11;
  • FIG. 13 is a schematic diagram of a part of the structure of a display panel provided by an embodiment of the application.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present application, “multiple” means two or more than two, unless otherwise specifically defined.
  • connection should be understood in a broad sense, unless otherwise clearly specified and limited.
  • it can be a fixed connection or a detachable connection.
  • Connected or integrally connected it can be mechanically connected, or electrically connected or can communicate with each other; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal communication of two components or the interaction of two components relationship.
  • connection should be understood according to specific circumstances.
  • the "on" or “under” of the first feature of the second feature may include direct contact between the first and second features, or may include the first and second features Not in direct contact but through other features between them.
  • the "above”, “above” and “above” of the first feature on the second feature include the first feature directly above and obliquely above the second feature, or it simply means that the first feature is higher in level than the second feature.
  • the “below”, “below” and “below” of the second feature of the first feature include the first feature directly below and obliquely below the second feature, or it simply means that the level of the first feature is smaller than the second feature.
  • an embodiment of the present application provides a TFT array substrate 1.
  • the TFT array substrate 1 includes a base substrate 2 and a gate 3 and a gate insulating layer 4 sequentially arranged on the base substrate 2.
  • the corresponding electrode covering area 7 is provided; the active layer 5 located in the first peripheral area 9 is distributed in multiple sections.
  • the gate 3, the gate insulating layer 4, the active layer 5, and the source and drain electrodes 6 constitute a thin film transistor (TFT) of the TFT array substrate 1.
  • TFT thin film transistor
  • the first peripheral area 9 can be arranged completely around the electrode covering area 7 and the channel area 8, or it can be arranged only on the periphery of the electrode covering area 7, that is, the first peripheral area 9 It refers to the active layer 5 that is not covered by the source and drain electrodes 6 except for the channel region 8.
  • the active layer 5 located in the first peripheral region 9 is distributed in multiple sections along the side adjacent to the electrode covering region 7 and the first peripheral region 9, and any two adjacent sections are arranged at intervals, and the shape of each section can be Rectangle can also be other shapes, and there is no restriction here.
  • a discontinuous multi-segment active layer located in the first peripheral region 9 is formed when the patterned active layer 5 is formed.
  • Layer 5 a discontinuous multi-segment active layer located in the first peripheral region 9 is formed when the patterned active layer 5 is formed.
  • the material of the active layer 5 includes, but is not limited to, any one of amorphous silicon and indium gallium zinc oxide (IGZO) with strong light sensitivity.
  • IGZO indium gallium zinc oxide
  • the source and drain electrodes 6 include a source electrode 10 and a drain electrode 11 arranged at intervals
  • the electrode covering area 7 includes a source covering area 12 and a drain covering area 13 arranged at intervals
  • the source electrode 10 is arranged corresponding to the source covering area 12
  • the drain 11 is arranged corresponding to the drain covering area 13
  • the source covering area 12 and the drain covering area 13 are connected through the channel area 8.
  • the TFT array substrate 1 in this embodiment can be prepared by a 5Mask process, wherein the active layer 5 and the source and drain electrodes 6 are prepared by using two different photomasks respectively.
  • the TFT array substrate 1 in this embodiment is suitable for a 4-domain (1TFT) pixel structure or an 8-domain (3TFT) pixel structure.
  • the type of pixel structure applicable to the TFT array substrate 1 is not limited to this.
  • the active layer 5 includes an electrode covering area 7 and a first peripheral area 9.
  • the source and drain electrodes 6 are arranged on the electrode covering area 7, and the first peripheral area 9 is arranged around the electrode covering area 7, that is, the first peripheral area. 9 is not covered by the source and drain electrodes 6, the active layer 5 located in the first peripheral area 9 is made into a multi-stage discontinuous structure.
  • the area of the active layer 5 located in the first peripheral area 9 is reduced, This reduces the number of photo-generated carriers generated by the active layer 5 of the first peripheral area 9 by light (including the backlight and natural light in the environment).
  • the active layer located in the first peripheral area 9 can be avoided.
  • the TFT array substrate 1 provided in the present application can effectively improve the photo-generation of thin film transistors.
  • the problem of leakage current is a problem of leakage current.
  • the orthographic projection of the gate 3 on the base substrate 2 completely covers the orthographic projection of the active layer 5 located in the electrode covering area 7 and the first peripheral area 9 on the base substrate 2.
  • the gate 3 can shield the light source under the active layer 5 to prevent the lower surface of the active layer 5 from being exposed to light to generate photocurrent.
  • the TFT array substrate 1 further includes a doped layer 14 between the active layer 5 and the source and drain electrodes 6, and the doped layer 14 includes a P-type doped semiconductor or an N-type doped semiconductor; as shown in FIG. 4 As shown, the doped layer 14 includes a first doped region 15 corresponding to the electrode covering region 7 and a second doped region 16 corresponding to the first peripheral region 9; the doped layer 14 located in the second doped region 16 It is distributed in multiple segments.
  • the area of the second doped region 16 is less than or equal to the area of the first peripheral region 9; the multi-stage doped layer 14 and the multi-stage active layer 5 are formed in the same manufacturing process, that is, the same photomask is used Formed, that is, the multi-stage doped layer 14 and the multi-stage active layer 5 are arranged in one-to-one correspondence.
  • the material of the doped layer 14 includes a semiconductor material and a doped material doped in the semiconductor material, wherein the semiconductor material is the same as the material of the active layer 5, therefore, the doped material not covered by the source and drain electrodes 6
  • the doped layer 14 (the doped layer 14 located in the second doped region 16) will also generate photo-generated current when exposed to light.
  • Making the doped layer 14 located in the second doped region 16 into a multi-stage structure can also reduce the photo-generated current. The number of electrons and the transmission efficiency of photo-generated carriers are reduced, thereby effectively improving the problem of photo-generated leakage current of thin film transistors.
  • an embodiment of the present application also provides a TFT array substrate 1.
  • the TFT array substrate 1 further includes metal traces 17 arranged in the same layer as the source and drain electrodes 6.
  • the active layer 5 also includes a metal wiring covering area 18 covered by the metal wiring 17, and a second peripheral area 19 arranged around the metal wiring covering area 18; located in the second periphery
  • the active layer 5 in the region 19 is distributed in multiple sections.
  • the TFT array substrate 1 in this embodiment can be prepared by using a 4Mask process, where the active layer 5, the source and drain electrodes 6, and the metal wiring 17 are prepared by using the same photomask, and the metal wiring 17 and the source and drain The electrodes 6 are arranged in the same layer and have the same material. It can be understood that the active layer 5 as shown in FIG. 6 exists under all the metal traces 17 formed by the same process as the source and drain electrodes 6, wherein the second layer of the active layer 5 A peripheral area 9 and a second peripheral area 19 are tailings of the active layer 5 produced by the patterning process.
  • the metal wiring 17 includes a data line 20 electrically connected to the source electrode 10 of the source and drain electrodes 6, and the data line 20 is electrically connected to the source electrode of the source and drain electrodes 6 to provide source electrical signals.
  • the active layer 5 includes a first peripheral area 9 that is not covered by the source and drain electrodes 6 and a second peripheral area 19 that is not covered by the metal wiring 17, which will be located in the first peripheral area 9 and the second peripheral area.
  • the active layer 5 of 19 is made as a multi-stage discontinuous structure.
  • the area of the active layer 5 located in the first and second peripheral regions 19 is reduced, thereby reducing the first and second peripheral regions 9 and 9
  • the number of photogenerated carriers generated by the active layer 5 of the peripheral area 19 by light including the backlight and natural light in the environment).
  • the active layers of the first peripheral area 9 and the second peripheral area 19 can be avoided 5 to form a continuous path for the photo-generated leakage current, thereby effectively reducing the transmission efficiency of photo-generated carriers on the active layer 5 of the first peripheral region 9 and the second peripheral region 19. Therefore, the TFT array substrate 1 provided by the present application can effectively Improve the problem of the photo-generated leakage current of the thin film transistor and the metal trace 17 position.
  • the TFT array substrate 1 further includes a doped layer 14 located between the active layer 5 and the source and drain electrodes 6; as shown in FIGS. 7 and 8, the doped layer 14 includes a corresponding electrode covering region 7 and The third doped region 22 provided in the metal trace covering region 18, and the fourth doped region 23 provided corresponding to the first peripheral region 9 and the second peripheral region 19; the doped layer 14 located in the fourth doped region 23 is Multi-stage distribution.
  • the multi-stage doped layer 14 and the multi-stage active layer 5 are formed in the same manufacturing process, that is, the same photomask is used, that is, the multi-stage doped layer 14 and the multi-stage distributed active layer 5 are formed in the same process.
  • the active layers 5 are arranged in one-to-one correspondence.
  • the material of the doped layer 14 includes a semiconductor material and a doped material doped in the semiconductor material, wherein the semiconductor material is the same as the material of the active layer 5, therefore, the doped material located in the fourth doped region 23
  • the doped layer 14 (the doped layer 14 not covered by the source and drain electrodes 6 and the metal traces 17) will also generate photocurrent when exposed to light.
  • the doped layer 14 located in the fourth doped region 23 can also be made into a multi-segment structure. The number of photo-generated carriers is reduced and the transmission efficiency of photo-generated carriers is reduced, thereby effectively improving the problem of photo-generated leakage current at the position of the thin film transistor and the metal wiring 17.
  • an embodiment of the present application also provides a TFT array substrate 1 with an 8-domain 3-thin film transistor pixel structure.
  • the difference from the above-mentioned embodiment is that the TFT array substrate 1 is formed with a plurality of arrays.
  • each sub-pixel 27 includes a main area and a sub-area; the TFT array substrate 1 is provided with a scan line 30 corresponding to each row of sub-pixels 27, and the scan line 30 is between the main area 28 and Between the sub-regions 29, and corresponding to each column of sub-pixels 27, a data line 20 (metal wiring 17 formed in the same layer as the source and drain 11) is respectively provided; the TFT array substrate 1 also includes a main region corresponding to each sub-pixel 27 Thin film transistor (TFT) 31, sub-region thin film transistor 32 and shared thin film transistor 33.
  • TFT Thin film transistor
  • Each thin film transistor is composed of a gate 3, a gate insulating layer 4, an active layer 5 and a source and drain electrode 6, and each thin film transistor
  • the first peripheral regions 9 in the active layer 5 that are not covered by the source and drain electrodes 6 are all distributed in multiple segments.
  • the TFT array substrate 1 further includes a passivation layer disposed on the source and drain electrodes 6 and the data line 20 (metal wiring 17) (because the passivation layer is generally transparent, it is not shown in FIG. 9 and can be referred to The passivation layer 24 in 12), and the pixel electrode 25 located on the passivation layer and electrically connected to the drain electrode 11 in the source and drain electrode 6 (electrical connection is achieved by providing a via on the passivation layer); TFT array substrate 1 also includes a shared common electrode (share bar) 26 electrically connected to the source electrode 10 of the source and drain electrodes 6 and at least partially covered by the pixel electrode 25, and the shared common electrode 26 is manufactured in the same process as the data line 20 and the source and drain electrodes 6 Since they are formed and made of the same material, the shared common electrode 26 and the data line 20 belong to the same metal wiring 17.
  • a shared common electrode shared common electrode
  • the pixel electrode 25 includes a main area pixel electrode 34 corresponding to the main area 28 and a sub area pixel electrode 35 corresponding to the sub area; the gate of the main area thin film transistor 31, the gate of the sub area thin film transistor 32, and the shared thin film
  • the gate of the transistor 33 is connected to the same scan line 30, the source of the thin film transistor 31 in the main region and the source of the thin film transistor 32 in the sub region are connected to the same data line 20, and the drain of the thin film transistor 31 in the main region is connected (via the passivation layer on the Via connection) the main area pixel electrode 34, the drain of the thin film transistor 32 in the sub area and the drain of the shared thin film transistor 33 are connected (connected through the via on the passivation layer) the pixel electrode 35 in the sub area, and the source of the shared thin film transistor 33
  • the electrode connection shares the common electrode 26.
  • the main area pixel electrode 34 includes a main area horizontal pixel main portion, a main area vertical pixel main portion, and a main area pixel branch portion
  • the sub-area pixel electrode 35 includes a sub-area horizontal pixel main portion and a sub-area vertical pixel main portion.
  • each main area pixel display area includes a plurality of main area pixel branches spaced apart and arranged in parallel, and the two ends of each main area pixel branch are respectively connected to the main area horizontal pixel main portion It is connected to the main area vertical pixel backbone, and the angle between the multiple main area pixel branches and the main area horizontal pixel backbone and the main area vertical pixel backbone is an acute angle (for example, 45°); the same, the secondary The sub-region horizontal pixel main portion and the sub-region vertical pixel main portion of the sub-region pixel electrode 35 intersect vertically, and the sub-region horizontal pixel main portion and the sub-region vertical pixel main portion vertically intersect to form 4 sub-region pixel display areas.
  • Each sub-area pixel display area includes a plurality of sub-area pixel branch portions spaced apart and arranged in parallel, and the two ends of each sub-area pixel branch portion are respectively connected with the sub-area horizontal pixel main portion and the sub-area vertical pixel main portion Connected, and the angles between the multiple sub-area pixel branch portions and the horizontal pixel main portion of the sub-area and the vertical pixel main portion of the sub-area are acute;
  • the vertical pixel main portion of the main area includes the vertical main area close to the data line 20
  • the vertical pixel main section of the secondary area includes the main section of the vertical frame of the secondary area close to the data line 20 and the cross at the center of the pixel electrode of the secondary area
  • the sub-area vertical center main trunk 37 is provided.
  • the shared common electrode 26 is at least partially covered by the vertical central trunk portion 36 of the main zone and the vertical central trunk portion 37 of the secondary zone.
  • the TFT array substrate 1 further includes a DBS (Data BM Saving, no black matrix on the data line) common electrode 38 arranged on the same layer as the pixel electrode 25 and corresponding to the data line 20. 20 shading; the materials of the DBS common electrode 38 and the pixel electrode 25 both include ITO (Indium Tin Oxide).
  • DBS Data BM Saving, no black matrix on the data line
  • the active layer 5 is provided under the data line 20 and the shared common electrode 26, and this part of the active layer 5 includes the metal wiring covering area 18 and the second The peripheral area 19, the data line 20 and the shared common electrode 26 are arranged in the metal trace coverage area 18, and the active layer 5 in the second peripheral area 19 is also distributed in multiple segments.
  • FIG. 10 only shows that the periphery of the active layer 5 (specifically, the first peripheral region 9) corresponding to the source and drain electrodes 6 is distributed in multiple segments, but it does not exclude that the data line 20 and the shared common electrode 26 are distributed in multiple segments.
  • the active layer 5 also exists under the inner metal wiring 17, if the active layer 5 also exists under the metal wiring 17, that is, the active layer 5 also includes the metal wiring covering area 18 and the second peripheral area 19, then The active layer 5 located in the second peripheral region 19 is also distributed in multiple segments; FIGS.
  • 11 and 12 are for the outer periphery of the active layer 5 corresponding to the shared common electrode 26 (specifically, the second peripheral region 19) is distributed in multiple segments Schematic diagram of the structure; it is understandable that when the periphery of the active layer 5 corresponding to the shared common electrode 26 (specifically the second peripheral region 19) is distributed in multiple segments in this embodiment, the periphery of the active layer 5 corresponding to the data line 20 ( Specifically, the second peripheral area 19) is also distributed in multiple sections (not shown in the figure).
  • the TFT array substrate 1 further includes a light-shielding layer 21 corresponding to the shared common electrode 26; the light-shielding layer 21 is located on the side of the active layer 5 away from the shared common electrode 26; the light-shielding layer 21 is perpendicular to the TFT array substrate 1.
  • the projection in the direction (orthogonal projection on the base substrate 2) completely covers the projection of the active layer 5 located in the metal trace coverage area 18 and the second peripheral area 19 in the direction perpendicular to the TFT array substrate 1.
  • the light-shielding layer 21 and the gate 3 are formed in the same manufacturing process and have the same material.
  • the light-shielding layer 21 can shield the light source located under the active layer 5 in the metal wiring coverage area 18 and the second peripheral area 19, and prevent the lower surface of the active layer 5 located in the metal wiring coverage area 18 and the second peripheral area 19 from being affected. Illumination produces photoelectric current.
  • the shared common electrode 26 of a specific potential is connected to the source 10 of the shared thin film transistor 33, and the voltage difference between the pixel electrode 35 of the sub-region and the common electrode of the upper plate can be adjusted, so that the pixel electrode 35 of the sub-region is connected to the upper plate common electrode.
  • the voltage difference between the plate common electrodes is smaller than the voltage difference between the pixel electrode 34 of the main area and the upper plate common electrode; because the shared common electrode 26, the data line 20, and the source and drain electrodes 6 are the same as the active layer 5.
  • the photomask is formed, and the active layer 5 includes a first peripheral region 9 not covered by the source and drain electrodes 6 and a second peripheral region 19 not covered by the metal wiring 17 and the shared common electrode 26, which will be located in the first peripheral region 9 and
  • the active layer 5 of the second peripheral area 19 is made as a multi-stage discontinuous structure.
  • the area of the active layer 5 located in the first peripheral area and the second peripheral area 19 is reduced, thereby reducing the first peripheral area.
  • the number of photo-generated carriers generated by the active layer 5 of the second peripheral area 9 and the second peripheral area 19 by light including the backlight and natural light in the environment).
  • the first peripheral area 9 and the second peripheral area 19 can be avoided
  • the active layer 5 forms a continuous path for the photo-generated leakage current, thereby effectively reducing the transmission efficiency of photo-generated carriers on the active layer 5 of the first peripheral region 9 and the second peripheral region 19. Therefore, the TFT array provided by the present application
  • the substrate 1 can effectively improve the problem of the light-generated leakage current of the thin film transistor, the data line 20 and the shared common electrode 26.
  • an embodiment of the present application also provides a display panel 39.
  • the display panel 39 includes the TFT array substrate 1 in the above embodiment, a counter substrate 40 disposed opposite to the TFT array substrate 1, and a display panel located on the TFT array substrate.
  • the liquid crystal layer 41 between the substrate 1 and the counter substrate 40.
  • the display panel 39 further includes a color filter 42.
  • the color filter 42 may be disposed on the side of the TFT array substrate 1 close to the liquid crystal layer 41, and may also be disposed on the side of the counter substrate 40 close to the liquid crystal layer 41. There is no restriction here.
  • the display panel 39 may also be an OLED display panel, that is, an organic light-emitting function layer is provided between the TFT array substrate 1 and the counter substrate 40.
  • the TFT array substrate 1 of the display panel 39 can be prepared by the 5Mask or 4Mask process: if the 5Mask process is used, the active layer 5 of the TFT array substrate 1 obtained includes the first layer that is not covered by the source and drain electrodes 6. In the peripheral area 9, the active layer 5 located in the first peripheral area 9 is made into a multi-stage discontinuous structure. On the one hand, the area of the active layer 5 located in the first peripheral area is reduced, thereby reducing the first peripheral area The number of photo-generated carriers generated by the active layer 5 of 9 under light (including backlight and natural light in the environment).
  • the active layer 5 of the first peripheral region 9 can prevent the active layer 5 of the first peripheral region 9 from forming a continuous path of photo-generated leakage current Therefore, the transmission efficiency of photogenerated carriers on the active layer 5 of the first peripheral region 9 is effectively reduced; if the 4Mask process is used, a photomask can be saved, but the active layer 5 of the TFT array substrate 1 obtained includes the The first peripheral area 9 covered by the source and drain electrodes 6 and the second peripheral area 19 not covered by the metal wiring 17, the active layer 5 located in the first peripheral area 9 and the second peripheral area 19 is made into a multi-segment type
  • the discontinuous structure reduces the area of the active layer 5 located in the first peripheral area and the second peripheral area 19, thereby reducing the light exposure of the active layer 5 in the first peripheral area 9 and the second peripheral area 19 ( Including the number of photo-generated carriers generated by the backlight and natural light in the environment.
  • the TFT array substrate 1 provided by the present application can be effectively prepared by adopting the 5Mask process or the 4Mask process Improve the problem of the photo-generated leakage current of the thin film transistor and the metal trace 17 position.

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Abstract

一种TFT阵列基板和显示面板，TFT阵列基板包括有源层(5)和设置在所述有源层(5)上的源漏电极(6)；所述有源层(5)包括电极覆盖区(7)、沟道区(8)以及围绕所述电极覆盖区(7)和所述沟道区(8)设置的第一***区(9)；所述源漏电极(6)对应所述电极覆盖区(7)设置；位于所述第一***区(9)的所述有源层呈多段式分布。

Description

TFT阵列基板和显示面板
本申请要求于2019年12月11日提交中国专利局、申请号为201911266374.7、发明名称为“一种TFT阵列基板和显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示面板技术领域，尤其涉及一种TFT阵列基板和显示面板。
 背景技术
通常，薄膜晶体管（Thin Film Transistor，TFT）被用作显示面板的驱动元件。薄膜晶体管中的有源层受到光照射后会产生光生载流子，导致薄膜晶体管的漏电流增加，从而影响显示面板的显示画面的质量，例如会产生串扰、残像等现象。
含有薄膜晶体管的阵列基板（Array）可以采用4Mask（光罩）工艺或5Mask工艺制作。5Mask工艺中，半导体层（有源层）和源漏电极分别采用不同的光罩制作形成，考虑到源漏电极与半导体层重叠时的对准良率，一般半导体层的图案较大，在半导体层上形成源漏电极后，图案较大的半导体层会在源极和漏极的***形成环路，这部分半导体层受光照后会成为光生电流的部分通路，将加重漏电流的问题；4Mask工艺制中，半导体层和源漏电极采用同一道光罩搭配不同的步骤制作形成，与源漏电极同时形成的还有数据线等金属图案，该金属图案下层也有对应的半导体层，受工艺的影响，源漏电极和包括数据线在内的金属图案的侧边均存在裸露的半导体层，这些裸露的半导体层受光照后也会成为光生电流的部分通路。
因此，需要对阵列基板的结构做改进，以改善薄膜晶体管中的半导体层光生漏电流的问题。
 技术问题
本申请提供一种TFT阵列基板和显示面板，通过将位于***区的有源层制作为多段式的不连续结构，可以改善薄膜晶体管中的有源层光生漏电流的问题。
 技术解决方案
本申请实施例提供一种TFT阵列基板，包括有源层和设置在所述有源层上的源漏电极；所述有源层包括电极覆盖区、沟道区以及围绕所述电极覆盖区和所述沟道区设置的第一***区；所述源漏电极对应所述电极覆盖区设置；
位于所述第一***区的所述有源层呈多段式分布。
在本申请实施例所提供的TFT阵列基板中，所述TFT阵列基板还包括位于所述有源层和所述源漏电极之间的掺杂层；所述掺杂层包括对应所述电极覆盖区设置的第一掺杂区，以及对应所述第一***区设置的第二掺杂区；
位于所述第二掺杂区的所述掺杂层呈多段式分布。
在本申请实施例所提供的TFT阵列基板中，所述掺杂层包括P型掺杂半导体和N型掺杂半导体中的任意一种。
在本申请实施例所提供的TFT阵列基板中，所述TFT阵列基板还包括与所述源漏电极同层设置的金属走线；对应的，所述有源层还包括被所述金属走线覆盖的金属走线覆盖区，以及围绕所述金属走线覆盖区设置的第二***区；
位于所述第二***区的所述有源层呈多段式分布。
在本申请实施例所提供的TFT阵列基板中，所述TFT阵列基板还包括位于所述有源层和所述源漏电极之间的掺杂层；所述掺杂层包括对应所述电极覆盖区和所述金属走线覆盖区设置的第三掺杂区，以及对应所述第一***区和所述第二***区设置的第四掺杂区；
位于所述第四掺杂区的所述掺杂层呈多段式分布。
在本申请实施例所提供的TFT阵列基板中，所述金属走线包括与所述源漏电极中的源极电连接的数据线。
在本申请实施例所提供的TFT阵列基板中，所述TFT阵列基板还包括设置在所述源漏电极和所述金属走线上的钝化层，以及位于所述钝化层上且与所述源漏电极中的漏极电连接的像素电极；
所述金属走线包括与所述源漏电极中的源极电连接且至少部分被所述像素电极覆盖的共享公共电极。
在本申请实施例所提供的TFT阵列基板中，所述TFT阵列基板还包括对应所述共享公共电极设置的遮光层；所述遮光层位于所述有源层远离所述金属走线的一侧；
所述遮光层在垂直于所述TFT阵列基板方向上的投影完全覆盖位于所述金属走线覆盖区和所述第二***区的所述有源层在垂直于所述TFT阵列基板方向上的投影。
在本申请实施例所提供的TFT阵列基板中，所述TFT阵列基板还包括衬底基板和依次设置在所述衬底基板上的栅极和栅极绝缘层，所述有源层设置在所述栅极绝缘层上；
所述栅极在所述衬底基板上的正投影完全覆盖位于所述电极覆盖区和所述第一***区的所述有源层在所述衬底基板上的正投影。
在本申请实施例所提供的TFT阵列基板中，所述有源层的材料包括非晶硅和铟镓锌氧化物中的任意一种。
在本申请实施例所提供的TFT阵列基板中，所述源漏电极包括间隔设置的源极和漏极，所述电极覆盖区包括间隔设置的源极覆盖区和漏极覆盖区，所述源极对应所述源极覆盖区设置，所述漏极对应所述漏极覆盖区设置，且所述源极覆盖区和所述漏极覆盖区通过所述沟道区连接。
本申请实施例还提供了一种显示面板，包括TFT阵列基板，以及与所述TFT阵列基板相对设置的对置基板；
所述TFT阵列基板包括有源层和设置在所述有源层上的源漏电极；所述有源层包括电极覆盖区、沟道区以及围绕所述电极覆盖区和所述沟道区设置的第一***区；所述源漏电极对应所述电极覆盖区设置；位于所述第一***区的所述有源层呈多段式分布。
在本申请实施例所提供的显示面板中，所述TFT阵列基板还包括位于所述有源层和所述源漏电极之间的掺杂层；所述掺杂层包括对应所述电极覆盖区设置的第一掺杂区，以及对应所述第一***区设置的第二掺杂区；
位于所述第二掺杂区的所述掺杂层呈多段式分布。
在本申请实施例所提供的显示面板中，所述掺杂层包括P型掺杂半导体和N型掺杂半导体中的任意一种。
在本申请实施例所提供的显示面板中，所述TFT阵列基板还包括与所述源漏电极同层设置的金属走线；对应的，所述有源层还包括被所述金属走线覆盖的金属走线覆盖区，以及围绕所述金属走线覆盖区设置的第二***区；
位于所述第二***区的所述有源层呈多段式分布。
在本申请实施例所提供的显示面板中，所述TFT阵列基板还包括位于所述有源层和所述源漏电极之间的掺杂层；所述掺杂层包括对应所述电极覆盖区和所述金属走线覆盖区设置的第三掺杂区，以及对应所述第一***区和所述第二***区设置的第四掺杂区；
位于所述第四掺杂区的所述掺杂层呈多段式分布。
在本申请实施例所提供的显示面板中，所述金属走线包括与所述源漏电极中的源极电连接的数据线。
在本申请实施例所提供的显示面板中，所述TFT阵列基板还包括设置在所述源漏电极和所述金属走线上的钝化层，以及位于所述钝化层上且与所述源漏电极中的漏极电连接的像素电极；
所述金属走线包括与所述源漏电极中的源极电连接且至少部分被所述像素电极覆盖的共享公共电极。
在本申请实施例所提供的显示面板中，所述显示面板还包括位于所述TFT阵列基板和所述对置基板之间的液晶层，以及位于所述TFT阵列基板靠近所述液晶层一侧的彩色滤光片。
在本申请实施例所提供的显示面板中，所述显示面板还包括位于所述TFT阵列基板和所述对置基板之间的液晶层，以及位于所述对置基板靠近所述液晶层一侧的彩色滤光片。
 有益效果
本申请实施例提供的TFT阵列基板中，有源层包括电极覆盖区和第一***区，源漏电极设置在电极覆盖区上，第一***区围绕电极覆盖区设置，即第一***区未被源漏电极覆盖，将位于第一***区的有源层制作为多段式的不连续结构，一方面，减小了位于第一***区的有源层的面积，从而减少了第一***区的有源层受光照（包括背光源和环境中的自然光）产生的光生载流子的数量，另一方面，可以避免第一***区的有源层形成光生漏电流的连续通路，从而有效的降低位于第一***区的有源层上光生载流子的传输效率，因此，本申请提供的TFT阵列基板可以有效的改善薄膜晶体管的光生漏电流的问题。
 附图说明
下面结合附图，通过对本申请的具体实施方式详细描述，将使本申请的技术方案及其它有益效果显而易见。
图1为本申请实施例提供的一种TFT阵列基板的部分结构示意图；
图2为图1中薄膜晶体管处的有源层的俯视图；
图3为图1中A-A’处的截面结构示意图；
图4为图1中薄膜晶体管处的有源层和掺杂层的俯视图；
图5为本申请实施例提供的另一种TFT阵列基板的部分结构示意图；
图6为图5中B区域的有源层的俯视图；
图7为图5中B区域的有源层和掺杂层的俯视图；
图8为图5中薄膜晶体管处的有源层和掺杂层的俯视图；
图9为本申请实施例提供的另一种TFT阵列基板的部分结构示意图；
图10为图9中C区域的放大示意图；
图11为图9中D区域的金属走线、有源层和遮光层的结构示意图；
图12为图11中E-E’处的截面结构示意图；
图13为本申请实施例提供的一种显示面板的部分结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”、“顺时针”、“逆时针”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个所述特征。在本申请的描述中，“多个”的含义是两个或两个以上，除非另有明确具体的限定。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接或可以相互通讯；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
在本申请中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本申请的不同结构。为了简化本申请的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本申请。此外，本申请可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本申请提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
如图1至图3所示，本申请实施例提供了一种TFT阵列基板1，TFT阵列基板1包括衬底基板2和依次设置在衬底基板2上的栅极3、栅极绝缘层4、有源层5和源漏电极6；其中，有源层5包括电极覆盖区7、沟道区8以及围绕电极覆盖区7和沟道区8设置的第一***区9；源漏电极6对应电极覆盖区7设置；位于第一***区9的有源层5呈多段式分布。其中，栅极3、栅极绝缘层4、有源层5和源漏电极6构成了TFT阵列基板1的薄膜晶体管（TFT）。需要说明的是，本实施例中，第一***区9可以完全围绕电极覆盖区7和沟道区8设置，也可以仅设置在电极覆盖区7的***，也就是说，第一***区9是指除沟道区8以外未被源漏电极6覆盖的有源层5。
具体的，位于第一***区9的有源层5沿电极覆盖区7与第一***区9相邻的边呈多段式分布，且任意相邻的两段间隔设置，每一段的形状可以是矩形，也可以是其他形状，此处不做限制。
具体的，通过在光罩（Mask）上制作间断式的凹陷或对光罩做曲折设计，使得在形成图案化的有源层5时形成位于第一***区9的不连续的多段式有源层5。
具体的，有源层5的材料包括但不限于光敏感性强烈的非晶硅和铟镓锌氧化物（IGZO）中的任意一种。
具体的，源漏电极6包括间隔设置的源极10和漏极11，电极覆盖区7包括间隔设置的源极覆盖区12和漏极覆盖区13，源极10对应源极覆盖区12设置，漏极11对应漏极覆盖区13设置，且源极覆盖区12和漏极覆盖区13通过沟道区8连接。
具体的，本实施例中的TFT阵列基板1可以采用5Mask工艺制备得到，其中，有源层5和源漏电极6分别采用两道不同的光罩制备得到。
具体的，本实施例中的TFT阵列基板1适用于4畴（1TFT）像素结构或8畴（3TFT）像素结构，当然，TFT阵列基板1适用的像素结构类型不限于此。
本实施例中，有源层5包括电极覆盖区7和第一***区9，源漏电极6设置在电极覆盖区7上，第一***区9围绕电极覆盖区7设置，即第一***区9未被源漏电极6覆盖，将位于第一***区9的有源层5制作为多段式的不连续结构，一方面，减小了位于第一***区9的有源层5的面积，从而减少了第一***区9的有源层5受光照（包括背光源和环境中的自然光）产生的光生载流子的数量，另一方面，可以避免位于第一***区9的有源层5形成光生漏电流的连续通路，从而有效的降低第一***区9的有源层5上光生载流子的传输效率，因此，本申请提供的TFT阵列基板1可以有效的改善薄膜晶体管的光生漏电流的问题。
在一实施例中，栅极3在衬底基板2上的正投影完全覆盖位于电极覆盖区7和第一***区9的有源层5在衬底基板2上的正投影。本实施例中，栅极3可以遮挡有源层5下方的光源，避免有源层5的下表面受到光照而产生光生电流。
在一实施例中，TFT阵列基板1还包括位于有源层5和源漏电极6之间的掺杂层14，掺杂层14包括P型掺杂半导体或N型掺杂半导体；如图4所示，掺杂层14包括对应电极覆盖区7设置的第一掺杂区15，以及对应第一***区9设置的第二掺杂区16；位于第二掺杂区16的掺杂层14呈多段式分布。
具体的，第二掺杂区16的面积小于或等于第一***区9的面积；多段式分布的掺杂层14与多段式分布的有源层5在同一制程中形成，即采用同一光罩形成，也就是说，多段式分布的掺杂层14与多段式分布的有源层5一一对应设置。
本实施例中，掺杂层14的材料包括半导体材料和掺杂在半导体材料中的掺杂材料，其中，半导体材料与有源层5的材料相同，因此，未被源漏电极6覆盖的掺杂层14（位于第二掺杂区16的掺杂层14）受到光照也会产生光生电流，将位于第二掺杂区16的掺杂层14制作成多段式结构也可以减小光生载流子的数量以及降低光生载流子的传输效率，从而有效的改善薄膜晶体管的光生漏电流的问题。
如图5和图6所示，本申请实施例还提供了一种TFT阵列基板1，与上述实施例不同的在于，TFT阵列基板1还包括与源漏电极6同层设置的金属走线17；对应的，如图6所示，有源层5还包括被金属走线17覆盖的金属走线覆盖区18，以及围绕金属走线覆盖区18设置的第二***区19；位于第二***区19的有源层5呈多段式分布。
具体的，本实施例中的TFT阵列基板1可以采用4Mask工艺制备得到，其中，有源层5、源漏电极6以及金属走线17采用同一道光罩制备得到，且金属走线17与源漏电极6同层设置且材料相同，可以理解的是，与源漏电极6同制程形成的所有金属走线17下方均存在如图6所示的有源层5，其中，有源层5的第一***区9和第二***区19是受图案化工艺影响而产生的有源层5的拖尾。
具体的，金属走线17包括与源漏电极6中的源极10电连接的数据线20，数据线20与源漏电极6的源极电连接，以提供源极电信号。
本实施例中，有源层5包括未被源漏电极6覆盖的第一***区9以及未被金属走线17覆盖的第二***区19，将位于第一***区9和第二***区19的有源层5制作为多段式的不连续结构，一方面，减小了位于第一***和第二***区19的有源层5的面积，从而减少了第一***区9和第二***区19的有源层5受光照（包括背光源和环境中的自然光）产生的光生载流子的数量，另一方面，可以避免第一***区9和第二***区19的有源层5形成光生漏电流的连续通路，从而有效的降低第一***区9和第二***区19的有源层5上光生载流子的传输效率，因此，本申请提供的TFT阵列基板1可以有效的改善薄膜晶体管以及金属走线17位置的光生漏电流的问题。
在一实施例中，TFT阵列基板1还包括位于有源层5和源漏电极6之间的掺杂层14；如图7和图8所示，掺杂层14包括对应电极覆盖区7和金属走线覆盖区18设置的第三掺杂区22，以及对应第一***区9和第二***区19设置的第四掺杂区23；位于第四掺杂区23的掺杂层14呈多段式分布。
具体的，多段式分布的掺杂层14与多段式分布的有源层5在同一制程中形成，即采用同一光罩形成，也就是说，多段式分布的掺杂层14与多段式分布的有源层5一一对应设置。
本实施例中，掺杂层14的材料包括半导体材料和掺杂在半导体材料中的掺杂材料，其中，半导体材料与有源层5的材料相同，因此，位于第四掺杂区23的掺杂层14（未被源漏电极6和金属走线17覆盖的掺杂层14）受到光照也会产生光生电流，将位于第四掺杂区23的掺杂层14制作成多段式结构也可以减小光生载流子的数量以及降低光生载流子的传输效率，从而有效的改善薄膜晶体管和金属走线17位置的光生漏电流的问题。
如图9和图10所示，本申请实施例还提供了一种具有8畴3薄膜晶体管像素结构的TFT阵列基板1，与上述实施例不同的在于，TFT阵列基板1形成有多个呈阵列分布的子像素27，每个子像素27包括主（main）区和次（sub）区；TFT阵列基板1对应每一行子像素27分别设置一条扫描线30，该扫描线30介于主区28和次区29之间，且对应每一列子像素27分别设置一条数据线20（与源漏极11同层形成的金属走线17）；TFT阵列基板1还包括对应每个子像素27设置的主区薄膜晶体管（TFT）31、次区薄膜晶体管32和共享薄膜晶体管33，每个薄膜晶体管均由栅极3、栅极绝缘层4、有源层5和源漏电极6构成，且每个薄膜晶体管的有源层5中未被源漏电极6覆盖的第一***区9均呈多段式分布。
具体的，TFT阵列基板1还包括设置在源漏电极6和数据线20（金属走线17）上的钝化层（由于钝化层一般为透明状，图9中未示出，可参考图12中的钝化层24），以及位于钝化层上且与源漏电极6中的漏极11电连接（通过在钝化层上设置过孔实现电连接）的像素电极25；TFT阵列基板1还包括与源漏电极6中的源极10电连接的且至少部分被像素电极25覆盖的共享公共电极（share bar）26，且共享公共电极26与数据线20以及源漏电极6同制程形成且材料相同，故共享公共电极26与数据线20同属于金属走线17。
具体的，像素电极25包括对应主区28设置的主区像素电极34和对应次区设置的次区像素电极35；主区薄膜晶体管31的栅极、次区薄膜晶体管32的栅极和共享薄膜晶体管33的栅极连接同一扫描线30，主区薄膜晶体管31的源极和次区薄膜晶体管32的源极连接同一数据线20，主区薄膜晶体管31的漏极连接（通过钝化层上的过孔连接）主区像素电极34，次区薄膜晶体管32的漏极和共享薄膜晶体管33的漏极连接（通过钝化层上的过孔连接）次区像素电极35，共享薄膜晶体管33的源极连接共享公共电极26。
具体的，主区像素电极34包括主区水平像素主干部、主区竖直像素主干部以及主区像素分支部，次区像素电极35包括次区水平像素主干部、次区竖直像素主干部以及次区像素分支部；主区像素电极34的主区水平像素主干部和主区竖直像素主干部垂直相交，且由主区水平像素主干部和主区竖直像素主干部垂直相交均分形成4个主区像素显示区域，每个主区像素显示区域内包括多个相互间隔且平行设置的主区像素分支部，每个主区像素分支部的两端分别与主区水平像素主干部和主区竖直像素主干部连接，且多个主区像素分支部与主区水平像素主干部和主区竖直像素主干部之间的夹角为锐角（例如45°）；同样的，次区像素电极35的次区水平像素主干部和次区竖直像素主干部垂直相交，且由次区水平像素主干部和次区竖直像素主干部垂直相交均分形成4个次区像素显示区域，每个次区像素显示区域内包括多个相互间隔且平行设置的次区像素分支部，每个次区像素分支部的两端分别与次区水平像素主干部和次区竖直像素主干部连接，且多个次区像素分支部与次区水平像素主干部和次区竖直像素主干部之间的夹角为锐角；主区竖直像素主干部包括靠近数据线20的主区竖直边框主干部和位于主区像素电极34中心十字的主区竖直中心主干部36；次区竖直像素主干部包括靠近数据线20的次区竖直边框主干部和位于次区像素电极中心十字的次区竖直中心主干部37。
具体的，共享公共电极26至少部分被主区竖直中心主干部36和次区竖直中心主干部37覆盖。
具体的，TFT阵列基板1还包括与像素电极25同层设置且与数据线20对应的DBS（Data BM Saving，数据线上无黑色矩阵）公共电极38，DBS公共电极38通过电场实现对数据线20遮光；DBS公共电极38与像素电极25的材料均包括ITO（氧化铟锡）。
在一实施例中，如图11和图12所示，数据线20和共享公共电极26的下方均设有有源层5，且这部分有源层5包括金属走线覆盖区18和第二***区19，数据线20和共享公共电极26设置在金属走线覆盖区18，位于第二***区19的有源层5也呈多段式分布。
需要说明的是，图10中仅示出源漏电极6对应的有源层5的***（具体为第一***区9）呈多段式分布，但不排除包括数据线20和共享公共电极26在内的金属走线17下方也存在有源层5的情况，若金属走线17下方也存在有源层5，即有源层5还包括金属走线覆盖区18和第二***区19，则位于第二***区19的有源层5也呈多段式分布；图11和图12针对的是共享公共电极26对应的有源层5的***（具体为第二***区19）多段式分布的结构示意图；可以理解的是，本实施例中共享公共电极26对应的有源层5的***（具体为第二***区19）多段式分布时，数据线20对应的有源层5的***（具体为第二***区19）也呈多段式分布（未在图中示出）。
在一实施例中，TFT阵列基板1还包括对应共享公共电极26设置的遮光层21；遮光层21位于有源层5远离共享公共电极26的一侧；遮光层21在垂直于TFT阵列基板1方向上的投影（在衬底基板2上的正投影）完全覆盖位于金属走线覆盖区18和第二***区19的有源层5在垂直于TFT阵列基板1方向上的投影。其中，遮光层21与栅极3同制程形成，且材料相同。遮光层21可以遮挡位于金属走线覆盖区18和第二***区19的有源层5下方的光源，避免位于金属走线覆盖区18和第二***区19的有源层5的下表面受到光照而产生光生电流。
本实施例中，采用特定电位的共享公共电极26与共享薄膜晶体管33的源极10连接，可以调控次区像素电极35与上板公共电极之间的压差，使次区像素电极35与上板公共电极之间的压差相对于主区像素电极34与上板公共电极之间的压差差异较小；由于共享公共电极26、数据线20和源漏电极6与有源层5采用同一光罩形成，有源层5包括未被源漏电极6覆盖的第一***区9以及未被金属走线17和共享公共电极26覆盖的第二***区19，将位于第一***区9和第二***区19的有源层5制作为多段式的不连续结构，一方面，减小了位于第一***和第二***区19的有源层5的面积，从而减少了第一***区9和第二***区19的有源层5受光照（包括背光源和环境中的自然光）产生的光生载流子的数量，另一方面，可以避免第一***区9和第二***区19的有源层5形成光生漏电流的连续通路，从而有效的降低第一***区9和第二***区19的有源层5上光生载流子的传输效率，因此，本申请提供的TFT阵列基板1可以有效的改善薄膜晶体管以及数据线20和共享公共电极26等位置的光生漏电流的问题。
如图13所示，本申请实施例还提供了一种显示面板39，显示面板39包括上述实施例中的TFT阵列基板1，与TFT阵列基板1相对设置的对置基板40，以及位于TFT阵列基板1和对置基板40之间的液晶层41。
具体的，显示面板39还包括彩色滤光片42，彩色滤光片42可以设置在TFT阵列基板1靠近液晶层41的一侧，还可以设置在对置基板40靠近液晶层41的一侧，此处不做限制。
当然，显示面板39还可以是OLED显示面板，即TFT阵列基板1和对置基板40之间设置有有机发光功能层。
本实施例中，显示面板39的TFT阵列基板1可以采用5Mask或4Mask工艺制备得到：若采用5Mask工艺制备，得到的TFT阵列基板1的有源层5包括未被源漏电极6覆盖的第一***区9，将位于第一***区9的有源层5制作为多段式的不连续结构，一方面，减小了位于第一***的有源层5的面积，从而减少了第一***区9的有源层5受光照（包括背光源和环境中的自然光）产生的光生载流子的数量，另一方面，可以避免第一***区9的有源层5形成光生漏电流的连续通路，从而有效的降低第一***区9的有源层5上光生载流子的传输效率；若采用4Mask工艺制备，可以节省一道光罩，但是得到的TFT阵列基板1的有源层5包括未被源漏电极6覆盖的第一***区9以及未被金属走线17覆盖的第二***区19，将位于第一***区9和第二***区19的有源层5制作为多段式的不连续结构，一方面，减小了位于第一***和第二***区19的有源层5的面积，从而减少了第一***区9和第二***区19的有源层5受光照（包括背光源和环境中的自然光）产生的光生载流子的数量，另一方面，可以避免第一***区9和第二***区19的有源层5形成光生漏电流的连续通路，从而有效的降低第一***区9和第二***区19的有源层5上光生载流子的传输效率；因此，本申请提供的TFT阵列基板1无论是采用5Mask工艺还是采用4Mask工艺制备均可以有效的改善薄膜晶体管以及金属走线17位置的光生漏电流的问题。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例所提供的一种TFT阵列基板和显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种TFT阵列基板，包括有源层和设置在所述有源层上的源漏电极；所述有源层包括电极覆盖区、沟道区以及围绕所述电极覆盖区和所述沟道区设置的第一***区；所述源漏电极对应所述电极覆盖区设置；
    位于所述第一***区的所述有源层呈多段式分布。
  2. 如权利要求1所述的TFT阵列基板，其中，所述TFT阵列基板还包括位于所述有源层和所述源漏电极之间的掺杂层；所述掺杂层包括对应所述电极覆盖区设置的第一掺杂区，以及对应所述第一***区设置的第二掺杂区；
    位于所述第二掺杂区的所述掺杂层呈多段式分布。
  3. 如权利要求2所述的TFT阵列基板，其中，所述掺杂层包括P型掺杂半导体和N型掺杂半导体中的任意一种。
  4. 如权利要求1所述的TFT阵列基板，其中，所述TFT阵列基板还包括与所述源漏电极同层设置的金属走线；对应的，所述有源层还包括被所述金属走线覆盖的金属走线覆盖区，以及围绕所述金属走线覆盖区设置的第二***区；
    位于所述第二***区的所述有源层呈多段式分布。
  5. 如权利要求4所述的TFT阵列基板，其中，所述TFT阵列基板还包括位于所述有源层和所述源漏电极之间的掺杂层；所述掺杂层包括对应所述电极覆盖区和所述金属走线覆盖区设置的第三掺杂区，以及对应所述第一***区和所述第二***区设置的第四掺杂区；
    位于所述第四掺杂区的所述掺杂层呈多段式分布。
  6. 如权利要求4所述的TFT阵列基板，其中，所述金属走线包括与所述源漏电极中的源极电连接的数据线。
  7. 如权利要求4所述的TFT阵列基板，其中，所述TFT阵列基板还包括设置在所述源漏电极和所述金属走线上的钝化层，以及位于所述钝化层上且与所述源漏电极中的漏极电连接的像素电极；
    所述金属走线包括与所述源漏电极中的源极电连接且至少部分被所述像素电极覆盖的共享公共电极。
  8. 如权利要求7所述的TFT阵列基板，其中，所述TFT阵列基板还包括对应所述共享公共电极设置的遮光层；所述遮光层位于所述有源层远离所述金属走线的一侧；
    所述遮光层在垂直于所述TFT阵列基板方向上的投影完全覆盖位于所述金属走线覆盖区和所述第二***区的所述有源层在垂直于所述TFT阵列基板方向上的投影。
  9. 如权利要求1所述的TFT阵列基板，其中，所述TFT阵列基板还包括衬底基板和依次设置在所述衬底基板上的栅极和栅极绝缘层，所述有源层设置在所述栅极绝缘层上；
    所述栅极在所述衬底基板上的正投影完全覆盖位于所述电极覆盖区和所述第一***区的所述有源层在所述衬底基板上的正投影。
  10. 如权利要求1所述的TFT阵列基板，其中，所述有源层的材料包括非晶硅和铟镓锌氧化物中的任意一种。
  11. 如权利要求1所述的TFT阵列基板，其中，所述源漏电极包括间隔设置的源极和漏极，所述电极覆盖区包括间隔设置的源极覆盖区和漏极覆盖区，所述源极对应所述源极覆盖区设置，所述漏极对应所述漏极覆盖区设置，且所述源极覆盖区和所述漏极覆盖区通过所述沟道区连接。
  12. 一种显示面板，其特征在于，包括如权利要求1所述TFT阵列基板，以及与所述TFT阵列基板相对设置的对置基板。
  13. 如权利要求12所述的显示面板，其中，所述TFT阵列基板还包括位于所述有源层和所述源漏电极之间的掺杂层；所述掺杂层包括对应所述电极覆盖区设置的第一掺杂区，以及对应所述第一***区设置的第二掺杂区；
    位于所述第二掺杂区的所述掺杂层呈多段式分布。
  14. 如权利要求13所述的显示面板，其中，所述掺杂层包括P型掺杂半导体和N型掺杂半导体中的任意一种。
  15. 如权利要求12所述的显示面板，其中，所述TFT阵列基板还包括与所述源漏电极同层设置的金属走线；对应的，所述有源层还包括被所述金属走线覆盖的金属走线覆盖区，以及围绕所述金属走线覆盖区设置的第二***区；
    位于所述第二***区的所述有源层呈多段式分布。
  16. 如权利要求15所述的显示面板，其中，所述TFT阵列基板还包括位于所述有源层和所述源漏电极之间的掺杂层；所述掺杂层包括对应所述电极覆盖区和所述金属走线覆盖区设置的第三掺杂区，以及对应所述第一***区和所述第二***区设置的第四掺杂区；
    位于所述第四掺杂区的所述掺杂层呈多段式分布。
  17. 如权利要求15所述的显示面板，其中，所述金属走线包括与所述源漏电极中的源极电连接的数据线。
  18. 如权利要求15所述的显示面板，其中，所述TFT阵列基板还包括设置在所述源漏电极和所述金属走线上的钝化层，以及位于所述钝化层上且与所述源漏电极中的漏极电连接的像素电极；
    所述金属走线包括与所述源漏电极中的源极电连接且至少部分被所述像素电极覆盖的共享公共电极。
  19. 如权利要求12所述的显示面板，其中，所述显示面板还包括位于所述TFT阵列基板和所述对置基板之间的液晶层，以及位于所述TFT阵列基板靠近所述液晶层一侧的彩色滤光片。
  20. 如权利要求12所述的显示面板，其中，所述显示面板还包括位于所述TFT阵列基板和所述对置基板之间的液晶层，以及位于所述对置基板靠近所述液晶层一侧的彩色滤光片。
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